Console Output
+ /eda/oss-cad-suite/bin/nextpnr-ecp5 --json ./build/out.json --write ./build/out_pnr.json --45k --lpf Risco-5/fpga/ecp5/pinout.lpf --textcfg ./build/out.config --package CABGA381 --speed 6 --lpf-allow-unconstrained
Info: constraining clock net 'clk' to 25.00 MHz
Info: Logic utilisation before packing:
Info: Total LUT4s: 5207/43848 11%
Info: logic LUTs: 2935/43848 6%
Info: carry LUTs: 424/43848 0%
Info: RAM LUTs: 1232/ 5481 22%
Info: RAMW LUTs: 616/10962 5%
Info: Total DFFs: 1018/43848 2%
Info: Packing IOs..
Info: $gpios[5]$iobuf_i: gpios_$_TBUF__Y.Y
Info: pin 'gpios[5]$tr_io' constrained to Bel 'X0/Y23/PIOC'.
Info: $gpios[4]$iobuf_i: gpios_$_TBUF__Y_1.Y
Info: pin 'gpios[4]$tr_io' constrained to Bel 'X0/Y44/PIOA'.
Info: $gpios[3]$iobuf_i: gpios_$_TBUF__Y_2.Y
Info: pin 'gpios[3]$tr_io' constrained to Bel 'X0/Y23/PIOA'.
Info: $gpios[2]$iobuf_i: gpios_$_TBUF__Y_3.Y
Info: pin 'gpios[2]$tr_io' constrained to Bel 'X90/Y23/PIOD'.
Info: $gpios[1]$iobuf_i: gpios_$_TBUF__Y_4.Y
Info: pin 'gpios[1]$tr_io' constrained to Bel 'X0/Y14/PIOD'.
Info: $gpios[0]$iobuf_i: gpios_$_TBUF__Y_5.Y
Info: pin 'gpios[0]$tr_io' constrained to Bel 'X0/Y44/PIOB'.
Info: pin 'tx$tr_io' constrained to Bel 'X90/Y20/PIOC'.
Info: pin 'rx$tr_io' constrained to Bel 'X90/Y20/PIOA'.
Info: pin 'reset$tr_io' constrained to Bel 'X0/Y29/PIOA'.
Info: pin 'led[7]$tr_io' constrained to Bel 'X90/Y20/PIOD'.
Info: pin 'led[6]$tr_io' constrained to Bel 'X0/Y44/PIOD'.
Info: pin 'led[5]$tr_io' constrained to Bel 'X0/Y59/PIOA'.
Info: pin 'led[4]$tr_io' constrained to Bel 'X15/Y71/PIOB'.
Info: pin 'led[3]$tr_io' constrained to Bel 'X90/Y29/PIOC'.
Info: pin 'led[2]$tr_io' constrained to Bel 'X90/Y44/PIOB'.
Info: pin 'led[1]$tr_io' constrained to Bel 'X0/Y44/PIOC'.
Info: pin 'led[0]$tr_io' constrained to Bel 'X0/Y59/PIOC'.
Info: pin 'clk$tr_io' constrained to Bel 'X0/Y68/PIOC'.
Info: Packing constants..
Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info: 464 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info: Promoting globals...
Info: promoting clock net clk$TRELLIS_IO_IN to global network
Info: Checksum: 0x7d39623b
Info: Device utilisation:
Info: TRELLIS_IO: 18/ 245 7%
Info: DCCA: 1/ 56 1%
Info: DP16KD: 0/ 108 0%
Info: MULT18X18D: 0/ 72 0%
Info: ALU54B: 0/ 36 0%
Info: EHXPLLL: 0/ 4 0%
Info: EXTREFB: 0/ 2 0%
Info: DCUA: 0/ 2 0%
Info: PCSCLKDIV: 0/ 2 0%
Info: IOLOGIC: 0/ 160 0%
Info: SIOLOGIC: 0/ 85 0%
Info: GSR: 0/ 1 0%
Info: JTAGG: 0/ 1 0%
Info: OSCG: 0/ 1 0%
Info: SEDGA: 0/ 1 0%
Info: DTR: 0/ 1 0%
Info: USRMCLK: 0/ 1 0%
Info: CLKDIVF: 0/ 4 0%
Info: ECLKSYNCB: 0/ 10 0%
Info: DLLDELD: 0/ 8 0%
Info: DDRDLL: 0/ 4 0%
Info: DQSBUFM: 0/ 10 0%
Info: TRELLIS_ECLKBUF: 0/ 8 0%
Info: ECLKBRIDGECS: 0/ 2 0%
Info: DCSC: 0/ 2 0%
Info: TRELLIS_FF: 1018/ 43848 2%
Info: TRELLIS_COMB: 5303/ 43848 12%
Info: TRELLIS_RAMW: 308/ 5481 5%
Info: Placed 18 cells based on constraints.
Info: Creating initial analytic placement for 3603 cells, random placement wirelen = 315935.
Info: at initial placer iter 0, wirelen = 2477
Info: at initial placer iter 1, wirelen = 2095
Info: at initial placer iter 2, wirelen = 1855
Info: at initial placer iter 3, wirelen = 1899
Info: Running main analytical placer, max placement attempts per cell = 5524488.
Info: at iteration #1, type ALL: wirelen solved = 1825, spread = 35220, legal = 35898; time = 0.16s
Info: at iteration #2, type ALL: wirelen solved = 4703, spread = 30193, legal = 30735; time = 0.21s
Info: at iteration #3, type ALL: wirelen solved = 6968, spread = 27555, legal = 28262; time = 0.21s
Info: at iteration #4, type ALL: wirelen solved = 8861, spread = 27301, legal = 28069; time = 0.20s
Info: at iteration #5, type ALL: wirelen solved = 10407, spread = 25510, legal = 26224; time = 0.18s
Info: at iteration #6, type ALL: wirelen solved = 11586, spread = 24785, legal = 25668; time = 0.14s
Info: at iteration #7, type ALL: wirelen solved = 12632, spread = 24019, legal = 24939; time = 0.14s
Info: at iteration #8, type ALL: wirelen solved = 13101, spread = 23300, legal = 24357; time = 0.14s
Info: at iteration #9, type ALL: wirelen solved = 13511, spread = 23369, legal = 24420; time = 0.14s
Info: at iteration #10, type ALL: wirelen solved = 14083, spread = 23326, legal = 24415; time = 0.14s
Info: at iteration #11, type ALL: wirelen solved = 14778, spread = 23288, legal = 24053; time = 0.13s
Info: at iteration #12, type ALL: wirelen solved = 14978, spread = 23256, legal = 24071; time = 0.13s
Info: at iteration #13, type ALL: wirelen solved = 15755, spread = 23981, legal = 24824; time = 0.13s
Info: at iteration #14, type ALL: wirelen solved = 16613, spread = 23989, legal = 24688; time = 0.13s
Info: at iteration #15, type ALL: wirelen solved = 16789, spread = 22898, legal = 24053; time = 0.15s
Info: at iteration #16, type ALL: wirelen solved = 16996, spread = 23251, legal = 24149; time = 0.19s
Info: HeAP Placer Time: 3.98s
Info: of which solving equations: 2.47s
Info: of which spreading cells: 0.32s
Info: of which strict legalisation: 0.09s
Info: Running simulated annealing placer for refinement.
Info: at iteration #1: temp = 0.000000, timing cost = 1275, wirelen = 24053
Info: at iteration #5: temp = 0.000000, timing cost = 1176, wirelen = 21258
Info: at iteration #10: temp = 0.000000, timing cost = 1058, wirelen = 20472
Info: at iteration #15: temp = 0.000000, timing cost = 972, wirelen = 20139
Info: at iteration #20: temp = 0.000000, timing cost = 991, wirelen = 20026
Info: at iteration #25: temp = 0.000000, timing cost = 999, wirelen = 19989
Info: at iteration #27: temp = 0.000000, timing cost = 964, wirelen = 19983
Info: SA placement time 15.67s
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 30.98 MHz (PASS at 25.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 8.95 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 10.52 ns
Info: Slack histogram:
Info: legend: * represents 41 endpoint(s)
Info: + represents [1,41) endpoint(s)
Info: [ 7723, 9299) |+
Info: [ 9299, 10875) |+
Info: [ 10875, 12451) |
Info: [ 12451, 14027) |+
Info: [ 14027, 15603) |+
Info: [ 15603, 17179) |*+
Info: [ 17179, 18755) |*+
Info: [ 18755, 20331) |*********+
Info: [ 20331, 21907) |*******+
Info: [ 21907, 23483) |*******+
Info: [ 23483, 25059) |****************+
Info: [ 25059, 26635) |***********+
Info: [ 26635, 28211) |*******************************************+
Info: [ 28211, 29787) |************************************************************
Info: [ 29787, 31363) |*****************+
Info: [ 31363, 32939) |****************+
Info: [ 32939, 34515) |*****+
Info: [ 34515, 36091) |********************
Info: [ 36091, 37667) |**************+
Info: [ 37667, 39243) |**********+
Info: Checksum: 0x125daf43
Info: Routing globals...
Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
Info: Routing..
Info: Setting up routing queue.
Info: Routing 25408 arcs.
Info: | (re-)routed arcs | delta | remaining| time spent |
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
Info: 1000 | 98 901 | 98 901 | 24561| 0.57 0.57|
Info: 2000 | 215 1784 | 117 883 | 23697| 0.25 0.82|
Info: 3000 | 299 2700 | 84 916 | 22844| 0.23 1.05|
Info: 4000 | 392 3607 | 93 907 | 21953| 0.24 1.30|
Info: 5000 | 499 4500 | 107 893 | 21267| 0.22 1.52|
Info: 6000 | 658 5341 | 159 841 | 20487| 0.25 1.77|
Info: 7000 | 857 6142 | 199 801 | 19735| 0.25 2.02|
Info: 8000 | 1059 6940 | 202 798 | 18993| 0.27 2.29|
Info: 9000 | 1246 7753 | 187 813 | 18308| 0.28 2.58|
Info: 10000 | 1474 8525 | 228 772 | 17676| 0.30 2.87|
Info: 11000 | 1732 9267 | 258 742 | 17041| 0.31 3.18|
Info: 12000 | 1995 10004 | 263 737 | 16405| 0.32 3.50|
Info: 13000 | 2256 10743 | 261 739 | 15744| 0.30 3.80|
Info: 14000 | 2552 11447 | 296 704 | 15112| 0.31 4.12|
Info: 15000 | 2896 12103 | 344 656 | 14567| 0.31 4.43|
Info: 16000 | 3228 12771 | 332 668 | 14016| 0.30 4.73|
Info: 17000 | 3537 13462 | 309 691 | 13426| 0.31 5.04|
Info: 18000 | 3866 14133 | 329 671 | 12910| 0.36 5.39|
Info: 19000 | 4264 14732 | 398 599 | 12409| 0.34 5.74|
Info: 20000 | 4789 15204 | 525 472 | 12033| 0.33 6.07|
Info: 21000 | 5216 15765 | 427 561 | 11593| 0.33 6.40|
Info: 22000 | 5689 16277 | 473 512 | 11180| 0.32 6.72|
Info: 23000 | 6095 16834 | 406 557 | 10640| 0.31 7.03|
Info: 24000 | 6455 17435 | 360 601 | 10060| 0.30 7.34|
Info: 25000 | 6776 18068 | 321 633 | 9529| 0.30 7.63|
Info: 26000 | 7152 18683 | 376 615 | 9003| 0.31 7.95|
Info: 27000 | 7382 19430 | 230 747 | 8325| 0.29 8.24|
Info: 28000 | 7666 20133 | 284 703 | 7695| 0.31 8.55|
Info: 29000 | 7988 20803 | 322 670 | 7051| 0.31 8.86|
Info: 30000 | 8218 21569 | 230 766 | 6363| 0.37 9.23|
Info: 31000 | 8263 22524 | 45 955 | 5440| 0.14 9.37|
Info: 32000 | 8289 23498 | 26 974 | 4468| 0.09 9.46|
Info: 33000 | 8358 24427 | 69 929 | 3568| 0.19 9.66|
Info: 34000 | 8420 25349 | 62 922 | 2644| 0.17 9.82|
Info: 35000 | 8566 26163 | 146 814 | 1821| 0.31 10.13|
Info: 36000 | 8669 26949 | 103 786 | 942| 0.25 10.38|
Info: 37000 | 8791 27759 | 122 810 | 115| 0.30 10.68|
Info: 37120 | 8794 27847 | 3 88 | 0| 0.06 10.74|
Info: Routing complete.
Info: Router1 time 10.74s
Info: Checksum: 0xcde9e3a9
Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
Info: curr total
Info: 0.5 0.5 Source SOC.Core.Control_Unit.state_TRELLIS_FF_Q_3.Q
Info: 0.9 1.4 Net SOC.Core.read_data_PFUMX_Z_C0_LUT4_D_B_LUT4_D_Z_LUT4_Z_C_LUT4_Z_B[1] (20,18) -> (19,18)
Info: Sink SOC.Uart.response_LUT4_B_Z_LUT4_Z_2_D_LUT4_Z_1.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 1.6 Source SOC.Uart.response_LUT4_B_Z_LUT4_Z_2_D_LUT4_Z_1.F
Info: 0.7 2.3 Net SOC.Uart.response_LUT4_B_Z_LUT4_Z_2_D[1] (19,18) -> (19,18)
Info: Sink SOC.Core.Control_Unit.save_write_value_LUT4_Z_D_LUT4_Z_D_LUT4_D_1_Z_LUT4_Z_1.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 2.5 Source SOC.Core.Control_Unit.save_write_value_LUT4_Z_D_LUT4_Z_D_LUT4_D_1_Z_LUT4_Z_1.F
Info: 0.2 2.8 Net SOC.Core.Control_Unit.save_write_value_LUT4_Z_D_LUT4_Z_D_LUT4_D_1_Z[2] (19,18) -> (19,18)
Info: Sink SOC.Core.Control_Unit.save_write_value_LUT4_Z_D_LUT4_Z_D_LUT4_D_1_Z_LUT4_D.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 3.0 Source SOC.Core.Control_Unit.save_write_value_LUT4_Z_D_LUT4_Z_D_LUT4_D_1_Z_LUT4_D.F
Info: 0.5 3.5 Net SOC.Core.Control_Unit.save_write_value_LUT4_Z_D_LUT4_Z_D_LUT4_D_1_Z_LUT4_D_Z[1] (19,18) -> (19,18)
Info: Sink SOC.Core.Control_Unit.save_write_value_LUT4_Z_D_LUT4_D_Z_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 3.7 Source SOC.Core.Control_Unit.save_write_value_LUT4_Z_D_LUT4_D_Z_LUT4_Z.F
Info: 0.5 4.2 Net SOC.Core.Control_Unit.nextstate_LUT4_Z_4_C_LUT4_Z_A[3] (19,18) -> (19,17)
Info: Sink SOC.Core.read_data_PFUMX_Z_C0_LUT4_D_B_LUT4_D_Z_LUT4_Z_B_LUT4_C_1_D_LUT4_Z_1.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 4.4 Source SOC.Core.read_data_PFUMX_Z_C0_LUT4_D_B_LUT4_D_Z_LUT4_Z_B_LUT4_C_1_D_LUT4_Z_1.F
Info: 0.9 5.3 Net SOC.Core.read_data_PFUMX_Z_C0_LUT4_D_B_LUT4_D_Z_LUT4_Z_B_LUT4_C_1_D[1] (19,17) -> (19,16)
Info: Sink SOC.Core.read_data_PFUMX_Z_C0_LUT4_D_B_LUT4_D_Z_LUT4_Z_B_LUT4_C_Z_LUT4_Z_2.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 5.6 Source SOC.Core.read_data_PFUMX_Z_C0_LUT4_D_B_LUT4_D_Z_LUT4_Z_B_LUT4_C_Z_LUT4_Z_2.F
Info: 1.1 6.7 Net SOC.Core.read_data_PFUMX_Z_C0_LUT4_D_B_LUT4_D_Z_LUT4_Z_B_LUT4_C_Z[3] (19,16) -> (15,16)
Info: Sink SOC.Core.read_data_PFUMX_Z_C0_LUT4_D_B_LUT4_D_Z_LUT4_Z_B_LUT4_C_1_Z_LUT4_Z_1_D_LUT4_D_Z_LUT4_B_Z_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 6.9 Source SOC.Core.read_data_PFUMX_Z_C0_LUT4_D_B_LUT4_D_Z_LUT4_Z_B_LUT4_C_1_Z_LUT4_Z_1_D_LUT4_D_Z_LUT4_B_Z_LUT4_Z.F
Info: 0.3 7.2 Net SOC.Core.read_data_PFUMX_Z_C0_LUT4_D_B_LUT4_D_Z_LUT4_Z_B_LUT4_C_1_Z_LUT4_Z_1_D_LUT4_D_Z_LUT4_B_Z[1] (15,16) -> (15,18)
Info: Sink SOC.Core.RegisterBank.registers.0.0_DO_LUT4_A_Z_LUT4_Z_C_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 7.4 Source SOC.Core.RegisterBank.registers.0.0_DO_LUT4_A_Z_LUT4_Z_C_LUT4_Z.F
Info: 0.0 7.5 Net SOC.Core.RegisterBank.registers.0.0_DO_LUT4_A_Z_LUT4_Z_C[1] (15,18) -> (15,18)
Info: Sink SOC.Core.RegisterBank.registers.0.4_DO_2_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_2.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 7.7 Source SOC.Core.RegisterBank.registers.0.4_DO_2_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_2.F
Info: 1.0 8.8 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_8_C_CCU2C_S0_COUT_CCU2C_CIN_S1_LUT4_C_Z_LUT4_Z_A[2] (15,18) -> (17,14)
Info: Sink SOC.Core.RegisterBank.registers.0.4_DO_2_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_C.C
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 9.0 Source SOC.Core.RegisterBank.registers.0.4_DO_2_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_C.F
Info: 0.5 9.5 Net SOC.Core.RegisterBank.registers.0.6_DO_LUT4_A_Z_LUT4_Z_1_D[3] (17,14) -> (17,14)
Info: Sink SOC.Core.RegisterBank.registers.0.7_DO_3_LUT4_A_Z_LUT4_Z_1.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 9.7 Source SOC.Core.RegisterBank.registers.0.7_DO_3_LUT4_A_Z_LUT4_Z_1.F
Info: 0.7 10.4 Net SOC.Core.RegisterBank.registers.0.7_DO_3_LUT4_A_Z[3] (17,14) -> (17,13)
Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_16_C_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0_LUT4_C_Z_LUT4_Z_2.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 10.7 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_16_C_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0_LUT4_C_Z_LUT4_Z_2.F
Info: 0.6 11.3 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_16_C_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0_LUT4_C_Z[3] (17,13) -> (17,13)
Info: Sink SOC.Core.RegisterBank.registers.0.1_DO_LUT4_A_Z_LUT4_B_Z_LUT4_D_Z_LUT4_Z_1.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 11.5 Source SOC.Core.RegisterBank.registers.0.1_DO_LUT4_A_Z_LUT4_B_Z_LUT4_D_Z_LUT4_Z_1.F
Info: 0.7 12.2 Net SOC.Core.RegisterBank.registers.0.1_DO_LUT4_A_Z_LUT4_B_Z_LUT4_D_Z[3] (17,13) -> (15,13)
Info: Sink SOC.Core.RegisterBank.registers.0.0_DO_3_LUT4_A_Z_LUT4_A_Z_LUT4_Z_B_LUT4_Z_1.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 12.4 Source SOC.Core.RegisterBank.registers.0.0_DO_3_LUT4_A_Z_LUT4_A_Z_LUT4_Z_B_LUT4_Z_1.F
Info: 1.6 14.0 Net SOC.Core.RegisterBank.registers.0.0_DO_3_LUT4_A_Z_LUT4_A_Z_LUT4_Z_B[2] (15,13) -> (10,18)
Info: Sink SOC.Core.RegisterBank.registers.0.0_DO_3_LUT4_A_Z_LUT4_A_Z_LUT4_Z.C
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 14.3 Source SOC.Core.RegisterBank.registers.0.0_DO_3_LUT4_A_Z_LUT4_A_Z_LUT4_Z.F
Info: 1.0 15.2 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_15_C_CCU2C_S1_COUT_CCU2C_CIN_B1[3] (10,18) -> (10,21)
Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_6_C_CCU2C_S1_S0_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_LUT4_Z_C_LUT4_D_Z_LUT4_D_Z_LUT4_Z_1_D_LUT4_Z_C_LUT4_Z_1.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 15.5 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_6_C_CCU2C_S1_S0_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_LUT4_Z_C_LUT4_D_Z_LUT4_D_Z_LUT4_Z_1_D_LUT4_Z_C_LUT4_Z_1.F
Info: 0.9 16.3 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_6_C_CCU2C_S1_S0_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_LUT4_Z_C_LUT4_D_Z_LUT4_D_Z_LUT4_Z_1_D_LUT4_Z_C[2] (10,21) -> (10,23)
Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_6_C_CCU2C_S1_S0_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_LUT4_Z_C_LUT4_D_Z_LUT4_D_Z_LUT4_Z_1_D_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 16.6 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_6_C_CCU2C_S1_S0_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_LUT4_Z_C_LUT4_D_Z_LUT4_D_Z_LUT4_Z_1_D_LUT4_Z.F
Info: 0.4 17.0 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_6_C_CCU2C_S1_S0_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_LUT4_Z_C_LUT4_D_Z_LUT4_D_Z_LUT4_Z_1_D[2] (10,23) -> (10,23)
Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_6_C_CCU2C_S1_S0_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_LUT4_Z_C_LUT4_D_Z_LUT4_D_Z_LUT4_Z_1_D_LUT4_C.C
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 17.2 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_6_C_CCU2C_S1_S0_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_LUT4_Z_C_LUT4_D_Z_LUT4_D_Z_LUT4_Z_1_D_LUT4_C.F
Info: 0.8 18.0 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_6_C_CCU2C_S1_S0_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_LUT4_Z_C_LUT4_D_Z_LUT4_D_Z_LUT4_Z_1_D_LUT4_C_Z[4] (10,23) -> (8,24)
Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_6_C_CCU2C_S1_S0_CCU2C_S0_CIN_CCU2C_COUT_S0_LUT4_Z_1_C_LUT4_Z_C_PFUMX_Z_BLUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 18.2 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_6_C_CCU2C_S1_S0_CCU2C_S0_CIN_CCU2C_COUT_S0_LUT4_Z_1_C_LUT4_Z_C_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: 0.7 19.0 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_6_C_CCU2C_S1_S0_CCU2C_S0_CIN_CCU2C_COUT_S0_LUT4_Z_1_C_LUT4_Z_C[3] (8,24) -> (9,21)
Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_6_C_CCU2C_S1_S0_CCU2C_S0_CIN_CCU2C_COUT_S0_LUT4_Z_1_C_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 19.2 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_6_C_CCU2C_S1_S0_CCU2C_S0_CIN_CCU2C_COUT_S0_LUT4_Z_1_C_LUT4_Z.F
Info: 0.6 19.8 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_6_C_CCU2C_S1_S0_CCU2C_S0_CIN_CCU2C_COUT_S0_LUT4_Z_1_C[3] (9,21) -> (9,21)
Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_6_C_CCU2C_S1_S0_CCU2C_S0_CIN_CCU2C_COUT_S0_LUT4_Z_1.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 20.1 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_6_C_CCU2C_S1_S0_CCU2C_S0_CIN_CCU2C_COUT_S0_LUT4_Z_1.F
Info: 0.8 20.9 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_6_C_CCU2C_S1_S0_CCU2C_S0_CIN_CCU2C_COUT_S0[3] (9,21) -> (5,20)
Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_3_C_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 21.1 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_3_C_LUT4_Z.F
Info: 0.4 21.5 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_3_C[2] (5,20) -> (5,20)
Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_3.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 21.8 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_3.F
Info: 0.7 22.4 Net SOC.Core.alu_out[4] (5,20) -> (5,20)
Info: Sink SOC.Core.Control_Unit.nextstate_LUT4_Z_5_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z.D
Info: Defined in:
Info: Risco-5/src/core/core.v:60.31-60.38
Info: 0.2 22.7 Source SOC.Core.Control_Unit.nextstate_LUT4_Z_5_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z.F
Info: 0.9 23.6 Net SOC.Core.Control_Unit.nextstate_LUT4_Z_5_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D[3] (5,20) -> (6,19)
Info: Sink SOC.Core.Control_Unit.nextstate_LUT4_Z_5_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 23.8 Source SOC.Core.Control_Unit.nextstate_LUT4_Z_5_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z.F
Info: 0.8 24.6 Net SOC.Core.Control_Unit.nextstate_LUT4_Z_5_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D[3] (6,19) -> (9,19)
Info: Sink SOC.Core.Control_Unit.nextstate_LUT4_Z_5_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 24.9 Source SOC.Core.Control_Unit.nextstate_LUT4_Z_5_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z.F
Info: 0.8 25.7 Net SOC.Core.Control_Unit.nextstate_LUT4_Z_5_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D[3] (9,19) -> (11,17)
Info: Sink SOC.Core.Control_Unit.nextstate_LUT4_Z_5_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 25.9 Source SOC.Core.Control_Unit.nextstate_LUT4_Z_5_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z.F
Info: 0.2 26.1 Net SOC.Core.Control_Unit.nextstate_LUT4_Z_5_D_LUT4_Z_D_LUT4_Z_D[3] (11,17) -> (11,17)
Info: Sink SOC.Core.Control_Unit.nextstate_LUT4_Z_5_D_LUT4_Z_D_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 26.3 Source SOC.Core.Control_Unit.nextstate_LUT4_Z_5_D_LUT4_Z_D_LUT4_Z.F
Info: 0.9 27.3 Net SOC.Core.Control_Unit.nextstate_LUT4_Z_5_D_LUT4_Z_D[3] (11,17) -> (13,16)
Info: Sink SOC.Core.Control_Unit.nextstate_LUT4_Z_5_D_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 27.5 Source SOC.Core.Control_Unit.nextstate_LUT4_Z_5_D_LUT4_Z.F
Info: 0.2 27.7 Net SOC.Core.Control_Unit.nextstate_LUT4_Z_5_D[3] (13,16) -> (13,16)
Info: Sink SOC.Core.Pc.load_LUT4_Z_B_LUT4_Z_1_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 28.0 Source SOC.Core.Pc.load_LUT4_Z_B_LUT4_Z_1_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z.F
Info: 0.6 28.6 Net SOC.Core.Pc.load_LUT4_Z_B_LUT4_Z_1_D_LUT4_Z_D_LUT4_Z_D[3] (13,16) -> (13,16)
Info: Sink SOC.Core.Pc.load_LUT4_Z_B_LUT4_Z_1_D_LUT4_Z_D_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 28.8 Source SOC.Core.Pc.load_LUT4_Z_B_LUT4_Z_1_D_LUT4_Z_D_LUT4_Z.F
Info: 0.7 29.5 Net SOC.Core.Pc.load_LUT4_Z_B_LUT4_Z_1_D_LUT4_Z_D[3] (13,16) -> (15,14)
Info: Sink SOC.Core.Pc.load_LUT4_Z_B_LUT4_Z_1_D_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 29.8 Source SOC.Core.Pc.load_LUT4_Z_B_LUT4_Z_1_D_LUT4_Z.F
Info: 0.4 30.2 Net SOC.Core.Pc.load_LUT4_Z_B_LUT4_Z_1_D[3] (15,14) -> (15,14)
Info: Sink SOC.Core.Pc.load_LUT4_Z_B_LUT4_Z_1.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 30.4 Source SOC.Core.Pc.load_LUT4_Z_B_LUT4_Z_1.F
Info: 0.4 30.8 Net SOC.Core.Pc.load_LUT4_Z_B[3] (15,14) -> (15,14)
Info: Sink SOC.Core.Pc.load_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 31.1 Source SOC.Core.Pc.load_LUT4_Z.F
Info: 1.6 32.7 Net SOC.Core.pc_load (15,14) -> (5,21)
Info: Sink SOC.Core.Pc.Output_TRELLIS_FF_Q_27.CE
Info: Defined in:
Info: Risco-5/src/core/core.v:52.32-52.39
Info: 0.0 32.7 Setup SOC.Core.Pc.Output_TRELLIS_FF_Q_27.CE
Info: 8.6 ns logic, 24.2 ns routing
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
Info: curr total
Info: 0.0 0.0 Source gpios[2]$tr_io.O
Info: 4.6 4.6 Net gpios[2]$TRELLIS_IO_IN (90,23) -> (15,25)
Info: Sink SOC.GPIOS.Gpios[2].data_in_LUT4_C.A
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:7.16-7.21
Info: 0.2 4.8 Source SOC.GPIOS.Gpios[2].data_in_LUT4_C.F
Info: 0.4 5.2 Net SOC.GPIOS.Gpios[2].data_in_LUT4_C_Z[2] (15,25) -> (15,25)
Info: Sink SOC.Core.read_data_LUT4_Z_2.C
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 5.5 Source SOC.Core.read_data_LUT4_Z_2.F
Info: 1.0 6.5 Net SOC.read_data[2] (15,25) -> (16,21)
Info: Sink SOC.Core.instruction_register_TRELLIS_FF_Q_29.M
Info: Defined in:
Info: Risco-5/src/peripheral/soc.v:22.34-22.43
Info: 0.0 6.5 Setup SOC.Core.instruction_register_TRELLIS_FF_Q_29.M
Info: 0.5 ns logic, 6.0 ns routing
Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
Info: curr total
Info: 0.5 0.5 Source SOC.GPIOS.Gpios[2].direction_TRELLIS_FF_Q.Q
Info: 4.6 5.1 Net SOC.GPIOS.gpio_direction[2] (9,25) -> (86,24)
Info: Sink SOC.GPIOS.Gpios[2].direction_LUT4_D.D
Info: Defined in:
Info: Risco-5/src/peripheral/gpios.v:16.19-16.33
Info: 0.2 5.3 Source SOC.GPIOS.Gpios[2].direction_LUT4_D.F
Info: 0.4 5.8 Net gpios_$_TBUF__Y_3_E (86,24) -> (86,24)
Info: Sink gpios[2]$tr_io$invert_T.A
Info: 0.2 6.0 Source gpios[2]$tr_io$invert_T.F
Info: 1.1 7.1 Net gpios[2]$tr_io$invert_T$conn$Z (86,24) -> (90,23)
Info: Sink gpios[2]$tr_io.T
Info: 1.0 ns logic, 6.1 ns routing
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 30.56 MHz (PASS at 25.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 6.46 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 7.13 ns
Info: Slack histogram:
Info: legend: * represents 43 endpoint(s)
Info: + represents [1,43) endpoint(s)
Info: [ 7278, 8867) |+
Info: [ 8867, 10456) |
Info: [ 10456, 12045) |
Info: [ 12045, 13634) |
Info: [ 13634, 15223) |
Info: [ 15223, 16812) |+
Info: [ 16812, 18401) |*+
Info: [ 18401, 19990) |*+
Info: [ 19990, 21579) |*******+
Info: [ 21579, 23168) |*********+
Info: [ 23168, 24757) |***+
Info: [ 24757, 26346) |***********************+
Info: [ 26346, 27935) |********+
Info: [ 27935, 29524) |************************************************************
Info: [ 29524, 31113) |************************************+
Info: [ 31113, 32702) |************************+
Info: [ 32702, 34291) |***********+
Info: [ 34291, 35880) |*******+
Info: [ 35880, 37469) |**********************+
Info: [ 37469, 39058) |*************+
Info: Program finished normally.
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