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Started by timer [Pipeline] Start of Pipeline [Pipeline] node Running on Jenkins in /var/lib/jenkins/workspace/Risco_5 [Pipeline] { [Pipeline] stage [Pipeline] { (Git Clone) [Pipeline] sh + rm -Rf Risco-5/ build/ [Pipeline] sh + git clone https://github.com/JN513/Risco-5 Cloning into 'Risco-5'... [Pipeline] sh + cd Risco-5 [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (IVerilog) [Pipeline] sh + mkdir -p build [Pipeline] sh + cp Risco-5/software/memory/add.hex Risco-5/software/memory/generic.hex [Pipeline] sh + /eda/oss-cad-suite/bin/iverilog -o build/soc_test.o -s soc_tb Risco-5/src/core/alu.v Risco-5/src/core/alu_control.v Risco-5/src/core/control_unit.v Risco-5/src/core/core.v Risco-5/src/core/csr_unit.v Risco-5/src/core/immediate_generator.v Risco-5/src/core/mdu.v Risco-5/src/core/mux.v Risco-5/src/core/pc.v Risco-5/src/core/registers.v Risco-5/src/peripheral/bus.v Risco-5/src/peripheral/fifo.v Risco-5/src/peripheral/gpio.v Risco-5/src/peripheral/gpios.v Risco-5/src/peripheral/leds.v Risco-5/src/peripheral/memory.v Risco-5/src/peripheral/pwm.v Risco-5/src/peripheral/soc.v Risco-5/src/peripheral/uart.v Risco-5/src/peripheral/uart_rx.v Risco-5/src/peripheral/uart_tx.v Risco-5/tests/soc_test.v [Pipeline] sh + /eda/oss-cad-suite/bin/vvp build/soc_test.o ERROR: Risco-5/src/peripheral/memory.v:35: $readmemh: Unable to open software/memory/generic.hex for reading. VCD info: dumpfile build/soc.vcd opened for output. Risco-5/tests/soc_test.v:42: $finish called at 3606 (1s) [Pipeline] sh + rm -f Risco-5/software/memory/generic.hex [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Síntese) [Pipeline] parallel [Pipeline] { (Branch: OSS-Cad-Suite) [Pipeline] { (Branch: Gowin) [Pipeline] { (Branch: Vivado) [Pipeline] stage [Pipeline] { (OSS-Cad-Suite) [Pipeline] stage [Pipeline] { (Gowin) [Pipeline] stage [Pipeline] { (Vivado) [Pipeline] stage [Pipeline] { (Yosys) [Pipeline] sh [Pipeline] sh + rm -rf Risco-5/impl/pnr [Pipeline] sh + cd Risco-5/fpga/nexys4_ddr + mkdir build + /eda/vivado/Vivado/2023.2/bin/vivado -mode batch -nolog -nojournal -source run.tcl + /eda/oss-cad-suite/bin/yosys -p read_verilog Risco-5/fpga/ecp5/*.v; read_verilog Risco-5/debug/reset.v; read_verilog Risco-5/src/core/*.v; read_verilog Risco-5/src/peripheral/*.v; synth_ecp5 -json ./build/out.json -abc9 /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2024 Claire Xenia Wolf <claire@yosyshq.com> | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.42+15 (git sha1 74a1dd99a, clang++ 14.0.0-1ubuntu1.1 -fPIC -Os) -- Running command ` read_verilog Risco-5/fpga/ecp5/*.v; read_verilog Risco-5/debug/reset.v; read_verilog Risco-5/src/core/*.v; read_verilog Risco-5/src/peripheral/*.v; synth_ecp5 -json ./build/out.json -abc9 ' -- 1. Executing Verilog-2005 frontend: Risco-5/fpga/ecp5/main.v Parsing Verilog input from `Risco-5/fpga/ecp5/main.v' to AST representation. Generating RTLIL representation for module `\top'. Successfully finished Verilog frontend. 2. Executing Verilog-2005 frontend: Risco-5/debug/reset.v Parsing Verilog input from `Risco-5/debug/reset.v' to AST representation. Generating RTLIL representation for module `\ResetBootSystem'. Successfully finished Verilog frontend. 3. Executing Verilog-2005 frontend: Risco-5/src/core/alu.v Parsing Verilog input from `Risco-5/src/core/alu.v' to AST representation. Generating RTLIL representation for module `\Alu'. Successfully finished Verilog frontend. 4. Executing Verilog-2005 frontend: Risco-5/src/core/alu_control.v Parsing Verilog input from `Risco-5/src/core/alu_control.v' to AST representation. Generating RTLIL representation for module `\ALU_Control'. Successfully finished Verilog frontend. 5. Executing Verilog-2005 frontend: Risco-5/src/core/control_unit.v Parsing Verilog input from `Risco-5/src/core/control_unit.v' to AST representation. Generating RTLIL representation for module `\Control_Unit'. Successfully finished Verilog frontend. 6. Executing Verilog-2005 frontend: Risco-5/src/core/core.v Parsing Verilog input from `Risco-5/src/core/core.v' to AST representation. Generating RTLIL representation for module `\Core'. Risco-5/src/core/core.v:164: Warning: Identifier `\pc_source' is implicitly declared. Successfully finished Verilog frontend. 7. Executing Verilog-2005 frontend: Risco-5/src/core/csr_unit.v Parsing Verilog input from `Risco-5/src/core/csr_unit.v' to AST representation. Generating RTLIL representation for module `\CSR_Unit'. Successfully finished Verilog frontend. 8. Executing Verilog-2005 frontend: Risco-5/src/core/immediate_generator.v Parsing Verilog input from `Risco-5/src/core/immediate_generator.v' to AST representation. Generating RTLIL representation for module `\Immediate_Generator'. Successfully finished Verilog frontend. 9. Executing Verilog-2005 frontend: Risco-5/src/core/mdu.v Parsing Verilog input from `Risco-5/src/core/mdu.v' to AST representation. Successfully finished Verilog frontend. 10. Executing Verilog-2005 frontend: Risco-5/src/core/mux.v Parsing Verilog input from `Risco-5/src/core/mux.v' to AST representation. Generating RTLIL representation for module `\MUX'. Successfully finished Verilog frontend. 11. Executing Verilog-2005 frontend: Risco-5/src/core/pc.v Parsing Verilog input from `Risco-5/src/core/pc.v' to AST representation. Generating RTLIL representation for module `\PC'. Successfully finished Verilog frontend. 12. Executing Verilog-2005 frontend: Risco-5/src/core/registers.v Parsing Verilog input from `Risco-5/src/core/registers.v' to AST representation. Generating RTLIL representation for module `\Registers'. Successfully finished Verilog frontend. 13. Executing Verilog-2005 frontend: Risco-5/src/peripheral/bus.v Parsing Verilog input from `Risco-5/src/peripheral/bus.v' to AST representation. Generating RTLIL representation for module `\BUS'. Successfully finished Verilog frontend. 14. Executing Verilog-2005 frontend: Risco-5/src/peripheral/fifo.v Parsing Verilog input from `Risco-5/src/peripheral/fifo.v' to AST representation. Generating RTLIL representation for module `\FIFO'. Successfully finished Verilog frontend. 15. Executing Verilog-2005 frontend: Risco-5/src/peripheral/gpio.v Parsing Verilog input from `Risco-5/src/peripheral/gpio.v' to AST representation. Warning: Yosys has only limited support for tri-state logic at the moment. (Risco-5/src/peripheral/gpio.v:9) Generating RTLIL representation for module `\GPIO'. Successfully finished Verilog frontend. 16. Executing Verilog-2005 frontend: Risco-5/src/peripheral/gpios.v Parsing Verilog input from `Risco-5/src/peripheral/gpios.v' to AST representation. Generating RTLIL representation for module `\GPIOS'. Successfully finished Verilog frontend. 17. Executing Verilog-2005 frontend: Risco-5/src/peripheral/leds.v Parsing Verilog input from `Risco-5/src/peripheral/leds.v' to AST representation. Generating RTLIL representation for module `\LEDs'. Successfully finished Verilog frontend. 18. Executing Verilog-2005 frontend: Risco-5/src/peripheral/memory.v Parsing Verilog input from `Risco-5/src/peripheral/memory.v' to AST representation. Generating RTLIL representation for module `\Memory'. Successfully finished Verilog frontend. 19. Executing Verilog-2005 frontend: Risco-5/src/peripheral/pwm.v Parsing Verilog input from `Risco-5/src/peripheral/pwm.v' to AST representation. Generating RTLIL representation for module `\PWM'. Successfully finished Verilog frontend. 20. Executing Verilog-2005 frontend: Risco-5/src/peripheral/soc.v Parsing Verilog input from `Risco-5/src/peripheral/soc.v' to AST representation. Generating RTLIL representation for module `\Risco_5_SOC'. Successfully finished Verilog frontend. 21. Executing Verilog-2005 frontend: Risco-5/src/peripheral/uart.v Parsing Verilog input from `Risco-5/src/peripheral/uart.v' to AST representation. Generating RTLIL representation for module `\UART'. Successfully finished Verilog frontend. 22. Executing Verilog-2005 frontend: Risco-5/src/peripheral/uart_rx.v Parsing Verilog input from `Risco-5/src/peripheral/uart_rx.v' to AST representation. Generating RTLIL representation for module `\uart_tool_rx'. Successfully finished Verilog frontend. 23. Executing Verilog-2005 frontend: Risco-5/src/peripheral/uart_tx.v Parsing Verilog input from `Risco-5/src/peripheral/uart_tx.v' to AST representation. Generating RTLIL representation for module `\uart_tool_tx'. Successfully finished Verilog frontend. 24. Executing SYNTH_ECP5 pass. 24.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v' to AST representation. Generating RTLIL representation for module `\LUT4'. Generating RTLIL representation for module `\$__ABC9_LUT5'. Generating RTLIL representation for module `\$__ABC9_LUT6'. Generating RTLIL representation for module `\$__ABC9_LUT7'. Generating RTLIL representation for module `\L6MUX21'. Generating RTLIL representation for module `\CCU2C'. Generating RTLIL representation for module `\TRELLIS_RAM16X2'. Generating RTLIL representation for module `\PFUMX'. Generating RTLIL representation for module `\TRELLIS_DPR16X4'. Generating RTLIL representation for module `\DPR16X4C'. Generating RTLIL representation for module `\LUT2'. Generating RTLIL representation for module `\TRELLIS_FF'. Generating RTLIL representation for module `\TRELLIS_IO'. Generating RTLIL representation for module `\INV'. Generating RTLIL representation for module `\TRELLIS_COMB'. Generating RTLIL representation for module `\DP16KD'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Successfully finished Verilog frontend. 24.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_bb.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_bb.v' to AST representation. Generating RTLIL representation for module `\MULT18X18D'. Generating RTLIL representation for module `\ALU54B'. Generating RTLIL representation for module `\EHXPLLL'. Generating RTLIL representation for module `\DTR'. Generating RTLIL representation for module `\OSCG'. Generating RTLIL representation for module `\USRMCLK'. Generating RTLIL representation for module `\JTAGG'. Generating RTLIL representation for module `\DELAYF'. Generating RTLIL representation for module `\DELAYG'. Generating RTLIL representation for module `\IDDRX1F'. Generating RTLIL representation for module `\IDDRX2F'. Generating RTLIL representation for module `\IDDR71B'. Generating RTLIL representation for module `\IDDRX2DQA'. Generating RTLIL representation for module `\ODDRX1F'. Generating RTLIL representation for module `\ODDRX2F'. Generating RTLIL representation for module `\ODDR71B'. Generating RTLIL representation for module `\OSHX2A'. Generating RTLIL representation for module `\ODDRX2DQA'. Generating RTLIL representation for module `\ODDRX2DQSB'. Generating RTLIL representation for module `\TSHX2DQA'. Generating RTLIL representation for module `\TSHX2DQSA'. Generating RTLIL representation for module `\DQSBUFM'. Generating RTLIL representation for module `\DDRDLLA'. Generating RTLIL representation for module `\DLLDELD'. Generating RTLIL representation for module `\CLKDIVF'. Generating RTLIL representation for module `\ECLKSYNCB'. Generating RTLIL representation for module `\ECLKBRIDGECS'. Generating RTLIL representation for module `\DCCA'. Generating RTLIL representation for module `\DCSC'. Generating RTLIL representation for module `\DCUA'. Generating RTLIL representation for module `\EXTREFB'. Generating RTLIL representation for module `\PCSCLKDIV'. Generating RTLIL representation for module `\PUR'. Generating RTLIL representation for module `\GSR'. Generating RTLIL representation for module `\SGSR'. Generating RTLIL representation for module `\PDPW16KD'. Successfully finished Verilog frontend. 24.3. Executing HIERARCHY pass (managing design hierarchy). 24.3.1. Finding top of design hierarchy.. root of 0 design levels: uart_tool_tx root of 0 design levels: uart_tool_rx root of 1 design levels: UART root of 2 design levels: Risco_5_SOC root of 0 design levels: PWM root of 0 design levels: Memory root of 0 design levels: LEDs root of 1 design levels: GPIOS root of 0 design levels: GPIO root of 0 design levels: FIFO root of 0 design levels: BUS root of 0 design levels: Registers root of 0 design levels: PC root of 0 design levels: MUX root of 0 design levels: Immediate_Generator root of 0 design levels: CSR_Unit root of 1 design levels: Core root of 0 design levels: Control_Unit root of 0 design levels: ALU_Control root of 0 design levels: Alu root of 0 design levels: ResetBootSystem root of 3 design levels: top Automatically selected top as design top module. 24.3.2. Analyzing design hierarchy.. Top module: \top Used module: \Risco_5_SOC Used module: \GPIOS Used module: \GPIO Used module: \PWM Used module: \UART Used module: \uart_tool_tx Used module: \uart_tool_rx Used module: \FIFO Used module: \LEDs Used module: \BUS Used module: \Memory Used module: \Core Used module: \CSR_Unit Used module: \Immediate_Generator Used module: \Alu Used module: \ALU_Control Used module: \Control_Unit Used module: \Registers Used module: \MUX Used module: \PC Used module: \ResetBootSystem Parameter \CLOCK_FREQ = 25000000 Parameter \BIT_RATE = 115200 Parameter \MEMORY_SIZE = 2048 Parameter \MEMORY_FILE = 88'0111000001110010011011110110011101110010011000010110110100101110011010000110010101111000 Parameter \GPIO_WIDHT = 6 Parameter \UART_BUFFER_SIZE = 16 24.3.3. Executing AST frontend in derive mode using pre-parsed AST for module `\Risco_5_SOC'. Parameter \CLOCK_FREQ = 25000000 Parameter \BIT_RATE = 115200 Parameter \MEMORY_SIZE = 2048 Parameter \MEMORY_FILE = 88'0111000001110010011011110110011101110010011000010110110100101110011010000110010101111000 Parameter \GPIO_WIDHT = 6 Parameter \UART_BUFFER_SIZE = 16 Generating RTLIL representation for module `$paramod$383aded2cdc2965dfd3cb4bb8d57b3da5a93863f\Risco_5_SOC'. Parameter \CYCLES = 20 24.3.4. Executing AST frontend in derive mode using pre-parsed AST for module `\ResetBootSystem'. Parameter \CYCLES = 20 Generating RTLIL representation for module `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100'. Parameter \WIDHT = 5 24.3.5. Executing AST frontend in derive mode using pre-parsed AST for module `\GPIOS'. Parameter \WIDHT = 5 Generating RTLIL representation for module `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000101'. Parameter \CLK_FREQ = 25000000 Parameter \BIT_RATE = 9600 Parameter \BUFFER_SIZE = 8 24.3.6. Executing AST frontend in derive mode using pre-parsed AST for module `\UART'. Parameter \CLK_FREQ = 25000000 Parameter \BIT_RATE = 9600 Parameter \BUFFER_SIZE = 8 Generating RTLIL representation for module `$paramod$65634474087d1ba2b03796f9a45556e4bd507a57\UART'. Parameter \MEMORY_FILE = { } Parameter \MEMORY_SIZE = 4096 24.3.7. Executing AST frontend in derive mode using pre-parsed AST for module `\Memory'. Parameter \MEMORY_FILE = { } Parameter \MEMORY_SIZE = 4096 Generating RTLIL representation for module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'. Parameter \BOOT_ADDRESS = 0 24.3.8. Executing AST frontend in derive mode using pre-parsed AST for module `\Core'. Parameter \BOOT_ADDRESS = 0 Generating RTLIL representation for module `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000'. Risco-5/src/core/core.v:164: Warning: Identifier `\pc_source' is implicitly declared. Reprocessing module GPIOS because instantiated module PWM has become available. Generating RTLIL representation for module `\GPIOS'. Parameter \BIT_RATE = 9600 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 24.3.9. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tool_tx'. Parameter \BIT_RATE = 9600 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 Generating RTLIL representation for module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx'. Parameter \BIT_RATE = 9600 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 24.3.10. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tool_rx'. Parameter \BIT_RATE = 9600 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 Generating RTLIL representation for module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx'. Parameter \DEPTH = 8 Parameter \WIDTH = 8 24.3.11. Executing AST frontend in derive mode using pre-parsed AST for module `\FIFO'. Parameter \DEPTH = 8 Parameter \WIDTH = 8 Generating RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'. Parameter \DEPTH = 8 Parameter \WIDTH = 8 Found cached RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'. 24.3.12. Analyzing design hierarchy.. Top module: \top Used module: $paramod$383aded2cdc2965dfd3cb4bb8d57b3da5a93863f\Risco_5_SOC Used module: \GPIOS Used module: \GPIO Used module: \PWM Used module: \UART Used module: $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx Used module: $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx Used module: $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO Used module: \LEDs Used module: \BUS Used module: \Memory Used module: \Core Used module: \CSR_Unit Used module: \Immediate_Generator Used module: \Alu Used module: \ALU_Control Used module: \Control_Unit Used module: \Registers Used module: \MUX Used module: \PC Used module: $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100 Parameter \WIDHT = 6 24.3.13. Executing AST frontend in derive mode using pre-parsed AST for module `\GPIOS'. Parameter \WIDHT = 6 Generating RTLIL representation for module `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110'. Parameter \CLK_FREQ = 25000000 Parameter \BIT_RATE = 115200 Parameter \BUFFER_SIZE = 16 24.3.14. Executing AST frontend in derive mode using pre-parsed AST for module `\UART'. Parameter \CLK_FREQ = 25000000 Parameter \BIT_RATE = 115200 Parameter \BUFFER_SIZE = 16 Generating RTLIL representation for module `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART'. Parameter \MEMORY_FILE = 88'0111000001110010011011110110011101110010011000010110110100101110011010000110010101111000 Parameter \MEMORY_SIZE = 2048 24.3.15. Executing AST frontend in derive mode using pre-parsed AST for module `\Memory'. Risco-5/src/peripheral/memory.v:35: ERROR: Can not open file `program.hex` for \$readmemh. [Pipeline] sh + mkdir -p Risco-5/impl/pnr [Pipeline] } [Pipeline] // stage [Pipeline] sh + cd Risco-5/fpga/tangnano20k/ + /eda/gowin/IDE/bin/gw_sh run.tcl *** GOWIN Tcl Command Line Console *** current device: GW2AR-18C GW2AR-LV18QN88C8/I7 add new file: "pinout.cst" add new file: "top.sdc" add new file: "main.v" add new file: "../../debug/reset.v" add new file: "../../src/core/alu_control.v" add new file: "../../src/core/alu.v" add new file: "../../src/core/control_unit.v" add new file: "../../src/core/core.v" add new file: "../../src/core/immediate_generator.v" add new file: "../../src/core/mux.v" add new file: "../../src/core/pc.v" add new file: "../../src/core/registers.v" add new file: "../../src/core/csr_unit.v" add new file: "../../src/core/mdu.v" add new file: "../../src/peripheral/bus.v" add new file: "../../src/peripheral/gpio.v" add new file: "../../src/peripheral/gpios.v" add new file: "../../src/peripheral/leds.v" add new file: "../../src/peripheral/memory.v" add new file: "../../src/peripheral/soc.v" add new file: "../../src/peripheral/uart_rx.v" add new file: "../../src/peripheral/uart_tx.v" add new file: "../../src/peripheral/uart.v" add new file: "../../src/peripheral/fifo.v" add new file: "../../src/peripheral/pwm.v" GowinSynthesis start Running parser ... Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/main.v' Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/debug/reset.v' Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v' Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu.v' Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v' Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v' Undeclared symbol 'pc_source', assumed default net type 'wire'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":164) Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/immediate_generator.v' Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/mux.v' Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/pc.v' Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/registers.v' Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/csr_unit.v' Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/mdu.v' Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/bus.v' Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpio.v' Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v' Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/leds.v' Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v' WARN (EX3012) : Empty statement in sequential block("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v":54) Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v' Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_rx.v' Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_tx.v' Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart.v' Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/fifo.v' Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/pwm.v' WARN (EX3073) : Port 'resetn_o' remains unconnected for this instance("/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/main.v":18) Compiling module 'top'("/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/main.v":1) Compiling module 'ResetBootSystem'("/var/lib/jenkins/workspace/Risco_5/Risco-5/debug/reset.v":1) WARN (EX3791) : Expression size 7 truncated to fit in target size 6("/var/lib/jenkins/workspace/Risco_5/Risco-5/debug/reset.v":37) Compiling module 'Risco_5_SOC(CLOCK_FREQ=27000000,BIT_RATE=115200,MEMORY_SIZE=2048,MEMORY_FILE="../../software/memory/teste_uart_fpga.hex",UART_BUFFER_SIZE=16)'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":1) Compiling module 'Core(BOOT_ADDRESS=32'b00000000000000000000000000000000)'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":1) Compiling module 'PC'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/pc.v":1) Compiling module 'MUX'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/mux.v":1) Compiling module 'Registers'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/registers.v":1) Compiling module 'Control_Unit'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v":1) WARN (EX3791) : Expression size 7 truncated to fit in target size 3("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v":536) WARN (EX3791) : Expression size 7 truncated to fit in target size 3("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v":543) WARN (EX3791) : Expression size 7 truncated to fit in target size 3("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v":556) WARN (EX3791) : Expression size 7 truncated to fit in target size 3("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v":563) Compiling module 'ALU_Control'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v":1) Compiling module 'Alu'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu.v":1) Compiling module 'Immediate_Generator'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/immediate_generator.v":1) Compiling module 'CSR_Unit'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/csr_unit.v":1) Compiling module 'Memory(MEMORY_FILE="../../software/memory/teste_uart_fpga.hex",MEMORY_SIZE=2048)'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v":1) Extracting RAM for identifier 'memory'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v":16) Compiling module 'BUS'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/bus.v":1) Compiling module 'LEDs'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/leds.v":1) Compiling module 'UART(CLK_FREQ=27000000,BIT_RATE=115200,BUFFER_SIZE=16)'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart.v":1) Compiling module 'FIFO(DEPTH=16)'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/fifo.v":1) Extracting RAM for identifier 'memory'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/fifo.v":16) WARN (EX3791) : Expression size 7 truncated to fit in target size 6("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/fifo.v":40) Compiling module 'uart_tool_rx(BIT_RATE=115200,CLK_HZ=27000000)'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_rx.v":10) [Pipeline] stage [Pipeline] { (NextPNR) Stage "NextPNR" skipped due to earlier failure(s) Compiling module 'uart_tool_tx(BIT_RATE=115200,CLK_HZ=27000000)'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_tx.v":10) Compiling module 'GPIOS(WIDHT=5)'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":1) Compiling module 'GPIO'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpio.v":1) Compiling module 'PWM'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/pwm.v":1) WARN (EX2565) : Input 'halt' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":43) WARN (EX2565) : Input 'interruption_request_external' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":43) WARN (EX2565) : Input 'interruption_request_timer' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":43) WARN (EX2565) : Input 'interruption_request_software' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":43) WARN (EX2565) : Input 'interruption_request_fast[15]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":43) WARN (EX2565) : Input 'interruption_request_fast[14]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":43) WARN (EX2565) : Input 'interruption_request_fast[13]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":43) WARN (EX2565) : Input 'interruption_request_fast[12]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":43) WARN (EX2565) : Input 'interruption_request_fast[11]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":43) WARN (EX2565) : Input 'interruption_request_fast[10]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":43) WARN (EX2565) : Input 'interruption_request_fast[9]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":43) WARN (EX2565) : Input 'interruption_request_fast[8]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":43) WARN (EX2565) : Input 'interruption_request_fast[7]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":43) WARN (EX2565) : Input 'interruption_request_fast[6]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":43) WARN (EX2565) : Input 'interruption_request_fast[5]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":43) WARN (EX2565) : Input 'interruption_request_fast[4]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":43) WARN (EX2565) : Input 'interruption_request_fast[3]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":43) WARN (EX2565) : Input 'interruption_request_fast[2]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":43) WARN (EX2565) : Input 'interruption_request_fast[1]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":43) WARN (EX2565) : Input 'interruption_request_fast[0]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":43) NOTE (EX0101) : Current top module is "top" [5%] Running netlist conversion ... WARN (CV0016) : Input reset is unused("/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/main.v":3) [Pipeline] } Running device independent optimization ... [Pipeline] // stage [10%] Optimizing Phase 0 completed [15%] Optimizing Phase 1 completed [25%] Optimizing Phase 2 completed Running inference ... [30%] Inferring Phase 0 completed [40%] Inferring Phase 1 completed [50%] Inferring Phase 2 completed [55%] Inferring Phase 3 completed Running technical mapping ... [Pipeline] stage [Pipeline] { (ECPPACK) Stage "ECPPACK" skipped due to earlier failure(s) [Pipeline] } [Pipeline] // stage [Pipeline] } [60%] Tech-Mapping Phase 0 completed [65%] Tech-Mapping Phase 1 completed [75%] Tech-Mapping Phase 2 completed [Pipeline] // stage [Pipeline] } Failed in branch OSS-Cad-Suite Sending interrupt signal to process Sending interrupt signal to process Terminated script returned exit code 143 [Pipeline] } [Pipeline] // stage Terminated script returned exit code 143 [Pipeline] } Failed in branch Gowin [Pipeline] } [Pipeline] // stage [Pipeline] } Failed in branch Vivado [Pipeline] // parallel [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (FPGA Flash) Stage "FPGA Flash" skipped due to earlier failure(s) [Pipeline] parallel [Pipeline] { (Branch: openFPGAloader ECP5) [Pipeline] { (Branch: openFPGAloader Tangnano 20k) [Pipeline] { (Branch: openFPGAloader Nexys 4 DDR) [Pipeline] stage [Pipeline] { (openFPGAloader ECP5) [Pipeline] stage [Pipeline] { (openFPGAloader Tangnano 20k) [Pipeline] stage [Pipeline] { (openFPGAloader Nexys 4 DDR) Stage "openFPGAloader ECP5" skipped due to earlier failure(s) [Pipeline] } Stage "openFPGAloader Tangnano 20k" skipped due to earlier failure(s) [Pipeline] } Stage "openFPGAloader Nexys 4 DDR" skipped due to earlier failure(s) [Pipeline] } [Pipeline] // stage [Pipeline] // stage [Pipeline] // stage [Pipeline] } Failed in branch openFPGAloader ECP5 [Pipeline] } Failed in branch openFPGAloader Tangnano 20k [Pipeline] } Failed in branch openFPGAloader Nexys 4 DDR [Pipeline] // parallel [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Testes) Stage "Testes" skipped due to earlier failure(s) [Pipeline] parallel [Pipeline] { (Branch: ECP5 - Testes) [Pipeline] { (Branch: TangNano - Testes) [Pipeline] { (Branch: Nexys 4 - Testes) [Pipeline] stage [Pipeline] { (ECP5 - Testes) [Pipeline] stage [Pipeline] { (TangNano - Testes) [Pipeline] stage [Pipeline] { (Nexys 4 - Testes) Stage "ECP5 - Testes" skipped due to earlier failure(s) [Pipeline] } Stage "TangNano - Testes" skipped due to earlier failure(s) [Pipeline] } Stage "Nexys 4 - Testes" skipped due to earlier failure(s) [Pipeline] } [Pipeline] // stage [Pipeline] // stage [Pipeline] // stage [Pipeline] } Failed in branch ECP5 - Testes [Pipeline] } Failed in branch TangNano - Testes [Pipeline] } Failed in branch Nexys 4 - Testes [Pipeline] // parallel [Pipeline] } [Pipeline] // stage [Pipeline] } [Pipeline] // node [Pipeline] End of Pipeline ERROR: script returned exit code 1 Finished: FAILURE