Console Output
+ cd Risco-5/fpga/nexys4_ddr
+ mkdir build
+ /eda/vivado/Vivado/2023.2/bin/vivado -mode batch -nolog -nojournal -source run.tcl
****** Vivado v2023.2 (64-bit)
**** SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023
**** IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
**** SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023
** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
** Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
source run.tcl
# read_verilog "main.v"
read_verilog: Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1315.121 ; gain = 0.023 ; free physical = 2076 ; free virtual = 25540
# read_verilog ../../debug/reset.v
# read_verilog ../../src/core/alu_control.v
# read_verilog ../../src/core/alu.v
# read_verilog ../../src/core/control_unit.v
# read_verilog ../../src/core/core.v
# read_verilog ../../src/core/immediate_generator.v
# read_verilog ../../src/core/mux.v
# read_verilog ../../src/core/pc.v
# read_verilog ../../src/core/registers.v
# read_verilog ../../src/core/csr_unit.v
# read_verilog ../../src/core/mdu.v
# read_verilog ../../src/peripheral/bus.v
# read_verilog ../../src/peripheral/gpio.v
# read_verilog ../../src/peripheral/gpios.v
# read_verilog ../../src/peripheral/leds.v
# read_verilog ../../src/peripheral/memory.v
# read_verilog ../../src/peripheral/soc.v
# read_verilog ../../src/peripheral/uart_rx.v
# read_verilog ../../src/peripheral/uart_tx.v
# read_verilog ../../src/peripheral/uart.v
# read_verilog ../../src/peripheral/fifo.v
# read_verilog ../../src/peripheral/pwm.v
# read_xdc "digilent_nexys4_ddr.xdc"
# set_property PROCESSING_ORDER EARLY [get_files digilent_nexys4_ddr.xdc]
# synth_design -top "top" -part "xc7a100tcsg324-1"
Command: synth_design -top top -part xc7a100tcsg324-1
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a100t'
INFO: [Device 21-403] Loading part xc7a100tcsg324-1
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
INFO: [Synth 8-7075] Helper process launched with PID 272606
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2028.844 ; gain = 404.684 ; free physical = 941 ; free virtual = 24413
---------------------------------------------------------------------------------
INFO: [Synth 8-11241] undeclared symbol 'pc_source', assumed default net type 'wire' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:168]
WARNING: [Synth 8-9400] empty statement in sequential block [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v:54]
INFO: [Synth 8-6157] synthesizing module 'top' [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/main.v:1]
INFO: [Synth 8-6157] synthesizing module 'ResetBootSystem' [/var/lib/jenkins/workspace/Risco_5/Risco-5/debug/reset.v:1]
Parameter CYCLES bound to: 20 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'ResetBootSystem' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/debug/reset.v:1]
WARNING: [Synth 8-7071] port 'resetn_o' of module 'ResetBootSystem' is unconnected for instance 'ResetBootSystem' [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/main.v:24]
WARNING: [Synth 8-7023] instance 'ResetBootSystem' of module 'ResetBootSystem' has 3 connections declared, but only 2 given [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/main.v:24]
INFO: [Synth 8-6157] synthesizing module 'Risco_5_SOC' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:1]
Parameter CLOCK_FREQ bound to: 50000000 - type: integer
Parameter BIT_RATE bound to: 115200 - type: integer
Parameter MEMORY_SIZE bound to: 2048 - type: integer
Parameter MEMORY_FILE bound to: ../../software/memory/teste_uart_fpga.hex - type: string
Parameter GPIO_WIDHT bound to: 8 - type: integer
Parameter UART_BUFFER_SIZE bound to: 16 - type: integer
INFO: [Synth 8-6157] synthesizing module 'Core' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:2]
Parameter BOOT_ADDRESS bound to: 0 - type: integer
INFO: [Synth 8-6157] synthesizing module 'PC' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/pc.v:1]
INFO: [Synth 8-6155] done synthesizing module 'PC' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/pc.v:1]
INFO: [Synth 8-6157] synthesizing module 'MUX' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/mux.v:1]
INFO: [Synth 8-6155] done synthesizing module 'MUX' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/mux.v:1]
INFO: [Synth 8-6157] synthesizing module 'Registers' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/registers.v:1]
INFO: [Synth 8-6155] done synthesizing module 'Registers' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/registers.v:1]
INFO: [Synth 8-6157] synthesizing module 'Control_Unit' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v:2]
INFO: [Synth 8-155] case statement is not full and has no default [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v:166]
INFO: [Synth 8-155] case statement is not full and has no default [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v:363]
INFO: [Synth 8-6155] done synthesizing module 'Control_Unit' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v:2]
INFO: [Synth 8-6157] synthesizing module 'ALU_Control' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v:1]
INFO: [Synth 8-226] default block is never used [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v:34]
INFO: [Synth 8-155] case statement is not full and has no default [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v:11]
INFO: [Synth 8-6155] done synthesizing module 'ALU_Control' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v:1]
INFO: [Synth 8-6157] synthesizing module 'Alu' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu.v:1]
INFO: [Synth 8-6155] done synthesizing module 'Alu' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu.v:1]
INFO: [Synth 8-6157] synthesizing module 'Immediate_Generator' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/immediate_generator.v:1]
INFO: [Synth 8-6155] done synthesizing module 'Immediate_Generator' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/immediate_generator.v:1]
INFO: [Synth 8-6157] synthesizing module 'CSR_Unit' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/csr_unit.v:1]
INFO: [Synth 8-155] case statement is not full and has no default [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/csr_unit.v:117]
INFO: [Synth 8-6155] done synthesizing module 'CSR_Unit' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/csr_unit.v:1]
INFO: [Synth 8-6155] done synthesizing module 'Core' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:2]
WARNING: [Synth 8-7071] port 'halt' of module 'Core' is unconnected for instance 'Core' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:33]
WARNING: [Synth 8-7071] port 'interruption_request_external' of module 'Core' is unconnected for instance 'Core' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:33]
WARNING: [Synth 8-7071] port 'interruption_request_timer' of module 'Core' is unconnected for instance 'Core' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:33]
WARNING: [Synth 8-7071] port 'interruption_request_software' of module 'Core' is unconnected for instance 'Core' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:33]
WARNING: [Synth 8-7071] port 'interruption_request_fast' of module 'Core' is unconnected for instance 'Core' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:33]
WARNING: [Synth 8-7023] instance 'Core' of module 'Core' has 14 connections declared, but only 9 given [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:33]
INFO: [Synth 8-6157] synthesizing module 'Memory' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v:1]
Parameter MEMORY_FILE bound to: ../../software/memory/teste_uart_fpga.hex - type: string
Parameter MEMORY_SIZE bound to: 2048 - type: integer
INFO: [Synth 8-3876] $readmem data file '../../software/memory/teste_uart_fpga.hex' is read successfully [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v:35]
INFO: [Synth 8-6155] done synthesizing module 'Memory' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v:1]
INFO: [Synth 8-6157] synthesizing module 'BUS' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/bus.v:1]
INFO: [Synth 8-6155] done synthesizing module 'BUS' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/bus.v:1]
INFO: [Synth 8-6157] synthesizing module 'LEDs' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/leds.v:1]
INFO: [Synth 8-6155] done synthesizing module 'LEDs' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/leds.v:1]
INFO: [Synth 8-6157] synthesizing module 'UART' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart.v:1]
Parameter CLK_FREQ bound to: 50000000 - type: integer
Parameter BIT_RATE bound to: 115200 - type: integer
Parameter BUFFER_SIZE bound to: 16 - type: integer
INFO: [Synth 8-6157] synthesizing module 'FIFO' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/fifo.v:1]
Parameter DEPTH bound to: 16 - type: integer
Parameter WIDTH bound to: 8 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'FIFO' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/fifo.v:1]
INFO: [Synth 8-6157] synthesizing module 'uart_tool_rx' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_rx.v:10]
Parameter BIT_RATE bound to: 115200 - type: integer
Parameter CLK_HZ bound to: 50000000 - type: integer
Parameter PAYLOAD_BITS bound to: 8 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'uart_tool_rx' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_rx.v:10]
INFO: [Synth 8-6157] synthesizing module 'uart_tool_tx' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_tx.v:10]
Parameter BIT_RATE bound to: 115200 - type: integer
Parameter CLK_HZ bound to: 50000000 - type: integer
Parameter PAYLOAD_BITS bound to: 8 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'uart_tool_tx' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_tx.v:10]
INFO: [Synth 8-6155] done synthesizing module 'UART' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart.v:1]
INFO: [Synth 8-6157] synthesizing module 'GPIOS' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v:1]
Parameter WIDHT bound to: 8 - type: integer
INFO: [Synth 8-6157] synthesizing module 'GPIO' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpio.v:1]
INFO: [Synth 8-6155] done synthesizing module 'GPIO' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpio.v:1]
INFO: [Synth 8-6157] synthesizing module 'PWM' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/pwm.v:1]
INFO: [Synth 8-6155] done synthesizing module 'PWM' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/pwm.v:1]
INFO: [Synth 8-155] case statement is not full and has no default [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v:66]
INFO: [Synth 8-6155] done synthesizing module 'GPIOS' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v:1]
INFO: [Synth 8-6155] done synthesizing module 'Risco_5_SOC' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:1]
INFO: [Synth 8-6155] done synthesizing module 'top' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/main.v:1]
WARNING: [Synth 8-3848] Net mdu_done in module/entity Core does not have driver. [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:55]
WARNING: [Synth 8-6014] Unused sequential element tx_fifo_read_reg was removed. [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart.v:160]
WARNING: [Synth 8-7129] Port address[31] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[30] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[29] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[28] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[27] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[26] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[25] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[24] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[23] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[22] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[21] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[20] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[19] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[18] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[17] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[16] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[15] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[14] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[13] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[12] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[11] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[10] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[9] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[8] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[31] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[30] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[29] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[28] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[27] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[26] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[25] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[24] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[23] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[22] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[21] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[20] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[19] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[18] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[17] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[31] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[30] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[29] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[28] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[27] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[26] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[25] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[24] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[23] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[22] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[21] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[20] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[19] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[18] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[17] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[16] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[15] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[14] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[13] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[12] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[11] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[10] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[9] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[8] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[7] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[6] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[5] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[1] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[0] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[31] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[30] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[29] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[28] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[27] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[26] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[25] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[24] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[23] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[22] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[21] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[20] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[19] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[18] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[17] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[16] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[15] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[14] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[13] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[12] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[11] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[10] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[9] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[8] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[7] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[6] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[5] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[4] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[3] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[2] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[1] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[0] in module LEDs is either unconnected or has no load
INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
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Finished RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2117.812 ; gain = 493.652 ; free physical = 836 ; free virtual = 24309
---------------------------------------------------------------------------------
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Start Handling Custom Attributes
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Finished Handling Custom Attributes : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2135.625 ; gain = 511.465 ; free physical = 833 ; free virtual = 24306
---------------------------------------------------------------------------------
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Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2135.625 ; gain = 511.465 ; free physical = 833 ; free virtual = 24306
---------------------------------------------------------------------------------
Netlist sorting complete. Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2135.625 ; gain = 0.000 ; free physical = 828 ; free virtual = 24301
INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints
Initializing timing engine
Parsing XDC File [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc]
Finished Parsing XDC File [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc]
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Completed Processing XDC Constraints
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2283.375 ; gain = 0.000 ; free physical = 768 ; free virtual = 24241
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2283.410 ; gain = 0.000 ; free physical = 767 ; free virtual = 24240
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 2283.410 ; gain = 659.250 ; free physical = 755 ; free virtual = 24231
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7a100tcsg324-1
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 2283.410 ; gain = 659.250 ; free physical = 755 ; free virtual = 24231
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 2283.410 ; gain = 659.250 ; free physical = 755 ; free virtual = 24231
---------------------------------------------------------------------------------
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'ResetBootSystem'
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'Control_Unit'
INFO: [Synth 8-802] inferred FSM for state register 'fsm_state_reg' in module 'uart_tool_rx'
INFO: [Synth 8-802] inferred FSM for state register 'fsm_state_reg' in module 'uart_tool_tx'
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'UART'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
RESET_COUNTER | 00 | 01
IDLE | 01 | 10
INIT | 10 | 00
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'ResetBootSystem'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
FETCH | 00000000000000000000000000000000000000000000001 | 000000
VALIDATE_FETCH | 00000000000000000000000000000000000000000000010 | 101110
DECODE | 00000000000000000000000000000000000000000000100 | 000001
MEMADR | 00000000000000000000000000000000000000000001000 | 000010
MEMREAD_UNALIGNED | 00000000000000000000000000000000000000000010000 | 010110
LOAD_FIRST_BLOCK | 00000000000000000000000000000000000000000100000 | 010000
SAVE_FIRST_BLOCK | 00000000000000000000000000000000000000001000000 | 010001
CALC_NEXT_ADDRESS | 00000000000000000000000000000000000000010000000 | 010010
READ_SECOND_BLOCK | 00000000000000000000000000000000000000100000000 | 010011
LOAD_SECOND_BLOCK | 00000000000000000000000000000000000001000000000 | 010100
MERGE_BLOCKS | 00000000000000000000000000000000000010000000000 | 010101
FILTER_ALU_WB | 00000000000000000000000000000000000100000000000 | 010111
MEMREAD | 00000000000000000000000000000000001000000000000 | 000011
MEMWB | 00000000000000000000000000000000010000000000000 | 000100
MEMWRITE_UNALIGNED | 00000000000000000000000000000000100000000000000 | 011000
GEN_FIRST_BLOCK_PART_1 | 00000000000000000000000000000001000000000000000 | 011001
GEN_FIRST_BLOCK_PART_2 | 00000000000000000000000000000010000000000000000 | 011010
GEN_SECOND_BLOCK_PART_1 | 00000000000000000000000000000100000000000000000 | 011011
GEN_SECOND_BLOCK_PART_2 | 00000000000000000000000000001000000000000000000 | 011100
MERGE_WRITE_BLOCKS | 00000000000000000000000000010000000000000000000 | 011101
SWAP_VALUE_DIRECTION | 00000000000000000000000000100000000000000000000 | 011110
CLEAR_VALUE_HALF_BYTE_ONE_BLOCK | 00000000000000000000000001000000000000000000000 | 100010
CLEAR_VALUE_HALF_BYTE_ONE_BLOCK_2 | 00000000000000000000000010000000000000000000000 | 100011
CLEAR_VALUE_HALF_BYTE_ONE_BLOCK_3 | 00000000000000000000000100000000000000000000000 | 100100
CLEAR_VALUE | 00000000000000000000001000000000000000000000000 | 011111
MERGE_WRITE_VALUE_1 | 00000000000000000000010000000000000000000000000 | 100000
WRITE_VALUE_1 | 00000000000000000000100000000000000000000000000 | 100001
CALC_SECOND_BLOCK_ADDRESS_TO_WRITE | 00000000000000000001000000000000000000000000000 | 100101
READ_SECOND_BLOCK_TO_WRITE | 00000000000000000010000000000000000000000000000 | 100110
LOAD_SECOND_BLOCK_TO_WRITE | 00000000000000000100000000000000000000000000000 | 100111
LOAD_SECOND_BLOCK_TO_WRITE_2 | 00000000000000001000000000000000000000000000000 | 101000
SWAP_VALUE_DIRECTION_2 | 00000000000000010000000000000000000000000000000 | 101001
CLEAR_VALUE_PART_2 | 00000000000000100000000000000000000000000000000 | 101010
CLEAR_VALUE_PART_2_1 | 00000000000001000000000000000000000000000000000 | 101011
MERGE_WRITE_VALUE_2 | 00000000000010000000000000000000000000000000000 | 101100
WRITE_VALUE_2 | 00000000000100000000000000000000000000000000000 | 101101
MEMWRITE | 00000000001000000000000000000000000000000000000 | 000101
EXECUTER | 00000000010000000000000000000000000000000000000 | 000110
EXECUTEI | 00000000100000000000000000000000000000000000000 | 001000
JAL | 00000001000000000000000000000000000000000000000 | 001001
BRANCH | 00000010000000000000000000000000000000000000000 | 001010
AUIPC | 00000100000000000000000000000000000000000000000 | 001100
LUI | 00001000000000000000000000000000000000000000000 | 001101
JALR_PC | 00010000000000000000000000000000000000000000000 | 001110
JALR | 00100000000000000000000000000000000000000000000 | 001011
ALUWB | 01000000000000000000000000000000000000000000000 | 000111
EXECUTECSR | 10000000000000000000000000000000000000000000000 | 001111
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'Control_Unit'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
FSM_IDLE | 00 | 000
FSM_START | 11 | 001
FSM_RECV | 10 | 010
FSM_STOP | 01 | 011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'fsm_state_reg' using encoding 'sequential' in module 'uart_tool_rx'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
FSM_IDLE | 00 | 000
FSM_START | 11 | 001
FSM_SEND | 10 | 010
FSM_STOP | 01 | 011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'fsm_state_reg' using encoding 'sequential' in module 'uart_tool_tx'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
IDLE | 0000 | 0000
COPY_WRITE_BUFFER | 0001 | 0100
WRITE | 0010 | 0010
READ | 0011 | 0001
READ_RX_FIFO_EMPTY | 0100 | 0110
READ_TX_FIFO_EMPTY | 0101 | 0111
READ_RX_FIFO_FULL | 0110 | 1000
READ_TX_FIFO_FULL | 0111 | 1001
WB | 1000 | 0101
FINISH | 1001 | 0011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'UART'
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2283.410 ; gain = 659.250 ; free physical = 731 ; free virtual = 24208
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Component Statistics
---------------------------------------------------------------------------------
Detailed RTL Component Info :
+---Adders :
2 Input 32 Bit Adders := 1
3 Input 32 Bit Adders := 1
2 Input 10 Bit Adders := 2
2 Input 6 Bit Adders := 6
2 Input 5 Bit Adders := 1
2 Input 4 Bit Adders := 2
2 Input 3 Bit Adders := 2
2 Input 2 Bit Adders := 1
+---XORs :
2 Input 32 Bit XORs := 1
+---XORs :
2 Bit Wide XORs := 1
+---Registers :
64 Bit Registers := 2
32 Bit Registers := 51
16 Bit Registers := 4
10 Bit Registers := 2
8 Bit Registers := 8
6 Bit Registers := 5
4 Bit Registers := 2
3 Bit Registers := 1
2 Bit Registers := 1
1 Bit Registers := 15
+---RAMs :
16K Bit (512 X 32 bit) RAMs := 1
128 Bit (16 X 8 bit) RAMs := 2
+---Muxes :
4 Input 64 Bit Muxes := 1
47 Input 47 Bit Muxes := 1
2 Input 47 Bit Muxes := 17
11 Input 47 Bit Muxes := 1
2 Input 32 Bit Muxes := 8
8 Input 32 Bit Muxes := 1
15 Input 32 Bit Muxes := 1
6 Input 32 Bit Muxes := 1
4 Input 32 Bit Muxes := 1
10 Input 32 Bit Muxes := 2
2 Input 8 Bit Muxes := 3
3 Input 6 Bit Muxes := 1
2 Input 6 Bit Muxes := 4
2 Input 5 Bit Muxes := 1
47 Input 4 Bit Muxes := 1
9 Input 4 Bit Muxes := 1
10 Input 4 Bit Muxes := 2
23 Input 4 Bit Muxes := 1
2 Input 4 Bit Muxes := 3
6 Input 4 Bit Muxes := 1
5 Input 3 Bit Muxes := 1
2 Input 3 Bit Muxes := 3
4 Input 3 Bit Muxes := 2
47 Input 3 Bit Muxes := 3
10 Input 3 Bit Muxes := 2
3 Input 2 Bit Muxes := 1
2 Input 2 Bit Muxes := 16
47 Input 2 Bit Muxes := 2
4 Input 2 Bit Muxes := 4
3 Input 1 Bit Muxes := 6
2 Input 1 Bit Muxes := 77
47 Input 1 Bit Muxes := 12
6 Input 1 Bit Muxes := 12
4 Input 1 Bit Muxes := 2
10 Input 1 Bit Muxes := 8
---------------------------------------------------------------------------------
Finished RTL Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 240 (col length:80)
BRAMs: 270 (col length: RAMB18 80 RAMB36 40)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
INFO: [Synth 8-6851] RAM (SOC/Memory/memory_reg) has partial Byte Wide Write Enable pattern, however no output register found in fanout of RAM. Recommended to use supported Byte Wide Write Enable template.
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:30 ; elapsed = 00:00:30 . Memory (MB): peak = 2283.410 ; gain = 659.250 ; free physical = 566 ; free virtual = 24050
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
Distributed RAM: Preliminary Mapping Report (see note below)
+------------+-----------------------------+-----------+----------------------+-----------------+
|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
+------------+-----------------------------+-----------+----------------------+-----------------+
|top | SOC/Memory/memory_reg | Implied | 512 x 32 | RAM256X1S x 64 |
|top | SOC/Uart/RX_FIFO/memory_reg | Implied | 16 x 8 | RAM32M x 2 |
|top | SOC/Uart/TX_FIFO/memory_reg | Implied | 16 x 8 | RAM32M x 2 |
+------------+-----------------------------+-----------+----------------------+-----------------+
Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once.
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:35 ; elapsed = 00:00:35 . Memory (MB): peak = 2283.410 ; gain = 659.250 ; free physical = 553 ; free virtual = 24037
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:00:38 ; elapsed = 00:00:38 . Memory (MB): peak = 2283.410 ; gain = 659.250 ; free physical = 565 ; free virtual = 24049
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
Distributed RAM: Final Mapping Report
+------------+-----------------------------+-----------+----------------------+-----------------+
|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
+------------+-----------------------------+-----------+----------------------+-----------------+
|top | SOC/Memory/memory_reg | Implied | 512 x 32 | RAM256X1S x 64 |
|top | SOC/Uart/RX_FIFO/memory_reg | Implied | 16 x 8 | RAM32M x 2 |
|top | SOC/Uart/TX_FIFO/memory_reg | Implied | 16 x 8 | RAM32M x 2 |
+------------+-----------------------------+-----------+----------------------+-----------------+
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 2283.410 ; gain = 659.250 ; free physical = 560 ; free virtual = 24044
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:00:45 ; elapsed = 00:00:45 . Memory (MB): peak = 2283.410 ; gain = 659.250 ; free physical = 513 ; free virtual = 23997
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:00:45 ; elapsed = 00:00:45 . Memory (MB): peak = 2283.410 ; gain = 659.250 ; free physical = 513 ; free virtual = 23997
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:45 ; elapsed = 00:00:45 . Memory (MB): peak = 2283.410 ; gain = 659.250 ; free physical = 511 ; free virtual = 23996
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:00:45 ; elapsed = 00:00:45 . Memory (MB): peak = 2283.410 ; gain = 659.250 ; free physical = 511 ; free virtual = 23996
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:45 ; elapsed = 00:00:45 . Memory (MB): peak = 2283.410 ; gain = 659.250 ; free physical = 511 ; free virtual = 23995
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:00:45 ; elapsed = 00:00:45 . Memory (MB): peak = 2283.410 ; gain = 659.250 ; free physical = 511 ; free virtual = 23995
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------
Report BlackBoxes:
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+
Report Cell Usage:
+------+----------+------+
| |Cell |Count |
+------+----------+------+
|1 |BUFG | 2|
|2 |CARRY4 | 71|
|3 |LUT1 | 19|
|4 |LUT2 | 185|
|5 |LUT3 | 258|
|6 |LUT4 | 308|
|7 |LUT5 | 260|
|8 |LUT6 | 1515|
|9 |MUXF7 | 458|
|10 |MUXF8 | 15|
|11 |RAM256X1S | 64|
|12 |RAM32M | 2|
|13 |RAM32X1D | 4|
|14 |FDRE | 2091|
|15 |FDSE | 4|
|16 |IBUF | 3|
|17 |IOBUF | 8|
|18 |OBUF | 9|
+------+----------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:45 ; elapsed = 00:00:45 . Memory (MB): peak = 2283.410 ; gain = 659.250 ; free physical = 511 ; free virtual = 23995
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 63 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:43 ; elapsed = 00:00:43 . Memory (MB): peak = 2283.410 ; gain = 511.465 ; free physical = 510 ; free virtual = 23994
Synthesis Optimization Complete : Time (s): cpu = 00:00:45 ; elapsed = 00:00:45 . Memory (MB): peak = 2283.410 ; gain = 659.250 ; free physical = 510 ; free virtual = 23994
INFO: [Project 1-571] Translating synthesized netlist
Netlist sorting complete. Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2283.410 ; gain = 0.000 ; free physical = 776 ; free virtual = 24260
INFO: [Netlist 29-17] Analyzing 622 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc]
Finished Parsing XDC File [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2347.406 ; gain = 0.000 ; free physical = 730 ; free virtual = 24214
INFO: [Project 1-111] Unisim Transformation Summary:
A total of 78 instances were transformed.
IOBUF => IOBUF (IBUF, OBUFT): 8 instances
RAM256X1S => RAM256X1S (MUXF7(x2), MUXF8, RAMS64E(x4)): 64 instances
RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 2 instances
RAM32X1D => RAM32X1D (RAMD32(x2)): 4 instances
Synth Design complete | Checksum: 4323e98b
INFO: [Common 17-83] Releasing license: Synthesis
79 Infos, 112 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:55 ; elapsed = 00:00:52 . Memory (MB): peak = 2347.441 ; gain = 1032.320 ; free physical = 725 ; free virtual = 24213
INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 2032.189; main = 1753.505; forked = 422.550
INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3221.020; main = 2347.410; forked = 969.656
# opt_design
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command opt_design
Starting DRC Task
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.72 . Memory (MB): peak = 2411.438 ; gain = 63.996 ; free physical = 1049 ; free virtual = 24553
Starting Cache Timing Information Task
INFO: [Timing 38-35] Done setting XDC timing constraints.
Ending Cache Timing Information Task | Checksum: 146decbe9
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2521.250 ; gain = 109.812 ; free physical = 988 ; free virtual = 24493
Starting Logic Optimization Task
Phase 1 Initialization
Phase 1.1 Core Generation And Design Setup
Phase 1.1 Core Generation And Design Setup | Checksum: 146decbe9
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2772.156 ; gain = 0.000 ; free physical = 718 ; free virtual = 24223
Phase 1.2 Setup Constraints And Sort Netlist
Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 146decbe9
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2772.156 ; gain = 0.000 ; free physical = 718 ; free virtual = 24223
Phase 1 Initialization | Checksum: 146decbe9
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2772.156 ; gain = 0.000 ; free physical = 718 ; free virtual = 24223
Phase 2 Timer Update And Timing Data Collection
Phase 2.1 Timer Update
Phase 2.1 Timer Update | Checksum: 146decbe9
Time (s): cpu = 00:00:00.19 ; elapsed = 00:00:00.07 . Memory (MB): peak = 2772.156 ; gain = 0.000 ; free physical = 718 ; free virtual = 24223
Phase 2.2 Timing Data Collection
Phase 2.2 Timing Data Collection | Checksum: 146decbe9
Time (s): cpu = 00:00:00.2 ; elapsed = 00:00:00.07 . Memory (MB): peak = 2772.156 ; gain = 0.000 ; free physical = 718 ; free virtual = 24223
Phase 2 Timer Update And Timing Data Collection | Checksum: 146decbe9
Time (s): cpu = 00:00:00.2 ; elapsed = 00:00:00.08 . Memory (MB): peak = 2772.156 ; gain = 0.000 ; free physical = 718 ; free virtual = 24223
Phase 3 Retarget
INFO: [Opt 31-1566] Pulled 5 inverters resulting in an inversion of 15 pins
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 3 Retarget | Checksum: 1823b20f2
Time (s): cpu = 00:00:00.32 ; elapsed = 00:00:00.16 . Memory (MB): peak = 2772.156 ; gain = 0.000 ; free physical = 718 ; free virtual = 24223
Retarget | Checksum: 1823b20f2
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 5 cells
Phase 4 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 4 Constant propagation | Checksum: 1823b20f2
Time (s): cpu = 00:00:00.36 ; elapsed = 00:00:00.2 . Memory (MB): peak = 2772.156 ; gain = 0.000 ; free physical = 718 ; free virtual = 24223
Constant propagation | Checksum: 1823b20f2
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
Phase 5 Sweep
Phase 5 Sweep | Checksum: 20fd107b2
Time (s): cpu = 00:00:00.4 ; elapsed = 00:00:00.25 . Memory (MB): peak = 2772.156 ; gain = 0.000 ; free physical = 718 ; free virtual = 24222
Sweep | Checksum: 20fd107b2
INFO: [Opt 31-389] Phase Sweep created 8 cells and removed 0 cells
Phase 6 BUFG optimization
Phase 6 BUFG optimization | Checksum: 20fd107b2
Time (s): cpu = 00:00:00.5 ; elapsed = 00:00:00.29 . Memory (MB): peak = 2804.172 ; gain = 32.016 ; free physical = 718 ; free virtual = 24222
BUFG optimization | Checksum: 20fd107b2
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
Phase 7 Shift Register Optimization
INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
Phase 7 Shift Register Optimization | Checksum: 20fd107b2
Time (s): cpu = 00:00:00.5 ; elapsed = 00:00:00.3 . Memory (MB): peak = 2804.172 ; gain = 32.016 ; free physical = 718 ; free virtual = 24222
Shift Register Optimization | Checksum: 20fd107b2
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
Phase 8 Post Processing Netlist
Phase 8 Post Processing Netlist | Checksum: 1b2306da5
Time (s): cpu = 00:00:00.51 ; elapsed = 00:00:00.31 . Memory (MB): peak = 2804.172 ; gain = 32.016 ; free physical = 718 ; free virtual = 24222
Post Processing Netlist | Checksum: 1b2306da5
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
Phase 9 Finalization
Phase 9.1 Finalizing Design Cores and Updating Shapes
Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 13af42843
Time (s): cpu = 00:00:00.59 ; elapsed = 00:00:00.36 . Memory (MB): peak = 2804.172 ; gain = 32.016 ; free physical = 718 ; free virtual = 24222
Phase 9.2 Verifying Netlist Connectivity
Starting Connectivity Check Task
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2804.172 ; gain = 0.000 ; free physical = 718 ; free virtual = 24222
Phase 9.2 Verifying Netlist Connectivity | Checksum: 13af42843
Time (s): cpu = 00:00:00.6 ; elapsed = 00:00:00.37 . Memory (MB): peak = 2804.172 ; gain = 32.016 ; free physical = 718 ; free virtual = 24222
Phase 9 Finalization | Checksum: 13af42843
Time (s): cpu = 00:00:00.6 ; elapsed = 00:00:00.37 . Memory (MB): peak = 2804.172 ; gain = 32.016 ; free physical = 718 ; free virtual = 24222
Opt_design Change Summary
=========================
-------------------------------------------------------------------------------------------------------------------------
| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
-------------------------------------------------------------------------------------------------------------------------
| Retarget | 0 | 5 | 0 |
| Constant propagation | 0 | 0 | 0 |
| Sweep | 8 | 0 | 0 |
| BUFG optimization | 0 | 0 | 0 |
| Shift Register Optimization | 0 | 0 | 0 |
| Post Processing Netlist | 0 | 0 | 0 |
-------------------------------------------------------------------------------------------------------------------------
Ending Logic Optimization Task | Checksum: 13af42843
Time (s): cpu = 00:00:00.6 ; elapsed = 00:00:00.37 . Memory (MB): peak = 2804.172 ; gain = 32.016 ; free physical = 718 ; free virtual = 24222
INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8
Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2804.172 ; gain = 0.000 ; free physical = 718 ; free virtual = 24222
Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
Ending Power Optimization Task | Checksum: 13af42843
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2804.172 ; gain = 0.000 ; free physical = 718 ; free virtual = 24222
Starting Final Cleanup Task
Ending Final Cleanup Task | Checksum: 13af42843
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2804.172 ; gain = 0.000 ; free physical = 718 ; free virtual = 24222
Starting Netlist Obfuscation Task
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2804.172 ; gain = 0.000 ; free physical = 718 ; free virtual = 24222
Ending Netlist Obfuscation Task | Checksum: 13af42843
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2804.172 ; gain = 0.000 ; free physical = 718 ; free virtual = 24222
INFO: [Common 17-83] Releasing license: Implementation
19 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 2804.172 ; gain = 456.730 ; free physical = 718 ; free virtual = 24222
# place_design
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-83] Releasing license: Implementation
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs
Starting Placer Task
Phase 1 Placer Initialization
Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2836.188 ; gain = 0.000 ; free physical = 717 ; free virtual = 24222
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: c04d5782
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2836.188 ; gain = 0.000 ; free physical = 717 ; free virtual = 24222
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2836.188 ; gain = 0.000 ; free physical = 717 ; free virtual = 24222
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: bad7e1af
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.75 . Memory (MB): peak = 2836.188 ; gain = 0.000 ; free physical = 698 ; free virtual = 24203
Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: bdb759a9
Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2843.215 ; gain = 7.027 ; free physical = 714 ; free virtual = 24218
Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: bdb759a9
Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2843.215 ; gain = 7.027 ; free physical = 714 ; free virtual = 24218
Phase 1 Placer Initialization | Checksum: bdb759a9
Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2843.215 ; gain = 7.027 ; free physical = 714 ; free virtual = 24218
Phase 2 Global Placement
Phase 2.1 Floorplanning
Phase 2.1 Floorplanning | Checksum: d65f425b
Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 2843.215 ; gain = 7.027 ; free physical = 710 ; free virtual = 24215
Phase 2.2 Update Timing before SLR Path Opt
Phase 2.2 Update Timing before SLR Path Opt | Checksum: 15c583a28
Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 2843.215 ; gain = 7.027 ; free physical = 711 ; free virtual = 24216
Phase 2.3 Post-Processing in Floorplanning
Phase 2.3 Post-Processing in Floorplanning | Checksum: 15c583a28
Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 2843.215 ; gain = 7.027 ; free physical = 711 ; free virtual = 24216
Phase 2.4 Global Placement Core
Phase 2.4.1 UpdateTiming Before Physical Synthesis
Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 13270fcb8
Time (s): cpu = 00:00:15 ; elapsed = 00:00:04 . Memory (MB): peak = 2843.215 ; gain = 7.027 ; free physical = 700 ; free virtual = 24205
Phase 2.4.2 Physical Synthesis In Placer
INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 89 LUT instances to create LUTNM shape
INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0
INFO: [Physopt 32-1138] End 1 Pass. Optimized 34 nets or LUTs. Breaked 0 LUT, combined 34 existing LUTs and moved 0 existing LUT
INFO: [Physopt 32-65] No nets found for high-fanout optimization.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found. Shift Register to Pipeline Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found. URAM Register Optimization was not performed.
INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2843.215 ; gain = 0.000 ; free physical = 710 ; free virtual = 24215
Summary of Physical Synthesis Optimizations
============================================
-----------------------------------------------------------------------------------------------------------------------------------------------------------
| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |
-----------------------------------------------------------------------------------------------------------------------------------------------------------
| LUT Combining | 0 | 34 | 34 | 0 | 1 | 00:00:00 |
| Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| Shift Register to Pipeline | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| URAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| Total | 0 | 34 | 34 | 0 | 4 | 00:00:00 |
-----------------------------------------------------------------------------------------------------------------------------------------------------------
Phase 2.4.2 Physical Synthesis In Placer | Checksum: 1456691e6
Time (s): cpu = 00:00:16 ; elapsed = 00:00:05 . Memory (MB): peak = 2843.215 ; gain = 7.027 ; free physical = 710 ; free virtual = 24215
Phase 2.4 Global Placement Core | Checksum: 11d0214de
Time (s): cpu = 00:00:20 ; elapsed = 00:00:05 . Memory (MB): peak = 2843.215 ; gain = 7.027 ; free physical = 710 ; free virtual = 24215
Phase 2 Global Placement | Checksum: 11d0214de
Time (s): cpu = 00:00:20 ; elapsed = 00:00:05 . Memory (MB): peak = 2843.215 ; gain = 7.027 ; free physical = 710 ; free virtual = 24215
Phase 3 Detail Placement
Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: 1a95a0775
Time (s): cpu = 00:00:20 ; elapsed = 00:00:05 . Memory (MB): peak = 2843.215 ; gain = 7.027 ; free physical = 710 ; free virtual = 24215
Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 123e0a448
Time (s): cpu = 00:00:20 ; elapsed = 00:00:05 . Memory (MB): peak = 2843.215 ; gain = 7.027 ; free physical = 710 ; free virtual = 24215
Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 15c081164
Time (s): cpu = 00:00:20 ; elapsed = 00:00:05 . Memory (MB): peak = 2843.215 ; gain = 7.027 ; free physical = 710 ; free virtual = 24215
Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: 104d545db
Time (s): cpu = 00:00:20 ; elapsed = 00:00:05 . Memory (MB): peak = 2843.215 ; gain = 7.027 ; free physical = 710 ; free virtual = 24215
Phase 3.5 Small Shape Detail Placement
Phase 3.5 Small Shape Detail Placement | Checksum: 150d95eed
Time (s): cpu = 00:00:22 ; elapsed = 00:00:07 . Memory (MB): peak = 2843.215 ; gain = 7.027 ; free physical = 707 ; free virtual = 24212
Phase 3.6 Re-assign LUT pins
Phase 3.6 Re-assign LUT pins | Checksum: fe87775e
Time (s): cpu = 00:00:22 ; elapsed = 00:00:07 . Memory (MB): peak = 2843.215 ; gain = 7.027 ; free physical = 709 ; free virtual = 24214
Phase 3.7 Pipeline Register Optimization
Phase 3.7 Pipeline Register Optimization | Checksum: 1575cc3c3
Time (s): cpu = 00:00:22 ; elapsed = 00:00:07 . Memory (MB): peak = 2843.215 ; gain = 7.027 ; free physical = 709 ; free virtual = 24214
Phase 3 Detail Placement | Checksum: 1575cc3c3
Time (s): cpu = 00:00:22 ; elapsed = 00:00:07 . Memory (MB): peak = 2843.215 ; gain = 7.027 ; free physical = 709 ; free virtual = 24214
Phase 4 Post Placement Optimization and Clean-Up
Phase 4.1 Post Commit Optimization
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 4.1.1 Post Placement Optimization
Post Placement Optimization Initialization | Checksum: 12b1c98e3
Phase 4.1.1.1 BUFG Insertion
Starting Physical Synthesis Task
Phase 1 Physical Synthesis Initialization
INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=9.081 | TNS=0.000 |
Phase 1 Physical Synthesis Initialization | Checksum: 1722e4068
Time (s): cpu = 00:00:00.21 ; elapsed = 00:00:00.07 . Memory (MB): peak = 2843.215 ; gain = 0.000 ; free physical = 709 ; free virtual = 24214
INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0.
Ending Physical Synthesis Task | Checksum: 1722e4068
Time (s): cpu = 00:00:00.26 ; elapsed = 00:00:00.12 . Memory (MB): peak = 2843.215 ; gain = 0.000 ; free physical = 709 ; free virtual = 24214
Phase 4.1.1.1 BUFG Insertion | Checksum: 12b1c98e3
Time (s): cpu = 00:00:25 ; elapsed = 00:00:08 . Memory (MB): peak = 2843.215 ; gain = 7.027 ; free physical = 709 ; free virtual = 24214
Phase 4.1.1.2 Post Placement Timing Optimization
INFO: [Place 30-746] Post Placement Timing Summary WNS=9.081. For the most accurate timing information please run report_timing.
Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 12ce860c2
Time (s): cpu = 00:00:25 ; elapsed = 00:00:08 . Memory (MB): peak = 2843.215 ; gain = 7.027 ; free physical = 709 ; free virtual = 24214
Time (s): cpu = 00:00:25 ; elapsed = 00:00:08 . Memory (MB): peak = 2843.215 ; gain = 7.027 ; free physical = 709 ; free virtual = 24214
Phase 4.1 Post Commit Optimization | Checksum: 12ce860c2
Time (s): cpu = 00:00:25 ; elapsed = 00:00:08 . Memory (MB): peak = 2843.215 ; gain = 7.027 ; free physical = 709 ; free virtual = 24214
Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: 12ce860c2
Time (s): cpu = 00:00:26 ; elapsed = 00:00:08 . Memory (MB): peak = 2843.215 ; gain = 7.027 ; free physical = 709 ; free virtual = 24214
Phase 4.3 Placer Reporting
Phase 4.3.1 Print Estimated Congestion
INFO: [Place 30-612] Post-Placement Estimated Congestion
____________________________________________________
| | Global Congestion | Short Congestion |
| Direction | Region Size | Region Size |
|___________|___________________|___________________|
| North| 1x1| 2x2|
|___________|___________________|___________________|
| South| 1x1| 1x1|
|___________|___________________|___________________|
| East| 1x1| 1x1|
|___________|___________________|___________________|
| West| 1x1| 1x1|
|___________|___________________|___________________|
Phase 4.3.1 Print Estimated Congestion | Checksum: 12ce860c2
Time (s): cpu = 00:00:26 ; elapsed = 00:00:08 . Memory (MB): peak = 2843.215 ; gain = 7.027 ; free physical = 709 ; free virtual = 24214
Phase 4.3 Placer Reporting | Checksum: 12ce860c2
Time (s): cpu = 00:00:26 ; elapsed = 00:00:08 . Memory (MB): peak = 2843.215 ; gain = 7.027 ; free physical = 709 ; free virtual = 24214
Phase 4.4 Final Placement Cleanup
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2843.215 ; gain = 0.000 ; free physical = 709 ; free virtual = 24214
Time (s): cpu = 00:00:26 ; elapsed = 00:00:08 . Memory (MB): peak = 2843.215 ; gain = 7.027 ; free physical = 709 ; free virtual = 24214
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 862fa997
Time (s): cpu = 00:00:26 ; elapsed = 00:00:08 . Memory (MB): peak = 2843.215 ; gain = 7.027 ; free physical = 709 ; free virtual = 24214
Ending Placer Task | Checksum: 50ceb87c
Time (s): cpu = 00:00:26 ; elapsed = 00:00:08 . Memory (MB): peak = 2843.215 ; gain = 7.027 ; free physical = 709 ; free virtual = 24214
29 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
place_design: Time (s): cpu = 00:00:27 ; elapsed = 00:00:09 . Memory (MB): peak = 2843.215 ; gain = 39.043 ; free physical = 709 ; free virtual = 24214
# report_utilization -hierarchical -file digilent_nexys4ddr_utilization_hierarchical_place.rpt
# report_utilization -file digilent_nexys4ddr_utilization_place.rpt
# report_io -file digilent_nexys4ddr_io.rpt
report_io: Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.15 . Memory (MB): peak = 2843.215 ; gain = 0.000 ; free physical = 707 ; free virtual = 24212
# report_control_sets -verbose -file digilent_nexys4ddr_control_sets.rpt
report_control_sets: Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.09 . Memory (MB): peak = 2843.215 ; gain = 0.000 ; free physical = 708 ; free virtual = 24213
# report_clock_utilization -file digilent_nexys4ddr_clock_utilization.rpt
# route_design
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command route_design
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs
Phase 1 Build RT Design
Checksum: PlaceDB: 20ab9d53 ConstDB: 0 ShapeSum: 30231b29 RouteDB: 0
Post Restoration Checksum: NetGraph: 38316509 | NumContArr: 4ed83706 | Constraints: c2a8fa9d | Timing: c2a8fa9d
Phase 1 Build RT Design | Checksum: 20c5b9149
Time (s): cpu = 00:00:33 ; elapsed = 00:00:27 . Memory (MB): peak = 2843.215 ; gain = 0.000 ; free physical = 619 ; free virtual = 24124
Phase 2 Router Initialization
Phase 2.1 Fix Topology Constraints
Phase 2.1 Fix Topology Constraints | Checksum: 20c5b9149
Time (s): cpu = 00:00:33 ; elapsed = 00:00:27 . Memory (MB): peak = 2843.215 ; gain = 0.000 ; free physical = 619 ; free virtual = 24124
Phase 2.2 Pre Route Cleanup
Phase 2.2 Pre Route Cleanup | Checksum: 20c5b9149
Time (s): cpu = 00:00:33 ; elapsed = 00:00:27 . Memory (MB): peak = 2843.215 ; gain = 0.000 ; free physical = 619 ; free virtual = 24124
Number of Nodes with overlaps = 0
Phase 2.3 Update Timing
Phase 2.3 Update Timing | Checksum: 2a589208d
Time (s): cpu = 00:00:37 ; elapsed = 00:00:29 . Memory (MB): peak = 2843.215 ; gain = 0.000 ; free physical = 590 ; free virtual = 24096
INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.996 | TNS=0.000 | WHS=-0.066 | THS=-0.066 |
Router Utilization Summary
Global Vertical Routing Utilization = 8.70436e-05 %
Global Horizontal Routing Utilization = 7.10429e-05 %
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
Number of Failed Nets = 3835
(Failed Nets is the sum of unrouted and partially routed nets)
Number of Unrouted Nets = 3834
Number of Partially Routed Nets = 1
Number of Node Overlaps = 0
Phase 2 Router Initialization | Checksum: 2dc8ebc9d
Time (s): cpu = 00:00:39 ; elapsed = 00:00:29 . Memory (MB): peak = 2843.215 ; gain = 0.000 ; free physical = 583 ; free virtual = 24088
Phase 3 Initial Routing
Phase 3.1 Global Routing
Phase 3.1 Global Routing | Checksum: 2dc8ebc9d
Time (s): cpu = 00:00:39 ; elapsed = 00:00:29 . Memory (MB): peak = 2843.215 ; gain = 0.000 ; free physical = 583 ; free virtual = 24088
Phase 3.2 Initial Net Routing
Phase 3.2 Initial Net Routing | Checksum: 216aa9269
Time (s): cpu = 00:00:41 ; elapsed = 00:00:29 . Memory (MB): peak = 2843.215 ; gain = 0.000 ; free physical = 580 ; free virtual = 24085
Phase 3 Initial Routing | Checksum: 216aa9269
Time (s): cpu = 00:00:41 ; elapsed = 00:00:29 . Memory (MB): peak = 2843.215 ; gain = 0.000 ; free physical = 579 ; free virtual = 24084
Phase 4 Rip-up And Reroute
Phase 4.1 Global Iteration 0
Number of Nodes with overlaps = 570
Number of Nodes with overlaps = 3
Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.788 | TNS=0.000 | WHS=N/A | THS=N/A |
Phase 4.1 Global Iteration 0 | Checksum: 1fcf7f3f8
Time (s): cpu = 00:00:44 ; elapsed = 00:00:31 . Memory (MB): peak = 2843.215 ; gain = 0.000 ; free physical = 578 ; free virtual = 24083
Phase 4 Rip-up And Reroute | Checksum: 1fcf7f3f8
Time (s): cpu = 00:00:44 ; elapsed = 00:00:31 . Memory (MB): peak = 2843.215 ; gain = 0.000 ; free physical = 578 ; free virtual = 24083
Phase 5 Delay and Skew Optimization
Phase 5.1 Delay CleanUp
Phase 5.1 Delay CleanUp | Checksum: 1fcf7f3f8
Time (s): cpu = 00:00:44 ; elapsed = 00:00:31 . Memory (MB): peak = 2843.215 ; gain = 0.000 ; free physical = 578 ; free virtual = 24083
Phase 5.2 Clock Skew Optimization
Phase 5.2 Clock Skew Optimization | Checksum: 1fcf7f3f8
Time (s): cpu = 00:00:44 ; elapsed = 00:00:31 . Memory (MB): peak = 2843.215 ; gain = 0.000 ; free physical = 578 ; free virtual = 24083
Phase 5 Delay and Skew Optimization | Checksum: 1fcf7f3f8
Time (s): cpu = 00:00:44 ; elapsed = 00:00:31 . Memory (MB): peak = 2843.215 ; gain = 0.000 ; free physical = 578 ; free virtual = 24083
Phase 6 Post Hold Fix
Phase 6.1 Hold Fix Iter
Phase 6.1.1 Update Timing
Phase 6.1.1 Update Timing | Checksum: 22b9bb45d
Time (s): cpu = 00:00:44 ; elapsed = 00:00:31 . Memory (MB): peak = 2843.215 ; gain = 0.000 ; free physical = 578 ; free virtual = 24083
INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.884 | TNS=0.000 | WHS=0.247 | THS=0.000 |
Phase 6.1 Hold Fix Iter | Checksum: 22b9bb45d
Time (s): cpu = 00:00:44 ; elapsed = 00:00:31 . Memory (MB): peak = 2843.215 ; gain = 0.000 ; free physical = 578 ; free virtual = 24083
Phase 6 Post Hold Fix | Checksum: 22b9bb45d
Time (s): cpu = 00:00:44 ; elapsed = 00:00:31 . Memory (MB): peak = 2843.215 ; gain = 0.000 ; free physical = 578 ; free virtual = 24083
Phase 7 Route finalize
Router Utilization Summary
Global Vertical Routing Utilization = 0.781825 %
Global Horizontal Routing Utilization = 0.994317 %
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
Number of Failed Nets = 0
(Failed Nets is the sum of unrouted and partially routed nets)
Number of Unrouted Nets = 0
Number of Partially Routed Nets = 0
Number of Node Overlaps = 0
Phase 7 Route finalize | Checksum: 22b9bb45d
Time (s): cpu = 00:00:45 ; elapsed = 00:00:31 . Memory (MB): peak = 2843.215 ; gain = 0.000 ; free physical = 578 ; free virtual = 24083
Phase 8 Verifying routed nets
Verification completed successfully
Phase 8 Verifying routed nets | Checksum: 22b9bb45d
Time (s): cpu = 00:00:45 ; elapsed = 00:00:31 . Memory (MB): peak = 2843.215 ; gain = 0.000 ; free physical = 578 ; free virtual = 24083
Phase 9 Depositing Routes
Phase 9 Depositing Routes | Checksum: 20bb02aaf
Time (s): cpu = 00:00:45 ; elapsed = 00:00:31 . Memory (MB): peak = 2843.215 ; gain = 0.000 ; free physical = 578 ; free virtual = 24083
Phase 10 Post Router Timing
INFO: [Route 35-57] Estimated Timing Summary | WNS=8.884 | TNS=0.000 | WHS=0.247 | THS=0.000 |
INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
Phase 10 Post Router Timing | Checksum: 20bb02aaf
Time (s): cpu = 00:00:46 ; elapsed = 00:00:31 . Memory (MB): peak = 2843.215 ; gain = 0.000 ; free physical = 578 ; free virtual = 24083
INFO: [Route 35-16] Router Completed Successfully
Phase 11 Post-Route Event Processing
Phase 11 Post-Route Event Processing | Checksum: 12a061842
Time (s): cpu = 00:00:46 ; elapsed = 00:00:31 . Memory (MB): peak = 2843.215 ; gain = 0.000 ; free physical = 578 ; free virtual = 24083
Ending Routing Task | Checksum: 12a061842
Time (s): cpu = 00:00:46 ; elapsed = 00:00:31 . Memory (MB): peak = 2843.215 ; gain = 0.000 ; free physical = 578 ; free virtual = 24083
Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
12 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:00:47 ; elapsed = 00:00:32 . Memory (MB): peak = 2843.215 ; gain = 0.000 ; free physical = 578 ; free virtual = 24083
# report_timing_summary -no_header -no_detailed_paths
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------
Enable Multi Corner Analysis : Yes
Enable Pessimism Removal : Yes
Pessimism Removal Resolution : Nearest Common Node
Enable Input Delay Default Clock : No
Enable Preset / Clear Arcs : No
Disable Flight Delays : No
Ignore I/O Paths : No
Timing Early Launch at Borrowing Latches : No
Borrow Time for Max Delay Exceptions : Yes
Merge Timing Exceptions : Yes
Inter-SLR Compensation : Conservative
Corner Analyze Analyze
Name Max Paths Min Paths
------ --------- ---------
Slow Yes Yes
Fast Yes Yes
------------------------------------------------------------------------------------------------
| Report Methodology
| ------------------
------------------------------------------------------------------------------------------------
No report available as report_methodology has not been run prior. Run report_methodology on the current design for the summary of methodology violations.
check_timing report
Table of Contents
-----------------
1. checking no_clock (2381)
2. checking constant_clock (0)
3. checking pulse_width_clock (0)
4. checking unconstrained_internal_endpoints (7609)
5. checking no_input_delay (10)
6. checking no_output_delay (17)
7. checking multiple_clock (0)
8. checking generated_clocks (0)
9. checking loops (0)
10. checking partial_input_delay (0)
11. checking partial_output_delay (0)
12. checking latch_loops (0)
1. checking no_clock (2381)
---------------------------
There are 2381 register/latch pins with no clock driven by root clock pin: clk_o_reg/Q (HIGH)
2. checking constant_clock (0)
------------------------------
There are 0 register/latch pins with constant_clock.
3. checking pulse_width_clock (0)
---------------------------------
There are 0 register/latch pins which need pulse_width check
4. checking unconstrained_internal_endpoints (7609)
---------------------------------------------------
There are 7609 pins that are not constrained for maximum delay. (HIGH)
There are 0 pins that are not constrained for maximum delay due to constant clock.
5. checking no_input_delay (10)
-------------------------------
There are 10 input ports with no input delay specified. (HIGH)
There are 0 input ports with no input delay but user has a false path constraint.
6. checking no_output_delay (17)
--------------------------------
There are 17 ports with no output delay specified. (HIGH)
There are 0 ports with no output delay but user has a false path constraint
There are 0 ports with no output delay but with a timing clock defined on it or propagating through it
7. checking multiple_clock (0)
------------------------------
There are 0 register/latch pins with multiple clocks.
8. checking generated_clocks (0)
--------------------------------
There are 0 generated clocks that are not connected to a clock source.
9. checking loops (0)
---------------------
There are 0 combinational loops in the design.
10. checking partial_input_delay (0)
------------------------------------
There are 0 input ports with partial input delay specified.
11. checking partial_output_delay (0)
-------------------------------------
There are 0 ports with partial output delay specified.
12. checking latch_loops (0)
----------------------------
There are 0 combinational latch loops in the design through latch input
------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------
WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
8.908 0.000 0 1 0.263 0.000 0 1 4.500 0.000 0 3
All user specified timing constraints are met.
------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------
Clock Waveform(ns) Period(ns) Frequency(MHz)
----- ------------ ---------- --------------
sys_clk_pin {0.000 5.000} 10.000 100.000
------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------
Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
sys_clk_pin 8.908 0.000 0 1 0.263 0.000 0 1 4.500 0.000 0 3
------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------
From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------
Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
# report_route_status -file digilent_nexys4ddr_route_status.rpt
# report_drc -file digilent_nexys4ddr_drc.rpt
Command: report_drc -file digilent_nexys4ddr_drc.rpt
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/eda/vivado/Vivado/2023.2/data/ip'.
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 2-168] The results of DRC are in file /var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4ddr_drc.rpt.
report_drc completed successfully
# report_timing_summary -datasheet -max_paths 10 -file digilent_nexys4ddr_timing.rpt
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
# report_power -file digilent_nexys4ddr_power.rpt
Command: report_power -file digilent_nexys4ddr_power.rpt
Running Vector-less Activity Propagation...
Finished Running Vector-less Activity Propagation
WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis.
Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report.
0 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
# write_bitstream -force "./build/out.bit"
Command: write_bitstream -force ./build/out.bit
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command write_bitstream
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [DRC 23-27] Running DRC with 8 threads
WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
set_property CFGBVS value1 [current_design]
#where value1 is either VCCO or GND
set_property CONFIG_VOLTAGE value2 [current_design]
#where value2 is the voltage provided to configuration bank 0
Refer to the device configuration user guide for more information.
INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
INFO: [Designutils 20-2272] Running write_bitstream with 8 threads.
Loading data files...
Loading site data...
Loading route data...
Processing options...
Creating bitmap...
Creating bitstream...
Writing bitstream ./build/out.bit...
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
INFO: [Project 1-1876] WebTalk data collection is mandatory when using a ULT device. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
INFO: [Common 17-83] Releasing license: Implementation
9 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
write_bitstream completed successfully
write_bitstream: Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 3156.270 ; gain = 246.176 ; free physical = 557 ; free virtual = 24076
INFO: [Common 17-206] Exiting Vivado at Sun Jun 23 02:46:49 2024...
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