![[Jenkins]](/jenkins/static/b6fe011e/images/svgs/logo.svg){kind=logo}
Started by user Julio Nunes Avelar [Pipeline] Start of Pipeline [Pipeline] node Running on Jenkins in /var/lib/jenkins/workspace/Risco_5 [Pipeline] { [Pipeline] stage [Pipeline] { (Git Clone) [Pipeline] sh + rm -Rf Risco-5/ build/ [Pipeline] sh + git clone https://github.com/JN513/Risco-5 Cloning into 'Risco-5'... [Pipeline] sh + cd Risco-5 [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (IVerilog) [Pipeline] sh + mkdir -p build [Pipeline] sh + cp Risco-5/software/memory/add.hex Risco-5/software/memory/generic.hex [Pipeline] sh + /eda/oss-cad-suite/bin/iverilog -o build/soc_test.o -s soc_tb Risco-5/src/core/alu.v Risco-5/src/core/alu_control.v Risco-5/src/core/control_unit.v Risco-5/src/core/core.v Risco-5/src/core/csr_unit.v Risco-5/src/core/immediate_generator.v Risco-5/src/core/mdu.v Risco-5/src/core/mux.v Risco-5/src/core/pc.v Risco-5/src/core/registers.v Risco-5/src/peripheral/bus.v Risco-5/src/peripheral/fifo.v Risco-5/src/peripheral/gpio.v Risco-5/src/peripheral/gpios.v Risco-5/src/peripheral/leds.v Risco-5/src/peripheral/memory.v Risco-5/src/peripheral/pwm.v Risco-5/src/peripheral/soc.v Risco-5/src/peripheral/uart.v Risco-5/src/peripheral/uart_rx.v Risco-5/src/peripheral/uart_tx.v Risco-5/tests/soc_test.v [Pipeline] sh + /eda/oss-cad-suite/bin/vvp build/soc_test.o ERROR: Risco-5/src/peripheral/memory.v:35: $readmemh: Unable to open software/memory/generic.hex for reading. VCD info: dumpfile build/soc.vcd opened for output. Risco-5/tests/soc_test.v:42: $finish called at 3606 (1s) [Pipeline] sh + rm -f Risco-5/software/memory/generic.hex [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Síntese) [Pipeline] parallel [Pipeline] { (Branch: OSS-Cad-Suite) [Pipeline] { (Branch: Gowin) [Pipeline] { (Branch: Vivado) [Pipeline] stage [Pipeline] { (OSS-Cad-Suite) [Pipeline] stage [Pipeline] { (Gowin) [Pipeline] stage [Pipeline] { (Vivado) [Pipeline] stage [Pipeline] { (Yosys) [Pipeline] sh [Pipeline] sh + rm -rf Risco-5/impl/pnr [Pipeline] sh + cd Risco-5/fpga/nexys4_ddr + mkdir build + /eda/vivado/Vivado/2023.2/bin/vivado -mode batch -nolog -nojournal -source run.tcl + /eda/oss-cad-suite/bin/yosys -p read_verilog Risco-5/fpga/ecp5/*.v; read_verilog Risco-5/debug/reset.v; read_verilog Risco-5/src/core/*.v; read_verilog Risco-5/src/peripheral/*.v; synth_ecp5 -json ./build/out.json -abc9 /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2024 Claire Xenia Wolf <claire@yosyshq.com> | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.42+15 (git sha1 74a1dd99a, clang++ 14.0.0-1ubuntu1.1 -fPIC -Os) -- Running command ` read_verilog Risco-5/fpga/ecp5/*.v; read_verilog Risco-5/debug/reset.v; read_verilog Risco-5/src/core/*.v; read_verilog Risco-5/src/peripheral/*.v; synth_ecp5 -json ./build/out.json -abc9 ' -- 1. Executing Verilog-2005 frontend: Risco-5/fpga/ecp5/main.v Parsing Verilog input from `Risco-5/fpga/ecp5/main.v' to AST representation. Generating RTLIL representation for module `\top'. Successfully finished Verilog frontend. 2. Executing Verilog-2005 frontend: Risco-5/debug/reset.v Parsing Verilog input from `Risco-5/debug/reset.v' to AST representation. Generating RTLIL representation for module `\ResetBootSystem'. Successfully finished Verilog frontend. 3. Executing Verilog-2005 frontend: Risco-5/src/core/alu.v Parsing Verilog input from `Risco-5/src/core/alu.v' to AST representation. Generating RTLIL representation for module `\Alu'. Successfully finished Verilog frontend. 4. Executing Verilog-2005 frontend: Risco-5/src/core/alu_control.v Parsing Verilog input from `Risco-5/src/core/alu_control.v' to AST representation. Generating RTLIL representation for module `\ALU_Control'. Successfully finished Verilog frontend. 5. Executing Verilog-2005 frontend: Risco-5/src/core/control_unit.v Parsing Verilog input from `Risco-5/src/core/control_unit.v' to AST representation. Generating RTLIL representation for module `\Control_Unit'. Successfully finished Verilog frontend. 6. Executing Verilog-2005 frontend: Risco-5/src/core/core.v Parsing Verilog input from `Risco-5/src/core/core.v' to AST representation. Generating RTLIL representation for module `\Core'. Risco-5/src/core/core.v:168: Warning: Identifier `\pc_source' is implicitly declared. Successfully finished Verilog frontend. 7. Executing Verilog-2005 frontend: Risco-5/src/core/csr_unit.v Parsing Verilog input from `Risco-5/src/core/csr_unit.v' to AST representation. Generating RTLIL representation for module `\CSR_Unit'. Successfully finished Verilog frontend. 8. Executing Verilog-2005 frontend: Risco-5/src/core/immediate_generator.v Parsing Verilog input from `Risco-5/src/core/immediate_generator.v' to AST representation. Generating RTLIL representation for module `\Immediate_Generator'. Successfully finished Verilog frontend. 9. Executing Verilog-2005 frontend: Risco-5/src/core/mdu.v Parsing Verilog input from `Risco-5/src/core/mdu.v' to AST representation. Successfully finished Verilog frontend. 10. Executing Verilog-2005 frontend: Risco-5/src/core/mux.v Parsing Verilog input from `Risco-5/src/core/mux.v' to AST representation. Generating RTLIL representation for module `\MUX'. Successfully finished Verilog frontend. 11. Executing Verilog-2005 frontend: Risco-5/src/core/pc.v Parsing Verilog input from `Risco-5/src/core/pc.v' to AST representation. Generating RTLIL representation for module `\PC'. Successfully finished Verilog frontend. 12. Executing Verilog-2005 frontend: Risco-5/src/core/registers.v Parsing Verilog input from `Risco-5/src/core/registers.v' to AST representation. Generating RTLIL representation for module `\Registers'. Successfully finished Verilog frontend. 13. Executing Verilog-2005 frontend: Risco-5/src/peripheral/bus.v Parsing Verilog input from `Risco-5/src/peripheral/bus.v' to AST representation. Generating RTLIL representation for module `\BUS'. Successfully finished Verilog frontend. 14. Executing Verilog-2005 frontend: Risco-5/src/peripheral/fifo.v Parsing Verilog input from `Risco-5/src/peripheral/fifo.v' to AST representation. Generating RTLIL representation for module `\FIFO'. Successfully finished Verilog frontend. 15. Executing Verilog-2005 frontend: Risco-5/src/peripheral/gpio.v Parsing Verilog input from `Risco-5/src/peripheral/gpio.v' to AST representation. Warning: Yosys has only limited support for tri-state logic at the moment. (Risco-5/src/peripheral/gpio.v:9) Generating RTLIL representation for module `\GPIO'. Successfully finished Verilog frontend. 16. Executing Verilog-2005 frontend: Risco-5/src/peripheral/gpios.v Parsing Verilog input from `Risco-5/src/peripheral/gpios.v' to AST representation. Generating RTLIL representation for module `\GPIOS'. Successfully finished Verilog frontend. 17. Executing Verilog-2005 frontend: Risco-5/src/peripheral/leds.v Parsing Verilog input from `Risco-5/src/peripheral/leds.v' to AST representation. Generating RTLIL representation for module `\LEDs'. Successfully finished Verilog frontend. 18. Executing Verilog-2005 frontend: Risco-5/src/peripheral/memory.v Parsing Verilog input from `Risco-5/src/peripheral/memory.v' to AST representation. Generating RTLIL representation for module `\Memory'. Successfully finished Verilog frontend. 19. Executing Verilog-2005 frontend: Risco-5/src/peripheral/pwm.v Parsing Verilog input from `Risco-5/src/peripheral/pwm.v' to AST representation. Generating RTLIL representation for module `\PWM'. Successfully finished Verilog frontend. 20. Executing Verilog-2005 frontend: Risco-5/src/peripheral/soc.v Parsing Verilog input from `Risco-5/src/peripheral/soc.v' to AST representation. Generating RTLIL representation for module `\Risco_5_SOC'. Successfully finished Verilog frontend. 21. Executing Verilog-2005 frontend: Risco-5/src/peripheral/uart.v Parsing Verilog input from `Risco-5/src/peripheral/uart.v' to AST representation. Generating RTLIL representation for module `\UART'. Successfully finished Verilog frontend. 22. Executing Verilog-2005 frontend: Risco-5/src/peripheral/uart_rx.v Parsing Verilog input from `Risco-5/src/peripheral/uart_rx.v' to AST representation. Generating RTLIL representation for module `\uart_tool_rx'. Successfully finished Verilog frontend. 23. Executing Verilog-2005 frontend: Risco-5/src/peripheral/uart_tx.v Parsing Verilog input from `Risco-5/src/peripheral/uart_tx.v' to AST representation. Generating RTLIL representation for module `\uart_tool_tx'. Successfully finished Verilog frontend. 24. Executing SYNTH_ECP5 pass. 24.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v' to AST representation. Generating RTLIL representation for module `\LUT4'. Generating RTLIL representation for module `\$__ABC9_LUT5'. Generating RTLIL representation for module `\$__ABC9_LUT6'. Generating RTLIL representation for module `\$__ABC9_LUT7'. Generating RTLIL representation for module `\L6MUX21'. Generating RTLIL representation for module `\CCU2C'. Generating RTLIL representation for module `\TRELLIS_RAM16X2'. Generating RTLIL representation for module `\PFUMX'. Generating RTLIL representation for module `\TRELLIS_DPR16X4'. Generating RTLIL representation for module `\DPR16X4C'. Generating RTLIL representation for module `\LUT2'. Generating RTLIL representation for module `\TRELLIS_FF'. Generating RTLIL representation for module `\TRELLIS_IO'. Generating RTLIL representation for module `\INV'. Generating RTLIL representation for module `\TRELLIS_COMB'. Generating RTLIL representation for module `\DP16KD'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Successfully finished Verilog frontend. 24.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_bb.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_bb.v' to AST representation. Generating RTLIL representation for module `\MULT18X18D'. Generating RTLIL representation for module `\ALU54B'. Generating RTLIL representation for module `\EHXPLLL'. Generating RTLIL representation for module `\DTR'. Generating RTLIL representation for module `\OSCG'. Generating RTLIL representation for module `\USRMCLK'. Generating RTLIL representation for module `\JTAGG'. Generating RTLIL representation for module `\DELAYF'. Generating RTLIL representation for module `\DELAYG'. Generating RTLIL representation for module `\IDDRX1F'. Generating RTLIL representation for module `\IDDRX2F'. Generating RTLIL representation for module `\IDDR71B'. Generating RTLIL representation for module `\IDDRX2DQA'. Generating RTLIL representation for module `\ODDRX1F'. Generating RTLIL representation for module `\ODDRX2F'. Generating RTLIL representation for module `\ODDR71B'. Generating RTLIL representation for module `\OSHX2A'. Generating RTLIL representation for module `\ODDRX2DQA'. Generating RTLIL representation for module `\ODDRX2DQSB'. Generating RTLIL representation for module `\TSHX2DQA'. Generating RTLIL representation for module `\TSHX2DQSA'. Generating RTLIL representation for module `\DQSBUFM'. Generating RTLIL representation for module `\DDRDLLA'. Generating RTLIL representation for module `\DLLDELD'. Generating RTLIL representation for module `\CLKDIVF'. Generating RTLIL representation for module `\ECLKSYNCB'. Generating RTLIL representation for module `\ECLKBRIDGECS'. Generating RTLIL representation for module `\DCCA'. Generating RTLIL representation for module `\DCSC'. Generating RTLIL representation for module `\DCUA'. Generating RTLIL representation for module `\EXTREFB'. Generating RTLIL representation for module `\PCSCLKDIV'. Generating RTLIL representation for module `\PUR'. Generating RTLIL representation for module `\GSR'. Generating RTLIL representation for module `\SGSR'. Generating RTLIL representation for module `\PDPW16KD'. Successfully finished Verilog frontend. 24.3. Executing HIERARCHY pass (managing design hierarchy). 24.3.1. Finding top of design hierarchy.. root of 0 design levels: uart_tool_tx root of 0 design levels: uart_tool_rx root of 1 design levels: UART root of 2 design levels: Risco_5_SOC root of 0 design levels: PWM root of 0 design levels: Memory root of 0 design levels: LEDs root of 1 design levels: GPIOS root of 0 design levels: GPIO root of 0 design levels: FIFO root of 0 design levels: BUS root of 0 design levels: Registers root of 0 design levels: PC root of 0 design levels: MUX root of 0 design levels: Immediate_Generator root of 0 design levels: CSR_Unit root of 1 design levels: Core root of 0 design levels: Control_Unit root of 0 design levels: ALU_Control root of 0 design levels: Alu root of 0 design levels: ResetBootSystem root of 3 design levels: top Automatically selected top as design top module. 24.3.2. Analyzing design hierarchy.. Top module: \top Used module: \Risco_5_SOC Used module: \GPIOS Used module: \GPIO Used module: \PWM Used module: \UART Used module: \uart_tool_tx Used module: \uart_tool_rx Used module: \FIFO Used module: \LEDs Used module: \BUS Used module: \Memory Used module: \Core Used module: \CSR_Unit Used module: \Immediate_Generator Used module: \Alu Used module: \ALU_Control Used module: \Control_Unit Used module: \Registers Used module: \MUX Used module: \PC Used module: \ResetBootSystem Parameter \CLOCK_FREQ = 25000000 Parameter \BIT_RATE = 115200 Parameter \MEMORY_SIZE = 2048 Parameter \MEMORY_FILE = 328'0010111000101110001011110010111000101110001011110111001101101111011001100111010001110111011000010111001001100101001011110110110101100101011011010110111101110010011110010010111101110100011001010111001101110100011001010101111101110101011000010111001001110100010111110110011001110000011001110110000100101110011010000110010101111000 Parameter \GPIO_WIDHT = 6 Parameter \UART_BUFFER_SIZE = 16 24.3.3. Executing AST frontend in derive mode using pre-parsed AST for module `\Risco_5_SOC'. Parameter \CLOCK_FREQ = 25000000 Parameter \BIT_RATE = 115200 Parameter \MEMORY_SIZE = 2048 Parameter \MEMORY_FILE = 328'0010111000101110001011110010111000101110001011110111001101101111011001100111010001110111011000010111001001100101001011110110110101100101011011010110111101110010011110010010111101110100011001010111001101110100011001010101111101110101011000010111001001110100010111110110011001110000011001110110000100101110011010000110010101111000 Parameter \GPIO_WIDHT = 6 Parameter \UART_BUFFER_SIZE = 16 Generating RTLIL representation for module `$paramod$17da5723ec326559b6c02dbd8a25e71c752daf0f\Risco_5_SOC'. Parameter \CYCLES = 20 24.3.4. Executing AST frontend in derive mode using pre-parsed AST for module `\ResetBootSystem'. Parameter \CYCLES = 20 Generating RTLIL representation for module `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100'. Parameter \WIDHT = 5 24.3.5. Executing AST frontend in derive mode using pre-parsed AST for module `\GPIOS'. Parameter \WIDHT = 5 Generating RTLIL representation for module `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000101'. Parameter \CLK_FREQ = 25000000 Parameter \BIT_RATE = 9600 Parameter \BUFFER_SIZE = 8 24.3.6. Executing AST frontend in derive mode using pre-parsed AST for module `\UART'. Parameter \CLK_FREQ = 25000000 Parameter \BIT_RATE = 9600 Parameter \BUFFER_SIZE = 8 Generating RTLIL representation for module `$paramod$65634474087d1ba2b03796f9a45556e4bd507a57\UART'. Parameter \MEMORY_FILE = { } Parameter \MEMORY_SIZE = 4096 24.3.7. Executing AST frontend in derive mode using pre-parsed AST for module `\Memory'. Parameter \MEMORY_FILE = { } Parameter \MEMORY_SIZE = 4096 Generating RTLIL representation for module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'. Parameter \BOOT_ADDRESS = 0 24.3.8. Executing AST frontend in derive mode using pre-parsed AST for module `\Core'. Parameter \BOOT_ADDRESS = 0 Generating RTLIL representation for module `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000'. Risco-5/src/core/core.v:168: Warning: Identifier `\pc_source' is implicitly declared. Reprocessing module GPIOS because instantiated module PWM has become available. Generating RTLIL representation for module `\GPIOS'. Parameter \BIT_RATE = 9600 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 24.3.9. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tool_tx'. Parameter \BIT_RATE = 9600 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 Generating RTLIL representation for module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx'. Parameter \BIT_RATE = 9600 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 24.3.10. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tool_rx'. Parameter \BIT_RATE = 9600 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 Generating RTLIL representation for module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx'. Parameter \DEPTH = 8 Parameter \WIDTH = 8 24.3.11. Executing AST frontend in derive mode using pre-parsed AST for module `\FIFO'. Parameter \DEPTH = 8 Parameter \WIDTH = 8 Generating RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'. Parameter \DEPTH = 8 Parameter \WIDTH = 8 Found cached RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'. 24.3.12. Analyzing design hierarchy.. Top module: \top Used module: $paramod$17da5723ec326559b6c02dbd8a25e71c752daf0f\Risco_5_SOC Used module: \GPIOS Used module: \GPIO Used module: \PWM Used module: \UART Used module: $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx Used module: $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx Used module: $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO Used module: \LEDs Used module: \BUS Used module: \Memory Used module: \Core Used module: \CSR_Unit Used module: \Immediate_Generator Used module: \Alu Used module: \ALU_Control Used module: \Control_Unit Used module: \Registers Used module: \MUX Used module: \PC Used module: $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100 Parameter \WIDHT = 6 24.3.13. Executing AST frontend in derive mode using pre-parsed AST for module `\GPIOS'. Parameter \WIDHT = 6 Generating RTLIL representation for module `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110'. Parameter \CLK_FREQ = 25000000 Parameter \BIT_RATE = 115200 Parameter \BUFFER_SIZE = 16 24.3.14. Executing AST frontend in derive mode using pre-parsed AST for module `\UART'. Parameter \CLK_FREQ = 25000000 Parameter \BIT_RATE = 115200 Parameter \BUFFER_SIZE = 16 Generating RTLIL representation for module `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART'. Parameter \MEMORY_FILE = 328'0010111000101110001011110010111000101110001011110111001101101111011001100111010001110111011000010111001001100101001011110110110101100101011011010110111101110010011110010010111101110100011001010111001101110100011001010101111101110101011000010111001001110100010111110110011001110000011001110110000100101110011010000110010101111000 Parameter \MEMORY_SIZE = 2048 24.3.15. Executing AST frontend in derive mode using pre-parsed AST for module `\Memory'. Parameter \MEMORY_FILE = 328'0010111000101110001011110010111000101110001011110111001101101111011001100111010001110111011000010111001001100101001011110110110101100101011011010110111101110010011110010010111101110100011001010111001101110100011001010101111101110101011000010111001001110100010111110110011001110000011001110110000100101110011010000110010101111000 Parameter \MEMORY_SIZE = 2048 Generating RTLIL representation for module `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory'. Parameter \BOOT_ADDRESS = 0 Found cached RTLIL representation for module `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000'. 24.3.16. Analyzing design hierarchy.. Top module: \top Used module: $paramod$17da5723ec326559b6c02dbd8a25e71c752daf0f\Risco_5_SOC Used module: $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110 Used module: \GPIO Used module: \PWM Used module: $paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART Used module: \uart_tool_tx Used module: \uart_tool_rx Used module: \FIFO Used module: \LEDs Used module: \BUS Used module: $paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory Used module: $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000 Used module: \CSR_Unit Used module: \Immediate_Generator Used module: \Alu Used module: \ALU_Control Used module: \Control_Unit Used module: \Registers Used module: \MUX Used module: \PC Used module: $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100 Parameter \BIT_RATE = 115200 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 24.3.17. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tool_tx'. Parameter \BIT_RATE = 115200 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 Generating RTLIL representation for module `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx'. Parameter \BIT_RATE = 115200 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 24.3.18. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tool_rx'. Parameter \BIT_RATE = 115200 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 Generating RTLIL representation for module `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx'. Parameter \DEPTH = 16 Parameter \WIDTH = 8 24.3.19. Executing AST frontend in derive mode using pre-parsed AST for module `\FIFO'. Parameter \DEPTH = 16 Parameter \WIDTH = 8 Generating RTLIL representation for module `$paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO'. Parameter \DEPTH = 16 Parameter \WIDTH = 8 Found cached RTLIL representation for module `$paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO'. 24.3.20. Analyzing design hierarchy.. Top module: \top Used module: $paramod$17da5723ec326559b6c02dbd8a25e71c752daf0f\Risco_5_SOC Used module: $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110 Used module: \GPIO Used module: \PWM Used module: $paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART Used module: $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx Used module: $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx Used module: $paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO Used module: \LEDs Used module: \BUS Used module: $paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory Used module: $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000 Used module: \CSR_Unit Used module: \Immediate_Generator Used module: \Alu Used module: \ALU_Control Used module: \Control_Unit Used module: \Registers Used module: \MUX Used module: \PC Used module: $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100 24.3.21. Analyzing design hierarchy.. Top module: \top Used module: $paramod$17da5723ec326559b6c02dbd8a25e71c752daf0f\Risco_5_SOC Used module: $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110 Used module: \GPIO Used module: \PWM Used module: $paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART Used module: $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx Used module: $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx Used module: $paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO Used module: \LEDs Used module: \BUS Used module: $paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory Used module: $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000 Used module: \CSR_Unit Used module: \Immediate_Generator Used module: \Alu Used module: \ALU_Control Used module: \Control_Unit Used module: \Registers Used module: \MUX Used module: \PC Used module: $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100 Removing unused module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx'. Removing unused module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx'. Removing unused module `\GPIOS'. Removing unused module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'. Removing unused module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'. Removing unused module `$paramod$65634474087d1ba2b03796f9a45556e4bd507a57\UART'. Removing unused module `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000101'. Removing unused module `\uart_tool_tx'. Removing unused module `\uart_tool_rx'. Removing unused module `\UART'. Removing unused module `\Risco_5_SOC'. Removing unused module `\Memory'. Removing unused module `\FIFO'. Removing unused module `\Core'. Removing unused module `\ResetBootSystem'. Removed 15 unused modules. 24.4. Executing PROC pass (convert processes to netlists). 24.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$692'. Found and cleaned up 1 empty switch in `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$proc$Risco-5/src/peripheral/memory.v:0$1427'. Found and cleaned up 1 empty switch in `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:128$122'. Cleaned up 3 empty switches. 24.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$799 in module TRELLIS_FF. Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$751 in module DPR16X4C. Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$693 in module TRELLIS_DPR16X4. Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:189$1520 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx. Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:178$1518 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx. Marked 2 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:163$1510 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx. Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:152$1507 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx. Marked 2 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:140$1501 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx. Marked 3 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:125$1496 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx. Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:108$1491 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx. Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:89$1482 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx. Marked 4 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:167$1469 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx. Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:156$1467 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx. Marked 2 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:141$1459 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx. Marked 4 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:124$1445 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx. Marked 3 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:109$1439 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx. Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:92$1434 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx. Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/memory.v:59$1425 in module $paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory. Marked 3 switch rules as full_case in process $proc$Risco-5/src/peripheral/memory.v:47$1388 in module $paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory. Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart.v:158$1369 in module $paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART. Marked 7 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart.v:64$1361 in module $paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART. Marked 3 switch rules as full_case in process $proc$Risco-5/src/peripheral/pwm.v:11$456 in module PWM. Marked 3 switch rules as full_case in process $proc$Risco-5/src/peripheral/gpios.v:61$1291 in module $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110. Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/leds.v:23$405 in module LEDs. Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/core.v:273$977 in module $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000. Marked 2 switch rules as full_case in process $proc$Risco-5/src/peripheral/fifo.v:28$1525 in module $paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO. Marked 2 switch rules as full_case in process $proc$Risco-5/src/core/registers.v:24$156 in module Registers. Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/pc.v:15$145 in module PC. Marked 2 switch rules as full_case in process $proc$Risco-5/src/core/immediate_generator.v:18$128 in module Immediate_Generator. Marked 2 switch rules as full_case in process $proc$Risco-5/src/core/csr_unit.v:128$122 in module CSR_Unit. Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/csr_unit.v:104$120 in module CSR_Unit. Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/csr_unit.v:76$119 in module CSR_Unit. Marked 5 switch rules as full_case in process $proc$Risco-5/debug/reset.v:24$802 in module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100. Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/control_unit.v:683$86 in module Control_Unit. Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/control_unit.v:673$85 in module Control_Unit. Marked 19 switch rules as full_case in process $proc$Risco-5/src/core/control_unit.v:152$40 in module Control_Unit. Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/control_unit.v:144$39 in module Control_Unit. Removed 1 dead cases from process $proc$Risco-5/src/core/alu_control.v:9$31 in module ALU_Control. Marked 4 switch rules as full_case in process $proc$Risco-5/src/core/alu_control.v:9$31 in module ALU_Control. Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/alu.v:26$11 in module Alu. Removed a total of 1 dead cases. 24.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 14 redundant assignments. Promoted 147 assignments to connections. 24.4.4. Executing PROC_INIT pass (extract init attributes). Found init rule in `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$800'. Set init value: \Q = 1'0 Found init rule in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:124$1522'. Set init value: \i = 0 Found init rule in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:108$1475'. Set init value: \i = 0 Found init rule in `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$proc$Risco-5/src/peripheral/memory.v:0$1427'. Set init value: \memory_response = 1'0 Found init rule in `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.$proc$Risco-5/src/peripheral/uart.v:0$1379'. Set init value: \state = 4'0000 Set init value: \counter = 3'000 Set init value: \read_data = 0 Set init value: \response = 1'0 Set init value: \uart_tx_en = 1'0 Set init value: \tx_fifo_read = 1'0 Set init value: \tx_fifo_write = 1'0 Set init value: \rx_fifo_read = 1'0 Set init value: \rx_fifo_write = 1'0 Set init value: \uart_tx_data = 8'00000000 Set init value: \tx_fifo_write_data = 8'00000000 Set init value: \rx_fifo_write_data = 8'00000000 Found init rule in `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:0$1358'. Set init value: \is_pwm = 2'00 Found init rule in `\LEDs.$proc$Risco-5/src/peripheral/leds.v:0$408'. Set init value: \data = 0 Found init rule in `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:0$983'. Set init value: \instruction_register = 0 Set init value: \memory_register = 0 Set init value: \alu_out_register = 0 Set init value: \register_data_1 = 0 Set init value: \register_data_2 = 0 Set init value: \pc_old = 0 Set init value: \temp_address = 0 Set init value: \temp_reg2 = 0 Set init value: \temp_write_value = 0 Found init rule in `$paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO.$proc$Risco-5/src/peripheral/fifo.v:0$1552'. Set init value: \counter = 6'000000 Set init value: \read_ptr = 6'000000 Set init value: \write_ptr = 6'000000 Found init rule in `\PC.$proc$Risco-5/src/core/pc.v:0$148'. Set init value: \Output = 0 Found init rule in `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:0$127'. Set init value: \mepc = 0 Set init value: \mscratch = 0 Set init value: \mcause = 0 Set init value: \mtval = 0 Set init value: \mtvec = 0 Set init value: \mcycle = 64'0000000000000000000000000000000000000000000000000000000000000000 Set init value: \minstret = 64'0000000000000000000000000000000000000000000000000000000000000000 Set init value: \utime = 64'0000000000000000000000000000000000000000000000000000000000000000 Found init rule in `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:0$808'. Set init value: \reset_o = 1'0 Set init value: \state = 2'01 Set init value: \counter = 6'000000 Found init rule in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:0$87'. Set init value: \state = 6'000000 Set init value: \is_immediate = 1'0 Set init value: \pc_write = 1'0 Set init value: \ir_write = 1'0 Set init value: \pc_source = 1'0 Set init value: \reg_write = 1'0 Set init value: \memory_read = 1'0 Set init value: \memory_write = 1'0 Set init value: \pc_write_cond = 1'0 Set init value: \csr_write_enable = 1'0 Set init value: \alu_input_selector = 1'0 Set init value: \save_address = 1'0 Set init value: \save_value = 1'0 Set init value: \save_value_2 = 1'0 Set init value: \save_write_value = 1'0 Set init value: \control_memory_op = 1'0 Set init value: \write_data_in = 1'0 Set init value: \mdu_start = 1'0 Set init value: \lorD = 2'00 Set init value: \aluop = 2'00 Set init value: \alu_src_a = 3'000 Set init value: \alu_src_b = 3'000 Set init value: \memory_to_reg = 3'000 Set init value: \control_unit_memory_op = 3'010 Set init value: \control_unit_aluop = 4'0000 Set init value: \clear_hal_byte_one_block_option = 3'000 Set init value: \clear_hal_byte_one_block_option_2 = 3'000 Set init value: \nextstate = 6'000000 24.4.5. Executing PROC_ARST pass (detect async resets in processes). 24.4.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~121 debug messages> 24.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$800'. Creating decoders for process `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$799'. 1/1: $0\Q[0:0] Creating decoders for process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$774'. Creating decoders for process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$751'. 1/3: $1$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$750_EN[3:0]$757 2/3: $1$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$750_DATA[3:0]$756 3/3: $1$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$750_ADDR[3:0]$755 Creating decoders for process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$717'. Creating decoders for process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$693'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$691_EN[3:0]$699 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$691_DATA[3:0]$698 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$691_ADDR[3:0]$697 Creating decoders for process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$692'. Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:124$1522'. Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:189$1520'. 1/2: $0\rxd_reg_0[0:0] 2/2: $0\rxd_reg[0:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:178$1518'. 1/1: $0\fsm_state[2:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:163$1510'. 1/1: $0\cycle_counter[8:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:152$1507'. 1/1: $0\bit_sample[0:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:140$1501'. 1/1: $0\bit_counter[3:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:125$1496'. 1/11: $3\i[31:0] 2/11: $0\recieved_data[7:0] [1] 3/11: $0\recieved_data[7:0] [0] 4/11: $0\recieved_data[7:0] [2] 5/11: $0\recieved_data[7:0] [3] 6/11: $0\recieved_data[7:0] [4] 7/11: $0\recieved_data[7:0] [5] 8/11: $0\recieved_data[7:0] [6] 9/11: $0\recieved_data[7:0] [7] 10/11: $1\i[31:0] 11/11: $2\i[31:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:108$1491'. 1/1: $1\n_fsm_state[2:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:89$1482'. 1/1: $0\uart_rx_data[7:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:108$1475'. Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:167$1469'. 1/1: $0\txd_reg[0:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:156$1467'. 1/1: $0\fsm_state[2:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:141$1459'. 1/1: $0\cycle_counter[8:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:124$1445'. 1/1: $0\bit_counter[3:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:109$1439'. 1/11: $3\i[31:0] 2/11: $0\data_to_send[7:0] [1] 3/11: $0\data_to_send[7:0] [0] 4/11: $0\data_to_send[7:0] [2] 5/11: $0\data_to_send[7:0] [3] 6/11: $0\data_to_send[7:0] [4] 7/11: $0\data_to_send[7:0] [5] 8/11: $0\data_to_send[7:0] [6] 9/11: $0\data_to_send[7:0] [7] 10/11: $1\i[31:0] 11/11: $2\i[31:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:92$1434'. 1/1: $1\n_fsm_state[2:0] Creating decoders for process `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$proc$Risco-5/src/peripheral/memory.v:0$1427'. Creating decoders for process `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$proc$Risco-5/src/peripheral/memory.v:59$1425'. 1/1: $1\read_data[31:0] Creating decoders for process `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$proc$Risco-5/src/peripheral/memory.v:47$1388'. 1/24: $3$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1381_EN[31:0]$1423 2/24: $3$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1381_DATA[31:0]$1424 3/24: $3$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1381_ADDR[31:0]$1419 4/24: $3$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1382_ADDR[31:0]$1422 5/24: $3$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1382_DATA[31:0]$1421 6/24: $3$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1382_EN[31:0]$1420 7/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1380_EN[31:0]$1410 8/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1380_DATA[31:0]$1411 9/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1380_ADDR[31:0]$1412 10/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1381_DATA[31:0]$1417 11/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1381_EN[31:0]$1416 12/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1382_ADDR[31:0]$1415 13/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1382_DATA[31:0]$1414 14/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1382_EN[31:0]$1413 15/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1381_ADDR[31:0]$1409 16/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1381_DATA[31:0]$1407 17/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1381_EN[31:0]$1406 18/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1382_ADDR[31:0]$1405 19/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1382_DATA[31:0]$1404 20/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1382_EN[31:0]$1403 21/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1380_ADDR[31:0]$1402 22/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1380_DATA[31:0]$1401 23/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1380_EN[31:0]$1400 24/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1381_ADDR[31:0]$1399 Creating decoders for process `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$proc$Risco-5/src/peripheral/memory.v:39$1386'. 1/1: $0\memory_response[0:0] Creating decoders for process `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.$proc$Risco-5/src/peripheral/uart.v:0$1379'. Creating decoders for process `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.$proc$Risco-5/src/peripheral/uart.v:158$1369'. 1/5: $0\rx_fifo_write[0:0] 2/5: $0\tx_fifo_read[0:0] 3/5: $0\uart_tx_en[0:0] 4/5: $0\rx_fifo_write_data[7:0] 5/5: $0\uart_tx_data[7:0] Creating decoders for process `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.$proc$Risco-5/src/peripheral/uart.v:64$1361'. 1/8: $0\tx_fifo_write[0:0] 2/8: $0\rx_fifo_read[0:0] 3/8: $0\response[0:0] 4/8: $0\write_data_buffer[31:0] 5/8: $0\tx_fifo_write_data[7:0] 6/8: $0\read_data[31:0] 7/8: $0\counter[2:0] 8/8: $0\state[3:0] Creating decoders for process `\PWM.$proc$Risco-5/src/peripheral/pwm.v:11$456'. 1/2: $0\pwm_out[0:0] 2/2: $0\counter[31:0] Creating decoders for process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:0$1358'. Creating decoders for process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:61$1291'. 1/21: $3$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:71$1286_EN[15:0]$1315 2/21: $3$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:71$1286_DATA[15:0]$1314 3/21: $3$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:71$1286_ADDR[0:0]$1313 4/21: $3$memwr$\period$Risco-5/src/peripheral/gpios.v:70$1285_EN[15:0]$1312 5/21: $3$memwr$\period$Risco-5/src/peripheral/gpios.v:70$1285_DATA[15:0]$1311 6/21: $3$memwr$\period$Risco-5/src/peripheral/gpios.v:70$1285_ADDR[0:0]$1310 7/21: $2$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:71$1286_EN[15:0]$1309 8/21: $2$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:71$1286_DATA[15:0]$1308 9/21: $2$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:71$1286_ADDR[0:0]$1307 10/21: $2$memwr$\period$Risco-5/src/peripheral/gpios.v:70$1285_EN[15:0]$1306 11/21: $2$memwr$\period$Risco-5/src/peripheral/gpios.v:70$1285_DATA[15:0]$1305 12/21: $2$memwr$\period$Risco-5/src/peripheral/gpios.v:70$1285_ADDR[0:0]$1304 13/21: $1$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:71$1286_EN[15:0]$1303 14/21: $1$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:71$1286_DATA[15:0]$1302 15/21: $1$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:71$1286_ADDR[0:0]$1301 16/21: $1$memwr$\period$Risco-5/src/peripheral/gpios.v:70$1285_EN[15:0]$1300 17/21: $1$memwr$\period$Risco-5/src/peripheral/gpios.v:70$1285_DATA[15:0]$1299 18/21: $1$memwr$\period$Risco-5/src/peripheral/gpios.v:70$1285_ADDR[0:0]$1298 19/21: $0\is_pwm[1:0] 20/21: $0\gpio_value[5:0] 21/21: $0\gpio_direction[5:0] Creating decoders for process `\LEDs.$proc$Risco-5/src/peripheral/leds.v:0$408'. Creating decoders for process `\LEDs.$proc$Risco-5/src/peripheral/leds.v:23$405'. 1/1: $0\data[31:0] Creating decoders for process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:0$983'. Creating decoders for process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:273$977'. 1/10: $0\alu_out_register[31:0] 2/10: $0\register_data_2[31:0] 3/10: $0\register_data_1[31:0] 4/10: $0\memory_register[31:0] 5/10: $0\temp_write_value[31:0] 6/10: $0\temp_reg3[31:0] 7/10: $0\temp_reg2[31:0] 8/10: $0\temp_address[31:0] 9/10: $0\pc_old[31:0] 10/10: $0\instruction_register[31:0] Creating decoders for process `$paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO.$proc$Risco-5/src/peripheral/fifo.v:0$1552'. Creating decoders for process `$paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO.$proc$Risco-5/src/peripheral/fifo.v:28$1525'. 1/9: $2$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1523_EN[7:0]$1537 2/9: $2$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1523_DATA[7:0]$1536 3/9: $2$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1523_ADDR[5:0]$1535 4/9: $1$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1523_EN[7:0]$1532 5/9: $1$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1523_DATA[7:0]$1531 6/9: $1$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1523_ADDR[5:0]$1530 7/9: $0\write_ptr[5:0] 8/9: $0\read_ptr[5:0] 9/9: $0\counter[5:0] Creating decoders for process `\Registers.$proc$Risco-5/src/core/registers.v:0$174'. Creating decoders for process `\Registers.$proc$Risco-5/src/core/registers.v:24$156'. 1/9: $2$memwr$\registers$Risco-5/src/core/registers.v:28$151_EN[31:0]$171 2/9: $2$memwr$\registers$Risco-5/src/core/registers.v:28$151_DATA[31:0]$170 3/9: $2$memwr$\registers$Risco-5/src/core/registers.v:28$151_ADDR[4:0]$169 4/9: $2$memwr$\registers$Risco-5/src/core/registers.v:30$152_EN[31:0]$172 5/9: $1$memwr$\registers$Risco-5/src/core/registers.v:26$150_EN[31:0]$163 6/9: $1$memwr$\registers$Risco-5/src/core/registers.v:30$152_EN[31:0]$167 7/9: $1$memwr$\registers$Risco-5/src/core/registers.v:28$151_EN[31:0]$166 8/9: $1$memwr$\registers$Risco-5/src/core/registers.v:28$151_DATA[31:0]$165 9/9: $1$memwr$\registers$Risco-5/src/core/registers.v:28$151_ADDR[4:0]$164 Creating decoders for process `\PC.$proc$Risco-5/src/core/pc.v:0$148'. Creating decoders for process `\PC.$proc$Risco-5/src/core/pc.v:15$145'. 1/1: $0\Output[31:0] Creating decoders for process `\Immediate_Generator.$proc$Risco-5/src/core/immediate_generator.v:18$128'. 1/2: $2\immediate[31:0] 2/2: $1\immediate[31:0] Creating decoders for process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:0$127'. Creating decoders for process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:128$122'. 1/1: $0\minstret[63:0] Creating decoders for process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:104$120'. 1/7: $0\mcycle[63:0] 2/7: $0\utime[63:0] 3/7: $0\mtvec[31:0] 4/7: $0\mtval[31:0] 5/7: $0\mcause[31:0] 6/7: $0\mscratch[31:0] 7/7: $0\mepc[31:0] Creating decoders for process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:76$119'. 1/1: $0\csr_data_out[31:0] Creating decoders for process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:0$808'. Creating decoders for process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$802'. 1/3: $0\counter[5:0] 2/3: $0\state[1:0] 3/3: $0\reset_o[0:0] Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:0$87'. Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:683$86'. 1/2: $0\clear_hal_byte_one_block_option_2[2:0] 2/2: $0\clear_hal_byte_one_block_option[2:0] Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:673$85'. 1/1: $0\wb_filter[2:0] Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$72'. 1/22: $0\save_write_value[0:0] 2/22: $0\write_data_in[0:0] 3/22: $0\save_value_2[0:0] 4/22: $0\save_value[0:0] 5/22: $0\control_memory_op[0:0] 6/22: $0\save_address[0:0] 7/22: $0\control_unit_aluop[3:0] 8/22: $0\alu_input_selector[0:0] 9/22: $0\csr_write_enable[0:0] 10/22: $0\is_immediate[0:0] 11/22: $0\reg_write[0:0] 12/22: $0\alu_src_a[2:0] 13/22: $0\alu_src_b[2:0] 14/22: $0\aluop[1:0] 15/22: $0\pc_source[0:0] 16/22: $0\memory_to_reg[2:0] 17/22: $0\memory_write[0:0] 18/22: $0\memory_read[0:0] 19/22: $0\lorD[1:0] 20/22: $0\ir_write[0:0] 21/22: $0\pc_write[0:0] 22/22: $0\pc_write_cond[0:0] Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:152$40'. 1/19: $19\nextstate[5:0] 2/19: $18\nextstate[5:0] 3/19: $17\nextstate[5:0] 4/19: $16\nextstate[5:0] 5/19: $15\nextstate[5:0] 6/19: $14\nextstate[5:0] 7/19: $13\nextstate[5:0] 8/19: $12\nextstate[5:0] 9/19: $11\nextstate[5:0] 10/19: $10\nextstate[5:0] 11/19: $9\nextstate[5:0] 12/19: $8\nextstate[5:0] 13/19: $7\nextstate[5:0] 14/19: $6\nextstate[5:0] 15/19: $5\nextstate[5:0] 16/19: $4\nextstate[5:0] 17/19: $3\nextstate[5:0] 18/19: $2\nextstate[5:0] 19/19: $1\nextstate[5:0] Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:144$39'. 1/1: $0\state[5:0] Creating decoders for process `\ALU_Control.$proc$Risco-5/src/core/alu_control.v:9$31'. 1/1: $0\aluop_out[3:0] Creating decoders for process `\Alu.$proc$Risco-5/src/core/alu.v:26$11'. 1/1: $1\ALU_out_S[31:0] 24.4.8. Executing PROC_DLATCH pass (convert process syncs to latches). No latch inferred for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\n_fsm_state' from process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:108$1491'. No latch inferred for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.\n_fsm_state' from process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:92$1434'. No latch inferred for signal `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.\read_data' from process `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$proc$Risco-5/src/peripheral/memory.v:59$1425'. No latch inferred for signal `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$memwr$\period$Risco-5/src/peripheral/gpios.v:25$1283_EN' from process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:0$1358'. No latch inferred for signal `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:26$1284_EN' from process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:0$1358'. No latch inferred for signal `\Registers.$memwr$\registers$Risco-5/src/core/registers.v:17$149_EN' from process `\Registers.$proc$Risco-5/src/core/registers.v:0$174'. No latch inferred for signal `\Immediate_Generator.\immediate' from process `\Immediate_Generator.$proc$Risco-5/src/core/immediate_generator.v:18$128'. No latch inferred for signal `\CSR_Unit.\csr_data_out' from process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:76$119'. No latch inferred for signal `\Control_Unit.\clear_hal_byte_one_block_option' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:683$86'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\clear_hal_byte_one_block_option [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:683$86`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\clear_hal_byte_one_block_option [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:683$86`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\clear_hal_byte_one_block_option [2]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:683$86`. No latch inferred for signal `\Control_Unit.\clear_hal_byte_one_block_option_2' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:683$86'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\clear_hal_byte_one_block_option_2 [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:683$86`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\clear_hal_byte_one_block_option_2 [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:683$86`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\clear_hal_byte_one_block_option_2 [2]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:683$86`. No latch inferred for signal `\Control_Unit.\wb_filter' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:673$85'. No latch inferred for signal `\Control_Unit.\is_immediate' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$72'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\is_immediate` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$72`. No latch inferred for signal `\Control_Unit.\pc_write' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$72'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\pc_write` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$72`. No latch inferred for signal `\Control_Unit.\ir_write' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$72'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\ir_write` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$72`. No latch inferred for signal `\Control_Unit.\pc_source' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$72'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\pc_source` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$72`. No latch inferred for signal `\Control_Unit.\reg_write' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$72'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\reg_write` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$72`. No latch inferred for signal `\Control_Unit.\memory_read' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$72'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_read` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$72`. No latch inferred for signal `\Control_Unit.\memory_write' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$72'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_write` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$72`. No latch inferred for signal `\Control_Unit.\pc_write_cond' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$72'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\pc_write_cond` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$72`. No latch inferred for signal `\Control_Unit.\csr_write_enable' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$72'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\csr_write_enable` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$72`. No latch inferred for signal `\Control_Unit.\alu_input_selector' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$72'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_input_selector` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$72`. No latch inferred for signal `\Control_Unit.\save_address' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$72'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\save_address` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$72`. No latch inferred for signal `\Control_Unit.\save_value' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$72'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\save_value` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$72`. No latch inferred for signal `\Control_Unit.\save_value_2' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$72'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\save_value_2` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$72`. No latch inferred for signal `\Control_Unit.\save_write_value' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$72'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\save_write_value` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$72`. No latch inferred for signal `\Control_Unit.\control_memory_op' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$72'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\control_memory_op` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$72`. No latch inferred for signal `\Control_Unit.\write_data_in' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$72'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\write_data_in` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$72`. No latch inferred for signal `\Control_Unit.\mdu_start' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$72'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\mdu_start` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$72`. No latch inferred for signal `\Control_Unit.\lorD' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$72'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\lorD [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$72`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\lorD [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$72`. No latch inferred for signal `\Control_Unit.\aluop' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$72'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\aluop [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$72`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\aluop [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$72`. No latch inferred for signal `\Control_Unit.\alu_src_a' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$72'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_a [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$72`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_a [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$72`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_a [2]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$72`. No latch inferred for signal `\Control_Unit.\alu_src_b' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$72'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_b [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$72`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_b [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$72`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_b [2]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$72`. No latch inferred for signal `\Control_Unit.\memory_to_reg' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$72'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_to_reg [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$72`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_to_reg [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$72`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_to_reg [2]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$72`. No latch inferred for signal `\Control_Unit.\control_unit_memory_op' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$72'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\control_unit_memory_op [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$72`. Removing init bit 1'1 for non-memory siginal `\Control_Unit.\control_unit_memory_op [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$72`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\control_unit_memory_op [2]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$72`. No latch inferred for signal `\Control_Unit.\control_unit_aluop' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$72'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\control_unit_aluop [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$72`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\control_unit_aluop [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$72`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\control_unit_aluop [2]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$72`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\control_unit_aluop [3]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$72`. No latch inferred for signal `\Control_Unit.\nextstate' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:152$40'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:152$40`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:152$40`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [2]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:152$40`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [3]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:152$40`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [4]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:152$40`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [5]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:152$40`. No latch inferred for signal `\ALU_Control.\aluop_out' from process `\ALU_Control.$proc$Risco-5/src/core/alu_control.v:9$31'. No latch inferred for signal `\Alu.\ALU_out_S' from process `\Alu.$proc$Risco-5/src/core/alu.v:26$11'. 24.4.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `\TRELLIS_FF.\Q' using process `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$799'. created $dff cell `$procdff$3716' with positive edge clock. Creating register for signal `\DPR16X4C.\i' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$774'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$735_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$774'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$736_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$774'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$737_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$774'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$738_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$774'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$739_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$774'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$740_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$774'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$741_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$774'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$742_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$774'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$743_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$774'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$744_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$774'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$745_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$774'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$746_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$774'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$747_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$774'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$748_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$774'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$749_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$774'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$750_ADDR' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$751'. created $dff cell `$procdff$3717' with positive edge clock. Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$750_DATA' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$751'. created $dff cell `$procdff$3718' with positive edge clock. Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$750_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$751'. created $dff cell `$procdff$3719' with positive edge clock. Creating register for signal `\TRELLIS_DPR16X4.\i' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$717'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$675_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$717'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$676_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$717'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$677_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$717'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$678_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$717'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$679_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$717'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$680_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$717'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$681_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$717'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$682_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$717'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$683_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$717'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$684_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$717'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$685_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$717'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$686_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$717'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$687_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$717'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$688_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$717'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$689_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$717'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$690_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$717'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$691_ADDR' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$693'. created $dff cell `$procdff$3720' with positive edge clock. Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$691_DATA' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$693'. created $dff cell `$procdff$3721' with positive edge clock. Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$691_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$693'. created $dff cell `$procdff$3722' with positive edge clock. Creating register for signal `\TRELLIS_DPR16X4.\muxwre' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$692'. created direct connection (no actual register cell created). Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\rxd_reg' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:189$1520'. created $dff cell `$procdff$3723' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\rxd_reg_0' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:189$1520'. created $dff cell `$procdff$3724' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\fsm_state' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:178$1518'. created $dff cell `$procdff$3725' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\cycle_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:163$1510'. created $dff cell `$procdff$3726' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\bit_sample' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:152$1507'. created $dff cell `$procdff$3727' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\bit_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:140$1501'. created $dff cell `$procdff$3728' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\recieved_data' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:125$1496'. created $dff cell `$procdff$3729' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\i' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:125$1496'. created $dff cell `$procdff$3730' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\uart_rx_data' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:89$1482'. created $dff cell `$procdff$3731' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.\txd_reg' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:167$1469'. created $dff cell `$procdff$3732' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.\fsm_state' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:156$1467'. created $dff cell `$procdff$3733' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.\cycle_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:141$1459'. created $dff cell `$procdff$3734' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.\bit_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:124$1445'. created $dff cell `$procdff$3735' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.\i' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:109$1439'. created $dff cell `$procdff$3736' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.\data_to_send' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:109$1439'. created $dff cell `$procdff$3737' with positive edge clock. Creating register for signal `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1381_ADDR' using process `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$proc$Risco-5/src/peripheral/memory.v:47$1388'. created $dff cell `$procdff$3738' with positive edge clock. Creating register for signal `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1380_EN' using process `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$proc$Risco-5/src/peripheral/memory.v:47$1388'. created $dff cell `$procdff$3739' with positive edge clock. Creating register for signal `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1380_DATA' using process `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$proc$Risco-5/src/peripheral/memory.v:47$1388'. created $dff cell `$procdff$3740' with positive edge clock. Creating register for signal `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1380_ADDR' using process `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$proc$Risco-5/src/peripheral/memory.v:47$1388'. created $dff cell `$procdff$3741' with positive edge clock. Creating register for signal `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1382_EN' using process `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$proc$Risco-5/src/peripheral/memory.v:47$1388'. created $dff cell `$procdff$3742' with positive edge clock. Creating register for signal `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1382_DATA' using process `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$proc$Risco-5/src/peripheral/memory.v:47$1388'. created $dff cell `$procdff$3743' with positive edge clock. Creating register for signal `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1382_ADDR' using process `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$proc$Risco-5/src/peripheral/memory.v:47$1388'. created $dff cell `$procdff$3744' with positive edge clock. Creating register for signal `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1381_EN' using process `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$proc$Risco-5/src/peripheral/memory.v:47$1388'. created $dff cell `$procdff$3745' with positive edge clock. Creating register for signal `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1381_DATA' using process `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$proc$Risco-5/src/peripheral/memory.v:47$1388'. created $dff cell `$procdff$3746' with positive edge clock. Creating register for signal `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.\memory_response' using process `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$proc$Risco-5/src/peripheral/memory.v:39$1386'. created $dff cell `$procdff$3747' with positive edge clock. Creating register for signal `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.\uart_tx_en' using process `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.$proc$Risco-5/src/peripheral/uart.v:158$1369'. created $dff cell `$procdff$3748' with positive edge clock. Creating register for signal `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.\tx_fifo_read' using process `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.$proc$Risco-5/src/peripheral/uart.v:158$1369'. created $dff cell `$procdff$3749' with positive edge clock. Creating register for signal `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.\rx_fifo_write' using process `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.$proc$Risco-5/src/peripheral/uart.v:158$1369'. created $dff cell `$procdff$3750' with positive edge clock. Creating register for signal `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.\uart_tx_data' using process `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.$proc$Risco-5/src/peripheral/uart.v:158$1369'. created $dff cell `$procdff$3751' with positive edge clock. Creating register for signal `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.\rx_fifo_write_data' using process `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.$proc$Risco-5/src/peripheral/uart.v:158$1369'. created $dff cell `$procdff$3752' with positive edge clock. Creating register for signal `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.\state' using process `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.$proc$Risco-5/src/peripheral/uart.v:64$1361'. created $dff cell `$procdff$3753' with positive edge clock. Creating register for signal `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.\counter' using process `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.$proc$Risco-5/src/peripheral/uart.v:64$1361'. created $dff cell `$procdff$3754' with positive edge clock. Creating register for signal `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.\read_data' using process `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.$proc$Risco-5/src/peripheral/uart.v:64$1361'. created $dff cell `$procdff$3755' with positive edge clock. Creating register for signal `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.\response' using process `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.$proc$Risco-5/src/peripheral/uart.v:64$1361'. created $dff cell `$procdff$3756' with positive edge clock. Creating register for signal `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.\tx_fifo_write' using process `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.$proc$Risco-5/src/peripheral/uart.v:64$1361'. created $dff cell `$procdff$3757' with positive edge clock. Creating register for signal `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.\rx_fifo_read' using process `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.$proc$Risco-5/src/peripheral/uart.v:64$1361'. created $dff cell `$procdff$3758' with positive edge clock. Creating register for signal `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.\tx_fifo_write_data' using process `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.$proc$Risco-5/src/peripheral/uart.v:64$1361'. created $dff cell `$procdff$3759' with positive edge clock. Creating register for signal `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.\write_data_buffer' using process `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.$proc$Risco-5/src/peripheral/uart.v:64$1361'. created $dff cell `$procdff$3760' with positive edge clock. Creating register for signal `\PWM.\counter' using process `\PWM.$proc$Risco-5/src/peripheral/pwm.v:11$456'. created $dff cell `$procdff$3761' with positive edge clock. Creating register for signal `\PWM.\pwm_out' using process `\PWM.$proc$Risco-5/src/peripheral/pwm.v:11$456'. created $dff cell `$procdff$3762' with positive edge clock. Creating register for signal `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.\gpio_direction' using process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:61$1291'. created $dff cell `$procdff$3763' with positive edge clock. Creating register for signal `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.\gpio_value' using process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:61$1291'. created $dff cell `$procdff$3764' with positive edge clock. Creating register for signal `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.\is_pwm' using process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:61$1291'. created $dff cell `$procdff$3765' with positive edge clock. Creating register for signal `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$memwr$\period$Risco-5/src/peripheral/gpios.v:70$1285_ADDR' using process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:61$1291'. created $dff cell `$procdff$3766' with positive edge clock. Creating register for signal `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$memwr$\period$Risco-5/src/peripheral/gpios.v:70$1285_DATA' using process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:61$1291'. created $dff cell `$procdff$3767' with positive edge clock. Creating register for signal `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$memwr$\period$Risco-5/src/peripheral/gpios.v:70$1285_EN' using process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:61$1291'. created $dff cell `$procdff$3768' with positive edge clock. Creating register for signal `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:71$1286_ADDR' using process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:61$1291'. created $dff cell `$procdff$3769' with positive edge clock. Creating register for signal `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:71$1286_DATA' using process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:61$1291'. created $dff cell `$procdff$3770' with positive edge clock. Creating register for signal `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:71$1286_EN' using process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:61$1291'. created $dff cell `$procdff$3771' with positive edge clock. Creating register for signal `\LEDs.\data' using process `\LEDs.$proc$Risco-5/src/peripheral/leds.v:23$405'. created $dff cell `$procdff$3772' with positive edge clock. Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\instruction_register' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:273$977'. created $dff cell `$procdff$3773' with positive edge clock. Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\memory_register' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:273$977'. created $dff cell `$procdff$3774' with positive edge clock. Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\alu_out_register' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:273$977'. created $dff cell `$procdff$3775' with positive edge clock. Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\register_data_1' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:273$977'. created $dff cell `$procdff$3776' with positive edge clock. Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\register_data_2' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:273$977'. created $dff cell `$procdff$3777' with positive edge clock. Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\pc_old' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:273$977'. created $dff cell `$procdff$3778' with positive edge clock. Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\temp_address' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:273$977'. created $dff cell `$procdff$3779' with positive edge clock. Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\temp_reg2' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:273$977'. created $dff cell `$procdff$3780' with positive edge clock. Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\temp_reg3' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:273$977'. created $dff cell `$procdff$3781' with positive edge clock. Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\temp_write_value' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:273$977'. created $dff cell `$procdff$3782' with positive edge clock. Creating register for signal `$paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO.\counter' using process `$paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO.$proc$Risco-5/src/peripheral/fifo.v:28$1525'. created $dff cell `$procdff$3783' with positive edge clock. Creating register for signal `$paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO.\read_ptr' using process `$paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO.$proc$Risco-5/src/peripheral/fifo.v:28$1525'. created $dff cell `$procdff$3784' with positive edge clock. Creating register for signal `$paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO.\write_ptr' using process `$paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO.$proc$Risco-5/src/peripheral/fifo.v:28$1525'. created $dff cell `$procdff$3785' with positive edge clock. Creating register for signal `$paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO.$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1523_ADDR' using process `$paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO.$proc$Risco-5/src/peripheral/fifo.v:28$1525'. created $dff cell `$procdff$3786' with positive edge clock. Creating register for signal `$paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO.$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1523_DATA' using process `$paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO.$proc$Risco-5/src/peripheral/fifo.v:28$1525'. created $dff cell `$procdff$3787' with positive edge clock. Creating register for signal `$paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO.$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1523_EN' using process `$paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO.$proc$Risco-5/src/peripheral/fifo.v:28$1525'. created $dff cell `$procdff$3788' with positive edge clock. Creating register for signal `\Registers.$memwr$\registers$Risco-5/src/core/registers.v:26$150_EN' using process `\Registers.$proc$Risco-5/src/core/registers.v:24$156'. created $dff cell `$procdff$3789' with positive edge clock. Creating register for signal `\Registers.$memwr$\registers$Risco-5/src/core/registers.v:28$151_ADDR' using process `\Registers.$proc$Risco-5/src/core/registers.v:24$156'. created $dff cell `$procdff$3790' with positive edge clock. Creating register for signal `\Registers.$memwr$\registers$Risco-5/src/core/registers.v:28$151_DATA' using process `\Registers.$proc$Risco-5/src/core/registers.v:24$156'. created $dff cell `$procdff$3791' with positive edge clock. Creating register for signal `\Registers.$memwr$\registers$Risco-5/src/core/registers.v:28$151_EN' using process `\Registers.$proc$Risco-5/src/core/registers.v:24$156'. created $dff cell `$procdff$3792' with positive edge clock. Creating register for signal `\Registers.$memwr$\registers$Risco-5/src/core/registers.v:30$152_EN' using process `\Registers.$proc$Risco-5/src/core/registers.v:24$156'. created $dff cell `$procdff$3793' with positive edge clock. Creating register for signal `\PC.\Output' using process `\PC.$proc$Risco-5/src/core/pc.v:15$145'. created $dff cell `$procdff$3794' with positive edge clock. Creating register for signal `\CSR_Unit.\minstret' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:128$122'. created $dff cell `$procdff$3795' with positive edge clock. Creating register for signal `\CSR_Unit.\mepc' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:104$120'. created $dff cell `$procdff$3796' with positive edge clock. Creating register for signal `\CSR_Unit.\mscratch' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:104$120'. created $dff cell `$procdff$3797' with positive edge clock. Creating register for signal `\CSR_Unit.\mcause' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:104$120'. created $dff cell `$procdff$3798' with positive edge clock. Creating register for signal `\CSR_Unit.\mtval' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:104$120'. created $dff cell `$procdff$3799' with positive edge clock. Creating register for signal `\CSR_Unit.\mtvec' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:104$120'. created $dff cell `$procdff$3800' with positive edge clock. Creating register for signal `\CSR_Unit.\mcycle' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:104$120'. created $dff cell `$procdff$3801' with positive edge clock. Creating register for signal `\CSR_Unit.\utime' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:104$120'. created $dff cell `$procdff$3802' with positive edge clock. Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\reset_o' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$802'. created $dff cell `$procdff$3803' with positive edge clock. Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\state' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$802'. created $dff cell `$procdff$3804' with positive edge clock. Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\counter' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$802'. created $dff cell `$procdff$3805' with positive edge clock. Creating register for signal `\Control_Unit.\state' using process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:144$39'. created $dff cell `$procdff$3806' with positive edge clock. 24.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 24.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$800'. Found and cleaned up 2 empty switches in `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$799'. Removing empty process `TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$799'. Removing empty process `DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$774'. Found and cleaned up 1 empty switch in `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$751'. Removing empty process `TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$717'. Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$693'. Removing empty process `TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$692'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:124$1522'. Found and cleaned up 2 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:189$1520'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:189$1520'. Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:178$1518'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:178$1518'. Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:163$1510'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:163$1510'. Found and cleaned up 2 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:152$1507'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:152$1507'. Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:140$1501'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:140$1501'. Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:125$1496'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:125$1496'. Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:108$1491'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:108$1491'. Found and cleaned up 2 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:89$1482'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:89$1482'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:108$1475'. Found and cleaned up 5 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:167$1469'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:167$1469'. Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:156$1467'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:156$1467'. Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:141$1459'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:141$1459'. Found and cleaned up 5 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:124$1445'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:124$1445'. Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:109$1439'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:109$1439'. Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:92$1434'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:92$1434'. Removing empty process `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$proc$Risco-5/src/peripheral/memory.v:0$1427'. Found and cleaned up 1 empty switch in `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$proc$Risco-5/src/peripheral/memory.v:59$1425'. Removing empty process `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$proc$Risco-5/src/peripheral/memory.v:59$1425'. Found and cleaned up 3 empty switches in `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$proc$Risco-5/src/peripheral/memory.v:47$1388'. Removing empty process `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$proc$Risco-5/src/peripheral/memory.v:47$1388'. Found and cleaned up 1 empty switch in `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$proc$Risco-5/src/peripheral/memory.v:39$1386'. Removing empty process `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$proc$Risco-5/src/peripheral/memory.v:39$1386'. Removing empty process `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.$proc$Risco-5/src/peripheral/uart.v:0$1379'. Found and cleaned up 3 empty switches in `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.$proc$Risco-5/src/peripheral/uart.v:158$1369'. Removing empty process `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.$proc$Risco-5/src/peripheral/uart.v:158$1369'. Found and cleaned up 9 empty switches in `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.$proc$Risco-5/src/peripheral/uart.v:64$1361'. Removing empty process `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.$proc$Risco-5/src/peripheral/uart.v:64$1361'. Found and cleaned up 3 empty switches in `\PWM.$proc$Risco-5/src/peripheral/pwm.v:11$456'. Removing empty process `PWM.$proc$Risco-5/src/peripheral/pwm.v:11$456'. Removing empty process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:0$1358'. Found and cleaned up 3 empty switches in `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:61$1291'. Removing empty process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:61$1291'. Removing empty process `LEDs.$proc$Risco-5/src/peripheral/leds.v:0$408'. Found and cleaned up 2 empty switches in `\LEDs.$proc$Risco-5/src/peripheral/leds.v:23$405'. Removing empty process `LEDs.$proc$Risco-5/src/peripheral/leds.v:23$405'. Removing empty process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:0$983'. Found and cleaned up 6 empty switches in `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:273$977'. Removing empty process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:273$977'. Removing empty process `$paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO.$proc$Risco-5/src/peripheral/fifo.v:0$1552'. Found and cleaned up 3 empty switches in `$paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO.$proc$Risco-5/src/peripheral/fifo.v:28$1525'. Removing empty process `$paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO.$proc$Risco-5/src/peripheral/fifo.v:28$1525'. Removing empty process `Registers.$proc$Risco-5/src/core/registers.v:0$174'. Found and cleaned up 2 empty switches in `\Registers.$proc$Risco-5/src/core/registers.v:24$156'. Removing empty process `Registers.$proc$Risco-5/src/core/registers.v:24$156'. Removing empty process `PC.$proc$Risco-5/src/core/pc.v:0$148'. Found and cleaned up 2 empty switches in `\PC.$proc$Risco-5/src/core/pc.v:15$145'. Removing empty process `PC.$proc$Risco-5/src/core/pc.v:15$145'. Found and cleaned up 2 empty switches in `\Immediate_Generator.$proc$Risco-5/src/core/immediate_generator.v:18$128'. Removing empty process `Immediate_Generator.$proc$Risco-5/src/core/immediate_generator.v:18$128'. Removing empty process `CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:0$127'. Found and cleaned up 4 empty switches in `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:128$122'. Removing empty process `CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:128$122'. Found and cleaned up 3 empty switches in `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:104$120'. Removing empty process `CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:104$120'. Found and cleaned up 1 empty switch in `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:76$119'. Removing empty process `CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:76$119'. Removing empty process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:0$808'. Found and cleaned up 5 empty switches in `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$802'. Removing empty process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$802'. Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:0$87'. Found and cleaned up 1 empty switch in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:683$86'. Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:683$86'. Found and cleaned up 1 empty switch in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:673$85'. Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:673$85'. Found and cleaned up 1 empty switch in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$72'. Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$72'. Found and cleaned up 19 empty switches in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:152$40'. Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:152$40'. Found and cleaned up 1 empty switch in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:144$39'. Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:144$39'. Found and cleaned up 5 empty switches in `\ALU_Control.$proc$Risco-5/src/core/alu_control.v:9$31'. Removing empty process `ALU_Control.$proc$Risco-5/src/core/alu_control.v:9$31'. Found and cleaned up 1 empty switch in `\Alu.$proc$Risco-5/src/core/alu.v:26$11'. Removing empty process `Alu.$proc$Risco-5/src/core/alu.v:26$11'. Cleaned up 121 empty switches. 24.4.12. Executing OPT_EXPR pass (perform const folding). Optimizing module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx. <suppressed ~21 debug messages> Optimizing module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx. <suppressed ~19 debug messages> Optimizing module $paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory. <suppressed ~5 debug messages> Optimizing module $paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART. <suppressed ~17 debug messages> Optimizing module PWM. Optimizing module $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110. <suppressed ~2 debug messages> Optimizing module LEDs. <suppressed ~2 debug messages> Optimizing module $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000. <suppressed ~9 debug messages> Optimizing module GPIO. <suppressed ~1 debug messages> Optimizing module $paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO. <suppressed ~4 debug messages> Optimizing module BUS. <suppressed ~4 debug messages> Optimizing module Registers. <suppressed ~2 debug messages> Optimizing module PC. <suppressed ~2 debug messages> Optimizing module MUX. <suppressed ~1 debug messages> Optimizing module Immediate_Generator. Optimizing module CSR_Unit. <suppressed ~1 debug messages> Optimizing module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100. <suppressed ~7 debug messages> Optimizing module Control_Unit. <suppressed ~23 debug messages> Optimizing module ALU_Control. <suppressed ~4 debug messages> Optimizing module Alu. <suppressed ~1 debug messages> Optimizing module $paramod$17da5723ec326559b6c02dbd8a25e71c752daf0f\Risco_5_SOC. Optimizing module top. 24.5. Executing FLATTEN pass (flatten design). [Pipeline] sh Deleting now unused module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx. Deleting now unused module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx. Deleting now unused module $paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory. Deleting now unused module $paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART. Deleting now unused module PWM. Deleting now unused module $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110. Deleting now unused module LEDs. Deleting now unused module $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000. Deleting now unused module GPIO. Deleting now unused module $paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO. Deleting now unused module BUS. Deleting now unused module Registers. Deleting now unused module PC. Deleting now unused module MUX. Deleting now unused module Immediate_Generator. Deleting now unused module CSR_Unit. Deleting now unused module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100. Deleting now unused module Control_Unit. Deleting now unused module ALU_Control. Deleting now unused module Alu. Deleting now unused module $paramod$17da5723ec326559b6c02dbd8a25e71c752daf0f\Risco_5_SOC. <suppressed ~32 debug messages> 24.6. Executing TRIBUF pass. 24.7. Executing DEMINOUT pass (demote inout ports to input or output). 24.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~47 debug messages> 24.9. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 74 unused cells and 908 unused wires. <suppressed ~95 debug messages> 24.10. Executing CHECK pass (checking for obvious problems). Checking module top... Found and reported 0 problems. 24.11. Executing OPT pass (performing simple optimizations). 24.11.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~21 debug messages> 24.11.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~831 debug messages> Removed a total of 277 cells. 24.11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$3022. dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$3035. dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$3051. dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$3053. dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$3068. dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$3086. dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$3107. dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$3132. dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$3159. dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$3189. dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$3222. dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$3267. dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$3314. dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$3362. dead port 1/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$3412. dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$3414. dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$3464. dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$3466. dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$3515. dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$3574. dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$3626. dead port 2/2 on $mux $flatten\SOC.\Core.\Immediate_Generator.$procmux$2469. dead port 1/2 on $mux $flatten\SOC.\Core.\RegisterBank.$procmux$2420. dead port 1/2 on $mux $flatten\SOC.\Core.\RegisterBank.$procmux$2426. dead port 1/2 on $mux $flatten\SOC.\Core.\RegisterBank.$procmux$2432. dead port 1/2 on $mux $flatten\SOC.\Core.\RegisterBank.$procmux$2438. dead port 2/2 on $mux $flatten\SOC.\GPIOS.$procmux$2177. dead port 1/2 on $mux $flatten\SOC.\GPIOS.$procmux$2180. dead port 2/2 on $mux $flatten\SOC.\GPIOS.$procmux$2186. dead port 1/2 on $mux $flatten\SOC.\GPIOS.$procmux$2189. dead port 2/2 on $mux $flatten\SOC.\GPIOS.$procmux$2195. dead port 1/2 on $mux $flatten\SOC.\GPIOS.$procmux$2198. dead port 2/2 on $mux $flatten\SOC.\GPIOS.$procmux$2205. dead port 1/2 on $mux $flatten\SOC.\GPIOS.$procmux$2208. dead port 2/2 on $mux $flatten\SOC.\GPIOS.$procmux$2215. dead port 1/2 on $mux $flatten\SOC.\GPIOS.$procmux$2218. dead port 2/2 on $mux $flatten\SOC.\GPIOS.$procmux$2225. dead port 1/2 on $mux $flatten\SOC.\GPIOS.$procmux$2228. dead port 1/2 on $mux $flatten\SOC.\GPIOS.$procmux$2234. dead port 1/2 on $mux $flatten\SOC.\GPIOS.$procmux$2240. dead port 1/2 on $mux $flatten\SOC.\GPIOS.$procmux$2246. dead port 1/2 on $mux $flatten\SOC.\GPIOS.$procmux$2252. dead port 1/2 on $mux $flatten\SOC.\GPIOS.$procmux$2258. dead port 1/2 on $mux $flatten\SOC.\GPIOS.$procmux$2264. dead port 1/2 on $mux $flatten\SOC.\Memory.$procmux$1855. dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1857. dead port 1/2 on $mux $flatten\SOC.\Memory.$procmux$1864. dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1866. dead port 1/2 on $mux $flatten\SOC.\Memory.$procmux$1873. dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1875. dead port 1/2 on $mux $flatten\SOC.\Memory.$procmux$1882. dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1884. dead port 1/2 on $mux $flatten\SOC.\Memory.$procmux$1891. dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1893. dead port 1/2 on $mux $flatten\SOC.\Memory.$procmux$1900. dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1902. dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1908. dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1914. dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1920. dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1926. dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1932. dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1938. dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1944. dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1950. dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1956. dead port 1/2 on $mux $flatten\SOC.\Uart.\RX_FIFO.$procmux$2371. dead port 1/2 on $mux $flatten\SOC.\Uart.\RX_FIFO.$procmux$2377. dead port 1/2 on $mux $flatten\SOC.\Uart.\RX_FIFO.$procmux$2383. dead port 1/2 on $mux $flatten\SOC.\Uart.\TX_FIFO.$procmux$2371. dead port 1/2 on $mux $flatten\SOC.\Uart.\TX_FIFO.$procmux$2377. dead port 1/2 on $mux $flatten\SOC.\Uart.\TX_FIFO.$procmux$2383. Removed 71 multiplexer ports. <suppressed ~150 debug messages> 24.11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2845: { $flatten\SOC.\Core.\Control_Unit.$procmux$2838_CMP $auto$opt_reduce.cc:134:opt_pmux$3873 $auto$opt_reduce.cc:134:opt_pmux$3871 $auto$opt_reduce.cc:134:opt_pmux$3869 $flatten\SOC.\Core.\Control_Unit.$procmux$2760_CMP $auto$opt_reduce.cc:134:opt_pmux$3867 $flatten\SOC.\Core.\Control_Unit.$procmux$2757_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2756_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2755_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2754_CMP $auto$opt_reduce.cc:134:opt_pmux$3865 $auto$opt_reduce.cc:134:opt_pmux$3863 $auto$opt_reduce.cc:134:opt_pmux$3861 } New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2880: { $auto$opt_reduce.cc:134:opt_pmux$3875 $flatten\SOC.\Core.\Control_Unit.$procmux$2816_CMP } New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2887: $auto$opt_reduce.cc:134:opt_pmux$3877 New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2891: { $flatten\SOC.\Core.\Control_Unit.$procmux$2809_CMP $auto$opt_reduce.cc:134:opt_pmux$3879 $flatten\SOC.\Core.\Control_Unit.$procmux$2797_CMP } New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2907: $auto$opt_reduce.cc:134:opt_pmux$3881 New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2929: $auto$opt_reduce.cc:134:opt_pmux$3883 New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2948: $auto$opt_reduce.cc:134:opt_pmux$3885 New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$3007: $auto$opt_reduce.cc:134:opt_pmux$3887 New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2753: { $auto$opt_reduce.cc:134:opt_pmux$3891 $auto$opt_reduce.cc:134:opt_pmux$3889 } New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2781: $auto$opt_reduce.cc:134:opt_pmux$3893 New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$3563: { $auto$opt_reduce.cc:134:opt_pmux$3895 $flatten\SOC.\Core.\Control_Unit.$procmux$3571_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$3570_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$3569_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$3568_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$3567_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$3566_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$3565_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$3564_CMP } New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$3629: { $flatten\SOC.\Core.\Control_Unit.$procmux$2936_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2874_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2843_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2739_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2934_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2716_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2910_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2815_CMP $auto$opt_reduce.cc:134:opt_pmux$3899 $flatten\SOC.\Core.\Control_Unit.$procmux$2767_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2808_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2738_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2715_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2766_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2838_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2714_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2698_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2665_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2664_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2762_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2833_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2663_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2760_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2759_CMP $auto$opt_reduce.cc:134:opt_pmux$3897 $flatten\SOC.\Core.\Control_Unit.$procmux$2631_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2645_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2737_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2712_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2757_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2756_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2662_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2755_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2754_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2630_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2644_CMP } New ctrl vector for $pmux cell $flatten\SOC.\Core.\CSR_Unit.$procmux$2544: { $flatten\SOC.\Core.\CSR_Unit.$procmux$2561_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$2558_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$2556_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$2555_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$2554_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$2499_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$2526_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$2537_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$2516_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$2507_CMP $auto$opt_reduce.cc:134:opt_pmux$3907 $auto$opt_reduce.cc:134:opt_pmux$3905 $auto$opt_reduce.cc:134:opt_pmux$3903 $auto$opt_reduce.cc:134:opt_pmux$3901 } New ctrl vector for $pmux cell $flatten\SOC.\Core.\Immediate_Generator.$procmux$2472: { $flatten\SOC.\Core.\Control_Unit.$procmux$3568_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$3569_CMP $auto$opt_reduce.cc:134:opt_pmux$3911 $flatten\SOC.\Core.\Control_Unit.$procmux$3570_CMP $auto$opt_reduce.cc:134:opt_pmux$3909 $flatten\SOC.\Core.\Control_Unit.$procmux$3564_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$3572_CMP } Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\RegisterBank.$procmux$2417: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\SOC.\Core.\RegisterBank.$procmux$2417_Y New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Core.\RegisterBank.$procmux$2417_Y [0] New connections: $flatten\SOC.\Core.\RegisterBank.$procmux$2417_Y [31:1] = { $flatten\SOC.\Core.\RegisterBank.$procmux$2417_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2417_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2417_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2417_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2417_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2417_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2417_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2417_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2417_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2417_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2417_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2417_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2417_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2417_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2417_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2417_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2417_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2417_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2417_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2417_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2417_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2417_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2417_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2417_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2417_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2417_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2417_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2417_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2417_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2417_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2417_Y [0] } Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\RegisterBank.$procmux$2435: Old ports: A=32'11111111111111111111111111111111, B=0, Y=$flatten\SOC.\Core.\RegisterBank.$procmux$2435_Y New ports: A=1'1, B=1'0, Y=$flatten\SOC.\Core.\RegisterBank.$procmux$2435_Y [0] New connections: $flatten\SOC.\Core.\RegisterBank.$procmux$2435_Y [31:1] = { $flatten\SOC.\Core.\RegisterBank.$procmux$2435_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2435_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2435_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2435_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2435_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2435_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2435_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2435_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2435_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2435_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2435_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2435_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2435_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2435_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2435_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2435_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2435_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2435_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2435_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2435_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2435_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2435_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2435_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2435_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2435_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2435_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2435_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2435_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2435_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2435_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2435_Y [0] } Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\RegisterBank.$procmux$2441: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$150_EN[31:0]$157 New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$150_EN[31:0]$157 [0] New connections: $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$150_EN[31:0]$157 [31:1] = { $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$150_EN[31:0]$157 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$150_EN[31:0]$157 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$150_EN[31:0]$157 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$150_EN[31:0]$157 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$150_EN[31:0]$157 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$150_EN[31:0]$157 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$150_EN[31:0]$157 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$150_EN[31:0]$157 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$150_EN[31:0]$157 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$150_EN[31:0]$157 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$150_EN[31:0]$157 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$150_EN[31:0]$157 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$150_EN[31:0]$157 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$150_EN[31:0]$157 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$150_EN[31:0]$157 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$150_EN[31:0]$157 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$150_EN[31:0]$157 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$150_EN[31:0]$157 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$150_EN[31:0]$157 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$150_EN[31:0]$157 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$150_EN[31:0]$157 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$150_EN[31:0]$157 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$150_EN[31:0]$157 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$150_EN[31:0]$157 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$150_EN[31:0]$157 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$150_EN[31:0]$157 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$150_EN[31:0]$157 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$150_EN[31:0]$157 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$150_EN[31:0]$157 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$150_EN[31:0]$157 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$150_EN[31:0]$157 [0] } New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2736: $auto$opt_reduce.cc:134:opt_pmux$3913 Consolidated identical input bits for $mux cell $flatten\SOC.\GPIOS.$procmux$2175: Old ports: A=16'0000000000000000, B=16'1111111111111111, Y=$flatten\SOC.\GPIOS.$procmux$2175_Y New ports: A=1'0, B=1'1, Y=$flatten\SOC.\GPIOS.$procmux$2175_Y [0] New connections: $flatten\SOC.\GPIOS.$procmux$2175_Y [15:1] = { $flatten\SOC.\GPIOS.$procmux$2175_Y [0] $flatten\SOC.\GPIOS.$procmux$2175_Y [0] $flatten\SOC.\GPIOS.$procmux$2175_Y [0] $flatten\SOC.\GPIOS.$procmux$2175_Y [0] $flatten\SOC.\GPIOS.$procmux$2175_Y [0] $flatten\SOC.\GPIOS.$procmux$2175_Y [0] $flatten\SOC.\GPIOS.$procmux$2175_Y [0] $flatten\SOC.\GPIOS.$procmux$2175_Y [0] $flatten\SOC.\GPIOS.$procmux$2175_Y [0] $flatten\SOC.\GPIOS.$procmux$2175_Y [0] $flatten\SOC.\GPIOS.$procmux$2175_Y [0] $flatten\SOC.\GPIOS.$procmux$2175_Y [0] $flatten\SOC.\GPIOS.$procmux$2175_Y [0] $flatten\SOC.\GPIOS.$procmux$2175_Y [0] $flatten\SOC.\GPIOS.$procmux$2175_Y [0] } Consolidated identical input bits for $mux cell $flatten\SOC.\GPIOS.$procmux$2203: Old ports: A=16'0000000000000000, B=16'1111111111111111, Y=$flatten\SOC.\GPIOS.$procmux$2203_Y New ports: A=1'0, B=1'1, Y=$flatten\SOC.\GPIOS.$procmux$2203_Y [0] New connections: $flatten\SOC.\GPIOS.$procmux$2203_Y [15:1] = { $flatten\SOC.\GPIOS.$procmux$2203_Y [0] $flatten\SOC.\GPIOS.$procmux$2203_Y [0] $flatten\SOC.\GPIOS.$procmux$2203_Y [0] $flatten\SOC.\GPIOS.$procmux$2203_Y [0] $flatten\SOC.\GPIOS.$procmux$2203_Y [0] $flatten\SOC.\GPIOS.$procmux$2203_Y [0] $flatten\SOC.\GPIOS.$procmux$2203_Y [0] $flatten\SOC.\GPIOS.$procmux$2203_Y [0] $flatten\SOC.\GPIOS.$procmux$2203_Y [0] $flatten\SOC.\GPIOS.$procmux$2203_Y [0] $flatten\SOC.\GPIOS.$procmux$2203_Y [0] $flatten\SOC.\GPIOS.$procmux$2203_Y [0] $flatten\SOC.\GPIOS.$procmux$2203_Y [0] $flatten\SOC.\GPIOS.$procmux$2203_Y [0] $flatten\SOC.\GPIOS.$procmux$2203_Y [0] } New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2801: $auto$opt_reduce.cc:134:opt_pmux$3915 New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2804: $auto$opt_reduce.cc:134:opt_pmux$3917 New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2811: { $flatten\SOC.\Core.\Control_Unit.$procmux$2664_CMP $auto$opt_reduce.cc:134:opt_pmux$3929 $auto$opt_reduce.cc:134:opt_pmux$3927 $auto$opt_reduce.cc:134:opt_pmux$3925 $auto$opt_reduce.cc:134:opt_pmux$3923 $auto$opt_reduce.cc:134:opt_pmux$3921 $auto$opt_reduce.cc:134:opt_pmux$3919 } Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1852: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\SOC.\Memory.$procmux$1852_Y New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Memory.$procmux$1852_Y [0] New connections: $flatten\SOC.\Memory.$procmux$1852_Y [31:1] = { $flatten\SOC.\Memory.$procmux$1852_Y [0] $flatten\SOC.\Memory.$procmux$1852_Y [0] $flatten\SOC.\Memory.$procmux$1852_Y [0] $flatten\SOC.\Memory.$procmux$1852_Y [0] $flatten\SOC.\Memory.$procmux$1852_Y [0] $flatten\SOC.\Memory.$procmux$1852_Y [0] $flatten\SOC.\Memory.$procmux$1852_Y [0] $flatten\SOC.\Memory.$procmux$1852_Y [0] $flatten\SOC.\Memory.$procmux$1852_Y [0] $flatten\SOC.\Memory.$procmux$1852_Y [0] $flatten\SOC.\Memory.$procmux$1852_Y [0] $flatten\SOC.\Memory.$procmux$1852_Y [0] $flatten\SOC.\Memory.$procmux$1852_Y [0] $flatten\SOC.\Memory.$procmux$1852_Y [0] $flatten\SOC.\Memory.$procmux$1852_Y [0] $flatten\SOC.\Memory.$procmux$1852_Y [0] $flatten\SOC.\Memory.$procmux$1852_Y [0] $flatten\SOC.\Memory.$procmux$1852_Y [0] $flatten\SOC.\Memory.$procmux$1852_Y [0] $flatten\SOC.\Memory.$procmux$1852_Y [0] $flatten\SOC.\Memory.$procmux$1852_Y [0] $flatten\SOC.\Memory.$procmux$1852_Y [0] $flatten\SOC.\Memory.$procmux$1852_Y [0] $flatten\SOC.\Memory.$procmux$1852_Y [0] $flatten\SOC.\Memory.$procmux$1852_Y [0] $flatten\SOC.\Memory.$procmux$1852_Y [0] $flatten\SOC.\Memory.$procmux$1852_Y [0] $flatten\SOC.\Memory.$procmux$1852_Y [0] $flatten\SOC.\Memory.$procmux$1852_Y [0] $flatten\SOC.\Memory.$procmux$1852_Y [0] $flatten\SOC.\Memory.$procmux$1852_Y [0] } Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1897: Old ports: A=32'11111111111111111111111111111111, B=0, Y=$flatten\SOC.\Memory.$procmux$1897_Y New ports: A=1'1, B=1'0, Y=$flatten\SOC.\Memory.$procmux$1897_Y [0] New connections: $flatten\SOC.\Memory.$procmux$1897_Y [31:1] = { $flatten\SOC.\Memory.$procmux$1897_Y [0] $flatten\SOC.\Memory.$procmux$1897_Y [0] $flatten\SOC.\Memory.$procmux$1897_Y [0] $flatten\SOC.\Memory.$procmux$1897_Y [0] $flatten\SOC.\Memory.$procmux$1897_Y [0] $flatten\SOC.\Memory.$procmux$1897_Y [0] $flatten\SOC.\Memory.$procmux$1897_Y [0] $flatten\SOC.\Memory.$procmux$1897_Y [0] $flatten\SOC.\Memory.$procmux$1897_Y [0] $flatten\SOC.\Memory.$procmux$1897_Y [0] $flatten\SOC.\Memory.$procmux$1897_Y [0] $flatten\SOC.\Memory.$procmux$1897_Y [0] $flatten\SOC.\Memory.$procmux$1897_Y [0] $flatten\SOC.\Memory.$procmux$1897_Y [0] $flatten\SOC.\Memory.$procmux$1897_Y [0] $flatten\SOC.\Memory.$procmux$1897_Y [0] $flatten\SOC.\Memory.$procmux$1897_Y [0] $flatten\SOC.\Memory.$procmux$1897_Y [0] $flatten\SOC.\Memory.$procmux$1897_Y [0] $flatten\SOC.\Memory.$procmux$1897_Y [0] $flatten\SOC.\Memory.$procmux$1897_Y [0] $flatten\SOC.\Memory.$procmux$1897_Y [0] $flatten\SOC.\Memory.$procmux$1897_Y [0] $flatten\SOC.\Memory.$procmux$1897_Y [0] $flatten\SOC.\Memory.$procmux$1897_Y [0] $flatten\SOC.\Memory.$procmux$1897_Y [0] $flatten\SOC.\Memory.$procmux$1897_Y [0] $flatten\SOC.\Memory.$procmux$1897_Y [0] $flatten\SOC.\Memory.$procmux$1897_Y [0] $flatten\SOC.\Memory.$procmux$1897_Y [0] $flatten\SOC.\Memory.$procmux$1897_Y [0] } Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1906: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\SOC.\Memory.$procmux$1906_Y New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Memory.$procmux$1906_Y [0] New connections: $flatten\SOC.\Memory.$procmux$1906_Y [31:1] = { $flatten\SOC.\Memory.$procmux$1906_Y [0] $flatten\SOC.\Memory.$procmux$1906_Y [0] $flatten\SOC.\Memory.$procmux$1906_Y [0] $flatten\SOC.\Memory.$procmux$1906_Y [0] $flatten\SOC.\Memory.$procmux$1906_Y [0] $flatten\SOC.\Memory.$procmux$1906_Y [0] $flatten\SOC.\Memory.$procmux$1906_Y [0] $flatten\SOC.\Memory.$procmux$1906_Y [0] $flatten\SOC.\Memory.$procmux$1906_Y [0] $flatten\SOC.\Memory.$procmux$1906_Y [0] $flatten\SOC.\Memory.$procmux$1906_Y [0] $flatten\SOC.\Memory.$procmux$1906_Y [0] $flatten\SOC.\Memory.$procmux$1906_Y [0] $flatten\SOC.\Memory.$procmux$1906_Y [0] $flatten\SOC.\Memory.$procmux$1906_Y [0] $flatten\SOC.\Memory.$procmux$1906_Y [0] $flatten\SOC.\Memory.$procmux$1906_Y [0] $flatten\SOC.\Memory.$procmux$1906_Y [0] $flatten\SOC.\Memory.$procmux$1906_Y [0] $flatten\SOC.\Memory.$procmux$1906_Y [0] $flatten\SOC.\Memory.$procmux$1906_Y [0] $flatten\SOC.\Memory.$procmux$1906_Y [0] $flatten\SOC.\Memory.$procmux$1906_Y [0] $flatten\SOC.\Memory.$procmux$1906_Y [0] $flatten\SOC.\Memory.$procmux$1906_Y [0] $flatten\SOC.\Memory.$procmux$1906_Y [0] $flatten\SOC.\Memory.$procmux$1906_Y [0] $flatten\SOC.\Memory.$procmux$1906_Y [0] $flatten\SOC.\Memory.$procmux$1906_Y [0] $flatten\SOC.\Memory.$procmux$1906_Y [0] $flatten\SOC.\Memory.$procmux$1906_Y [0] } New ctrl vector for $pmux cell $flatten\SOC.\Uart.$procmux$2133: { $flatten\SOC.\Uart.$procmux$2127_CMP $flatten\SOC.\Uart.$procmux$2044_CMP $flatten\SOC.\Uart.$procmux$2069_CMP $flatten\SOC.\Uart.$procmux$2025_CMP $auto$opt_reduce.cc:134:opt_pmux$3931 $flatten\SOC.\Uart.$procmux$2051_CMP } New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2607: { $flatten\SOC.\Core.\Control_Unit.$procmux$2604_CMP $auto$opt_reduce.cc:134:opt_pmux$3933 } Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\RX_FIFO.$procmux$2368: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\SOC.\Uart.\RX_FIFO.$procmux$2368_Y New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Uart.\RX_FIFO.$procmux$2368_Y [0] New connections: $flatten\SOC.\Uart.\RX_FIFO.$procmux$2368_Y [7:1] = { $flatten\SOC.\Uart.\RX_FIFO.$procmux$2368_Y [0] $flatten\SOC.\Uart.\RX_FIFO.$procmux$2368_Y [0] $flatten\SOC.\Uart.\RX_FIFO.$procmux$2368_Y [0] $flatten\SOC.\Uart.\RX_FIFO.$procmux$2368_Y [0] $flatten\SOC.\Uart.\RX_FIFO.$procmux$2368_Y [0] $flatten\SOC.\Uart.\RX_FIFO.$procmux$2368_Y [0] $flatten\SOC.\Uart.\RX_FIFO.$procmux$2368_Y [0] } Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\TX_FIFO.$procmux$2368: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\SOC.\Uart.\TX_FIFO.$procmux$2368_Y New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Uart.\TX_FIFO.$procmux$2368_Y [0] New connections: $flatten\SOC.\Uart.\TX_FIFO.$procmux$2368_Y [7:1] = { $flatten\SOC.\Uart.\TX_FIFO.$procmux$2368_Y [0] $flatten\SOC.\Uart.\TX_FIFO.$procmux$2368_Y [0] $flatten\SOC.\Uart.\TX_FIFO.$procmux$2368_Y [0] $flatten\SOC.\Uart.\TX_FIFO.$procmux$2368_Y [0] $flatten\SOC.\Uart.\TX_FIFO.$procmux$2368_Y [0] $flatten\SOC.\Uart.\TX_FIFO.$procmux$2368_Y [0] $flatten\SOC.\Uart.\TX_FIFO.$procmux$2368_Y [0] } New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2629: $auto$opt_reduce.cc:134:opt_pmux$3935 New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2643: $auto$opt_reduce.cc:134:opt_pmux$3937 New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2661: $auto$opt_reduce.cc:134:opt_pmux$3939 New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2710: $auto$opt_reduce.cc:134:opt_pmux$3941 Optimizing cells in module \top. Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\RegisterBank.$procmux$2444: Old ports: A=$flatten\SOC.\Core.\RegisterBank.$2$memwr$\registers$Risco-5/src/core/registers.v:30$152_EN[31:0]$172, B=0, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$152_EN[31:0]$161 New ports: A=$flatten\SOC.\Core.\RegisterBank.$procmux$2435_Y [0], B=1'0, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$152_EN[31:0]$161 [0] New connections: $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$152_EN[31:0]$161 [31:1] = { $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$152_EN[31:0]$161 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$152_EN[31:0]$161 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$152_EN[31:0]$161 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$152_EN[31:0]$161 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$152_EN[31:0]$161 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$152_EN[31:0]$161 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$152_EN[31:0]$161 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$152_EN[31:0]$161 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$152_EN[31:0]$161 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$152_EN[31:0]$161 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$152_EN[31:0]$161 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$152_EN[31:0]$161 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$152_EN[31:0]$161 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$152_EN[31:0]$161 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$152_EN[31:0]$161 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$152_EN[31:0]$161 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$152_EN[31:0]$161 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$152_EN[31:0]$161 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$152_EN[31:0]$161 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$152_EN[31:0]$161 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$152_EN[31:0]$161 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$152_EN[31:0]$161 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$152_EN[31:0]$161 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$152_EN[31:0]$161 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$152_EN[31:0]$161 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$152_EN[31:0]$161 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$152_EN[31:0]$161 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$152_EN[31:0]$161 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$152_EN[31:0]$161 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$152_EN[31:0]$161 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$152_EN[31:0]$161 [0] } Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\RegisterBank.$procmux$2447: Old ports: A=$flatten\SOC.\Core.\RegisterBank.$2$memwr$\registers$Risco-5/src/core/registers.v:28$151_EN[31:0]$171, B=0, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$151_EN[31:0]$160 New ports: A=$flatten\SOC.\Core.\RegisterBank.$procmux$2417_Y [0], B=1'0, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$151_EN[31:0]$160 [0] New connections: $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$151_EN[31:0]$160 [31:1] = { $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$151_EN[31:0]$160 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$151_EN[31:0]$160 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$151_EN[31:0]$160 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$151_EN[31:0]$160 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$151_EN[31:0]$160 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$151_EN[31:0]$160 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$151_EN[31:0]$160 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$151_EN[31:0]$160 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$151_EN[31:0]$160 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$151_EN[31:0]$160 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$151_EN[31:0]$160 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$151_EN[31:0]$160 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$151_EN[31:0]$160 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$151_EN[31:0]$160 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$151_EN[31:0]$160 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$151_EN[31:0]$160 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$151_EN[31:0]$160 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$151_EN[31:0]$160 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$151_EN[31:0]$160 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$151_EN[31:0]$160 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$151_EN[31:0]$160 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$151_EN[31:0]$160 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$151_EN[31:0]$160 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$151_EN[31:0]$160 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$151_EN[31:0]$160 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$151_EN[31:0]$160 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$151_EN[31:0]$160 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$151_EN[31:0]$160 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$151_EN[31:0]$160 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$151_EN[31:0]$160 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$151_EN[31:0]$160 [0] } Consolidated identical input bits for $mux cell $flatten\SOC.\GPIOS.$procmux$2231: Old ports: A=16'0000000000000000, B=$flatten\SOC.\GPIOS.$3$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:71$1286_EN[15:0]$1315, Y=$flatten\SOC.\GPIOS.$procmux$2231_Y New ports: A=1'0, B=$flatten\SOC.\GPIOS.$procmux$2175_Y [0], Y=$flatten\SOC.\GPIOS.$procmux$2231_Y [0] New connections: $flatten\SOC.\GPIOS.$procmux$2231_Y [15:1] = { $flatten\SOC.\GPIOS.$procmux$2231_Y [0] $flatten\SOC.\GPIOS.$procmux$2231_Y [0] $flatten\SOC.\GPIOS.$procmux$2231_Y [0] $flatten\SOC.\GPIOS.$procmux$2231_Y [0] $flatten\SOC.\GPIOS.$procmux$2231_Y [0] $flatten\SOC.\GPIOS.$procmux$2231_Y [0] $flatten\SOC.\GPIOS.$procmux$2231_Y [0] $flatten\SOC.\GPIOS.$procmux$2231_Y [0] $flatten\SOC.\GPIOS.$procmux$2231_Y [0] $flatten\SOC.\GPIOS.$procmux$2231_Y [0] $flatten\SOC.\GPIOS.$procmux$2231_Y [0] $flatten\SOC.\GPIOS.$procmux$2231_Y [0] $flatten\SOC.\GPIOS.$procmux$2231_Y [0] $flatten\SOC.\GPIOS.$procmux$2231_Y [0] $flatten\SOC.\GPIOS.$procmux$2231_Y [0] } Consolidated identical input bits for $mux cell $flatten\SOC.\GPIOS.$procmux$2249: Old ports: A=16'0000000000000000, B=$flatten\SOC.\GPIOS.$3$memwr$\period$Risco-5/src/peripheral/gpios.v:70$1285_EN[15:0]$1312, Y=$flatten\SOC.\GPIOS.$procmux$2249_Y New ports: A=1'0, B=$flatten\SOC.\GPIOS.$procmux$2203_Y [0], Y=$flatten\SOC.\GPIOS.$procmux$2249_Y [0] New connections: $flatten\SOC.\GPIOS.$procmux$2249_Y [15:1] = { $flatten\SOC.\GPIOS.$procmux$2249_Y [0] $flatten\SOC.\GPIOS.$procmux$2249_Y [0] $flatten\SOC.\GPIOS.$procmux$2249_Y [0] $flatten\SOC.\GPIOS.$procmux$2249_Y [0] $flatten\SOC.\GPIOS.$procmux$2249_Y [0] $flatten\SOC.\GPIOS.$procmux$2249_Y [0] $flatten\SOC.\GPIOS.$procmux$2249_Y [0] $flatten\SOC.\GPIOS.$procmux$2249_Y [0] $flatten\SOC.\GPIOS.$procmux$2249_Y [0] $flatten\SOC.\GPIOS.$procmux$2249_Y [0] $flatten\SOC.\GPIOS.$procmux$2249_Y [0] $flatten\SOC.\GPIOS.$procmux$2249_Y [0] $flatten\SOC.\GPIOS.$procmux$2249_Y [0] $flatten\SOC.\GPIOS.$procmux$2249_Y [0] $flatten\SOC.\GPIOS.$procmux$2249_Y [0] } Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1930: Old ports: A=$flatten\SOC.\Memory.$3$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1381_EN[31:0]$1423, B=0, Y=$flatten\SOC.\Memory.$procmux$1930_Y New ports: A=$flatten\SOC.\Memory.$procmux$1852_Y [0], B=1'0, Y=$flatten\SOC.\Memory.$procmux$1930_Y [0] New connections: $flatten\SOC.\Memory.$procmux$1930_Y [31:1] = { $flatten\SOC.\Memory.$procmux$1930_Y [0] $flatten\SOC.\Memory.$procmux$1930_Y [0] $flatten\SOC.\Memory.$procmux$1930_Y [0] $flatten\SOC.\Memory.$procmux$1930_Y [0] $flatten\SOC.\Memory.$procmux$1930_Y [0] $flatten\SOC.\Memory.$procmux$1930_Y [0] $flatten\SOC.\Memory.$procmux$1930_Y [0] $flatten\SOC.\Memory.$procmux$1930_Y [0] $flatten\SOC.\Memory.$procmux$1930_Y [0] $flatten\SOC.\Memory.$procmux$1930_Y [0] $flatten\SOC.\Memory.$procmux$1930_Y [0] $flatten\SOC.\Memory.$procmux$1930_Y [0] $flatten\SOC.\Memory.$procmux$1930_Y [0] $flatten\SOC.\Memory.$procmux$1930_Y [0] $flatten\SOC.\Memory.$procmux$1930_Y [0] $flatten\SOC.\Memory.$procmux$1930_Y [0] $flatten\SOC.\Memory.$procmux$1930_Y [0] $flatten\SOC.\Memory.$procmux$1930_Y [0] $flatten\SOC.\Memory.$procmux$1930_Y [0] $flatten\SOC.\Memory.$procmux$1930_Y [0] $flatten\SOC.\Memory.$procmux$1930_Y [0] $flatten\SOC.\Memory.$procmux$1930_Y [0] $flatten\SOC.\Memory.$procmux$1930_Y [0] $flatten\SOC.\Memory.$procmux$1930_Y [0] $flatten\SOC.\Memory.$procmux$1930_Y [0] $flatten\SOC.\Memory.$procmux$1930_Y [0] $flatten\SOC.\Memory.$procmux$1930_Y [0] $flatten\SOC.\Memory.$procmux$1930_Y [0] $flatten\SOC.\Memory.$procmux$1930_Y [0] $flatten\SOC.\Memory.$procmux$1930_Y [0] $flatten\SOC.\Memory.$procmux$1930_Y [0] } Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1948: Old ports: A=$flatten\SOC.\Memory.$3$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1382_EN[31:0]$1420, B=0, Y=$flatten\SOC.\Memory.$procmux$1948_Y New ports: A=$flatten\SOC.\Memory.$procmux$1897_Y [0], B=1'0, Y=$flatten\SOC.\Memory.$procmux$1948_Y [0] New connections: $flatten\SOC.\Memory.$procmux$1948_Y [31:1] = { $flatten\SOC.\Memory.$procmux$1948_Y [0] $flatten\SOC.\Memory.$procmux$1948_Y [0] $flatten\SOC.\Memory.$procmux$1948_Y [0] $flatten\SOC.\Memory.$procmux$1948_Y [0] $flatten\SOC.\Memory.$procmux$1948_Y [0] $flatten\SOC.\Memory.$procmux$1948_Y [0] $flatten\SOC.\Memory.$procmux$1948_Y [0] $flatten\SOC.\Memory.$procmux$1948_Y [0] $flatten\SOC.\Memory.$procmux$1948_Y [0] $flatten\SOC.\Memory.$procmux$1948_Y [0] $flatten\SOC.\Memory.$procmux$1948_Y [0] $flatten\SOC.\Memory.$procmux$1948_Y [0] $flatten\SOC.\Memory.$procmux$1948_Y [0] $flatten\SOC.\Memory.$procmux$1948_Y [0] $flatten\SOC.\Memory.$procmux$1948_Y [0] $flatten\SOC.\Memory.$procmux$1948_Y [0] $flatten\SOC.\Memory.$procmux$1948_Y [0] $flatten\SOC.\Memory.$procmux$1948_Y [0] $flatten\SOC.\Memory.$procmux$1948_Y [0] $flatten\SOC.\Memory.$procmux$1948_Y [0] $flatten\SOC.\Memory.$procmux$1948_Y [0] $flatten\SOC.\Memory.$procmux$1948_Y [0] $flatten\SOC.\Memory.$procmux$1948_Y [0] $flatten\SOC.\Memory.$procmux$1948_Y [0] $flatten\SOC.\Memory.$procmux$1948_Y [0] $flatten\SOC.\Memory.$procmux$1948_Y [0] $flatten\SOC.\Memory.$procmux$1948_Y [0] $flatten\SOC.\Memory.$procmux$1948_Y [0] $flatten\SOC.\Memory.$procmux$1948_Y [0] $flatten\SOC.\Memory.$procmux$1948_Y [0] $flatten\SOC.\Memory.$procmux$1948_Y [0] } Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1980: Old ports: A=0, B=$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1380_EN[31:0]$1410, Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1380_EN[31:0]$1390 New ports: A=1'0, B=$flatten\SOC.\Memory.$procmux$1906_Y [0], Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1380_EN[31:0]$1390 [0] New connections: $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1380_EN[31:0]$1390 [31:1] = { $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1380_EN[31:0]$1390 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1380_EN[31:0]$1390 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1380_EN[31:0]$1390 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1380_EN[31:0]$1390 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1380_EN[31:0]$1390 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1380_EN[31:0]$1390 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1380_EN[31:0]$1390 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1380_EN[31:0]$1390 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1380_EN[31:0]$1390 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1380_EN[31:0]$1390 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1380_EN[31:0]$1390 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1380_EN[31:0]$1390 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1380_EN[31:0]$1390 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1380_EN[31:0]$1390 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1380_EN[31:0]$1390 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1380_EN[31:0]$1390 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1380_EN[31:0]$1390 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1380_EN[31:0]$1390 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1380_EN[31:0]$1390 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1380_EN[31:0]$1390 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1380_EN[31:0]$1390 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1380_EN[31:0]$1390 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1380_EN[31:0]$1390 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1380_EN[31:0]$1390 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1380_EN[31:0]$1390 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1380_EN[31:0]$1390 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1380_EN[31:0]$1390 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1380_EN[31:0]$1390 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1380_EN[31:0]$1390 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1380_EN[31:0]$1390 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1380_EN[31:0]$1390 [0] } Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\RX_FIFO.$procmux$2386: Old ports: A=$flatten\SOC.\Uart.\RX_FIFO.$2$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1523_EN[7:0]$1537, B=8'00000000, Y=$flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1523_EN[7:0]$1528 New ports: A=$flatten\SOC.\Uart.\RX_FIFO.$procmux$2368_Y [0], B=1'0, Y=$flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1523_EN[7:0]$1528 [0] New connections: $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1523_EN[7:0]$1528 [7:1] = { $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1523_EN[7:0]$1528 [0] $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1523_EN[7:0]$1528 [0] $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1523_EN[7:0]$1528 [0] $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1523_EN[7:0]$1528 [0] $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1523_EN[7:0]$1528 [0] $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1523_EN[7:0]$1528 [0] $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1523_EN[7:0]$1528 [0] } Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\TX_FIFO.$procmux$2386: Old ports: A=$flatten\SOC.\Uart.\TX_FIFO.$2$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1523_EN[7:0]$1537, B=8'00000000, Y=$flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1523_EN[7:0]$1528 New ports: A=$flatten\SOC.\Uart.\TX_FIFO.$procmux$2368_Y [0], B=1'0, Y=$flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1523_EN[7:0]$1528 [0] New connections: $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1523_EN[7:0]$1528 [7:1] = { $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1523_EN[7:0]$1528 [0] $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1523_EN[7:0]$1528 [0] $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1523_EN[7:0]$1528 [0] $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1523_EN[7:0]$1528 [0] $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1523_EN[7:0]$1528 [0] $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1523_EN[7:0]$1528 [0] $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1523_EN[7:0]$1528 [0] } Optimizing cells in module \top. Consolidated identical input bits for $mux cell $flatten\SOC.\GPIOS.$procmux$2267: Old ports: A=$flatten\SOC.\GPIOS.$2$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:71$1286_EN[15:0]$1309, B=16'0000000000000000, Y=$flatten\SOC.\GPIOS.$0$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:71$1286_EN[15:0]$1297 New ports: A=$flatten\SOC.\GPIOS.$procmux$2231_Y [0], B=1'0, Y=$flatten\SOC.\GPIOS.$0$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:71$1286_EN[15:0]$1297 [0] New connections: $flatten\SOC.\GPIOS.$0$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:71$1286_EN[15:0]$1297 [15:1] = { $flatten\SOC.\GPIOS.$0$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:71$1286_EN[15:0]$1297 [0] $flatten\SOC.\GPIOS.$0$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:71$1286_EN[15:0]$1297 [0] $flatten\SOC.\GPIOS.$0$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:71$1286_EN[15:0]$1297 [0] $flatten\SOC.\GPIOS.$0$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:71$1286_EN[15:0]$1297 [0] $flatten\SOC.\GPIOS.$0$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:71$1286_EN[15:0]$1297 [0] $flatten\SOC.\GPIOS.$0$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:71$1286_EN[15:0]$1297 [0] $flatten\SOC.\GPIOS.$0$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:71$1286_EN[15:0]$1297 [0] $flatten\SOC.\GPIOS.$0$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:71$1286_EN[15:0]$1297 [0] $flatten\SOC.\GPIOS.$0$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:71$1286_EN[15:0]$1297 [0] $flatten\SOC.\GPIOS.$0$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:71$1286_EN[15:0]$1297 [0] $flatten\SOC.\GPIOS.$0$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:71$1286_EN[15:0]$1297 [0] $flatten\SOC.\GPIOS.$0$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:71$1286_EN[15:0]$1297 [0] $flatten\SOC.\GPIOS.$0$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:71$1286_EN[15:0]$1297 [0] $flatten\SOC.\GPIOS.$0$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:71$1286_EN[15:0]$1297 [0] $flatten\SOC.\GPIOS.$0$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:71$1286_EN[15:0]$1297 [0] } Consolidated identical input bits for $mux cell $flatten\SOC.\GPIOS.$procmux$2276: Old ports: A=$flatten\SOC.\GPIOS.$2$memwr$\period$Risco-5/src/peripheral/gpios.v:70$1285_EN[15:0]$1306, B=16'0000000000000000, Y=$flatten\SOC.\GPIOS.$0$memwr$\period$Risco-5/src/peripheral/gpios.v:70$1285_EN[15:0]$1294 New ports: A=$flatten\SOC.\GPIOS.$procmux$2249_Y [0], B=1'0, Y=$flatten\SOC.\GPIOS.$0$memwr$\period$Risco-5/src/peripheral/gpios.v:70$1285_EN[15:0]$1294 [0] New connections: $flatten\SOC.\GPIOS.$0$memwr$\period$Risco-5/src/peripheral/gpios.v:70$1285_EN[15:0]$1294 [15:1] = { $flatten\SOC.\GPIOS.$0$memwr$\period$Risco-5/src/peripheral/gpios.v:70$1285_EN[15:0]$1294 [0] $flatten\SOC.\GPIOS.$0$memwr$\period$Risco-5/src/peripheral/gpios.v:70$1285_EN[15:0]$1294 [0] $flatten\SOC.\GPIOS.$0$memwr$\period$Risco-5/src/peripheral/gpios.v:70$1285_EN[15:0]$1294 [0] $flatten\SOC.\GPIOS.$0$memwr$\period$Risco-5/src/peripheral/gpios.v:70$1285_EN[15:0]$1294 [0] $flatten\SOC.\GPIOS.$0$memwr$\period$Risco-5/src/peripheral/gpios.v:70$1285_EN[15:0]$1294 [0] $flatten\SOC.\GPIOS.$0$memwr$\period$Risco-5/src/peripheral/gpios.v:70$1285_EN[15:0]$1294 [0] $flatten\SOC.\GPIOS.$0$memwr$\period$Risco-5/src/peripheral/gpios.v:70$1285_EN[15:0]$1294 [0] $flatten\SOC.\GPIOS.$0$memwr$\period$Risco-5/src/peripheral/gpios.v:70$1285_EN[15:0]$1294 [0] $flatten\SOC.\GPIOS.$0$memwr$\period$Risco-5/src/peripheral/gpios.v:70$1285_EN[15:0]$1294 [0] $flatten\SOC.\GPIOS.$0$memwr$\period$Risco-5/src/peripheral/gpios.v:70$1285_EN[15:0]$1294 [0] $flatten\SOC.\GPIOS.$0$memwr$\period$Risco-5/src/peripheral/gpios.v:70$1285_EN[15:0]$1294 [0] $flatten\SOC.\GPIOS.$0$memwr$\period$Risco-5/src/peripheral/gpios.v:70$1285_EN[15:0]$1294 [0] $flatten\SOC.\GPIOS.$0$memwr$\period$Risco-5/src/peripheral/gpios.v:70$1285_EN[15:0]$1294 [0] $flatten\SOC.\GPIOS.$0$memwr$\period$Risco-5/src/peripheral/gpios.v:70$1285_EN[15:0]$1294 [0] $flatten\SOC.\GPIOS.$0$memwr$\period$Risco-5/src/peripheral/gpios.v:70$1285_EN[15:0]$1294 [0] } Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1962: Old ports: A=0, B=$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1381_EN[31:0]$1416, Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1381_EN[31:0]$1396 New ports: A=1'0, B=$flatten\SOC.\Memory.$procmux$1930_Y [0], Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1381_EN[31:0]$1396 [0] New connections: $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1381_EN[31:0]$1396 [31:1] = { $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1381_EN[31:0]$1396 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1381_EN[31:0]$1396 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1381_EN[31:0]$1396 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1381_EN[31:0]$1396 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1381_EN[31:0]$1396 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1381_EN[31:0]$1396 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1381_EN[31:0]$1396 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1381_EN[31:0]$1396 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1381_EN[31:0]$1396 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1381_EN[31:0]$1396 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1381_EN[31:0]$1396 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1381_EN[31:0]$1396 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1381_EN[31:0]$1396 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1381_EN[31:0]$1396 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1381_EN[31:0]$1396 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1381_EN[31:0]$1396 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1381_EN[31:0]$1396 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1381_EN[31:0]$1396 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1381_EN[31:0]$1396 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1381_EN[31:0]$1396 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1381_EN[31:0]$1396 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1381_EN[31:0]$1396 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1381_EN[31:0]$1396 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1381_EN[31:0]$1396 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1381_EN[31:0]$1396 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1381_EN[31:0]$1396 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1381_EN[31:0]$1396 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1381_EN[31:0]$1396 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1381_EN[31:0]$1396 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1381_EN[31:0]$1396 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1381_EN[31:0]$1396 [0] } Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1971: Old ports: A=0, B=$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1382_EN[31:0]$1413, Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1382_EN[31:0]$1393 New ports: A=1'0, B=$flatten\SOC.\Memory.$procmux$1948_Y [0], Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1382_EN[31:0]$1393 [0] New connections: $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1382_EN[31:0]$1393 [31:1] = { $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1382_EN[31:0]$1393 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1382_EN[31:0]$1393 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1382_EN[31:0]$1393 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1382_EN[31:0]$1393 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1382_EN[31:0]$1393 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1382_EN[31:0]$1393 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1382_EN[31:0]$1393 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1382_EN[31:0]$1393 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1382_EN[31:0]$1393 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1382_EN[31:0]$1393 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1382_EN[31:0]$1393 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1382_EN[31:0]$1393 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1382_EN[31:0]$1393 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1382_EN[31:0]$1393 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1382_EN[31:0]$1393 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1382_EN[31:0]$1393 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1382_EN[31:0]$1393 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1382_EN[31:0]$1393 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1382_EN[31:0]$1393 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1382_EN[31:0]$1393 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1382_EN[31:0]$1393 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1382_EN[31:0]$1393 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1382_EN[31:0]$1393 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1382_EN[31:0]$1393 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1382_EN[31:0]$1393 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1382_EN[31:0]$1393 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1382_EN[31:0]$1393 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1382_EN[31:0]$1393 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1382_EN[31:0]$1393 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1382_EN[31:0]$1393 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1382_EN[31:0]$1393 [0] } Optimizing cells in module \top. Performed a total of 47 changes. 24.11.5. Executing OPT_MERGE pass (detect identical cells). + mkdir -p Risco-5/impl/pnr Finding identical cells in module `\top'. <suppressed ~24 debug messages> Removed a total of 8 cells. 24.11.6. Executing OPT_DFF pass (perform DFF optimizations). 24.11.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 378 unused wires. <suppressed ~1 debug messages> 24.11.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 24.11.9. Rerunning OPT passes. (Maybe there is more to do..) 24.11.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~149 debug messages> 24.11.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. New ctrl vector for $pmux cell $flatten\SOC.\Core.\Alu.$procmux$3701: { $flatten\SOC.\Core.\Alu.$procmux$3715_CMP $flatten\SOC.\Core.\Alu.$procmux$3714_CMP $flatten\SOC.\Core.\Alu.$procmux$3713_CMP $flatten\SOC.\Core.\Alu.$procmux$3712_CMP $auto$opt_reduce.cc:134:opt_pmux$3945 $flatten\SOC.\Core.\Alu.$procmux$3709_CMP $flatten\SOC.\Core.\Alu.$procmux$3708_CMP $flatten\SOC.\Core.\Alu.$procmux$3707_CMP $flatten\SOC.\Core.\Alu.$procmux$3706_CMP $flatten\SOC.\Core.\Alu.$procmux$3705_CMP $flatten\SOC.\Core.\Alu.$procmux$3704_CMP $auto$opt_reduce.cc:134:opt_pmux$3943 } New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2845: { $flatten\SOC.\Core.\Control_Unit.$procmux$2838_CMP $auto$opt_reduce.cc:134:opt_pmux$3873 $auto$opt_reduce.cc:134:opt_pmux$3871 $auto$opt_reduce.cc:134:opt_pmux$3869 $flatten\SOC.\Core.\Control_Unit.$procmux$2760_CMP $auto$opt_reduce.cc:134:opt_pmux$3867 $auto$opt_reduce.cc:134:opt_pmux$3949 $auto$opt_reduce.cc:134:opt_pmux$3947 $auto$opt_reduce.cc:134:opt_pmux$3865 $auto$opt_reduce.cc:134:opt_pmux$3863 $auto$opt_reduce.cc:134:opt_pmux$3861 } New ctrl vector for $pmux cell $flatten\SOC.\Uart.$procmux$2133: { $flatten\SOC.\Uart.$procmux$2127_CMP $flatten\SOC.\Uart.$procmux$2069_CMP $auto$opt_reduce.cc:134:opt_pmux$3951 $auto$opt_reduce.cc:134:opt_pmux$3931 $flatten\SOC.\Uart.$procmux$2051_CMP } Optimizing cells in module \top. Performed a total of 3 changes. 24.11.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 24.11.13. Executing OPT_DFF pass (perform DFF optimizations). 24.11.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 24.11.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 24.11.16. Rerunning OPT passes. (Maybe there is more to do..) 24.11.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~149 debug messages> 24.11.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 24.11.19. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 24.11.20. Executing OPT_DFF pass (perform DFF optimizations). 24.11.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 24.11.22. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 24.11.23. Finished OPT passes. (There is nothing left to do.) 24.12. Executing FSM pass (extract and optimize FSM). 24.12.1. Executing FSM_DETECT pass (finding FSMs in design). Not marking top.ResetBootSystem.state as FSM state register: Register has an initialization value. Circuit seems to be self-resetting. Not marking top.SOC.Core.CSR_Unit.utime as FSM state register: Users of register don't seem to benefit from recoding. Register has an initialization value. Not marking top.SOC.Core.Control_Unit.state as FSM state register: Register has an initialization value. Found FSM state register top.SOC.Uart.i_uart_rx.fsm_state. Not marking top.SOC.Uart.i_uart_tx.fsm_state as FSM state register: Users of register don't seem to benefit from recoding. Not marking top.SOC.Uart.state as FSM state register: Register has an initialization value. 24.12.2. Executing FSM_EXTRACT pass (extracting FSM from design). Extracting FSM `\SOC.Uart.i_uart_rx.fsm_state' from module `\top'. found $dff cell for state register: $flatten\SOC.\Uart.\i_uart_rx.$procdff$3725 root of input selection tree: $flatten\SOC.\Uart.\i_uart_rx.$0\fsm_state[2:0] found reset state: 3'000 (guessed from mux tree) found ctrl input: \ResetBootSystem.reset_o found ctrl input: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:102$1486_Y found ctrl input: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:130$1499_Y found ctrl input: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:168$1512_Y found ctrl input: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:128$1498_Y found state code: 3'000 found ctrl input: \SOC.Uart.i_uart_rx.next_bit found state code: 3'011 found ctrl input: \SOC.Uart.i_uart_rx.payload_done found state code: 3'010 found state code: 3'001 found ctrl input: \SOC.Uart.i_uart_rx.rxd_reg found ctrl output: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:168$1512_Y found ctrl output: $flatten\SOC.\Uart.\i_uart_rx.$ne$Risco-5/src/peripheral/uart_rx.v:143$1503_Y found ctrl output: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:130$1499_Y found ctrl output: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:128$1498_Y found ctrl output: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:102$1486_Y ctrl inputs: { \SOC.Uart.i_uart_rx.rxd_reg \SOC.Uart.i_uart_rx.next_bit \SOC.Uart.i_uart_rx.payload_done \ResetBootSystem.reset_o } ctrl outputs: { $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:102$1486_Y $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:128$1498_Y $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:130$1499_Y $flatten\SOC.\Uart.\i_uart_rx.$ne$Risco-5/src/peripheral/uart_rx.v:143$1503_Y $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:168$1512_Y $flatten\SOC.\Uart.\i_uart_rx.$0\fsm_state[2:0] } transition: 3'000 4'0--0 -> 3'001 8'01010001 transition: 3'000 4'1--0 -> 3'000 8'01010000 transition: 3'000 4'---1 -> 3'000 8'01010000 transition: 3'010 4'--00 -> 3'010 8'00100010 transition: 3'010 4'--10 -> 3'011 8'00100011 transition: 3'010 4'---1 -> 3'000 8'00100000 transition: 3'001 4'-0-0 -> 3'001 8'00011001 transition: 3'001 4'-1-0 -> 3'010 8'00011010 transition: 3'001 4'---1 -> 3'000 8'00011000 transition: 3'011 4'-0-0 -> 3'011 8'10010011 transition: 3'011 4'-1-0 -> 3'000 8'10010000 transition: 3'011 4'---1 -> 3'000 8'10010000 24.12.3. Executing FSM_OPT pass (simple optimizations of FSMs). Optimizing FSM `$fsm$\SOC.Uart.i_uart_rx.fsm_state$3952' from module `\top'. 24.12.4. Executing OPT_CLEAN pass (remove unused cells and wires). [Pipeline] sh Finding unused cells or wires in module \top.. Removed 7 unused cells and 7 unused wires. <suppressed ~8 debug messages> 24.12.5. Executing FSM_OPT pass (simple optimizations of FSMs). Optimizing FSM `$fsm$\SOC.Uart.i_uart_rx.fsm_state$3952' from module `\top'. Removing unused output signal $flatten\SOC.\Uart.\i_uart_rx.$0\fsm_state[2:0] [0]. Removing unused output signal $flatten\SOC.\Uart.\i_uart_rx.$0\fsm_state[2:0] [1]. Removing unused output signal $flatten\SOC.\Uart.\i_uart_rx.$0\fsm_state[2:0] [2]. 24.12.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). Recoding FSM `$fsm$\SOC.Uart.i_uart_rx.fsm_state$3952' from module `\top' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 000 -> ---1 010 -> --1- 001 -> -1-- 011 -> 1--- 24.12.7. Executing FSM_INFO pass (dumping all available information on FSM cells). FSM `$fsm$\SOC.Uart.i_uart_rx.fsm_state$3952' from module `top': ------------------------------------- Information on FSM $fsm$\SOC.Uart.i_uart_rx.fsm_state$3952 (\SOC.Uart.i_uart_rx.fsm_state): Number of input signals: 4 Number of output signals: 5 Number of state bits: 4 Input signals: 0: \ResetBootSystem.reset_o 1: \SOC.Uart.i_uart_rx.payload_done 2: \SOC.Uart.i_uart_rx.next_bit 3: \SOC.Uart.i_uart_rx.rxd_reg Output signals: 0: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:168$1512_Y 1: $flatten\SOC.\Uart.\i_uart_rx.$ne$Risco-5/src/peripheral/uart_rx.v:143$1503_Y 2: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:130$1499_Y 3: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:128$1498_Y 4: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:102$1486_Y State encoding: 0: 4'---1 <RESET STATE> 1: 4'--1- 2: 4'-1-- 3: 4'1--- Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 4'1--0 -> 0 5'01010 1: 0 4'---1 -> 0 5'01010 2: 0 4'0--0 -> 2 5'01010 3: 1 4'---1 -> 0 5'00100 4: 1 4'--00 -> 1 5'00100 5: 1 4'--10 -> 3 5'00100 6: 2 4'---1 -> 0 5'00011 7: 2 4'-1-0 -> 1 5'00011 8: 2 4'-0-0 -> 2 5'00011 9: 3 4'-1-0 -> 0 5'10010 10: 3 4'---1 -> 0 5'10010 11: 3 4'-0-0 -> 3 5'10010 ------------------------------------- 24.12.8. Executing FSM_MAP pass (mapping FSMs to basic logic). Mapping FSM `$fsm$\SOC.Uart.i_uart_rx.fsm_state$3952' from module `\top'. 24.13. Executing OPT pass (performing simple optimizations). 24.13.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~5 debug messages> 24.13.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~6 debug messages> Removed a total of 2 cells. 24.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~148 debug messages> 24.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 24.13.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 24.13.6. Executing OPT_DFF pass (perform DFF optimizations). Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$3737 ($dff) from module top (D = { $flatten\SOC.\Uart.\i_uart_tx.$procmux$1823_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1817_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1808_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1799_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1790_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1781_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1763_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1772_Y }, Q = \SOC.Uart.i_uart_tx.data_to_send, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$4002 ($sdff) from module top (D = \SOC.Uart.uart_tx_data [7], Q = \SOC.Uart.i_uart_tx.data_to_send [7]). Adding EN signal on $auto$ff.cc:266:slice$4002 ($sdff) from module top (D = { $flatten\SOC.\Uart.\i_uart_tx.$procmux$1817_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1808_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1799_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1790_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1781_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1763_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1772_Y }, Q = \SOC.Uart.i_uart_tx.data_to_send [6:0]). Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$3735 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$1739_Y, Q = \SOC.Uart.i_uart_tx.bit_counter, rval = 4'0000). Adding EN signal on $auto$ff.cc:266:slice$4007 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$1739_Y, Q = \SOC.Uart.i_uart_tx.bit_counter). Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$3734 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$1728_Y, Q = \SOC.Uart.i_uart_tx.cycle_counter, rval = 9'000000000). Adding EN signal on $auto$ff.cc:266:slice$4013 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:149$1466_Y, Q = \SOC.Uart.i_uart_tx.cycle_counter). Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$3733 ($dff) from module top (D = \SOC.Uart.i_uart_tx.n_fsm_state, Q = \SOC.Uart.i_uart_tx.fsm_state, rval = 3'000). Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$3732 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$1717_Y, Q = \SOC.Uart.i_uart_tx.txd_reg, rval = 1'1). Adding EN signal on $auto$ff.cc:266:slice$4018 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$1717_Y, Q = \SOC.Uart.i_uart_tx.txd_reg). Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$3731 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$procmux$1706_Y, Q = \SOC.Uart.i_uart_rx.uart_rx_data, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$4024 ($sdff) from module top (D = \SOC.Uart.i_uart_rx.recieved_data, Q = \SOC.Uart.i_uart_rx.uart_rx_data). Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$3729 ($dff) from module top (D = { $flatten\SOC.\Uart.\i_uart_rx.$procmux$1683_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1674_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1665_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1656_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1647_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1638_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1620_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1629_Y }, Q = \SOC.Uart.i_uart_rx.recieved_data, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$4026 ($sdff) from module top (D = { \SOC.Uart.i_uart_rx.bit_sample \SOC.Uart.i_uart_rx.recieved_data [7:1] }, Q = \SOC.Uart.i_uart_rx.recieved_data). Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$3728 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$procmux$1602_Y, Q = \SOC.Uart.i_uart_rx.bit_counter, rval = 4'0000). Adding EN signal on $auto$ff.cc:266:slice$4030 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:146$1506_Y, Q = \SOC.Uart.i_uart_rx.bit_counter). Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$3727 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$procmux$1597_Y, Q = \SOC.Uart.i_uart_rx.bit_sample, rval = 1'0). Adding EN signal on $auto$ff.cc:266:slice$4034 ($sdff) from module top (D = \SOC.Uart.i_uart_rx.rxd_reg, Q = \SOC.Uart.i_uart_rx.bit_sample). Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$3726 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$procmux$1589_Y, Q = \SOC.Uart.i_uart_rx.cycle_counter, rval = 9'000000000). Adding EN signal on $auto$ff.cc:266:slice$4036 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:171$1517_Y, Q = \SOC.Uart.i_uart_rx.cycle_counter). Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$3724 ($dff) from module top (D = \rx, Q = \SOC.Uart.i_uart_rx.rxd_reg_0, rval = 1'1). Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$3723 ($dff) from module top (D = \SOC.Uart.i_uart_rx.rxd_reg_0, Q = \SOC.Uart.i_uart_rx.rxd_reg, rval = 1'1). Adding SRST signal on $flatten\SOC.\Uart.\TX_FIFO.$procdff$3785 ($dff) from module top (D = $flatten\SOC.\Uart.\TX_FIFO.$procmux$2395_Y, Q = \SOC.Uart.TX_FIFO.write_ptr, rval = 6'000000). Adding EN signal on $auto$ff.cc:266:slice$4042 ($sdff) from module top (D = $flatten\SOC.\Uart.\TX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:37$1541_Y, Q = \SOC.Uart.TX_FIFO.write_ptr). Adding SRST signal on $flatten\SOC.\Uart.\TX_FIFO.$procdff$3784 ($dff) from module top (D = $flatten\SOC.\Uart.\TX_FIFO.$procmux$2403_Y, Q = \SOC.Uart.TX_FIFO.read_ptr, rval = 6'000000). Adding EN signal on $auto$ff.cc:266:slice$4044 ($sdff) from module top (D = $flatten\SOC.\Uart.\TX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:40$1547_Y [5:0], Q = \SOC.Uart.TX_FIFO.read_ptr). Adding SRST signal on $flatten\SOC.\Uart.\TX_FIFO.$procdff$3783 ($dff) from module top (D = $flatten\SOC.\Uart.\TX_FIFO.$procmux$2411_Y, Q = \SOC.Uart.TX_FIFO.counter, rval = 6'000000). Adding EN signal on $auto$ff.cc:266:slice$4050 ($sdff) from module top (D = $flatten\SOC.\Uart.\TX_FIFO.$procmux$2411_Y, Q = \SOC.Uart.TX_FIFO.counter). Adding SRST signal on $flatten\SOC.\Uart.\RX_FIFO.$procdff$3785 ($dff) from module top (D = $flatten\SOC.\Uart.\RX_FIFO.$procmux$2395_Y, Q = \SOC.Uart.RX_FIFO.write_ptr, rval = 6'000000). Adding EN signal on $auto$ff.cc:266:slice$4054 ($sdff) from module top (D = $flatten\SOC.\Uart.\RX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:37$1541_Y, Q = \SOC.Uart.RX_FIFO.write_ptr). Adding SRST signal on $flatten\SOC.\Uart.\RX_FIFO.$procdff$3784 ($dff) from module top (D = $flatten\SOC.\Uart.\RX_FIFO.$procmux$2403_Y, Q = \SOC.Uart.RX_FIFO.read_ptr, rval = 6'000000). Adding EN signal on $auto$ff.cc:266:slice$4056 ($sdff) from module top (D = $flatten\SOC.\Uart.\RX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:40$1547_Y [5:0], Q = \SOC.Uart.RX_FIFO.read_ptr). Adding SRST signal on $flatten\SOC.\Uart.\RX_FIFO.$procdff$3783 ($dff) from module top (D = $flatten\SOC.\Uart.\RX_FIFO.$procmux$2411_Y, Q = \SOC.Uart.RX_FIFO.counter, rval = 6'000000). Adding EN signal on $auto$ff.cc:266:slice$4062 ($sdff) from module top (D = $flatten\SOC.\Uart.\RX_FIFO.$procmux$2411_Y, Q = \SOC.Uart.RX_FIFO.counter). Adding SRST signal on $flatten\SOC.\Uart.$procdff$3760 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$2067_Y, Q = \SOC.Uart.write_data_buffer, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$4066 ($sdff) from module top (D = $flatten\SOC.\Uart.$procmux$2067_Y, Q = \SOC.Uart.write_data_buffer). Adding SRST signal on $flatten\SOC.\Uart.$procdff$3759 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$2085_Y, Q = \SOC.Uart.tx_fifo_write_data, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$4076 ($sdff) from module top (D = \SOC.Uart.write_data_buffer [7:0], Q = \SOC.Uart.tx_fifo_write_data). Adding SRST signal on $flatten\SOC.\Uart.$procdff$3758 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$2039_Y, Q = \SOC.Uart.rx_fifo_read, rval = 1'0). Adding SRST signal on $flatten\SOC.\Uart.$procdff$3757 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$2020_Y, Q = \SOC.Uart.tx_fifo_write, rval = 1'0). Adding SRST signal on $flatten\SOC.\Uart.$procdff$3756 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$2050_Y, Q = \SOC.Uart.response, rval = 1'0). Adding SRST signal on $flatten\SOC.\Uart.$procdff$3755 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$2093_Y, Q = \SOC.Uart.read_data, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$4097 ($sdff) from module top (D = $flatten\SOC.\Uart.$procmux$2093_Y, Q = \SOC.Uart.read_data). Adding EN signal on $flatten\SOC.\Uart.$procdff$3754 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$2119_Y, Q = \SOC.Uart.counter). Adding SRST signal on $flatten\SOC.\Uart.$procdff$3753 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$2133_Y, Q = \SOC.Uart.state, rval = 4'0000). Adding EN signal on $auto$ff.cc:266:slice$4122 ($sdff) from module top (D = $flatten\SOC.\Uart.$procmux$2133_Y, Q = \SOC.Uart.state). Adding SRST signal on $flatten\SOC.\Uart.$procdff$3752 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$2002_Y, Q = \SOC.Uart.rx_fifo_write_data, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$4126 ($sdff) from module top (D = \SOC.Uart.i_uart_rx.uart_rx_data, Q = \SOC.Uart.rx_fifo_write_data). Adding SRST signal on $flatten\SOC.\Uart.$procdff$3751 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$2007_Y, Q = \SOC.Uart.uart_tx_data, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$4128 ($sdff) from module top (D = \SOC.Uart.tx_fifo_read_data, Q = \SOC.Uart.uart_tx_data). Adding SRST signal on $flatten\SOC.\Uart.$procdff$3750 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1987_Y, Q = \SOC.Uart.rx_fifo_write, rval = 1'0). Adding SRST signal on $flatten\SOC.\Uart.$procdff$3748 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1992_Y, Q = \SOC.Uart.uart_tx_en, rval = 1'0). Adding SRST signal on $flatten\SOC.\Leds.$procdff$3772 ($dff) from module top (D = $flatten\SOC.\Leds.$procmux$2320_Y, Q = \SOC.Leds.data, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$4132 ($sdff) from module top (D = { \SOC.Leds.write_data [31:17] \SOC.GPIOS.write_data [16:0] }, Q = \SOC.Leds.data). Adding SRST signal on $flatten\SOC.\GPIOS.\Pwm1.$procdff$3761 ($dff) from module top (D = $flatten\SOC.\GPIOS.\Pwm1.$add$Risco-5/src/peripheral/pwm.v:17$458_Y, Q = \SOC.GPIOS.Pwm1.counter, rval = 0). Adding SRST signal on $flatten\SOC.\GPIOS.\Pwm0.$procdff$3761 ($dff) from module top (D = $flatten\SOC.\GPIOS.\Pwm0.$add$Risco-5/src/peripheral/pwm.v:17$458_Y, Q = \SOC.GPIOS.Pwm0.counter, rval = 0). Adding EN signal on $flatten\SOC.\GPIOS.$procdff$3765 ($dff) from module top (D = \SOC.GPIOS.write_data [1:0], Q = \SOC.GPIOS.is_pwm). Adding SRST signal on $flatten\SOC.\GPIOS.$procdff$3764 ($dff) from module top (D = $flatten\SOC.\GPIOS.$procmux$2302_Y, Q = \SOC.GPIOS.gpio_value, rval = 6'000000). Adding EN signal on $auto$ff.cc:266:slice$4149 ($sdff) from module top (D = \SOC.GPIOS.write_data [5:0], Q = \SOC.GPIOS.gpio_value). Adding SRST signal on $flatten\SOC.\GPIOS.$procdff$3763 ($dff) from module top (D = $flatten\SOC.\GPIOS.$procmux$2315_Y, Q = \SOC.GPIOS.gpio_direction, rval = 6'000000). Adding EN signal on $auto$ff.cc:266:slice$4153 ($sdff) from module top (D = \SOC.GPIOS.write_data [5:0], Q = \SOC.GPIOS.gpio_direction). Adding SRST signal on $flatten\SOC.\Core.\Pc.$procdff$3794 ($dff) from module top (D = $flatten\SOC.\Core.\Pc.$procmux$2455_Y, Q = \SOC.Core.Pc.Output, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$4157 ($sdff) from module top (D = \SOC.Core.Pc.Input, Q = \SOC.Core.Pc.Output). Adding SRST signal on $flatten\SOC.\Core.\Control_Unit.$procdff$3806 ($dff) from module top (D = \SOC.Core.Control_Unit.nextstate, Q = \SOC.Core.Control_Unit.state, rval = 6'000000). Adding EN signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3802 ($dff) from module top (D = 64'0000000000000000000000000000000000000000000000000000000000000000, Q = \SOC.Core.CSR_Unit.utime). Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3801 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:114$121_Y, Q = \SOC.Core.CSR_Unit.mcycle, rval = 64'0000000000000000000000000000000000000000000000000000000000000000). Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3800 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$2500_Y, Q = \SOC.Core.CSR_Unit.mtvec, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$4162 ($sdff) from module top (D = \SOC.Core.register_data_1, Q = \SOC.Core.CSR_Unit.mtvec). Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3799 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$2508_Y, Q = \SOC.Core.CSR_Unit.mtval, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$4166 ($sdff) from module top (D = \SOC.Core.register_data_1, Q = \SOC.Core.CSR_Unit.mtval). Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3798 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$2517_Y, Q = \SOC.Core.CSR_Unit.mcause, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$4170 ($sdff) from module top (D = \SOC.Core.register_data_1, Q = \SOC.Core.CSR_Unit.mcause). Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3797 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$2527_Y, Q = \SOC.Core.CSR_Unit.mscratch, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$4174 ($sdff) from module top (D = \SOC.Core.register_data_1, Q = \SOC.Core.CSR_Unit.mscratch). Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3796 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$2538_Y, Q = \SOC.Core.CSR_Unit.mepc, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$4178 ($sdff) from module top (D = { \SOC.Core.register_data_1 [31:2] 2'00 }, Q = \SOC.Core.CSR_Unit.mepc). Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3795 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$2487_Y, Q = \SOC.Core.CSR_Unit.minstret, rval = 64'0000000000000000000000000000000000000000000000000000000000000000). Adding EN signal on $auto$ff.cc:266:slice$4182 ($sdff) from module top (D = \SOC.Core.register_data_1, Q = \SOC.Core.CSR_Unit.minstret [63:32]). Adding EN signal on $auto$ff.cc:266:slice$4182 ($sdff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$2485_Y [31:0], Q = \SOC.Core.CSR_Unit.minstret [31:0]). Adding SRST signal on $flatten\SOC.\Core.$procdff$3782 ($dff) from module top (D = $flatten\SOC.\Core.$procmux$2337_Y, Q = \SOC.Core.temp_write_value, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$4195 ($sdff) from module top (D = \SOC.Core.Alu.ALU_out_S, Q = \SOC.Core.temp_write_value). Adding SRST signal on $flatten\SOC.\Core.$procdff$3781 ($dff) from module top (D = $flatten\SOC.\Core.$procmux$2342_Y, Q = \SOC.Core.temp_reg3, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$4197 ($sdff) from module top (D = \SOC.Core.alu_out_register, Q = \SOC.Core.temp_reg3). Adding SRST signal on $flatten\SOC.\Core.$procdff$3780 ($dff) from module top (D = $flatten\SOC.\Core.$procmux$2347_Y, Q = \SOC.Core.temp_reg2, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$4199 ($sdff) from module top (D = \SOC.Core.memory_register, Q = \SOC.Core.temp_reg2). Adding SRST signal on $flatten\SOC.\Core.$procdff$3779 ($dff) from module top (D = $flatten\SOC.\Core.$procmux$2352_Y, Q = \SOC.Core.temp_address, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$4201 ($sdff) from module top (D = \SOC.Core.Alu.ALU_out_S, Q = \SOC.Core.temp_address). Adding SRST signal on $flatten\SOC.\Core.$procdff$3778 ($dff) from module top (D = $flatten\SOC.\Core.$procmux$2357_Y, Q = \SOC.Core.pc_old, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$4203 ($sdff) from module top (D = \SOC.Core.Pc.Output, Q = \SOC.Core.pc_old). Adding SRST signal on $flatten\SOC.\Core.$procdff$3777 ($dff) from module top (D = \SOC.Core.register_data_2_out, Q = \SOC.Core.register_data_2, rval = 0). Adding SRST signal on $flatten\SOC.\Core.$procdff$3776 ($dff) from module top (D = \SOC.Core.register_data_1_out, Q = \SOC.Core.register_data_1, rval = 0). Adding SRST signal on $flatten\SOC.\Core.$procdff$3775 ($dff) from module top (D = \SOC.Core.Alu.ALU_out_S, Q = \SOC.Core.alu_out_register, rval = 0). Adding SRST signal on $flatten\SOC.\Core.$procdff$3774 ($dff) from module top (D = \SOC.Core.read_data, Q = \SOC.Core.memory_register, rval = 0). Adding SRST signal on $flatten\SOC.\Core.$procdff$3773 ($dff) from module top (D = $flatten\SOC.\Core.$procmux$2362_Y, Q = \SOC.Core.instruction_register, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$4209 ($sdff) from module top (D = \SOC.Core.read_data, Q = \SOC.Core.instruction_register). Adding EN signal on $flatten\ResetBootSystem.$procdff$3805 ($dff) from module top (D = $flatten\ResetBootSystem.$0\counter[5:0], Q = \ResetBootSystem.counter). Adding EN signal on $flatten\ResetBootSystem.$procdff$3804 ($dff) from module top (D = $flatten\ResetBootSystem.$0\state[1:0], Q = \ResetBootSystem.state). Adding EN signal on $flatten\ResetBootSystem.$procdff$3803 ($dff) from module top (D = $flatten\ResetBootSystem.$0\reset_o[0:0], Q = \ResetBootSystem.reset_o). Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$4179 ($sdffe) from module top. Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$4179 ($sdffe) from module top. Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$4160 ($dffe) from module top. Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$4160 ($dffe) from module top. Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$4160 ($dffe) from module top. Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$4160 ($dffe) from module top. Setting constant 0-bit at position 4 on $auto$ff.cc:266:slice$4160 ($dffe) from module top. Setting constant 0-bit at position 5 on $auto$ff.cc:266:slice$4160 ($dffe) from module top. Setting constant 0-bit at position 6 on $auto$ff.cc:266:slice$4160 ($dffe) from module top. Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$4160 ($dffe) from module top. Setting constant 0-bit at position 8 on $auto$ff.cc:266:slice$4160 ($dffe) from module top. Setting constant 0-bit at position 9 on $auto$ff.cc:266:slice$4160 ($dffe) from module top. Setting constant 0-bit at position 10 on $auto$ff.cc:266:slice$4160 ($dffe) from module top. Setting constant 0-bit at position 11 on $auto$ff.cc:266:slice$4160 ($dffe) from module top. Setting constant 0-bit at position 12 on $auto$ff.cc:266:slice$4160 ($dffe) from module top. Setting constant 0-bit at position 13 on $auto$ff.cc:266:slice$4160 ($dffe) from module top. Setting constant 0-bit at position 14 on $auto$ff.cc:266:slice$4160 ($dffe) from module top. Setting constant 0-bit at position 15 on $auto$ff.cc:266:slice$4160 ($dffe) from module top. Setting constant 0-bit at position 16 on $auto$ff.cc:266:slice$4160 ($dffe) from module top. Setting constant 0-bit at position 17 on $auto$ff.cc:266:slice$4160 ($dffe) from module top. Setting constant 0-bit at position 18 on $auto$ff.cc:266:slice$4160 ($dffe) from module top. Setting constant 0-bit at position 19 on $auto$ff.cc:266:slice$4160 ($dffe) from module top. Setting constant 0-bit at position 20 on $auto$ff.cc:266:slice$4160 ($dffe) from module top. Setting constant 0-bit at position 21 on $auto$ff.cc:266:slice$4160 ($dffe) from module top. Setting constant 0-bit at position 22 on $auto$ff.cc:266:slice$4160 ($dffe) from module top. Setting constant 0-bit at position 23 on $auto$ff.cc:266:slice$4160 ($dffe) from module top. Setting constant 0-bit at position 24 on $auto$ff.cc:266:slice$4160 ($dffe) from module top. Setting constant 0-bit at position 25 on $auto$ff.cc:266:slice$4160 ($dffe) from module top. Setting constant 0-bit at position 26 on $auto$ff.cc:266:slice$4160 ($dffe) from module top. Setting constant 0-bit at position 27 on $auto$ff.cc:266:slice$4160 ($dffe) from module top. Setting constant 0-bit at position 28 on $auto$ff.cc:266:slice$4160 ($dffe) from module top. Setting constant 0-bit at position 29 on $auto$ff.cc:266:slice$4160 ($dffe) from module top. Setting constant 0-bit at position 30 on $auto$ff.cc:266:slice$4160 ($dffe) from module top. Setting constant 0-bit at position 31 on $auto$ff.cc:266:slice$4160 ($dffe) from module top. Setting constant 0-bit at position 32 on $auto$ff.cc:266:slice$4160 ($dffe) from module top. Setting constant 0-bit at position 33 on $auto$ff.cc:266:slice$4160 ($dffe) from module top. Setting constant 0-bit at position 34 on $auto$ff.cc:266:slice$4160 ($dffe) from module top. Setting constant 0-bit at position 35 on $auto$ff.cc:266:slice$4160 ($dffe) from module top. Setting constant 0-bit at position 36 on $auto$ff.cc:266:slice$4160 ($dffe) from module top. Setting constant 0-bit at position 37 on $auto$ff.cc:266:slice$4160 ($dffe) from module top. Setting constant 0-bit at position 38 on $auto$ff.cc:266:slice$4160 ($dffe) from module top. Setting constant 0-bit at position 39 on $auto$ff.cc:266:slice$4160 ($dffe) from module top. Setting constant 0-bit at position 40 on $auto$ff.cc:266:slice$4160 ($dffe) from module top. Setting constant 0-bit at position 41 on $auto$ff.cc:266:slice$4160 ($dffe) from module top. Setting constant 0-bit at position 42 on $auto$ff.cc:266:slice$4160 ($dffe) from module top. Setting constant 0-bit at position 43 on $auto$ff.cc:266:slice$4160 ($dffe) from module top. Setting constant 0-bit at position 44 on $auto$ff.cc:266:slice$4160 ($dffe) from module top. Setting constant 0-bit at position 45 on $auto$ff.cc:266:slice$4160 ($dffe) from module top. Setting constant 0-bit at position 46 on $auto$ff.cc:266:slice$4160 ($dffe) from module top. Setting constant 0-bit at position 47 on $auto$ff.cc:266:slice$4160 ($dffe) from module top. Setting constant 0-bit at position 48 on $auto$ff.cc:266:slice$4160 ($dffe) from module top. Setting constant 0-bit at position 49 on $auto$ff.cc:266:slice$4160 ($dffe) from module top. Setting constant 0-bit at position 50 on $auto$ff.cc:266:slice$4160 ($dffe) from module top. Setting constant 0-bit at position 51 on $auto$ff.cc:266:slice$4160 ($dffe) from module top. Setting constant 0-bit at position 52 on $auto$ff.cc:266:slice$4160 ($dffe) from module top. Setting constant 0-bit at position 53 on $auto$ff.cc:266:slice$4160 ($dffe) from module top. Setting constant 0-bit at position 54 on $auto$ff.cc:266:slice$4160 ($dffe) from module top. Setting constant 0-bit at position 55 on $auto$ff.cc:266:slice$4160 ($dffe) from module top. Setting constant 0-bit at position 56 on $auto$ff.cc:266:slice$4160 ($dffe) from module top. Setting constant 0-bit at position 57 on $auto$ff.cc:266:slice$4160 ($dffe) from module top. Setting constant 0-bit at position 58 on $auto$ff.cc:266:slice$4160 ($dffe) from module top. Setting constant 0-bit at position 59 on $auto$ff.cc:266:slice$4160 ($dffe) from module top. Setting constant 0-bit at position 60 on $auto$ff.cc:266:slice$4160 ($dffe) from module top. Setting constant 0-bit at position 61 on $auto$ff.cc:266:slice$4160 ($dffe) from module top. Setting constant 0-bit at position 62 on $auto$ff.cc:266:slice$4160 ($dffe) from module top. Setting constant 0-bit at position 63 on $auto$ff.cc:266:slice$4160 ($dffe) from module top. 24.13.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 140 unused cells and 136 unused wires. <suppressed ~141 debug messages> 24.13.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~11 debug messages> 24.13.9. Rerunning OPT passes. (Maybe there is more to do..) 24.13.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~105 debug messages> 24.13.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. New input vector for $reduce_or cell $auto$opt_dff.cc:254:combine_resets$4032: { \SOC.Uart.i_uart_rx.fsm_state [3:2] \SOC.Uart.i_uart_rx.fsm_state [0] \ResetBootSystem.reset_o } New ctrl vector for $pmux cell $flatten\SOC.\Core.\CSR_Unit.$procmux$2544: { $flatten\SOC.\Core.\CSR_Unit.$procmux$2556_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$2555_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$2554_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$2499_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$2526_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$2537_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$2516_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$2507_CMP $auto$opt_reduce.cc:134:opt_pmux$3907 $auto$opt_reduce.cc:134:opt_pmux$3905 $auto$opt_reduce.cc:134:opt_pmux$3903 $auto$opt_reduce.cc:134:opt_pmux$3901 } Optimizing cells in module \top. Performed a total of 2 changes. 24.13.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~21 debug messages> Removed a total of 7 cells. 24.13.13. Executing OPT_DFF pass (perform DFF optimizations). 24.13.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 3 unused cells and 10 unused wires. <suppressed ~4 debug messages> 24.13.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 24.13.16. Rerunning OPT passes. (Maybe there is more to do..) 24.13.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~105 debug messages> 24.13.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 24.13.19. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 24.13.20. Executing OPT_DFF pass (perform DFF optimizations). + cd Risco-5/fpga/tangnano20k/ + /eda/gowin/IDE/bin/gw_sh run.tcl *** GOWIN Tcl Command Line Console *** current device: GW2AR-18C GW2AR-LV18QN88C8/I7 add new file: "pinout.cst" add new file: "top.sdc" add new file: "main.v" add new file: "../../debug/reset.v" add new file: "../../src/core/alu_control.v" add new file: "../../src/core/alu.v" add new file: "../../src/core/control_unit.v" add new file: "../../src/core/core.v" add new file: "../../src/core/immediate_generator.v" add new file: "../../src/core/mux.v" add new file: "../../src/core/pc.v" add new file: "../../src/core/registers.v" add new file: "../../src/core/csr_unit.v" add new file: "../../src/core/mdu.v" add new file: "../../src/peripheral/bus.v" add new file: "../../src/peripheral/gpio.v" add new file: "../../src/peripheral/gpios.v" add new file: "../../src/peripheral/leds.v" add new file: "../../src/peripheral/memory.v" add new file: "../../src/peripheral/soc.v" add new file: "../../src/peripheral/uart_rx.v" add new file: "../../src/peripheral/uart_tx.v" add new file: "../../src/peripheral/uart.v" add new file: "../../src/peripheral/fifo.v" add new file: "../../src/peripheral/pwm.v" GowinSynthesis start Running parser ... Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/main.v' Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/debug/reset.v' Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v' Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu.v' Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v' Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v' Undeclared symbol 'pc_source', assumed default net type 'wire'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":168) Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/immediate_generator.v' Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/mux.v' Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/pc.v' Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/registers.v' Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/csr_unit.v' Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/mdu.v' Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/bus.v' Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpio.v' Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v' Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/leds.v' Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v' WARN (EX3012) : Empty statement in sequential block("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v":54) Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v' Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_rx.v' Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_tx.v' Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart.v' Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/fifo.v' Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/pwm.v' WARN (EX3073) : Port 'resetn_o' remains unconnected for this instance("/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/main.v":18) Compiling module 'top'("/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/main.v":1) Compiling module 'ResetBootSystem'("/var/lib/jenkins/workspace/Risco_5/Risco-5/debug/reset.v":1) WARN (EX3791) : Expression size 7 truncated to fit in target size 6("/var/lib/jenkins/workspace/Risco_5/Risco-5/debug/reset.v":37) Compiling module 'Risco_5_SOC(CLOCK_FREQ=27000000,BIT_RATE=115200,MEMORY_SIZE=2048,MEMORY_FILE="../../software/memory/teste_uart_fpga.hex",UART_BUFFER_SIZE=16)'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":1) Compiling module 'Core(BOOT_ADDRESS=32'b00000000000000000000000000000000)'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":2) Compiling module 'PC'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/pc.v":1) Compiling module 'MUX'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/mux.v":1) Compiling module 'Registers'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/registers.v":1) Compiling module 'Control_Unit'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v":2) WARN (EX3791) : Expression size 7 truncated to fit in target size 3("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v":546) WARN (EX3791) : Expression size 7 truncated to fit in target size 3("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v":553) WARN (EX3791) : Expression size 7 truncated to fit in target size 3("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v":566) WARN (EX3791) : Expression size 7 truncated to fit in target size 3("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v":573) Compiling module 'ALU_Control'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v":1) Compiling module 'Alu'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu.v":1) Compiling module 'Immediate_Generator'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/immediate_generator.v":1) Compiling module 'CSR_Unit'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/csr_unit.v":1) WARN (EX1998) : Net 'mdu_done' does not have a driver("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":55) Compiling module 'Memory(MEMORY_FILE="../../software/memory/teste_uart_fpga.hex",MEMORY_SIZE=2048)'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v":1) Extracting RAM for identifier 'memory'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v":16) Compiling module 'BUS'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/bus.v":1) 24.13.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 24.13.22. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 24.13.23. Finished OPT passes. (There is nothing left to do.) 24.14. Executing WREDUCE pass (reducing word size of cells). Removed top 27 address bits (of 32) from memory init port top.$flatten\SOC.\Core.\RegisterBank.$auto$proc_memwr.cc:45:proc_memwr$3813 (SOC.Core.RegisterBank.registers). Removed top 27 address bits (of 32) from memory init port top.$flatten\SOC.\Core.\RegisterBank.$auto$proc_memwr.cc:45:proc_memwr$3815 (SOC.Core.RegisterBank.registers). Removed top 27 address bits (of 32) from memory init port top.$flatten\SOC.\Core.\RegisterBank.$meminit$\registers$Risco-5/src/core/registers.v:17$173 (SOC.Core.RegisterBank.registers). Removed top 31 address bits (of 32) from memory init port top.$flatten\SOC.\GPIOS.$meminit$\duty_cycle$Risco-5/src/peripheral/gpios.v:26$1357 (SOC.GPIOS.duty_cycle). Removed top 31 address bits (of 32) from memory init port top.$flatten\SOC.\GPIOS.$meminit$\period$Risco-5/src/peripheral/gpios.v:25$1356 (SOC.GPIOS.period). Removed top 31 address bits (of 32) from memory read port top.$flatten\SOC.\GPIOS.$memrd$\duty_cycle$Risco-5/src/peripheral/gpios.v:48$1352 (SOC.GPIOS.duty_cycle). Removed top 31 address bits (of 32) from memory read port top.$flatten\SOC.\GPIOS.$memrd$\duty_cycle$Risco-5/src/peripheral/gpios.v:56$1354 (SOC.GPIOS.duty_cycle). Removed top 31 address bits (of 32) from memory read port top.$flatten\SOC.\GPIOS.$memrd$\period$Risco-5/src/peripheral/gpios.v:49$1353 (SOC.GPIOS.period). Removed top 31 address bits (of 32) from memory read port top.$flatten\SOC.\GPIOS.$memrd$\period$Risco-5/src/peripheral/gpios.v:57$1355 (SOC.GPIOS.period). Removed top 23 address bits (of 32) from memory init port top.$flatten\SOC.\Memory.$auto$proc_memwr.cc:45:proc_memwr$3807 (SOC.Memory.memory). Removed top 23 address bits (of 32) from memory init port top.$flatten\SOC.\Memory.$auto$proc_memwr.cc:45:proc_memwr$3808 (SOC.Memory.memory). Removed top 23 address bits (of 32) from memory init port top.$flatten\SOC.\Memory.$auto$proc_memwr.cc:45:proc_memwr$3809 (SOC.Memory.memory). Removed top 23 address bits (of 32) from memory init port top.$flatten\SOC.\Memory.$meminit$\memory$Risco-5/src/peripheral/memory.v:0$1426 (SOC.Memory.memory). Removed top 23 address bits (of 32) from memory read port top.$flatten\SOC.\Memory.$memrd$\memory$Risco-5/src/peripheral/memory.v:24$1384 (SOC.Memory.memory). Removed top 2 address bits (of 6) from memory init port top.$flatten\SOC.\Uart.\RX_FIFO.$auto$proc_memwr.cc:45:proc_memwr$3812 (SOC.Uart.RX_FIFO.memory). Removed top 2 address bits (of 6) from memory read port top.$flatten\SOC.\Uart.\RX_FIFO.$memrd$\memory$Risco-5/src/peripheral/fifo.v:20$1524 (SOC.Uart.RX_FIFO.memory). Removed top 2 address bits (of 6) from memory init port top.$flatten\SOC.\Uart.\TX_FIFO.$auto$proc_memwr.cc:45:proc_memwr$3812 (SOC.Uart.TX_FIFO.memory). Removed top 2 address bits (of 6) from memory read port top.$flatten\SOC.\Uart.\TX_FIFO.$memrd$\memory$Risco-5/src/peripheral/fifo.v:20$1524 (SOC.Uart.TX_FIFO.memory). Removed top 1 bits (of 2) from port B of cell top.$flatten\ResetBootSystem.$procmux$2592_CMP0 ($eq). Removed top 1 bits (of 6) from port B of cell top.$flatten\ResetBootSystem.$eq$Risco-5/debug/reset.v:38$806 ($eq). Removed top 31 bits (of 32) from port B of cell top.$flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$805 ($add). Removed top 26 bits (of 32) from port Y of cell top.$flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$805 ($add). Removed top 27 bits (of 32) from port B of cell top.$flatten\ResetBootSystem.$lt$Risco-5/debug/reset.v:36$804 ($lt). Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$4222 ($ne). Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$4217 ($ne). Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$4192 ($ne). Removed top 26 bits (of 32) from mux cell top.$flatten\SOC.\GPIOS.$ternary$Risco-5/src/peripheral/gpios.v:35$1290 ($mux). Removed top 3 bits (of 8) from port B of cell top.$flatten\SOC.\GPIOS.$procmux$2176_CMP0 ($eq). Removed top 4 bits (of 8) from port B of cell top.$flatten\SOC.\GPIOS.$procmux$2204_CMP0 ($eq). Removed top 4 bits (of 8) from port B of cell top.$flatten\SOC.\GPIOS.$procmux$2289_CMP0 ($eq). Removed top 5 bits (of 8) from port B of cell top.$flatten\SOC.\GPIOS.$procmux$2301_CMP0 ($eq). Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.$ne$Risco-5/src/peripheral/uart.v:113$1366 ($ne). Removed top 2 bits (of 4) from port B of cell top.$flatten\SOC.\Uart.$procmux$2025_CMP0 ($eq). Removed top 3 bits (of 4) from port B of cell top.$flatten\SOC.\Uart.$procmux$2044_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\SOC.\Uart.$procmux$2051_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\SOC.\Uart.$procmux$2069_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\SOC.\Uart.$procmux$2096_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\SOC.\Uart.$procmux$2097_CMP0 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.$procmux$2152_CMP0 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.$procmux$2153_CMP0 ($eq). Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.$procmux$2154_CMP0 ($eq). Removed top 2 bits (of 6) from mux cell top.$flatten\SOC.\Uart.\TX_FIFO.$procmux$2392 ($mux). Removed top 2 bits (of 6) from mux cell top.$flatten\SOC.\Uart.\TX_FIFO.$procmux$2380 ($mux). Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Uart.\TX_FIFO.$eq$Risco-5/src/peripheral/fifo.v:45$1548 ($eq). Removed top 26 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\TX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:40$1547 ($mux). Removed top 26 bits (of 32) from port Y of cell top.$flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:40$1546 ($add). Removed top 2 bits (of 6) from port B of cell top.$flatten\SOC.\Uart.\TX_FIFO.$eq$Risco-5/src/peripheral/fifo.v:40$1545 ($eq). Removed top 2 bits (of 6) from port B of cell top.$flatten\SOC.\Uart.\TX_FIFO.$eq$Risco-5/src/peripheral/fifo.v:37$1539 ($eq). Removed top 2 bits (of 6) from mux cell top.$flatten\SOC.\Uart.\RX_FIFO.$procmux$2392 ($mux). Removed top 2 bits (of 6) from mux cell top.$flatten\SOC.\Uart.\RX_FIFO.$procmux$2380 ($mux). Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Uart.\RX_FIFO.$eq$Risco-5/src/peripheral/fifo.v:45$1548 ($eq). Removed top 26 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\RX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:40$1547 ($mux). Removed top 26 bits (of 32) from port Y of cell top.$flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:40$1546 ($add). Removed top 2 bits (of 6) from port B of cell top.$flatten\SOC.\Uart.\RX_FIFO.$eq$Risco-5/src/peripheral/fifo.v:40$1545 ($eq). Removed top 2 bits (of 6) from port B of cell top.$flatten\SOC.\Uart.\RX_FIFO.$eq$Risco-5/src/peripheral/fifo.v:37$1539 ($eq). Removed top 30 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:113$1495 ($mux). Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:112$1494 ($mux). Removed top 30 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:111$1493 ($mux). Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:110$1492 ($mux). Removed top 2 bits (of 9) from port B of cell top.$flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:103$1487 ($eq). Removed top 1 bits (of 9) from port B of cell top.$flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:101$1485 ($eq). Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:146$1461 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:131$1453 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:129$1451 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$ne$Risco-5/src/peripheral/uart_tx.v:127$1448 ($ne). Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$ne$Risco-5/src/peripheral/uart_tx.v:127$1447 ($ne). Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:114$1443 ($eq). Removed top 30 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:97$1438 ($mux). Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:96$1437 ($mux). Removed top 30 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:95$1436 ($mux). Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:94$1435 ($mux). Removed top 3 bits (of 4) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:88$1431 ($eq). Removed top 1 bits (of 9) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:86$1429 ($eq). Removed top 1 bits (of 2) from port B of cell top.$flatten\SOC.\Bus.$eq$Risco-5/src/peripheral/bus.v:53$180 ($eq). Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Memory.$procmux$1848_CMP0 ($eq). Removed top 23 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1965 ($mux). Removed top 23 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1974 ($mux). Removed top 23 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1983 ($mux). Removed top 31 bits (of 32) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:114$121 ($add). Removed top 1 bits (of 2) from port B of cell top.$flatten\SOC.\Core.\MemoryAddressMUX.$eq$Risco-5/src/core/mux.v:15$130 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\MemoryDataMUX.$eq$Risco-5/src/core/mux.v:17$132 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\MemoryDataMUX.$eq$Risco-5/src/core/mux.v:16$131 ($eq). Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\MemoryDataMUX.$eq$Risco-5/src/core/mux.v:15$130 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\AluInputAMUX.$eq$Risco-5/src/core/mux.v:17$132 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\AluInputAMUX.$eq$Risco-5/src/core/mux.v:16$131 ($eq). Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\AluInputAMUX.$eq$Risco-5/src/core/mux.v:15$130 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\AluInputBMUX.$eq$Risco-5/src/core/mux.v:17$132 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\AluInputBMUX.$eq$Risco-5/src/core/mux.v:16$131 ($eq). Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\AluInputBMUX.$eq$Risco-5/src/core/mux.v:15$130 ($eq). Removed top 1 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$3572_CMP0 ($eq). Removed top 1 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$3571_CMP0 ($eq). Removed top 2 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$3570_CMP0 ($eq). Removed top 2 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$3567_CMP0 ($eq). Removed top 1 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$3566_CMP0 ($eq). Removed top 2 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$3563 ($pmux). Removed top 1 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$3462 ($mux). Removed top 1 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$3409 ($mux). Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$3360 ($mux). Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$3312 ($mux). Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$3265 ($mux). Removed top 1 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$3220 ($mux). Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$3187 ($mux). Removed top 5 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$3157 ($mux). Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$3130 ($mux). Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$3084 ($mux). Removed top 5 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$3033 ($mux). Removed top 4 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2934_CMP0 ($eq). Removed top 3 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2910_CMP0 ($eq). Removed top 5 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2843_CMP0 ($eq). Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2838_CMP0 ($eq). Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2833_CMP0 ($eq). Removed top 3 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2819_CMP0 ($eq). Removed top 2 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2817_CMP0 ($eq). Removed top 2 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2816_CMP0 ($eq). Removed top 2 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2815_CMP0 ($eq). Removed top 2 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2813_CMP0 ($eq). Removed top 2 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2812_CMP0 ($eq). Removed top 3 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2809_CMP0 ($eq). Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2808_CMP0 ($eq). Removed top 3 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2807_CMP0 ($eq). Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2806_CMP0 ($eq). Removed top 2 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2803_CMP0 ($eq). Removed top 2 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2802_CMP0 ($eq). Removed top 2 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2797_CMP0 ($eq). Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2767_CMP0 ($eq). Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2766_CMP0 ($eq). Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2762_CMP0 ($eq). Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2761_CMP0 ($eq). Removed top 4 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2739_CMP0 ($eq). Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2738_CMP0 ($eq). Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2716_CMP0 ($eq). Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2715_CMP0 ($eq). Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2714_CMP0 ($eq). Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2698_CMP0 ($eq). Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2665_CMP0 ($eq). Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2664_CMP0 ($eq). Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2663_CMP0 ($eq). Removed top 1 bits (of 3) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2607 ($pmux). Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2605_CMP0 ($eq). Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2604_CMP0 ($eq). Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$ternary$Risco-5/src/core/control_unit.v:566$81 ($mux). Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$ternary$Risco-5/src/core/control_unit.v:546$75 ($mux). Removed top 1 bits (of 2) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$eq$Risco-5/src/core/control_unit.v:263$54 ($eq). Removed top 5 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$eq$Risco-5/src/core/control_unit.v:191$41 ($eq). Removed top 1 bits (of 3) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$ternary$Risco-5/src/core/control_unit.v:111$38 ($mux). Removed top 1 bits (of 4) from mux cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$3687 ($mux). Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$3685_CMP0 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$3684_CMP0 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$3683_CMP0 ($eq). Removed top 1 bits (of 2) from port B of cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$3699_CMP0 ($eq). Removed top 3 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Alu.$procmux$3714_CMP0 ($eq). Removed top 2 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Alu.$procmux$3713_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Alu.$procmux$3712_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Alu.$procmux$3711_CMP0 ($eq). Removed top 2 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Alu.$procmux$3704_CMP0 ($eq). Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Core.\Alu.$ternary$Risco-5/src/core/alu.v:53$28 ($mux). Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Core.\Alu.$ternary$Risco-5/src/core/alu.v:37$17 ($mux). Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$2554_CMP0 ($eq). Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$2537_CMP0 ($eq). Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$2526_CMP0 ($eq). Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$2516_CMP0 ($eq). Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$2507_CMP0 ($eq). Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$2499_CMP0 ($eq). Removed top 32 bits (of 64) from mux cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$2485 ($mux). Removed cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$2482 ($mux). Removed top 23 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1918 ($mux). Removed top 23 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1936 ($mux). Removed top 23 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1954 ($mux). Removed top 23 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1870 ($mux). Removed top 23 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1879 ($mux). Removed top 26 bits (of 32) from wire top.$flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$805_Y. Removed top 1 bits (of 4) from wire top.$flatten\SOC.\Core.\ALU_Control.$procmux$3687_Y. Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Core.\Alu.$eq$Risco-5/src/core/alu.v:45$23_Y. Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Core.\Alu.$ternary$Risco-5/src/core/alu.v:37$17_Y. Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Core.\Alu.$ternary$Risco-5/src/core/alu.v:53$28_Y. Removed top 32 bits (of 64) from wire top.$flatten\SOC.\Core.\CSR_Unit.$procmux$2485_Y. Removed top 1 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$10\nextstate[5:0]. Removed top 3 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$11\nextstate[5:0]. Removed top 5 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$12\nextstate[5:0]. Removed top 3 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$13\nextstate[5:0]. Removed top 3 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$15\nextstate[5:0]. Removed top 5 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$18\nextstate[5:0]. Removed top 2 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$3\nextstate[5:0]. Removed top 1 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$5\nextstate[5:0]. Removed top 2 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$6\nextstate[5:0]. Removed top 3 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$7\nextstate[5:0]. Removed top 3 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$8\nextstate[5:0]. Removed top 4 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$9\nextstate[5:0]. Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Core.\Control_Unit.$ternary$Risco-5/src/core/control_unit.v:546$75_Y. Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Core.\Control_Unit.$ternary$Risco-5/src/core/control_unit.v:566$81_Y. Removed top 23 bits (of 32) from wire top.$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1380_ADDR[31:0]$1392. Removed top 23 bits (of 32) from wire top.$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1381_ADDR[31:0]$1389. Removed top 23 bits (of 32) from wire top.$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1382_ADDR[31:0]$1395. Removed top 23 bits (of 32) from wire top.$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1380_ADDR[31:0]$1412. Removed top 23 bits (of 32) from wire top.$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1381_ADDR[31:0]$1409. Removed top 23 bits (of 32) from wire top.$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1382_ADDR[31:0]$1415. Removed top 2 bits (of 32) from wire top.$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1382_DATA[31:0]$1414. Removed top 23 bits (of 32) from wire top.$flatten\SOC.\Memory.$3$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1381_ADDR[31:0]$1419. Removed top 23 bits (of 32) from wire top.$flatten\SOC.\Memory.$3$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1382_ADDR[31:0]$1422. Removed top 2 bits (of 6) from wire top.$flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1523_ADDR[5:0]$1526. Removed top 2 bits (of 6) from wire top.$flatten\SOC.\Uart.\RX_FIFO.$2$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1523_ADDR[5:0]$1535. Removed top 26 bits (of 32) from wire top.$flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:40$1546_Y. Removed top 26 bits (of 32) from wire top.$flatten\SOC.\Uart.\RX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:40$1547_Y. Removed top 2 bits (of 6) from wire top.$flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1523_ADDR[5:0]$1526. Removed top 2 bits (of 6) from wire top.$flatten\SOC.\Uart.\TX_FIFO.$2$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1523_ADDR[5:0]$1535. Removed top 26 bits (of 32) from wire top.$flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:40$1546_Y. Removed top 26 bits (of 32) from wire top.$flatten\SOC.\Uart.\TX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:40$1547_Y. Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:110$1492_Y. Removed top 30 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:111$1493_Y. Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:112$1494_Y. Removed top 30 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:113$1495_Y. Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:94$1435_Y. Removed top 30 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:95$1436_Y. Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:96$1437_Y. Removed top 30 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:97$1438_Y. 24.15. Executing PEEPOPT pass (run peephole optimizers). 24.16. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 46 unused wires. <suppressed ~1 debug messages> 24.17. Executing SHARE pass (SAT-based resource sharing). Found 6 cells in module top that may be considered for resource sharing. Analyzing resource sharing options for $flatten\SOC.\Uart.\RX_FIFO.$memrd$\memory$Risco-5/src/peripheral/fifo.v:20$1524 ($memrd): Found 1 activation_patterns using ctrl signal { \SOC.Uart.RX_FIFO.empty $flatten\SOC.\Uart.$procmux$2044_CMP $flatten\SOC.\Uart.$ne$Risco-5/src/peripheral/uart.v:113$1366_Y }. No candidates found. Analyzing resource sharing options for $flatten\SOC.\Memory.$memrd$\memory$Risco-5/src/peripheral/memory.v:24$1384 ($memrd): Found 7 activation_patterns using ctrl signal { $flatten\SOC.\Memory.$procmux$1849_CMP $flatten\SOC.\Memory.$procmux$1848_CMP $flatten\SOC.\Memory.$procmux$1847_CMP $flatten\SOC.\Memory.$procmux$1846_CMP \SOC.Memory.option [1:0] \SOC.Memory.memory_write \SOC.Memory.memory_read $flatten\SOC.\Bus.$eq$Risco-5/src/peripheral/bus.v:48$176_Y }. No candidates found. Analyzing resource sharing options for $flatten\SOC.\Core.\RegisterBank.$memrd$\registers$Risco-5/src/core/registers.v:22$155 ($memrd): Found 12 activation_patterns using ctrl signal { $flatten\SOC.\Core.\Alu.$procmux$3704_CMP $flatten\SOC.\Core.\Alu.$procmux$3705_CMP $flatten\SOC.\Core.\Alu.$procmux$3706_CMP $flatten\SOC.\Core.\Alu.$procmux$3707_CMP $flatten\SOC.\Core.\Alu.$procmux$3708_CMP $flatten\SOC.\Core.\Alu.$procmux$3709_CMP $flatten\SOC.\Core.\Alu.$procmux$3712_CMP $flatten\SOC.\Core.\Alu.$procmux$3713_CMP $flatten\SOC.\Core.\Alu.$procmux$3714_CMP $flatten\SOC.\Core.\Alu.$procmux$3715_CMP $flatten\SOC.\Core.\AluInputBMUX.$eq$Risco-5/src/core/mux.v:14$129_Y $flatten\SOC.\Core.\AluInputBMUX.$eq$Risco-5/src/core/mux.v:15$130_Y $flatten\SOC.\Core.\AluInputBMUX.$eq$Risco-5/src/core/mux.v:16$131_Y $flatten\SOC.\Core.\AluInputBMUX.$eq$Risco-5/src/core/mux.v:17$132_Y $auto$opt_reduce.cc:134:opt_pmux$3945 $auto$opt_reduce.cc:134:opt_pmux$3943 }. No candidates found. Analyzing resource sharing options for $flatten\SOC.\Core.\Alu.$sshr$Risco-5/src/core/alu.v:51$26 ($sshr): Found 1 activation_patterns using ctrl signal $flatten\SOC.\Core.\Alu.$procmux$3704_CMP. No candidates found. Analyzing resource sharing options for $flatten\SOC.\Core.\Alu.$shr$Risco-5/src/core/alu.v:49$25 ($shr): Found 1 activation_patterns using ctrl signal $flatten\SOC.\Core.\Alu.$procmux$3705_CMP. No candidates found. Analyzing resource sharing options for $flatten\SOC.\Core.\Alu.$shl$Risco-5/src/core/alu.v:47$24 ($shl): Found 1 activation_patterns using ctrl signal $flatten\SOC.\Core.\Alu.$procmux$3706_CMP. No candidates found. 24.18. Executing TECHMAP pass (map to technology primitives). 24.18.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/cmp2lut.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/cmp2lut.v' to AST representation. Generating RTLIL representation for module `\_90_lut_cmp_'. Successfully finished Verilog frontend. 24.18.2. Continuing TECHMAP pass. No more expansions possible. <suppressed ~114 debug messages> 24.19. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 24.20. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 24.21. Executing TECHMAP pass (map to technology primitives). 24.21.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v' to AST representation. Generating RTLIL representation for module `\_80_mul'. Generating RTLIL representation for module `\_90_soft_mul'. Successfully finished Verilog frontend. 24.21.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/dsp_map.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/dsp_map.v' to AST representation. Generating RTLIL representation for module `\$__MUL18X18'. Successfully finished Verilog frontend. 24.21.3. Continuing TECHMAP pass. No more expansions possible. <suppressed ~5 debug messages> 24.22. Executing ALUMACC pass (create $alu and $macc cells). Extracting $alu and $macc cells in module top: creating $macc model for $flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$805 ($add). creating $macc model for $flatten\SOC.\Core.$add$Risco-5/src/core/core.v:150$966 ($add). creating $macc model for $flatten\SOC.\Core.$sub$Risco-5/src/core/core.v:148$965 ($sub). creating $macc model for $flatten\SOC.\Core.\Alu.$add$Risco-5/src/core/alu.v:33$14 ($add). creating $macc model for $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:35$15 ($sub). creating $macc model for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:114$121 ($add). creating $macc model for $flatten\SOC.\GPIOS.\Pwm0.$add$Risco-5/src/peripheral/pwm.v:17$458 ($add). creating $macc model for $flatten\SOC.\GPIOS.\Pwm1.$add$Risco-5/src/peripheral/pwm.v:17$458 ($add). creating $macc model for $flatten\SOC.\Uart.$add$Risco-5/src/peripheral/uart.v:115$1368 ($add). creating $macc model for $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$1538 ($add). creating $macc model for $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:37$1540 ($add). creating $macc model for $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:40$1546 ($add). creating $macc model for $flatten\SOC.\Uart.\RX_FIFO.$sub$Risco-5/src/peripheral/fifo.v:39$1544 ($sub). creating $macc model for $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$1538 ($add). creating $macc model for $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:37$1540 ($add). creating $macc model for $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:40$1546 ($add). creating $macc model for $flatten\SOC.\Uart.\TX_FIFO.$sub$Risco-5/src/peripheral/fifo.v:39$1544 ($sub). creating $macc model for $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:146$1506 ($add). creating $macc model for $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:171$1517 ($add). creating $macc model for $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:132$1455 ($add). creating $macc model for $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:149$1466 ($add). creating $alu model for $macc $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:149$1466. creating $alu model for $macc $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:132$1455. creating $alu model for $macc $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:171$1517. creating $alu model for $macc $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:146$1506. creating $alu model for $macc $flatten\SOC.\Uart.\TX_FIFO.$sub$Risco-5/src/peripheral/fifo.v:39$1544. creating $alu model for $macc $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:40$1546. creating $alu model for $macc $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:37$1540. creating $alu model for $macc $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$1538. creating $alu model for $macc $flatten\SOC.\Uart.\RX_FIFO.$sub$Risco-5/src/peripheral/fifo.v:39$1544. creating $alu model for $macc $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:40$1546. creating $alu model for $macc $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:37$1540. creating $alu model for $macc $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$1538. creating $alu model for $macc $flatten\SOC.\Uart.$add$Risco-5/src/peripheral/uart.v:115$1368. creating $alu model for $macc $flatten\SOC.\GPIOS.\Pwm1.$add$Risco-5/src/peripheral/pwm.v:17$458. creating $alu model for $macc $flatten\SOC.\GPIOS.\Pwm0.$add$Risco-5/src/peripheral/pwm.v:17$458. creating $alu model for $macc $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:114$121. creating $alu model for $macc $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:35$15. creating $alu model for $macc $flatten\SOC.\Core.\Alu.$add$Risco-5/src/core/alu.v:33$14. creating $alu model for $macc $flatten\SOC.\Core.$sub$Risco-5/src/core/core.v:148$965. creating $alu model for $macc $flatten\SOC.\Core.$add$Risco-5/src/core/core.v:150$966. creating $alu model for $macc $flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$805. creating $alu model for $flatten\ResetBootSystem.$lt$Risco-5/debug/reset.v:36$804 ($lt): new $alu creating $alu model for $flatten\SOC.\Core.\Alu.$ge$Risco-5/src/core/alu.v:53$27 ($ge): merged with $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:35$15. creating $alu model for $flatten\SOC.\Core.\Alu.$lt$Risco-5/src/core/alu.v:37$16 ($lt): merged with $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:35$15. creating $alu model for $flatten\SOC.\GPIOS.\Pwm0.$lt$Risco-5/src/peripheral/pwm.v:16$457 ($lt): new $alu creating $alu model for $flatten\SOC.\GPIOS.\Pwm0.$lt$Risco-5/src/peripheral/pwm.v:23$459 ($lt): new $alu creating $alu model for $flatten\SOC.\GPIOS.\Pwm1.$lt$Risco-5/src/peripheral/pwm.v:16$457 ($lt): new $alu creating $alu model for $flatten\SOC.\GPIOS.\Pwm1.$lt$Risco-5/src/peripheral/pwm.v:23$459 ($lt): new $alu creating $alu model for $flatten\ResetBootSystem.$eq$Risco-5/debug/reset.v:38$806 ($eq): merged with $flatten\ResetBootSystem.$lt$Risco-5/debug/reset.v:36$804. creating $alu model for $flatten\SOC.\Core.\Alu.$eq$Risco-5/src/core/alu.v:45$23 ($eq): merged with $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:35$15. creating $alu cell for $flatten\SOC.\GPIOS.\Pwm1.$lt$Risco-5/src/peripheral/pwm.v:23$459: $auto$alumacc.cc:485:replace_alu$4286 creating $alu cell for $flatten\SOC.\GPIOS.\Pwm1.$lt$Risco-5/src/peripheral/pwm.v:16$457: $auto$alumacc.cc:485:replace_alu$4297 creating $alu cell for $flatten\SOC.\GPIOS.\Pwm0.$lt$Risco-5/src/peripheral/pwm.v:23$459: $auto$alumacc.cc:485:replace_alu$4308 creating $alu cell for $flatten\SOC.\GPIOS.\Pwm0.$lt$Risco-5/src/peripheral/pwm.v:16$457: $auto$alumacc.cc:485:replace_alu$4319 creating $alu cell for $flatten\ResetBootSystem.$lt$Risco-5/debug/reset.v:36$804, $flatten\ResetBootSystem.$eq$Risco-5/debug/reset.v:38$806: $auto$alumacc.cc:485:replace_alu$4330 creating $alu cell for $flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$805: $auto$alumacc.cc:485:replace_alu$4341 creating $alu cell for $flatten\SOC.\Core.$add$Risco-5/src/core/core.v:150$966: $auto$alumacc.cc:485:replace_alu$4344 creating $alu cell for $flatten\SOC.\Core.$sub$Risco-5/src/core/core.v:148$965: $auto$alumacc.cc:485:replace_alu$4347 creating $alu cell for $flatten\SOC.\Core.\Alu.$add$Risco-5/src/core/alu.v:33$14: $auto$alumacc.cc:485:replace_alu$4350 creating $alu cell for $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:35$15, $flatten\SOC.\Core.\Alu.$ge$Risco-5/src/core/alu.v:53$27, $flatten\SOC.\Core.\Alu.$lt$Risco-5/src/core/alu.v:37$16, $flatten\SOC.\Core.\Alu.$eq$Risco-5/src/core/alu.v:45$23: $auto$alumacc.cc:485:replace_alu$4353 creating $alu cell for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:114$121: $auto$alumacc.cc:485:replace_alu$4366 creating $alu cell for $flatten\SOC.\GPIOS.\Pwm0.$add$Risco-5/src/peripheral/pwm.v:17$458: $auto$alumacc.cc:485:replace_alu$4369 creating $alu cell for $flatten\SOC.\GPIOS.\Pwm1.$add$Risco-5/src/peripheral/pwm.v:17$458: $auto$alumacc.cc:485:replace_alu$4372 creating $alu cell for $flatten\SOC.\Uart.$add$Risco-5/src/peripheral/uart.v:115$1368: $auto$alumacc.cc:485:replace_alu$4375 creating $alu cell for $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$1538: $auto$alumacc.cc:485:replace_alu$4378 creating $alu cell for $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:37$1540: $auto$alumacc.cc:485:replace_alu$4381 creating $alu cell for $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:40$1546: $auto$alumacc.cc:485:replace_alu$4384 creating $alu cell for $flatten\SOC.\Uart.\RX_FIFO.$sub$Risco-5/src/peripheral/fifo.v:39$1544: $auto$alumacc.cc:485:replace_alu$4387 creating $alu cell for $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$1538: $auto$alumacc.cc:485:replace_alu$4390 creating $alu cell for $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:37$1540: $auto$alumacc.cc:485:replace_alu$4393 creating $alu cell for $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:40$1546: $auto$alumacc.cc:485:replace_alu$4396 creating $alu cell for $flatten\SOC.\Uart.\TX_FIFO.$sub$Risco-5/src/peripheral/fifo.v:39$1544: $auto$alumacc.cc:485:replace_alu$4399 creating $alu cell for $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:146$1506: $auto$alumacc.cc:485:replace_alu$4402 creating $alu cell for $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:171$1517: $auto$alumacc.cc:485:replace_alu$4405 creating $alu cell for $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:132$1455: $auto$alumacc.cc:485:replace_alu$4408 creating $alu cell for $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:149$1466: $auto$alumacc.cc:485:replace_alu$4411 created 26 $alu and 0 $macc cells. 24.23. Executing OPT pass (performing simple optimizations). 24.23.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~7 debug messages> 24.23.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 24.23.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~105 debug messages> 24.23.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 24.23.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~6 debug messages> Removed a total of 2 cells. 24.23.6. Executing OPT_DFF pass (perform DFF optimizations). 24.23.7. Executing OPT_CLEAN pass (remove unused cells and wires). Compiling module 'LEDs'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/leds.v":1) Compiling module 'UART(CLK_FREQ=27000000,BIT_RATE=115200,BUFFER_SIZE=16)'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart.v":1) Compiling module 'FIFO(DEPTH=16)'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/fifo.v":1) Extracting RAM for identifier 'memory'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/fifo.v":16) WARN (EX3791) : Expression size 7 truncated to fit in target size 6("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/fifo.v":40) Compiling module 'uart_tool_rx(BIT_RATE=115200,CLK_HZ=27000000)'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_rx.v":10) Compiling module 'uart_tool_tx(BIT_RATE=115200,CLK_HZ=27000000)'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_tx.v":10) Compiling module 'GPIOS(WIDHT=5)'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":1) Compiling module 'GPIO'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpio.v":1) Compiling module 'PWM'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/pwm.v":1) WARN (EX2565) : Input 'halt' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":43) WARN (EX2565) : Input 'interruption_request_external' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":43) WARN (EX2565) : Input 'interruption_request_timer' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":43) WARN (EX2565) : Input 'interruption_request_software' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":43) WARN (EX2565) : Input 'interruption_request_fast[15]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":43) WARN (EX2565) : Input 'interruption_request_fast[14]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":43) WARN (EX2565) : Input 'interruption_request_fast[13]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":43) WARN (EX2565) : Input 'interruption_request_fast[12]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":43) WARN (EX2565) : Input 'interruption_request_fast[11]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":43) WARN (EX2565) : Input 'interruption_request_fast[10]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":43) WARN (EX2565) : Input 'interruption_request_fast[9]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":43) WARN (EX2565) : Input 'interruption_request_fast[8]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":43) WARN (EX2565) : Input 'interruption_request_fast[7]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":43) WARN (EX2565) : Input 'interruption_request_fast[6]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":43) WARN (EX2565) : Input 'interruption_request_fast[5]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":43) WARN (EX2565) : Input 'interruption_request_fast[4]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":43) WARN (EX2565) : Input 'interruption_request_fast[3]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":43) WARN (EX2565) : Input 'interruption_request_fast[2]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":43) WARN (EX2565) : Input 'interruption_request_fast[1]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":43) WARN (EX2565) : Input 'interruption_request_fast[0]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":43) NOTE (EX0101) : Current top module is "top" [5%] Running netlist conversion ... Finding unused cells or wires in module \top.. Removed 4 unused cells and 17 unused wires. <suppressed ~5 debug messages> 24.23.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 24.23.9. Rerunning OPT passes. (Maybe there is more to do..) 24.23.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~105 debug messages> 24.23.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 24.23.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 24.23.13. Executing OPT_DFF pass (perform DFF optimizations). 24.23.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 24.23.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 24.23.16. Finished OPT passes. (There is nothing left to do.) 24.24. Executing MEMORY pass. 24.24.1. Executing OPT_MEM pass (optimize memories). Performed a total of 0 transformations. 24.24.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). Performed a total of 0 transformations. 24.24.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). Analyzing top.SOC.Core.RegisterBank.registers write port 0. Analyzing top.SOC.Core.RegisterBank.registers write port 1. Analyzing top.SOC.Core.RegisterBank.registers write port 2. Analyzing top.SOC.GPIOS.duty_cycle write port 0. Analyzing top.SOC.GPIOS.period write port 0. Analyzing top.SOC.Memory.memory write port 0. Analyzing top.SOC.Memory.memory write port 1. Analyzing top.SOC.Memory.memory write port 2. Analyzing top.SOC.Uart.RX_FIFO.memory write port 0. Analyzing top.SOC.Uart.TX_FIFO.memory write port 0. 24.24.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). 24.24.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). Checking read port `\SOC.Core.RegisterBank.registers'[0] in module `\top': no output FF found. Checking read port `\SOC.Core.RegisterBank.registers'[1] in module `\top': no output FF found. Checking read port `\SOC.Core.RegisterBank.registers'[2] in module `\top': merging output FF to cell. Write port 0: don't care on collision. Write port 1: non-transparent. Write port 2: non-transparent. Checking read port `\SOC.GPIOS.duty_cycle'[0] in module `\top': no output FF found. Checking read port `\SOC.GPIOS.duty_cycle'[1] in module `\top': no output FF found. Checking read port `\SOC.GPIOS.period'[0] in module `\top': no output FF found. Checking read port `\SOC.GPIOS.period'[1] in module `\top': no output FF found. Checking read port `\SOC.Memory.memory'[0] in module `\top': no output FF found. Checking read port `\SOC.Uart.RX_FIFO.memory'[0] in module `\top': no output FF found. Checking read port `\SOC.Uart.TX_FIFO.memory'[0] in module `\top': merging output FF to cell. Write port 0: non-transparent. Checking read port address `\SOC.Core.RegisterBank.registers'[0] in module `\top': address FF has fully-defined init value, not supported. Checking read port address `\SOC.Core.RegisterBank.registers'[1] in module `\top': address FF has fully-defined init value, not supported. Checking read port address `\SOC.GPIOS.duty_cycle'[0] in module `\top': no address FF found. Checking read port address `\SOC.GPIOS.duty_cycle'[1] in module `\top': no address FF found. Checking read port address `\SOC.GPIOS.period'[0] in module `\top': no address FF found. Checking read port address `\SOC.GPIOS.period'[1] in module `\top': no address FF found. Checking read port address `\SOC.Memory.memory'[0] in module `\top': no address FF found. Checking read port address `\SOC.Uart.RX_FIFO.memory'[0] in module `\top': address FF has fully-defined init value, not supported. 24.24.6. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 2 unused cells and 44 unused wires. <suppressed ~7 debug messages> 24.24.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). Consolidating read ports of memory top.SOC.Core.RegisterBank.registers by address: Consolidating write ports of memory top.SOC.Core.RegisterBank.registers by address: Merging ports 0, 2 (address 5'00000). Consolidating write ports of memory top.SOC.Core.RegisterBank.registers by address: Consolidating read ports of memory top.SOC.GPIOS.duty_cycle by address: Merging ports 0, 1 (address 1'1). Consolidating read ports of memory top.SOC.GPIOS.period by address: Merging ports 0, 1 (address 1'1). Consolidating write ports of memory top.SOC.Memory.memory by address: Merging ports 0, 1 (address { \SOC.Memory.address [10:8] \SOC.GPIOS.address [7:2] }). Merging ports 0, 2 (address { \SOC.Memory.address [10:8] \SOC.GPIOS.address [7:2] }). Consolidating write ports of memory top.SOC.Core.RegisterBank.registers using sat-based resource sharing: Checking group clocked with posedge \clk, width 32: ports 0, 1. Common input cone for all EN signals: 13 cells. Size of unconstrained SAT problem: 103 variables, 281 clauses Merging port 1 into port 0. 24.24.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). Performed a total of 0 transformations. 24.24.9. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 8 unused cells and 10 unused wires. <suppressed ~9 debug messages> 24.24.10. Executing MEMORY_COLLECT pass (generating $mem cells). 24.25. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 24.26. Executing MEMORY_LIBMAP pass (mapping memories to cells). WARN (CV0016) : Input reset is unused("/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/main.v":3) Running device independent optimization ... mapping memory top.SOC.Core.RegisterBank.registers via $__TRELLIS_DPR16X4_ Extracted data FF from read port 2 of top.SOC.Core.RegisterBank.registers: $\SOC.Core.RegisterBank.registers$rdreg[2] using FF mapping for memory top.SOC.GPIOS.duty_cycle using FF mapping for memory top.SOC.GPIOS.period mapping memory top.SOC.Memory.memory via $__TRELLIS_DPR16X4_ mapping memory top.SOC.Uart.RX_FIFO.memory via $__TRELLIS_DPR16X4_ mapping memory top.SOC.Uart.TX_FIFO.memory via $__TRELLIS_DPR16X4_ Extracted data FF from read port 0 of top.SOC.Uart.TX_FIFO.memory: $\SOC.Uart.TX_FIFO.memory$rdreg[0] <suppressed ~841 debug messages> 24.27. Executing TECHMAP pass (map to technology primitives). 24.27.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/lutrams_map.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/lutrams_map.v' to AST representation. Generating RTLIL representation for module `\$__TRELLIS_DPR16X4_'. Successfully finished Verilog frontend. 24.27.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/brams_map.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/brams_map.v' to AST representation. Generating RTLIL representation for module `\$__ECP5_DP16KD_'. Generating RTLIL representation for module `\$__ECP5_PDPW16KD_'. Successfully finished Verilog frontend. 24.27.3. Continuing TECHMAP pass. Using template $paramod$514fc941ac1ae997c717a8e6a1180ed8e0cf8fa9\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. [10%] Optimizing Phase 0 completed [15%] Optimizing Phase 1 completed Using template $paramod$04778961cc1285a5efea28f98f28381eb2862208\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$4e27082c5debfe2224cd4cfb46d57ecd26c2e614\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$293d72fa1e0ef78bf22001caecec6073cc652851\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$37d30a593e04dcef256e10d58b011be7c79b1d1f\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$394227e87be903825446790353e91eb2c5e10934\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$02769dd26fe80f975fe33f4663ba95c7f0fadfe5\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$898e3b9b58dbd39d9c6ca83e9bea083cb54c924d\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$e36787c87f120885851706179ae5031aec78e0c5\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$f9f95b558f368450632c01b302c670921c7d458c\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. No more expansions possible. <suppressed ~443 debug messages> 24.28. Executing OPT pass (performing simple optimizations). 24.28.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~108 debug messages> 24.28.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~9 debug messages> Removed a total of 3 cells. 24.28.3. Executing OPT_DFF pass (perform DFF optimizations). Adding SRST signal on $auto$ff.cc:266:slice$4211 ($dffe) from module top (D = $flatten\ResetBootSystem.$procmux$2572_Y, Q = \ResetBootSystem.counter, rval = 6'000000). 24.28.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 2 unused cells and 2260 unused wires. <suppressed ~3 debug messages> 24.28.5. Rerunning OPT passes. (Removed registers in this run.) 24.28.6. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 24.28.7. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 24.28.8. Executing OPT_DFF pass (perform DFF optimizations). Adding SRST signal on $auto$ff.cc:266:slice$5290 ($sdffce) from module top (D = $auto$wreduce.cc:461:run$4235 [5:0], Q = \ResetBootSystem.counter, rval = 6'000000). 24.28.9. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 1 unused cells and 1 unused wires. <suppressed ~2 debug messages> 24.28.10. Rerunning OPT passes. (Removed registers in this run.) 24.28.11. Executing OPT_EXPR pass (perform const folding). [25%] Optimizing Phase 2 completed Running inference ... Optimizing module top. 24.28.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 24.28.13. Executing OPT_DFF pass (perform DFF optimizations). 24.28.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 24.28.15. Finished fast OPT passes. 24.29. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). Mapping memory \SOC.GPIOS.duty_cycle in module \top: created 2 $dff cells and 0 static cells of width 16. read interface: 0 $dff and 0 $mux cells. write interface: 2 write mux blocks. Mapping memory \SOC.GPIOS.period in module \top: created 2 $dff cells and 0 static cells of width 16. read interface: 0 $dff and 0 $mux cells. write interface: 2 write mux blocks. 24.30. Executing OPT pass (performing simple optimizations). 24.30.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~2 debug messages> 24.30.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 24.30.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Replacing known input bits on port B of cell $auto$memory_share.cc:453:consolidate_wr_using_sat$4493: $auto$rtlil.cc:2489:ReduceOr$4487 -> 1'1 Analyzing evaluation results. dead port 2/2 on $mux $flatten\SOC.\Core.\PCSourceMUX.$ternary$Risco-5/src/core/mux.v:15$143. Removed 1 multiplexer ports. <suppressed ~69 debug messages> 24.30.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Consolidated identical input bits for $mux cell $auto$memory_share.cc:273:consolidate_wr_by_addr$4478: Old ports: A={ \SOC.Memory.buffer [31:16] \SOC.GPIOS.write_data [15:0] }, B={ \SOC.Leds.write_data [31:17] \SOC.GPIOS.write_data [16:0] }, Y=$auto$rtlil.cc:2582:Mux$4479 New ports: A=\SOC.Memory.buffer [31:16], B={ \SOC.Leds.write_data [31:17] \SOC.GPIOS.write_data [16] }, Y=$auto$rtlil.cc:2582:Mux$4479 [31:16] New connections: $auto$rtlil.cc:2582:Mux$4479 [15:0] = \SOC.GPIOS.write_data [15:0] New ctrl vector for $pmux cell $flatten\ResetBootSystem.$procmux$2581: { $flatten\ResetBootSystem.$procmux$2576_CMP $flatten\ResetBootSystem.$procmux$2575_CMP } Consolidated identical input bits for $mux cell $flatten\ResetBootSystem.$procmux$2584: Old ports: A=2'00, B=2'10, Y=$flatten\ResetBootSystem.$procmux$2584_Y New ports: A=1'0, B=1'1, Y=$flatten\ResetBootSystem.$procmux$2584_Y [1] New connections: $flatten\ResetBootSystem.$procmux$2584_Y [0] = 1'0 Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\ALU_Control.$procmux$3679: Old ports: A=4'1001, B=4'0011, Y=$flatten\SOC.\Core.\ALU_Control.$procmux$3679_Y New ports: A=2'10, B=2'01, Y={ $flatten\SOC.\Core.\ALU_Control.$procmux$3679_Y [3] $flatten\SOC.\Core.\ALU_Control.$procmux$3679_Y [1] } New connections: { $flatten\SOC.\Core.\ALU_Control.$procmux$3679_Y [2] $flatten\SOC.\Core.\ALU_Control.$procmux$3679_Y [0] } = 2'01 Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\ALU_Control.$procmux$3687: Old ports: A=3'010, B=3'110, Y=$auto$wreduce.cc:461:run$4236 [2:0] New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:461:run$4236 [2] New connections: $auto$wreduce.cc:461:run$4236 [1:0] = 2'10 Consolidated identical input bits for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2753: Old ports: A=4'0000, B=8'10001001, Y=\SOC.Core.control_unit_aluop New ports: A=2'00, B=4'1011, Y={ \SOC.Core.control_unit_aluop [3] \SOC.Core.control_unit_aluop [0] } New connections: \SOC.Core.control_unit_aluop [2:1] = 2'00 Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2948: Old ports: A=2'00, B=2'10, Y=\SOC.Core.lorD New ports: A=1'0, B=1'1, Y=\SOC.Core.lorD [1] New connections: \SOC.Core.lorD [0] = 1'0 Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$3020: Old ports: A=6'101101, B=6'000000, Y=$flatten\SOC.\Core.\Control_Unit.$19\nextstate[5:0] New ports: A=1'1, B=1'0, Y=$flatten\SOC.\Core.\Control_Unit.$19\nextstate[5:0] [0] New connections: $flatten\SOC.\Core.\Control_Unit.$19\nextstate[5:0] [5:1] = { $flatten\SOC.\Core.\Control_Unit.$19\nextstate[5:0] [0] 1'0 $flatten\SOC.\Core.\Control_Unit.$19\nextstate[5:0] [0] $flatten\SOC.\Core.\Control_Unit.$19\nextstate[5:0] [0] 1'0 } Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$3049: Old ports: A=6'000000, B=6'100101, Y=$flatten\SOC.\Core.\Control_Unit.$17\nextstate[5:0] New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Core.\Control_Unit.$17\nextstate[5:0] [0] New connections: $flatten\SOC.\Core.\Control_Unit.$17\nextstate[5:0] [5:1] = { $flatten\SOC.\Core.\Control_Unit.$17\nextstate[5:0] [0] 2'00 $flatten\SOC.\Core.\Control_Unit.$17\nextstate[5:0] [0] 1'0 } Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$3084: Old ports: A=3'000, B=3'100, Y=$auto$wreduce.cc:461:run$4245 [2:0] New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:461:run$4245 [2] New connections: $auto$wreduce.cc:461:run$4245 [1:0] = 2'00 Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$3105: Old ports: A=6'011111, B=6'100010, Y=$flatten\SOC.\Core.\Control_Unit.$14\nextstate[5:0] New ports: A=2'01, B=2'10, Y={ $flatten\SOC.\Core.\Control_Unit.$14\nextstate[5:0] [5] $flatten\SOC.\Core.\Control_Unit.$14\nextstate[5:0] [0] } New connections: $flatten\SOC.\Core.\Control_Unit.$14\nextstate[5:0] [4:1] = { $flatten\SOC.\Core.\Control_Unit.$14\nextstate[5:0] [0] $flatten\SOC.\Core.\Control_Unit.$14\nextstate[5:0] [0] $flatten\SOC.\Core.\Control_Unit.$14\nextstate[5:0] [0] 1'1 } Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$3130: Old ports: A=3'110, B=3'011, Y=$auto$wreduce.cc:461:run$4244 [2:0] New ports: A=2'10, B=2'01, Y={ $auto$wreduce.cc:461:run$4244 [2] $auto$wreduce.cc:461:run$4244 [0] } New connections: $auto$wreduce.cc:461:run$4244 [1] = 1'1 Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$3187: Old ports: A=3'011, B=3'100, Y=$auto$wreduce.cc:461:run$4242 [2:0] New ports: A=2'01, B=2'10, Y={ $auto$wreduce.cc:461:run$4242 [2] $auto$wreduce.cc:461:run$4242 [0] } New connections: $auto$wreduce.cc:461:run$4242 [1] = $auto$wreduce.cc:461:run$4242 [0] Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$3220: Old ports: A=5'00000, B=5'10010, Y=$auto$wreduce.cc:461:run$4241 [4:0] New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:461:run$4241 [1] New connections: { $auto$wreduce.cc:461:run$4241 [4:2] $auto$wreduce.cc:461:run$4241 [0] } = { $auto$wreduce.cc:461:run$4241 [1] 3'000 } Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$3265: Old ports: A=3'101, B=3'000, Y=$auto$wreduce.cc:461:run$4252 [2:0] New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$4252 [0] New connections: $auto$wreduce.cc:461:run$4252 [2:1] = { $auto$wreduce.cc:461:run$4252 [0] 1'0 } Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$3312: Old ports: A=3'110, B=3'000, Y=$auto$wreduce.cc:461:run$4251 [2:0] New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$4251 [1] New connections: { $auto$wreduce.cc:461:run$4251 [2] $auto$wreduce.cc:461:run$4251 [0] } = { $auto$wreduce.cc:461:run$4251 [1] 1'0 } Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$3409: Old ports: A=5'00101, B=5'11000, Y=$auto$wreduce.cc:461:run$4249 [4:0] New ports: A=2'01, B=2'10, Y={ $auto$wreduce.cc:461:run$4249 [3] $auto$wreduce.cc:461:run$4249 [0] } New connections: { $auto$wreduce.cc:461:run$4249 [4] $auto$wreduce.cc:461:run$4249 [2:1] } = { $auto$wreduce.cc:461:run$4249 [3] $auto$wreduce.cc:461:run$4249 [0] 1'0 } Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$3462: Old ports: A=5'00011, B=5'10110, Y=$auto$wreduce.cc:461:run$4248 [4:0] New ports: A=2'01, B=2'10, Y={ $auto$wreduce.cc:461:run$4248 [2] $auto$wreduce.cc:461:run$4248 [0] } New connections: { $auto$wreduce.cc:461:run$4248 [4:3] $auto$wreduce.cc:461:run$4248 [1] } = { $auto$wreduce.cc:461:run$4248 [2] 2'01 } Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$3513: Old ports: A={ 1'0 $auto$wreduce.cc:461:run$4249 [4:0] }, B={ 1'0 $auto$wreduce.cc:461:run$4248 [4:0] }, Y=$flatten\SOC.\Core.\Control_Unit.$4\nextstate[5:0] New ports: A=$auto$wreduce.cc:461:run$4249 [4:0], B=$auto$wreduce.cc:461:run$4248 [4:0], Y=$flatten\SOC.\Core.\Control_Unit.$4\nextstate[5:0] [4:0] New connections: $flatten\SOC.\Core.\Control_Unit.$4\nextstate[5:0] [5] = 1'0 Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$3624: Old ports: A=6'000000, B=6'101110, Y=$flatten\SOC.\Core.\Control_Unit.$2\nextstate[5:0] New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Core.\Control_Unit.$2\nextstate[5:0] [1] New connections: { $flatten\SOC.\Core.\Control_Unit.$2\nextstate[5:0] [5:2] $flatten\SOC.\Core.\Control_Unit.$2\nextstate[5:0] [0] } = { $flatten\SOC.\Core.\Control_Unit.$2\nextstate[5:0] [1] 1'0 $flatten\SOC.\Core.\Control_Unit.$2\nextstate[5:0] [1] $flatten\SOC.\Core.\Control_Unit.$2\nextstate[5:0] [1] 1'0 } Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$ternary$Risco-5/src/core/control_unit.v:111$38: Old ports: A=2'11, B=2'01, Y=\SOC.Core.Control_Unit.second_block_write_src_b [1:0] New ports: A=1'1, B=1'0, Y=\SOC.Core.Control_Unit.second_block_write_src_b [1] New connections: \SOC.Core.Control_Unit.second_block_write_src_b [0] = 1'1 Consolidated identical input bits for $pmux cell $flatten\SOC.\Core.\Immediate_Generator.$procmux$2465: Old ports: A={ \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31:20] }, B={ \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24:20] 20'00000000000000000000 \SOC.Core.instruction_register [31:20] 27'000000000000000000000000000 \SOC.Core.instruction_register [24:20] }, Y=$flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] New ports: A={ \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31:25] }, B={ \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] 1'0 \SOC.Core.instruction_register [31:25] 8'00000000 }, Y=$flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12:5] New connections: { $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [31:13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [4:0] } = { $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] \SOC.Core.instruction_register [24:20] } Consolidated identical input bits for $pmux cell $flatten\SOC.\Memory.$procmux$1845: Old ports: A=\SOC.Memory.buffer, B={ \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7:0] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15:0] 24'000000000000000000000000 \SOC.Memory.buffer [7:0] 16'0000000000000000 \SOC.Memory.buffer [15:0] }, Y=\SOC.Bus.slave_0_read_data New ports: A=\SOC.Memory.buffer [31:8], B={ \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15:8] 40'0000000000000000000000000000000000000000 \SOC.Memory.buffer [15:8] }, Y=\SOC.Bus.slave_0_read_data [31:8] New connections: \SOC.Bus.slave_0_read_data [7:0] = \SOC.Memory.buffer [7:0] New ctrl vector for $pmux cell $flatten\SOC.\Uart.$procmux$2119: $auto$opt_reduce.cc:134:opt_pmux$5325 New ctrl vector for $pmux cell $flatten\SOC.\Uart.$procmux$2133: { $flatten\SOC.\Uart.$procmux$2127_CMP $flatten\SOC.\Uart.$procmux$2069_CMP $auto$opt_reduce.cc:134:opt_pmux$5327 $flatten\SOC.\Uart.$procmux$2050_Y } Consolidated identical input bits for $pmux cell $flatten\SOC.\Uart.$procmux$2150: Old ports: A=4'0001, B=16'0110011110001001, Y=$flatten\SOC.\Uart.$procmux$2150_Y New ports: A=3'001, B=12'010011100101, Y={ $flatten\SOC.\Uart.$procmux$2150_Y [3] $flatten\SOC.\Uart.$procmux$2150_Y [1:0] } New connections: $flatten\SOC.\Uart.$procmux$2150_Y [2] = $flatten\SOC.\Uart.$procmux$2150_Y [1] Consolidated identical input bits for $pmux cell $flatten\SOC.\Uart.\i_uart_rx.$procmux$1701: Old ports: A=3'000, B={ 2'00 $auto$wreduce.cc:461:run$4272 [0] 1'0 $auto$wreduce.cc:461:run$4273 [1:0] 2'01 \SOC.Uart.i_uart_rx.payload_done 1'0 $auto$wreduce.cc:461:run$4275 [1:0] }, Y=\SOC.Uart.i_uart_rx.n_fsm_state New ports: A=2'00, B={ 1'0 $auto$wreduce.cc:461:run$4272 [0] $auto$wreduce.cc:461:run$4273 [1:0] 1'1 \SOC.Uart.i_uart_rx.payload_done $auto$wreduce.cc:461:run$4275 [1:0] }, Y=\SOC.Uart.i_uart_rx.n_fsm_state [1:0] New connections: \SOC.Uart.i_uart_rx.n_fsm_state [2] = 1'0 Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:113$1495: Old ports: A=2'11, B=2'00, Y=$auto$wreduce.cc:461:run$4275 [1:0] New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$4275 [0] New connections: $auto$wreduce.cc:461:run$4275 [1] = $auto$wreduce.cc:461:run$4275 [0] Consolidated identical input bits for $pmux cell $flatten\SOC.\Uart.\i_uart_tx.$procmux$1838: Old ports: A=3'000, B={ 2'00 \SOC.Uart.uart_tx_en 1'0 $auto$wreduce.cc:461:run$4277 [1:0] 2'01 \SOC.Uart.i_uart_tx.payload_done 1'0 $auto$wreduce.cc:461:run$4279 [1:0] }, Y=\SOC.Uart.i_uart_tx.n_fsm_state New ports: A=2'00, B={ 1'0 \SOC.Uart.uart_tx_en $auto$wreduce.cc:461:run$4277 [1:0] 1'1 \SOC.Uart.i_uart_tx.payload_done $auto$wreduce.cc:461:run$4279 [1:0] }, Y=\SOC.Uart.i_uart_tx.n_fsm_state [1:0] New connections: \SOC.Uart.i_uart_tx.n_fsm_state [2] = 1'0 Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:97$1438: Old ports: A=2'11, B=2'00, Y=$auto$wreduce.cc:461:run$4279 [1:0] New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$4279 [0] New connections: $auto$wreduce.cc:461:run$4279 [1] = $auto$wreduce.cc:461:run$4279 [0] New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_pmux$5326: { $flatten\SOC.\Uart.$procmux$2097_CMP $flatten\SOC.\Uart.$procmux$2096_CMP $flatten\SOC.\Uart.$procmux$2095_CMP $flatten\SOC.\Uart.$procmux$2094_CMP $flatten\SOC.\Uart.$procmux$2044_CMP $flatten\SOC.\Uart.$procmux$2025_CMP } Optimizing cells in module \top. Consolidated identical input bits for $mux cell $auto$memory_share.cc:273:consolidate_wr_by_addr$4482: Old ports: A=$auto$rtlil.cc:2582:Mux$4479, B={ \SOC.Memory.buffer [31:8] \SOC.GPIOS.write_data [7:0] }, Y=$auto$rtlil.cc:2582:Mux$4483 New ports: A={ $auto$rtlil.cc:2582:Mux$4479 [31:16] \SOC.GPIOS.write_data [15:8] }, B=\SOC.Memory.buffer [31:8], Y=$auto$rtlil.cc:2582:Mux$4483 [31:8] New connections: $auto$rtlil.cc:2582:Mux$4483 [7:0] = \SOC.GPIOS.write_data [7:0] Consolidated identical input bits for $mux cell $flatten\ResetBootSystem.$procmux$2590: Old ports: A=2'00, B=$flatten\ResetBootSystem.$procmux$2584_Y, Y=$flatten\ResetBootSystem.$procmux$2590_Y New ports: A=1'0, B=$flatten\ResetBootSystem.$procmux$2584_Y [1], Y=$flatten\ResetBootSystem.$procmux$2590_Y [1] New connections: $flatten\ResetBootSystem.$procmux$2590_Y [0] = 1'0 Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$3066: Old ports: A=6'100001, B=$flatten\SOC.\Core.\Control_Unit.$17\nextstate[5:0], Y=$flatten\SOC.\Core.\Control_Unit.$16\nextstate[5:0] New ports: A=2'01, B={ $flatten\SOC.\Core.\Control_Unit.$17\nextstate[5:0] [0] $flatten\SOC.\Core.\Control_Unit.$17\nextstate[5:0] [0] }, Y={ $flatten\SOC.\Core.\Control_Unit.$16\nextstate[5:0] [2] $flatten\SOC.\Core.\Control_Unit.$16\nextstate[5:0] [0] } New connections: { $flatten\SOC.\Core.\Control_Unit.$16\nextstate[5:0] [5:3] $flatten\SOC.\Core.\Control_Unit.$16\nextstate[5:0] [1] } = { $flatten\SOC.\Core.\Control_Unit.$16\nextstate[5:0] [0] 3'000 } Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.$procmux$2155: Old ports: A=4'0000, B=$flatten\SOC.\Uart.$procmux$2150_Y, Y=$flatten\SOC.\Uart.$procmux$2155_Y New ports: A=3'000, B={ $flatten\SOC.\Uart.$procmux$2150_Y [3] $flatten\SOC.\Uart.$procmux$2150_Y [1:0] }, Y={ $flatten\SOC.\Uart.$procmux$2155_Y [3] $flatten\SOC.\Uart.$procmux$2155_Y [1:0] } New connections: $flatten\SOC.\Uart.$procmux$2155_Y [2] = $flatten\SOC.\Uart.$procmux$2155_Y [1] Optimizing cells in module \top. Performed a total of 38 changes. 24.30.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~12 debug messages> Removed a total of 4 cells. 24.30.6. Executing OPT_DFF pass (perform DFF optimizations). Adding SRST signal on $auto$ff.cc:266:slice$4107 ($dffe) from module top (D = $flatten\SOC.\Uart.$add$Risco-5/src/peripheral/uart.v:115$1368_Y, Q = \SOC.Uart.counter, rval = 3'000). 24.30.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 2 unused cells and 12 unused wires. <suppressed ~3 debug messages> 24.30.8. Executing OPT_EXPR pass (perform const folding). [30%] Inferring Phase 0 completed [40%] Inferring Phase 1 completed [50%] Inferring Phase 2 completed [55%] Inferring Phase 3 completed Running technical mapping ... Optimizing module top. <suppressed ~8 debug messages> 24.30.9. Rerunning OPT passes. (Maybe there is more to do..) 24.30.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. dead port 2/2 on $mux $flatten\SOC.\Core.\MemoryAddressMUX.$ternary$Risco-5/src/core/mux.v:16$142. Removed 1 multiplexer ports. <suppressed ~70 debug messages> 24.30.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$3513: Old ports: A={ $auto$wreduce.cc:461:run$4248 [4] $auto$wreduce.cc:461:run$4248 [4] $auto$wreduce.cc:461:run$4248 [0] 1'0 $auto$wreduce.cc:461:run$4248 [0] }, B={ $auto$wreduce.cc:461:run$4248 [4] 1'0 $auto$wreduce.cc:461:run$4248 [4] 1'1 $auto$wreduce.cc:461:run$4248 [0] }, Y=$flatten\SOC.\Core.\Control_Unit.$4\nextstate[5:0] [4:0] New ports: A={ $auto$wreduce.cc:461:run$4248 [4] $auto$wreduce.cc:461:run$4248 [0] 1'0 }, B={ 1'0 $auto$wreduce.cc:461:run$4248 [4] 1'1 }, Y=$flatten\SOC.\Core.\Control_Unit.$4\nextstate[5:0] [3:1] New connections: { $flatten\SOC.\Core.\Control_Unit.$4\nextstate[5:0] [4] $flatten\SOC.\Core.\Control_Unit.$4\nextstate[5:0] [0] } = { $auto$wreduce.cc:461:run$4248 [4] $auto$wreduce.cc:461:run$4248 [0] } Optimizing cells in module \top. Performed a total of 1 changes. 24.30.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 24.30.13. Executing OPT_DFF pass (perform DFF optimizations). Adding EN signal on $memory\SOC.GPIOS.period[1]$5314 ($dff) from module top (D = \SOC.GPIOS.write_data [15:0], Q = \SOC.GPIOS.period[1]). Adding EN signal on $memory\SOC.GPIOS.period[0]$5312 ($dff) from module top (D = \SOC.GPIOS.write_data [15:0], Q = \SOC.GPIOS.period[0]). Adding EN signal on $memory\SOC.GPIOS.duty_cycle[1]$5298 ($dff) from module top (D = \SOC.GPIOS.write_data [15:0], Q = \SOC.GPIOS.duty_cycle[1]). Adding EN signal on $memory\SOC.GPIOS.duty_cycle[0]$5296 ($dff) from module top (D = \SOC.GPIOS.write_data [15:0], Q = \SOC.GPIOS.duty_cycle[0]). Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$4017 ($sdff) from module top. 24.30.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 4 unused cells and 10 unused wires. <suppressed ~5 debug messages> 24.30.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~2 debug messages> 24.30.16. Rerunning OPT passes. (Maybe there is more to do..) 24.30.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~67 debug messages> 24.30.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 24.30.19. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 24.30.20. Executing OPT_DFF pass (perform DFF optimizations). 24.30.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 24.30.22. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 24.30.23. Finished OPT passes. (There is nothing left to do.) 24.31. Executing TECHMAP pass (map to technology primitives). 24.31.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/techmap.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu_brent_kung'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `\$__div_mod_u'. Generating RTLIL representation for module `\$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `\$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_pmux'. Generating RTLIL representation for module `\_90_demux'. Generating RTLIL representation for module `\_90_lut'. Successfully finished Verilog frontend. 24.31.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v' to AST representation. Generating RTLIL representation for module `\_80_ecp5_alu'. Successfully finished Verilog frontend. 24.31.3. Continuing TECHMAP pass. Using extmapper simplemap for cells of type $sdffce. Using extmapper simplemap for cells of type $not. Using extmapper simplemap for cells of type $dffe. Using extmapper simplemap for cells of type $and. Using extmapper simplemap for cells of type $reduce_or. Using extmapper simplemap for cells of type $sdff. Using extmapper simplemap for cells of type $sdffe. Using extmapper simplemap for cells of type $mux. Using extmapper simplemap for cells of type $logic_not. Using extmapper simplemap for cells of type $eq. Using template $paramod$521ce43182eecb9f60c72393a788160d2c356bf5\_90_pmux for cells of type $pmux. Using extmapper simplemap for cells of type $reduce_bool. Using template $paramod$32efbfac1c4dc57230cf86180788fdfd12e3b511\_80_ecp5_alu for cells of type $alu. Using template $paramod$175e67c02b86e96b1288b9dc100122520d7240d8\_90_alu for cells of type $alu. Using extmapper simplemap for cells of type $reduce_and. Using extmapper simplemap for cells of type $or. Using extmapper simplemap for cells of type $bmux. Using template $paramod$824a2ca00d29d886599434cf8ea60471635f2955\_90_demux for cells of type $demux. Using template $paramod$2407ada40cc3dda6c6015be2b49b748cddb5a800\_90_demux for cells of type $demux. Using extmapper simplemap for cells of type $ne. Using extmapper simplemap for cells of type $dff. Using template $paramod$2bd81f420048247ff6903399c560fe0f8bd48ccc\_80_ecp5_alu for cells of type $alu. Using template $paramod$e04283ca12514baf3d204c6994bec8f178dd89f8\_80_ecp5_alu for cells of type $alu. Using template $paramod$6a42b6fefed750f8a1c58eab59479d960557103c\_80_ecp5_alu for cells of type $alu. Using template $paramod$3ef7d3dd227da7627a99c5e5a6a4deb817573e39\_90_alu for cells of type $alu. Using extmapper simplemap for cells of type $tribuf. Using extmapper simplemap for cells of type $logic_and. Using template $paramod$b098bc6f249c0ac91c4d6e19d54b23c285914115\_90_pmux for cells of type $pmux. Using template $paramod$20d3ee62d72123142eb855d7ddafd835e31ba009\_90_pmux for cells of type $pmux. Using template $paramod$d31bf4d7d72e59528d18fbd4f322e9d608532043\_90_pmux for cells of type $pmux. Using template $paramod$a04dd9d4d8b430140c4ff94b50470fb380fda2a0\_80_ecp5_alu for cells of type $alu. Using template $paramod$32a7b7b86c07519b7537abc18e96f0331f97914d\_90_alu for cells of type $alu. Using template $paramod$068ad458e7761d78e5eed8238508872e7b0aef95\_90_pmux for cells of type $pmux. Using extmapper simplemap for cells of type $logic_or. Using template $paramod$53700bbee849b2010ad0b60a61ccd204a10e24ca\_80_ecp5_alu for cells of type $alu. Using template $paramod$19e9557905baa9d3741d0daa66e2ef076e9bab7d\_90_pmux for cells of type $pmux. Using template $paramod$fbc7873bff55778c0b3173955b7e4bce1d9d6834\_80_ecp5_alu for cells of type $alu. Using template $paramod$2116a631f856d4d4902c2618dca73dafa3b8c9c0\_90_alu for cells of type $alu. Using template $paramod$4d45682f6d5f8751d24fc75184ef72226da353f7\_90_pmux for cells of type $pmux. Using template $paramod$e13ed4cc4d636b3e93547ec233231d1aa3a8ac92\_90_pmux for cells of type $pmux. Using template $paramod$85df5dc01c7df96a7d8e5f1fdf76ce9ac452af63\_90_pmux for cells of type $pmux. Using template $paramod$e25898cce02b4d043ab08e065e45db8cf66c901c\_90_pmux for cells of type $pmux. Using template $paramod$a285b5a57fe61eabc57c91b8c412748ee1151a85\_90_pmux for cells of type $pmux. Using extmapper simplemap for cells of type $reduce_xor. Using template $paramod$95ab7b964273918a033d1324366ecc612d202989\_90_pmux for cells of type $pmux. Using template $paramod$33afdd83bf3811dac2de7a968d39eea5718691bc\_90_pmux for cells of type $pmux. Using template $paramod$bf2533632d512eac76dd186c0da49367e29b8e98\_90_pmux for cells of type $pmux. Using template $paramod$constmap:4621fcf06a436d1e2a4080e2ed9866a7d07a6e07$paramod$5180471e6f22625c8e3c4261cd538e11648586b5\_90_shift_ops_shr_shl_sshl_sshr for cells of type $sshr. Using template $paramod$constmap:4621fcf06a436d1e2a4080e2ed9866a7d07a6e07$paramod$feecc7a0dbd012970970f2858f15e786e251f677\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shr. Using template $paramod$constmap:4621fcf06a436d1e2a4080e2ed9866a7d07a6e07$paramod$335cfd09f1afa8139c4aafcbbe5f361887b79c5e\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl. Using template $paramod$ed6389a5938b09f91843a91d67becca5abedb1bd\_90_pmux for cells of type $pmux. Using template $paramod$cc80a4e89b0341cb117f5d28b0e7244620640141\_80_ecp5_alu for cells of type $alu. Using extmapper simplemap for cells of type $xor. Using template $paramod$645fe0cc96ae5edb83bff90cc2c78f4a20ca3e3c\_90_pmux for cells of type $pmux. Using template $paramod$49f1dc3dcd6d2c748486fe94c6744a34a19bbafe\_90_pmux for cells of type $pmux. Using extmapper simplemap for cells of type $pos. Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000011 for cells of type $lcu. Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000100 for cells of type $lcu. Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000010 for cells of type $lcu. Using template $paramod$46c272b461898a6a76adeeeedb0917ce1a81b478\_90_demux for cells of type $demux. Using template $paramod$63301a5e78ceb1f2c17a4ac1894f292ed5701c1f\_90_demux for cells of type $demux. No more expansions possible. <suppressed ~4418 debug messages> 24.32. Executing OPT pass (performing simple optimizations). 24.32.1. Executing OPT_EXPR pass (perform const folding). [60%] Tech-Mapping Phase 0 completed [65%] Tech-Mapping Phase 1 completed Optimizing module top. <suppressed ~6386 debug messages> 24.32.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~4488 debug messages> Removed a total of 1496 cells. 24.32.3. Executing OPT_DFF pass (perform DFF optimizations). [75%] Tech-Mapping Phase 2 completed 24.32.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 490 unused cells and 3726 unused wires. <suppressed ~491 debug messages> 24.32.5. Finished fast OPT passes. 24.33. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 24.34. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). 24.35. Executing TECHMAP pass (map to technology primitives). 24.35.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v' to AST representation. Generating RTLIL representation for module `\$_DFF_N_'. Generating RTLIL representation for module `\$_DFF_P_'. Generating RTLIL representation for module `\$_DFFE_NN_'. Generating RTLIL representation for module `\$_DFFE_PN_'. Generating RTLIL representation for module `\$_DFFE_NP_'. Generating RTLIL representation for module `\$_DFFE_PP_'. Generating RTLIL representation for module `\$_DFF_NP0_'. Generating RTLIL representation for module `\$_DFF_NP1_'. Generating RTLIL representation for module `\$_DFF_PP0_'. Generating RTLIL representation for module `\$_DFF_PP1_'. Generating RTLIL representation for module `\$_SDFF_NP0_'. Generating RTLIL representation for module `\$_SDFF_NP1_'. Generating RTLIL representation for module `\$_SDFF_PP0_'. Generating RTLIL representation for module `\$_SDFF_PP1_'. Generating RTLIL representation for module `\$_DFFE_NP0P_'. Generating RTLIL representation for module `\$_DFFE_NP1P_'. Generating RTLIL representation for module `\$_DFFE_PP0P_'. Generating RTLIL representation for module `\$_DFFE_PP1P_'. Generating RTLIL representation for module `\$_DFFE_NP0N_'. Generating RTLIL representation for module `\$_DFFE_NP1N_'. Generating RTLIL representation for module `\$_DFFE_PP0N_'. Generating RTLIL representation for module `\$_DFFE_PP1N_'. Generating RTLIL representation for module `\$_SDFFE_NP0P_'. Generating RTLIL representation for module `\$_SDFFE_NP1P_'. Generating RTLIL representation for module `\$_SDFFE_PP0P_'. Generating RTLIL representation for module `\$_SDFFE_PP1P_'. Generating RTLIL representation for module `\$_SDFFE_NP0N_'. Generating RTLIL representation for module `\$_SDFFE_NP1N_'. Generating RTLIL representation for module `\$_SDFFE_PP0N_'. Generating RTLIL representation for module `\$_SDFFE_PP1N_'. Generating RTLIL representation for module `\$_ALDFF_NP_'. Generating RTLIL representation for module `\$_ALDFF_PP_'. Generating RTLIL representation for module `\$_ALDFFE_NPN_'. Generating RTLIL representation for module `\$_ALDFFE_NPP_'. Generating RTLIL representation for module `\$_ALDFFE_PPN_'. Generating RTLIL representation for module `\$_ALDFFE_PPP_'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Successfully finished Verilog frontend. 24.35.2. Continuing TECHMAP pass. Using template \$_SDFFE_PP0P_ for cells of type $_SDFFE_PP0P_. Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'0 for cells of type $_DFFE_PP_. Using template \$_SDFF_PP1_ for cells of type $_SDFF_PP1_. Using template \$_SDFFE_PP0N_ for cells of type $_SDFFE_PP0N_. Using template \$_SDFF_PP0_ for cells of type $_SDFF_PP0_. Using template $paramod\$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_. Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFFE_PP_. Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'1 for cells of type $_DFFE_PP_. Using template \$_SDFFE_PP1P_ for cells of type $_SDFFE_PP1P_. Using template $paramod\$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'0 for cells of type $_DFF_P_. No more expansions possible. <suppressed ~1152 debug messages> 24.36. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~19 debug messages> 24.37. Executing SIMPLEMAP pass (map simple cells to gate primitives). 24.38. Executing LATTICE_GSR pass (implement FF init values). Handling GSR in top. 24.39. Executing ATTRMVCP pass (move or copy attributes). 24.40. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 5802 unused wires. <suppressed ~1 debug messages> 24.41. Executing TECHMAP pass (map to technology primitives). 24.41.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/latches_map.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/latches_map.v' to AST representation. Generating RTLIL representation for module `\$_DLATCH_N_'. Generating RTLIL representation for module `\$_DLATCH_P_'. Successfully finished Verilog frontend. 24.41.2. Continuing TECHMAP pass. No more expansions possible. <suppressed ~4 debug messages> 24.42. Executing ABC9 pass. 24.42.1. Executing ABC9_OPS pass (helper functions for ABC9). 24.42.2. Executing ABC9_OPS pass (helper functions for ABC9). 24.42.3. Executing PROC pass (convert processes to netlists). 24.42.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$25557'. Cleaned up 1 empty switch. 24.42.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$25558 in module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 24.42.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 24.42.3.4. Executing PROC_INIT pass (extract init attributes). 24.42.3.5. Executing PROC_ARST pass (detect async resets in processes). 24.42.3.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 24.42.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25582'. Creating decoders for process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$25558'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$25556_EN[3:0]$25563 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$25556_DATA[3:0]$25562 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$25556_ADDR[3:0]$25564 Creating decoders for process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$25557'. 24.42.3.8. Executing PROC_DLATCH pass (convert process syncs to latches). 24.42.3.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.\i' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25582'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25545_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25582'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25540_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25582'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25554_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25582'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25549_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25582'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25544_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25582'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25541_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25582'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25553_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25582'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25548_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25582'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25552_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25582'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25555_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25582'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25551_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25582'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25542_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25582'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25550_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25582'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25546_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25582'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25543_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25582'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25547_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25582'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$25556_DATA' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$25558'. created $dff cell `$procdff$25608' with positive edge clock. Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$25556_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$25558'. created $dff cell `$procdff$25609' with positive edge clock. Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$25556_ADDR' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$25558'. created $dff cell `$procdff$25610' with positive edge clock. Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.\muxwre' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$25557'. created direct connection (no actual register cell created). 24.42.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 24.42.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25582'. Found and cleaned up 1 empty switch in `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$25558'. Removing empty process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$25557'. Cleaned up 1 empty switch. 24.42.3.12. Executing OPT_EXPR pass (perform const folding). 24.42.4. Executing PROC pass (convert processes to netlists). 24.42.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$25628'. Cleaned up 1 empty switch. 24.42.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$25629 in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 24.42.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 24.42.4.4. Executing PROC_INIT pass (extract init attributes). 24.42.4.5. Executing PROC_ARST pass (detect async resets in processes). 24.42.4.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 24.42.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25653'. Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$25629'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$25627_EN[3:0]$25634 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$25627_DATA[3:0]$25635 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$25627_ADDR[3:0]$25633 Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$25628'. 24.42.4.8. Executing PROC_DLATCH pass (convert process syncs to latches). 24.42.4.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25616_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25653'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.\i' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25653'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25619_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25653'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25611_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25653'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25622_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25653'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25617_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25653'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25612_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25653'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25620_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25653'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25624_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25653'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25615_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25653'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25623_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25653'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25614_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25653'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25613_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25653'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25618_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25653'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25625_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25653'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25621_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25653'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25626_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25653'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$25627_ADDR' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$25629'. created $dff cell `$procdff$25679' with positive edge clock. Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$25627_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$25629'. created $dff cell `$procdff$25680' with positive edge clock. Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$25627_DATA' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$25629'. created $dff cell `$procdff$25681' with positive edge clock. Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.\muxwre' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$25628'. created direct connection (no actual register cell created). 24.42.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 24.42.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25653'. Found and cleaned up 1 empty switch in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$25629'. Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$25628'. Cleaned up 1 empty switch. 24.42.4.12. Executing OPT_EXPR pass (perform const folding). 24.42.5. Executing PROC pass (convert processes to netlists). 24.42.5.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$25699'. Cleaned up 1 empty switch. 24.42.5.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$25700 in module $paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 24.42.5.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 24.42.5.4. Executing PROC_INIT pass (extract init attributes). 24.42.5.5. Executing PROC_ARST pass (detect async resets in processes). 24.42.5.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 24.42.5.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25724'. Creating decoders for process `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$25700'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$25698_EN[3:0]$25704 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$25698_DATA[3:0]$25705 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$25698_ADDR[3:0]$25706 Creating decoders for process `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$25699'. 24.42.5.8. Executing PROC_DLATCH pass (convert process syncs to latches). 24.42.5.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.\i' using process `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25724'. created direct connection (no actual register cell created). Creating register for signal `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25684_EN' using process `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25724'. created direct connection (no actual register cell created). Creating register for signal `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25696_EN' using process `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25724'. created direct connection (no actual register cell created). Creating register for signal `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25695_EN' using process `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25724'. created direct connection (no actual register cell created). Creating register for signal `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25694_EN' using process `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25724'. created direct connection (no actual register cell created). Creating register for signal `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25697_EN' using process `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25724'. created direct connection (no actual register cell created). Creating register for signal `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25688_EN' using process `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25724'. created direct connection (no actual register cell created). Creating register for signal `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25693_EN' using process `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25724'. created direct connection (no actual register cell created). Creating register for signal `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25692_EN' using process `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25724'. created direct connection (no actual register cell created). Creating register for signal `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25691_EN' using process `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25724'. created direct connection (no actual register cell created). Creating register for signal `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25687_EN' using process `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25724'. created direct connection (no actual register cell created). Creating register for signal `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25690_EN' using process `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25724'. created direct connection (no actual register cell created). Creating register for signal `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25685_EN' using process `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25724'. created direct connection (no actual register cell created). Creating register for signal `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25686_EN' using process `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25724'. created direct connection (no actual register cell created). Creating register for signal `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25689_EN' using process `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25724'. created direct connection (no actual register cell created). Creating register for signal `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25682_EN' using process `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25724'. created direct connection (no actual register cell created). Creating register for signal `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25683_EN' using process `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25724'. created direct connection (no actual register cell created). Creating register for signal `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$25698_EN' using process `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$25700'. created $dff cell `$procdff$25750' with positive edge clock. Creating register for signal `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$25698_DATA' using process `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$25700'. created $dff cell `$procdff$25751' with positive edge clock. Creating register for signal `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$25698_ADDR' using process `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$25700'. created $dff cell `$procdff$25752' with positive edge clock. Creating register for signal `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.\muxwre' using process `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$25699'. created direct connection (no actual register cell created). 24.42.5.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 24.42.5.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25724'. Found and cleaned up 1 empty switch in `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$25700'. Removing empty process `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$25699'. Cleaned up 1 empty switch. 24.42.5.12. Executing OPT_EXPR pass (perform const folding). 24.42.6. Executing PROC pass (convert processes to netlists). 24.42.6.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$25770'. Cleaned up 1 empty switch. 24.42.6.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$25771 in module $paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 24.42.6.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 24.42.6.4. Executing PROC_INIT pass (extract init attributes). 24.42.6.5. Executing PROC_ARST pass (detect async resets in processes). 24.42.6.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 24.42.6.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25795'. Creating decoders for process `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$25771'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$25769_EN[3:0]$25776 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$25769_DATA[3:0]$25777 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$25769_ADDR[3:0]$25775 Creating decoders for process `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$25770'. 24.42.6.8. Executing PROC_DLATCH pass (convert process syncs to latches). 24.42.6.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.\i' using process `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25795'. created direct connection (no actual register cell created). Creating register for signal `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25766_EN' using process `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25795'. created direct connection (no actual register cell created). Creating register for signal `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25760_EN' using process `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25795'. created direct connection (no actual register cell created). Creating register for signal `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25754_EN' using process `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25795'. created direct connection (no actual register cell created). Creating register for signal `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25765_EN' using process `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25795'. created direct connection (no actual register cell created). Creating register for signal `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25764_EN' using process `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25795'. created direct connection (no actual register cell created). Creating register for signal `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25759_EN' using process `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25795'. created direct connection (no actual register cell created). Creating register for signal `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25758_EN' using process `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25795'. created direct connection (no actual register cell created). Creating register for signal `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25768_EN' using process `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25795'. created direct connection (no actual register cell created). Creating register for signal `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25767_EN' using process `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25795'. created direct connection (no actual register cell created). Creating register for signal `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25763_EN' using process `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25795'. created direct connection (no actual register cell created). Creating register for signal `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25762_EN' using process `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25795'. created direct connection (no actual register cell created). Creating register for signal `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25761_EN' using process `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25795'. created direct connection (no actual register cell created). Creating register for signal `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25756_EN' using process `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25795'. created direct connection (no actual register cell created). Creating register for signal `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25757_EN' using process `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25795'. created direct connection (no actual register cell created). Creating register for signal `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25755_EN' using process `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25795'. created direct connection (no actual register cell created). Creating register for signal `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25753_EN' using process `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25795'. created direct connection (no actual register cell created). Creating register for signal `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$25769_ADDR' using process `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$25771'. created $dff cell `$procdff$25821' with positive edge clock. Creating register for signal `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$25769_EN' using process `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$25771'. created $dff cell `$procdff$25822' with positive edge clock. Creating register for signal `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$25769_DATA' using process `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$25771'. created $dff cell `$procdff$25823' with positive edge clock. Creating register for signal `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.\muxwre' using process `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$25770'. created direct connection (no actual register cell created). 24.42.6.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 24.42.6.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25795'. Found and cleaned up 1 empty switch in `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$25771'. Removing empty process `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$25770'. Cleaned up 1 empty switch. 24.42.6.12. Executing OPT_EXPR pass (perform const folding). 24.42.7. Executing PROC pass (convert processes to netlists). 24.42.7.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$25841'. Cleaned up 1 empty switch. 24.42.7.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$25842 in module $paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 24.42.7.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 24.42.7.4. Executing PROC_INIT pass (extract init attributes). 24.42.7.5. Executing PROC_ARST pass (detect async resets in processes). 24.42.7.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 24.42.7.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25866'. Creating decoders for process `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$25842'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$25840_EN[3:0]$25848 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$25840_DATA[3:0]$25846 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$25840_ADDR[3:0]$25847 Creating decoders for process `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$25841'. 24.42.7.8. Executing PROC_DLATCH pass (convert process syncs to latches). 24.42.7.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.\i' using process `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25866'. created direct connection (no actual register cell created). Creating register for signal `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25831_EN' using process `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25866'. created direct connection (no actual register cell created). Creating register for signal `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25835_EN' using process `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25866'. created direct connection (no actual register cell created). Creating register for signal `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25834_EN' using process `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25866'. created direct connection (no actual register cell created). Creating register for signal `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25824_EN' using process `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25866'. created direct connection (no actual register cell created). Creating register for signal `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25836_EN' using process `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25866'. created direct connection (no actual register cell created). Creating register for signal `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25830_EN' using process `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25866'. created direct connection (no actual register cell created). Creating register for signal `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25832_EN' using process `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25866'. created direct connection (no actual register cell created). Creating register for signal `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25833_EN' using process `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25866'. created direct connection (no actual register cell created). Creating register for signal `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25837_EN' using process `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25866'. created direct connection (no actual register cell created). Creating register for signal `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25839_EN' using process `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25866'. created direct connection (no actual register cell created). Creating register for signal `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25828_EN' using process `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25866'. created direct connection (no actual register cell created). Creating register for signal `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25826_EN' using process `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25866'. created direct connection (no actual register cell created). Creating register for signal `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25825_EN' using process `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25866'. created direct connection (no actual register cell created). Creating register for signal `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25838_EN' using process `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25866'. created direct connection (no actual register cell created). Creating register for signal `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25829_EN' using process `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25866'. created direct connection (no actual register cell created). Creating register for signal `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25827_EN' using process `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25866'. created direct connection (no actual register cell created). Creating register for signal `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$25840_DATA' using process `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$25842'. created $dff cell `$procdff$25892' with positive edge clock. Creating register for signal `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$25840_ADDR' using process `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$25842'. created $dff cell `$procdff$25893' with positive edge clock. Creating register for signal `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$25840_EN' using process `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$25842'. created $dff cell `$procdff$25894' with positive edge clock. Creating register for signal `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.\muxwre' using process `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$25841'. created direct connection (no actual register cell created). 24.42.7.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 24.42.7.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25866'. Found and cleaned up 1 empty switch in `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$25842'. Removing empty process `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$25841'. Cleaned up 1 empty switch. 24.42.7.12. Executing OPT_EXPR pass (perform const folding). 24.42.8. Executing PROC pass (convert processes to netlists). 24.42.8.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$25912'. Cleaned up 1 empty switch. 24.42.8.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$25913 in module $paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 24.42.8.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 24.42.8.4. Executing PROC_INIT pass (extract init attributes). 24.42.8.5. Executing PROC_ARST pass (detect async resets in processes). 24.42.8.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 24.42.8.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25937'. Creating decoders for process `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$25913'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$25911_EN[3:0]$25917 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$25911_DATA[3:0]$25919 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$25911_ADDR[3:0]$25918 Creating decoders for process `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$25912'. 24.42.8.8. Executing PROC_DLATCH pass (convert process syncs to latches). 24.42.8.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25910_EN' using process `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25937'. created direct connection (no actual register cell created). Creating register for signal `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.\i' using process `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25937'. created direct connection (no actual register cell created). Creating register for signal `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25896_EN' using process `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25937'. created direct connection (no actual register cell created). Creating register for signal `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25897_EN' using process `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25937'. created direct connection (no actual register cell created). Creating register for signal `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25902_EN' using process `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25937'. created direct connection (no actual register cell created). Creating register for signal `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25898_EN' using process `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25937'. created direct connection (no actual register cell created). Creating register for signal `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25907_EN' using process `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25937'. created direct connection (no actual register cell created). Creating register for signal `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25908_EN' using process `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25937'. created direct connection (no actual register cell created). Creating register for signal `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25903_EN' using process `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25937'. created direct connection (no actual register cell created). Creating register for signal `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25899_EN' using process `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25937'. created direct connection (no actual register cell created). Creating register for signal `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25895_EN' using process `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25937'. created direct connection (no actual register cell created). Creating register for signal `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25906_EN' using process `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25937'. created direct connection (no actual register cell created). Creating register for signal `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25900_EN' using process `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25937'. created direct connection (no actual register cell created). Creating register for signal `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25901_EN' using process `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25937'. created direct connection (no actual register cell created). Creating register for signal `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25905_EN' using process `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25937'. created direct connection (no actual register cell created). Creating register for signal `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25904_EN' using process `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25937'. created direct connection (no actual register cell created). Creating register for signal `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25909_EN' using process `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25937'. created direct connection (no actual register cell created). Creating register for signal `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$25911_EN' using process `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$25913'. created $dff cell `$procdff$25963' with positive edge clock. Creating register for signal `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$25911_ADDR' using process `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$25913'. created $dff cell `$procdff$25964' with positive edge clock. Creating register for signal `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$25911_DATA' using process `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$25913'. created $dff cell `$procdff$25965' with positive edge clock. Creating register for signal `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.\muxwre' using process `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$25912'. created direct connection (no actual register cell created). 24.42.8.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 24.42.8.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$25937'. Found and cleaned up 1 empty switch in `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$25913'. Removing empty process `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$25912'. Cleaned up 1 empty switch. 24.42.8.12. Executing OPT_EXPR pass (perform const folding). 24.42.9. Executing PROC pass (convert processes to netlists). 24.42.9.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$25983'. Cleaned up 1 empty switch. 24.42.9.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$25984 in module $paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 24.42.9.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 24.42.9.4. Executing PROC_INIT pass (extract init attributes). 24.42.9.5. Executing PROC_ARST pass (detect async resets in processes). 24.42.9.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 24.42.9.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$26008'. Creating decoders for process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$25984'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$25982_EN[3:0]$25989 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$25982_DATA[3:0]$25988 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$25982_ADDR[3:0]$25990 Creating decoders for process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$25983'. 24.42.9.8. Executing PROC_DLATCH pass (convert process syncs to latches). 24.42.9.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25978_EN' using process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$26008'. created direct connection (no actual register cell created). Creating register for signal `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25971_EN' using process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$26008'. created direct connection (no actual register cell created). Creating register for signal `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25972_EN' using process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$26008'. created direct connection (no actual register cell created). Creating register for signal `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.\i' using process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$26008'. created direct connection (no actual register cell created). Creating register for signal `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25980_EN' using process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$26008'. created direct connection (no actual register cell created). Creating register for signal `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25981_EN' using process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$26008'. created direct connection (no actual register cell created). Creating register for signal `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25966_EN' using process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$26008'. created direct connection (no actual register cell created). Creating register for signal `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25976_EN' using process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$26008'. created direct connection (no actual register cell created). Creating register for signal `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25970_EN' using process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$26008'. created direct connection (no actual register cell created). Creating register for signal `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25969_EN' using process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$26008'. created direct connection (no actual register cell created). Creating register for signal `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25979_EN' using process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$26008'. created direct connection (no actual register cell created). Creating register for signal `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25968_EN' using process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$26008'. created direct connection (no actual register cell created). Creating register for signal `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25975_EN' using process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$26008'. created direct connection (no actual register cell created). Creating register for signal `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25974_EN' using process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$26008'. created direct connection (no actual register cell created). Creating register for signal `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25977_EN' using process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$26008'. created direct connection (no actual register cell created). Creating register for signal `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25973_EN' using process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$26008'. created direct connection (no actual register cell created). Creating register for signal `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$25967_EN' using process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$26008'. created direct connection (no actual register cell created). Creating register for signal `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$25982_DATA' using process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$25984'. created $dff cell `$procdff$26034' with positive edge clock. Creating register for signal `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$25982_EN' using process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$25984'. created $dff cell `$procdff$26035' with positive edge clock. Creating register for signal `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$25982_ADDR' using process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$25984'. created $dff cell `$procdff$26036' with positive edge clock. Creating register for signal `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.\muxwre' using process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$25983'. created direct connection (no actual register cell created). 24.42.9.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 24.42.9.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$26008'. Found and cleaned up 1 empty switch in `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$25984'. Removing empty process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$25983'. Cleaned up 1 empty switch. 24.42.9.12. Executing OPT_EXPR pass (perform const folding). 24.42.10. Executing PROC pass (convert processes to netlists). 24.42.10.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$26054'. Cleaned up 1 empty switch. 24.42.10.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$26055 in module $paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 24.42.10.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 24.42.10.4. Executing PROC_INIT pass (extract init attributes). 24.42.10.5. Executing PROC_ARST pass (detect async resets in processes). 24.42.10.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 24.42.10.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$26079'. Creating decoders for process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$26055'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$26053_EN[3:0]$26061 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$26053_DATA[3:0]$26060 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$26053_ADDR[3:0]$26059 Creating decoders for process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$26054'. 24.42.10.8. Executing PROC_DLATCH pass (convert process syncs to latches). 24.42.10.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$26039_EN' using process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$26079'. created direct connection (no actual register cell created). Creating register for signal `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$26037_EN' using process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$26079'. created direct connection (no actual register cell created). Creating register for signal `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.\i' using process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$26079'. created direct connection (no actual register cell created). Creating register for signal `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$26041_EN' using process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$26079'. created direct connection (no actual register cell created). Creating register for signal `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$26042_EN' using process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$26079'. created direct connection (no actual register cell created). Creating register for signal `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$26043_EN' using process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$26079'. created direct connection (no actual register cell created). Creating register for signal `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$26047_EN' using process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$26079'. created direct connection (no actual register cell created). Creating register for signal `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$26038_EN' using process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$26079'. created direct connection (no actual register cell created). Creating register for signal `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$26049_EN' using process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$26079'. created direct connection (no actual register cell created). Creating register for signal `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$26044_EN' using process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$26079'. created direct connection (no actual register cell created). Creating register for signal `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$26045_EN' using process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$26079'. created direct connection (no actual register cell created). Creating register for signal `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$26048_EN' using process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$26079'. created direct connection (no actual register cell created). Creating register for signal `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$26052_EN' using process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$26079'. created direct connection (no actual register cell created). Creating register for signal `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$26046_EN' using process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$26079'. created direct connection (no actual register cell created). Creating register for signal `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$26040_EN' using process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$26079'. created direct connection (no actual register cell created). Creating register for signal `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$26050_EN' using process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$26079'. created direct connection (no actual register cell created). Creating register for signal `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$26051_EN' using process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$26079'. created direct connection (no actual register cell created). Creating register for signal `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$26053_ADDR' using process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$26055'. created $dff cell `$procdff$26105' with positive edge clock. Creating register for signal `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$26053_DATA' using process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$26055'. created $dff cell `$procdff$26106' with positive edge clock. Creating register for signal `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$26053_EN' using process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$26055'. created $dff cell `$procdff$26107' with positive edge clock. Creating register for signal `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.\muxwre' using process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$26054'. created direct connection (no actual register cell created). 24.42.10.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 24.42.10.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$26079'. Found and cleaned up 1 empty switch in `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$26055'. Removing empty process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$26054'. Cleaned up 1 empty switch. 24.42.10.12. Executing OPT_EXPR pass (perform const folding). 24.42.11. Executing PROC pass (convert processes to netlists). 24.42.11.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$26125'. Cleaned up 1 empty switch. 24.42.11.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$26126 in module $paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 24.42.11.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 24.42.11.4. Executing PROC_INIT pass (extract init attributes). 24.42.11.5. Executing PROC_ARST pass (detect async resets in processes). 24.42.11.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 24.42.11.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$26150'. Creating decoders for process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$26126'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$26124_EN[3:0]$26131 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$26124_DATA[3:0]$26132 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$26124_ADDR[3:0]$26130 Creating decoders for process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$26125'. 24.42.11.8. Executing PROC_DLATCH pass (convert process syncs to latches). 24.42.11.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.\i' using process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$26150'. created direct connection (no actual register cell created). Creating register for signal `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$26120_EN' using process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$26150'. created direct connection (no actual register cell created). Creating register for signal `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$26111_EN' using process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$26150'. created direct connection (no actual register cell created). Creating register for signal `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$26112_EN' using process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$26150'. created direct connection (no actual register cell created). Creating register for signal `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$26113_EN' using process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$26150'. created direct connection (no actual register cell created). Creating register for signal `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$26117_EN' using process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$26150'. created direct connection (no actual register cell created). Creating register for signal `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$26118_EN' using process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$26150'. created direct connection (no actual register cell created). Creating register for signal `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$26122_EN' using process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$26150'. created direct connection (no actual register cell created). Creating register for signal `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$26116_EN' using process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$26150'. created direct connection (no actual register cell created). Creating register for signal `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$26110_EN' using process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$26150'. created direct connection (no actual register cell created). Creating register for signal `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$26108_EN' using process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$26150'. created direct connection (no actual register cell created). Creating register for signal `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$26115_EN' using process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$26150'. created direct connection (no actual register cell created). Creating register for signal `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$26121_EN' using process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$26150'. created direct connection (no actual register cell created). Creating register for signal `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$26109_EN' using process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$26150'. created direct connection (no actual register cell created). Creating register for signal `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$26123_EN' using process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$26150'. created direct connection (no actual register cell created). Creating register for signal `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$26119_EN' using process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$26150'. created direct connection (no actual register cell created). Creating register for signal `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$26114_EN' using process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$26150'. created direct connection (no actual register cell created). Creating register for signal `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$26124_ADDR' using process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$26126'. created $dff cell `$procdff$26176' with positive edge clock. Creating register for signal `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$26124_EN' using process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$26126'. created $dff cell `$procdff$26177' with positive edge clock. Creating register for signal `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$26124_DATA' using process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$26126'. created $dff cell `$procdff$26178' with positive edge clock. Creating register for signal `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.\muxwre' using process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$26125'. created direct connection (no actual register cell created). 24.42.11.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 24.42.11.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$26150'. Found and cleaned up 1 empty switch in `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$26126'. Removing empty process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$26125'. Cleaned up 1 empty switch. 24.42.11.12. Executing OPT_EXPR pass (perform const folding). 24.42.12. Executing PROC pass (convert processes to netlists). 24.42.12.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$26196'. Cleaned up 1 empty switch. 24.42.12.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$26197 in module $paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 24.42.12.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 24.42.12.4. Executing PROC_INIT pass (extract init attributes). 24.42.12.5. Executing PROC_ARST pass (detect async resets in processes). 24.42.12.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 24.42.12.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$26221'. Creating decoders for process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$26197'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$26195_EN[3:0]$26202 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$26195_DATA[3:0]$26201 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$26195_ADDR[3:0]$26203 Creating decoders for process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$26196'. 24.42.12.8. Executing PROC_DLATCH pass (convert process syncs to latches). 24.42.12.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$26179_EN' using process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$26221'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.\i' using process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$26221'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$26187_EN' using process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$26221'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$26191_EN' using process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$26221'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$26181_EN' using process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$26221'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$26182_EN' using process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$26221'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$26183_EN' using process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$26221'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$26189_EN' using process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$26221'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$26188_EN' using process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$26221'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$26184_EN' using process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$26221'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$26194_EN' using process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$26221'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$26193_EN' using process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$26221'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$26185_EN' using process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$26221'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$26192_EN' using process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$26221'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$26186_EN' using process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$26221'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$26180_EN' using process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$26221'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$26190_EN' using process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$26221'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$26195_DATA' using process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$26197'. created $dff cell `$procdff$26247' with positive edge clock. Creating register for signal `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$26195_EN' using process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$26197'. created $dff cell `$procdff$26248' with positive edge clock. Creating register for signal `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$26195_ADDR' using process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$26197'. created $dff cell `$procdff$26249' with positive edge clock. Creating register for signal `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.\muxwre' using process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$26196'. created direct connection (no actual register cell created). 24.42.12.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 24.42.12.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$26221'. Found and cleaned up 1 empty switch in `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$26197'. Removing empty process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$26196'. Cleaned up 1 empty switch. 24.42.12.12. Executing OPT_EXPR pass (perform const folding). 24.42.13. Executing SCC pass (detecting logic loops). Found an SCC: $auto$simplemap.cc:75:simplemap_bitop$17399 $auto$opt_expr.cc:613:replace_const_cells$24232 $auto$ff.cc:266:slice$7689 $auto$simplemap.cc:75:simplemap_bitop$17406 $auto$simplemap.cc:38:simplemap_not$16803 $auto$ff.cc:266:slice$7696 $auto$simplemap.cc:38:simplemap_not$16827 $auto$ff.cc:266:slice$7720 $auto$simplemap.cc:126:simplemap_reduce$6805 $auto$simplemap.cc:38:simplemap_not$16826 $auto$ff.cc:266:slice$7719 $auto$simplemap.cc:38:simplemap_not$16825 $auto$ff.cc:266:slice$7718 $auto$simplemap.cc:126:simplemap_reduce$6814 $auto$simplemap.cc:126:simplemap_reduce$6804 $auto$simplemap.cc:38:simplemap_not$16824 $auto$ff.cc:266:slice$7717 $auto$simplemap.cc:38:simplemap_not$16823 $auto$ff.cc:266:slice$7716 $auto$simplemap.cc:38:simplemap_not$16821 $auto$ff.cc:266:slice$7714 $auto$simplemap.cc:126:simplemap_reduce$6802 $auto$simplemap.cc:38:simplemap_not$16820 $auto$ff.cc:266:slice$7713 $auto$simplemap.cc:38:simplemap_not$16819 $auto$ff.cc:266:slice$7712 $auto$simplemap.cc:126:simplemap_reduce$6801 $auto$simplemap.cc:38:simplemap_not$16818 $auto$ff.cc:266:slice$7711 $auto$simplemap.cc:38:simplemap_not$16817 $auto$ff.cc:266:slice$7710 $auto$simplemap.cc:126:simplemap_reduce$6812 $auto$simplemap.cc:126:simplemap_reduce$6800 $auto$simplemap.cc:38:simplemap_not$16816 $auto$ff.cc:266:slice$7709 $auto$simplemap.cc:38:simplemap_not$16815 $auto$ff.cc:266:slice$7708 $auto$simplemap.cc:126:simplemap_reduce$6799 $auto$simplemap.cc:38:simplemap_not$16814 $auto$ff.cc:266:slice$7707 $auto$simplemap.cc:38:simplemap_not$16813 $auto$ff.cc:266:slice$7706 $auto$simplemap.cc:126:simplemap_reduce$6818 $auto$simplemap.cc:126:simplemap_reduce$6811 $auto$simplemap.cc:126:simplemap_reduce$6798 $auto$simplemap.cc:38:simplemap_not$16812 $auto$ff.cc:266:slice$7705 $auto$simplemap.cc:38:simplemap_not$16811 $auto$ff.cc:266:slice$7704 $auto$simplemap.cc:75:simplemap_bitop$17413 $auto$simplemap.cc:38:simplemap_not$16810 $auto$ff.cc:266:slice$7703 $auto$simplemap.cc:75:simplemap_bitop$17412 $auto$simplemap.cc:38:simplemap_not$16809 $auto$ff.cc:266:slice$7702 $auto$simplemap.cc:126:simplemap_reduce$6716 $auto$simplemap.cc:75:simplemap_bitop$17411 $auto$simplemap.cc:38:simplemap_not$16808 $auto$ff.cc:266:slice$7701 $auto$simplemap.cc:75:simplemap_bitop$17410 $auto$simplemap.cc:38:simplemap_not$16807 $auto$ff.cc:266:slice$7700 $auto$simplemap.cc:126:simplemap_reduce$6715 $auto$simplemap.cc:75:simplemap_bitop$17409 $auto$simplemap.cc:38:simplemap_not$16806 $auto$ff.cc:266:slice$7699 $auto$simplemap.cc:75:simplemap_bitop$17408 $auto$simplemap.cc:38:simplemap_not$16805 $auto$ff.cc:266:slice$7698 $auto$simplemap.cc:126:simplemap_reduce$6729 $auto$simplemap.cc:126:simplemap_reduce$6714 $auto$simplemap.cc:75:simplemap_bitop$17407 $auto$simplemap.cc:38:simplemap_not$16804 $auto$ff.cc:266:slice$7697 $auto$simplemap.cc:126:simplemap_reduce$6710 $auto$simplemap.cc:75:simplemap_bitop$17400 $auto$simplemap.cc:38:simplemap_not$16797 $auto$alumacc.cc:485:replace_alu$4319.slice[0].ccu2c_i $auto$ff.cc:266:slice$7690 $auto$simplemap.cc:75:simplemap_bitop$17401 $auto$simplemap.cc:38:simplemap_not$16798 $auto$ff.cc:266:slice$7691 $auto$alumacc.cc:485:replace_alu$4319.slice[2].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$6727 $auto$simplemap.cc:126:simplemap_reduce$6711 $auto$simplemap.cc:75:simplemap_bitop$17402 $auto$simplemap.cc:38:simplemap_not$16799 $auto$ff.cc:266:slice$7692 $auto$simplemap.cc:75:simplemap_bitop$17403 $auto$simplemap.cc:38:simplemap_not$16800 $auto$ff.cc:266:slice$7693 $auto$alumacc.cc:485:replace_alu$4319.slice[4].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$6712 $auto$simplemap.cc:75:simplemap_bitop$17404 $auto$simplemap.cc:38:simplemap_not$16801 $auto$ff.cc:266:slice$7694 $auto$alumacc.cc:485:replace_alu$4319.slice[24].ccu2c_i $auto$alumacc.cc:485:replace_alu$4319.slice[22].ccu2c_i $auto$alumacc.cc:485:replace_alu$4319.slice[20].ccu2c_i $auto$alumacc.cc:485:replace_alu$4319.slice[18].ccu2c_i $auto$alumacc.cc:485:replace_alu$4319.slice[16].ccu2c_i $auto$alumacc.cc:485:replace_alu$4319.slice[14].ccu2c_i $auto$alumacc.cc:485:replace_alu$4319.slice[12].ccu2c_i $auto$alumacc.cc:485:replace_alu$4319.slice[10].ccu2c_i $auto$alumacc.cc:485:replace_alu$4319.slice[8].ccu2c_i $auto$alumacc.cc:485:replace_alu$4319.slice[6].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$6736 $auto$simplemap.cc:126:simplemap_reduce$6728 $auto$simplemap.cc:126:simplemap_reduce$6713 $auto$simplemap.cc:75:simplemap_bitop$17405 $auto$simplemap.cc:38:simplemap_not$16802 $auto$ff.cc:266:slice$7695 $auto$simplemap.cc:38:simplemap_not$5645 $auto$alumacc.cc:485:replace_alu$4319.slice[30].ccu2c_i $auto$alumacc.cc:485:replace_alu$4319.slice[28].ccu2c_i $auto$alumacc.cc:485:replace_alu$4319.slice[26].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$6822 $auto$simplemap.cc:126:simplemap_reduce$6819 $auto$simplemap.cc:126:simplemap_reduce$6813 $auto$simplemap.cc:126:simplemap_reduce$6803 $auto$simplemap.cc:38:simplemap_not$16822 $auto$ff.cc:266:slice$7715 $auto$simplemap.cc:126:simplemap_reduce$7045 $auto$simplemap.cc:75:simplemap_bitop$6708 $auto$simplemap.cc:126:simplemap_reduce$6744 $auto$simplemap.cc:126:simplemap_reduce$6741 $auto$simplemap.cc:126:simplemap_reduce$6737 $auto$simplemap.cc:126:simplemap_reduce$6730 $auto$simplemap.cc:126:simplemap_reduce$6717 $auto$simplemap.cc:75:simplemap_bitop$17414 Found an SCC: $auto$opt_expr.cc:613:replace_const_cells$24074 $auto$ff.cc:266:slice$8601 $auto$simplemap.cc:126:simplemap_reduce$8734 $auto$simplemap.cc:126:simplemap_reduce$8719 $auto$ff.cc:266:slice$8602 $auto$ff.cc:266:slice$8603 $auto$simplemap.cc:225:simplemap_logbin$8709 $auto$simplemap.cc:196:simplemap_lognot$8724 $auto$simplemap.cc:126:simplemap_reduce$8722 $auto$simplemap.cc:126:simplemap_reduce$8720 $auto$opt_expr.cc:613:replace_const_cells$24042 $auto$simplemap.cc:267:simplemap_mux$16165 $auto$simplemap.cc:126:simplemap_reduce$16179 $auto$simplemap.cc:126:simplemap_reduce$16176 $auto$simplemap.cc:75:simplemap_bitop$16169 $auto$simplemap.cc:196:simplemap_lognot$8739 $auto$simplemap.cc:126:simplemap_reduce$8737 $auto$simplemap.cc:126:simplemap_reduce$8735 $auto$opt_expr.cc:613:replace_const_cells$23904 $auto$ff.cc:266:slice$8604 $auto$simplemap.cc:126:simplemap_reduce$7167 $auto$simplemap.cc:126:simplemap_reduce$7165 $auto$simplemap.cc:225:simplemap_logbin$8665 $auto$simplemap.cc:196:simplemap_lognot$8675 $auto$simplemap.cc:126:simplemap_reduce$8673 $auto$opt_expr.cc:613:replace_const_cells$24044 $auto$simplemap.cc:267:simplemap_mux$16166 $auto$simplemap.cc:126:simplemap_reduce$16184 $auto$simplemap.cc:126:simplemap_reduce$16181 $auto$simplemap.cc:75:simplemap_bitop$16167 $auto$simplemap.cc:267:simplemap_mux$8706 Found an SCC: $auto$simplemap.cc:75:simplemap_bitop$15753 $auto$simplemap.cc:38:simplemap_not$15689 $auto$ff.cc:266:slice$8092 $auto$simplemap.cc:38:simplemap_not$15720 $auto$ff.cc:266:slice$8123 $auto$simplemap.cc:126:simplemap_reduce$7245 $auto$simplemap.cc:38:simplemap_not$17205 $auto$ff.cc:266:slice$8122 $auto$simplemap.cc:38:simplemap_not$17915 $auto$ff.cc:266:slice$8121 $auto$simplemap.cc:126:simplemap_reduce$7254 $auto$simplemap.cc:126:simplemap_reduce$7244 $auto$simplemap.cc:38:simplemap_not$17914 $auto$ff.cc:266:slice$8120 $auto$simplemap.cc:38:simplemap_not$17910 $auto$ff.cc:266:slice$8116 $auto$simplemap.cc:126:simplemap_reduce$7242 $auto$simplemap.cc:38:simplemap_not$15714 $auto$ff.cc:266:slice$8117 $auto$simplemap.cc:38:simplemap_not$15715 $auto$ff.cc:266:slice$8118 $auto$ff.cc:266:slice$8115 $auto$simplemap.cc:38:simplemap_not$17908 $auto$ff.cc:266:slice$8114 $auto$simplemap.cc:38:simplemap_not$17907 $auto$ff.cc:266:slice$8113 $auto$simplemap.cc:126:simplemap_reduce$7240 $auto$simplemap.cc:38:simplemap_not$17906 $auto$ff.cc:266:slice$8112 $auto$simplemap.cc:38:simplemap_not$17905 $auto$ff.cc:266:slice$8111 $auto$simplemap.cc:126:simplemap_reduce$7239 $auto$simplemap.cc:38:simplemap_not$15707 $auto$ff.cc:266:slice$8110 $auto$simplemap.cc:75:simplemap_bitop$15760 $auto$simplemap.cc:38:simplemap_not$17893 $auto$ff.cc:266:slice$8099 $auto$simplemap.cc:38:simplemap_not$15706 $auto$ff.cc:266:slice$8109 $auto$simplemap.cc:126:simplemap_reduce$7251 $auto$simplemap.cc:126:simplemap_reduce$7238 $auto$simplemap.cc:38:simplemap_not$15705 $auto$ff.cc:266:slice$8108 $auto$simplemap.cc:75:simplemap_bitop$15761 $auto$simplemap.cc:38:simplemap_not$17894 $auto$ff.cc:266:slice$8100 $auto$simplemap.cc:75:simplemap_bitop$15768 $auto$simplemap.cc:38:simplemap_not$15704 $auto$ff.cc:266:slice$8107 $auto$simplemap.cc:126:simplemap_reduce$7191 $auto$simplemap.cc:75:simplemap_bitop$15759 $auto$simplemap.cc:38:simplemap_not$17892 $auto$ff.cc:266:slice$8098 $auto$simplemap.cc:126:simplemap_reduce$7195 $auto$simplemap.cc:75:simplemap_bitop$15767 $auto$simplemap.cc:38:simplemap_not$15703 $auto$ff.cc:266:slice$8106 $auto$simplemap.cc:126:simplemap_reduce$7192 $auto$simplemap.cc:75:simplemap_bitop$15762 $auto$simplemap.cc:38:simplemap_not$15698 $auto$ff.cc:266:slice$8101 $auto$simplemap.cc:75:simplemap_bitop$15766 $auto$simplemap.cc:38:simplemap_not$15702 $auto$ff.cc:266:slice$8105 $auto$simplemap.cc:75:simplemap_bitop$15763 $auto$simplemap.cc:38:simplemap_not$15699 $auto$ff.cc:266:slice$8102 $auto$simplemap.cc:126:simplemap_reduce$7208 $auto$simplemap.cc:126:simplemap_reduce$7194 $auto$simplemap.cc:75:simplemap_bitop$15765 $auto$simplemap.cc:38:simplemap_not$17898 $auto$ff.cc:266:slice$8104 $auto$simplemap.cc:126:simplemap_reduce$7215 $auto$simplemap.cc:126:simplemap_reduce$7207 $auto$simplemap.cc:126:simplemap_reduce$7193 $auto$simplemap.cc:75:simplemap_bitop$15764 $auto$simplemap.cc:38:simplemap_not$17897 $auto$ff.cc:266:slice$8103 $auto$simplemap.cc:75:simplemap_bitop$15758 $auto$simplemap.cc:38:simplemap_not$17891 $auto$ff.cc:266:slice$8097 $auto$simplemap.cc:126:simplemap_reduce$7206 $auto$simplemap.cc:126:simplemap_reduce$7190 $auto$simplemap.cc:75:simplemap_bitop$15757 $auto$simplemap.cc:38:simplemap_not$17890 $auto$ff.cc:266:slice$8096 $auto$alumacc.cc:485:replace_alu$4297.slice[0].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$7188 $auto$simplemap.cc:75:simplemap_bitop$15754 $auto$simplemap.cc:38:simplemap_not$15690 $auto$ff.cc:266:slice$8093 $auto$simplemap.cc:75:simplemap_bitop$15756 $auto$simplemap.cc:38:simplemap_not$15692 $auto$ff.cc:266:slice$8095 $auto$simplemap.cc:126:simplemap_reduce$7259 $auto$simplemap.cc:126:simplemap_reduce$7253 $auto$simplemap.cc:126:simplemap_reduce$7243 $auto$simplemap.cc:38:simplemap_not$15716 $auto$ff.cc:266:slice$8119 $auto$simplemap.cc:38:simplemap_not$7266 $auto$alumacc.cc:485:replace_alu$4297.slice[30].ccu2c_i $auto$alumacc.cc:485:replace_alu$4297.slice[28].ccu2c_i $auto$alumacc.cc:485:replace_alu$4297.slice[26].ccu2c_i $auto$alumacc.cc:485:replace_alu$4297.slice[24].ccu2c_i $auto$alumacc.cc:485:replace_alu$4297.slice[22].ccu2c_i $auto$alumacc.cc:485:replace_alu$4297.slice[20].ccu2c_i $auto$alumacc.cc:485:replace_alu$4297.slice[18].ccu2c_i $auto$alumacc.cc:485:replace_alu$4297.slice[16].ccu2c_i $auto$alumacc.cc:485:replace_alu$4297.slice[14].ccu2c_i $auto$alumacc.cc:485:replace_alu$4297.slice[12].ccu2c_i $auto$alumacc.cc:485:replace_alu$4297.slice[10].ccu2c_i $auto$alumacc.cc:485:replace_alu$4297.slice[8].ccu2c_i $auto$alumacc.cc:485:replace_alu$4297.slice[6].ccu2c_i $auto$alumacc.cc:485:replace_alu$4297.slice[4].ccu2c_i $auto$alumacc.cc:485:replace_alu$4297.slice[2].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$7219 $auto$simplemap.cc:126:simplemap_reduce$7214 $auto$simplemap.cc:126:simplemap_reduce$7205 $auto$simplemap.cc:126:simplemap_reduce$7189 $auto$simplemap.cc:75:simplemap_bitop$15755 $auto$simplemap.cc:38:simplemap_not$15691 $auto$ff.cc:266:slice$8094 $auto$simplemap.cc:126:simplemap_reduce$7047 $auto$simplemap.cc:75:simplemap_bitop$6787 $auto$simplemap.cc:126:simplemap_reduce$7222 $auto$simplemap.cc:126:simplemap_reduce$7262 $auto$simplemap.cc:126:simplemap_reduce$7258 $auto$simplemap.cc:126:simplemap_reduce$7252 $auto$simplemap.cc:126:simplemap_reduce$7241 $auto$simplemap.cc:38:simplemap_not$17909 Found an SCC: $auto$simplemap.cc:38:simplemap_not$16021 $auto$ff.cc:266:slice$8609 $auto$simplemap.cc:126:simplemap_reduce$8756 $auto$ff.cc:266:slice$8610 $auto$ff.cc:266:slice$8605 $auto$ff.cc:266:slice$8606 $auto$ff.cc:266:slice$8607 $auto$simplemap.cc:126:simplemap_reduce$8755 $auto$simplemap.cc:38:simplemap_not$16020 $auto$ff.cc:266:slice$8608 $auto$simplemap.cc:38:simplemap_not$16023 $auto$ff.cc:266:slice$8611 $auto$simplemap.cc:126:simplemap_reduce$8760 $auto$simplemap.cc:126:simplemap_reduce$8757 $auto$simplemap.cc:38:simplemap_not$16024 $auto$ff.cc:266:slice$8612 $auto$ff.cc:266:slice$8613 $auto$simplemap.cc:126:simplemap_reduce$7161 $auto$simplemap.cc:196:simplemap_lognot$8766 $auto$simplemap.cc:126:simplemap_reduce$8764 $auto$simplemap.cc:126:simplemap_reduce$8762 $auto$simplemap.cc:126:simplemap_reduce$8759 $auto$simplemap.cc:126:simplemap_reduce$8754 $auto$simplemap.cc:38:simplemap_not$16017 Found an SCC: $auto$opt_expr.cc:613:replace_const_cells$24070 $auto$ff.cc:266:slice$8461 $auto$simplemap.cc:126:simplemap_reduce$8583 $auto$simplemap.cc:126:simplemap_reduce$8556 $auto$ff.cc:266:slice$8462 $auto$simplemap.cc:38:simplemap_not$16187 $auto$ff.cc:266:slice$8463 $auto$simplemap.cc:126:simplemap_reduce$8588 $auto$simplemap.cc:126:simplemap_reduce$8584 $auto$simplemap.cc:126:simplemap_reduce$8561 $auto$simplemap.cc:126:simplemap_reduce$8557 $auto$simplemap.cc:38:simplemap_not$16188 $auto$ff.cc:266:slice$8464 $auto$simplemap.cc:38:simplemap_not$16189 $auto$ff.cc:266:slice$8465 $auto$simplemap.cc:126:simplemap_reduce$8585 $auto$simplemap.cc:126:simplemap_reduce$8558 $auto$simplemap.cc:38:simplemap_not$16190 $auto$ff.cc:266:slice$8466 $auto$simplemap.cc:38:simplemap_not$16191 $auto$ff.cc:266:slice$8467 $auto$simplemap.cc:126:simplemap_reduce$8564 $auto$simplemap.cc:126:simplemap_reduce$8562 $auto$simplemap.cc:126:simplemap_reduce$8559 $auto$simplemap.cc:126:simplemap_reduce$8591 $auto$simplemap.cc:126:simplemap_reduce$8589 $auto$simplemap.cc:126:simplemap_reduce$8586 $auto$simplemap.cc:38:simplemap_not$16192 $auto$ff.cc:266:slice$8468 $auto$simplemap.cc:196:simplemap_lognot$8595 $auto$simplemap.cc:126:simplemap_reduce$8593 $auto$simplemap.cc:126:simplemap_reduce$8566 $auto$ff.cc:266:slice$8469 $auto$simplemap.cc:167:logic_reduce$7172 $auto$simplemap.cc:225:simplemap_logbin$8540 $auto$simplemap.cc:225:simplemap_logbin$8541 $auto$simplemap.cc:196:simplemap_lognot$8568 Found an SCC: $auto$ff.cc:266:slice$11071 $auto$dfflegalize.cc:941:flip_pol$24414 $auto$ff.cc:485:convert_ce_over_srst$24412 $auto$opt_expr.cc:613:replace_const_cells$24338 $auto$ff.cc:266:slice$11069 $auto$dfflegalize.cc:941:flip_pol$24406 $auto$ff.cc:485:convert_ce_over_srst$24404 $auto$simplemap.cc:126:simplemap_reduce$7095 $auto$simplemap.cc:126:simplemap_reduce$7086 $auto$simplemap.cc:126:simplemap_reduce$7127 $auto$simplemap.cc:126:simplemap_reduce$7125 $auto$opt_expr.cc:613:replace_const_cells$24352 $auto$simplemap.cc:126:simplemap_reduce$7058 $auto$simplemap.cc:126:simplemap_reduce$7134 $auto$simplemap.cc:126:simplemap_reduce$7768 $auto$simplemap.cc:126:simplemap_reduce$7766 $auto$ff.cc:266:slice$11070 $auto$dfflegalize.cc:941:flip_pol$24410 $auto$ff.cc:485:convert_ce_over_srst$24408 $auto$simplemap.cc:126:simplemap_reduce$7062 $auto$simplemap.cc:126:simplemap_reduce$7060 $auto$simplemap.cc:126:simplemap_reduce$7057 $auto$simplemap.cc:126:simplemap_reduce$7088 Found an SCC: $auto$simplemap.cc:126:simplemap_reduce$6970 $auto$simplemap.cc:38:simplemap_not$18095 $auto$ff.cc:266:slice$5421 $auto$ff.cc:479:convert_ce_over_srst$24416 $auto$alumacc.cc:485:replace_alu$4330.slice[0].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$7370 $auto$simplemap.cc:38:simplemap_not$18096 $auto$ff.cc:266:slice$5422 $auto$ff.cc:479:convert_ce_over_srst$24418 $auto$simplemap.cc:38:simplemap_not$17660 $auto$ff.cc:266:slice$5426 $auto$ff.cc:479:convert_ce_over_srst$24426 $auto$simplemap.cc:126:simplemap_reduce$7372 $auto$ff.cc:266:slice$5425 $auto$ff.cc:479:convert_ce_over_srst$24424 $auto$simplemap.cc:38:simplemap_not$7377 $auto$alumacc.cc:485:replace_alu$4330.slice[4].ccu2c_i $auto$alumacc.cc:485:replace_alu$4330.slice[2].ccu2c_i $auto$simplemap.cc:38:simplemap_not$18098 $auto$ff.cc:266:slice$5424 $auto$ff.cc:479:convert_ce_over_srst$24422 $auto$simplemap.cc:126:simplemap_reduce$6954 $auto$simplemap.cc:126:simplemap_reduce$6952 $auto$simplemap.cc:126:simplemap_reduce$6973 $auto$simplemap.cc:126:simplemap_reduce$6971 $auto$simplemap.cc:38:simplemap_not$7367 $auto$simplemap.cc:75:simplemap_bitop$7368 $auto$simplemap.cc:126:simplemap_reduce$7376 $auto$simplemap.cc:126:simplemap_reduce$7374 $auto$simplemap.cc:126:simplemap_reduce$7371 $auto$ff.cc:266:slice$5423 $auto$ff.cc:479:convert_ce_over_srst$24420 $auto$simplemap.cc:126:simplemap_reduce$6941 Found 7 SCCs in module top. Found 7 SCCs. 24.42.14. Executing ABC9_OPS pass (helper functions for ABC9). 24.42.15. Executing PROC pass (convert processes to netlists). 24.42.15.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 24.42.15.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 24.42.15.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 0 assignments to connections. 24.42.15.4. Executing PROC_INIT pass (extract init attributes). 24.42.15.5. Executing PROC_ARST pass (detect async resets in processes). 24.42.15.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 24.42.15.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 24.42.15.8. Executing PROC_DLATCH pass (convert process syncs to latches). 24.42.15.9. Executing PROC_DFF pass (convert process syncs to FFs). 24.42.15.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 24.42.15.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 24.42.15.12. Executing OPT_EXPR pass (perform const folding). 24.42.16. Executing TECHMAP pass (map to technology primitives). 24.42.16.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/techmap.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu_brent_kung'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `\$__div_mod_u'. Generating RTLIL representation for module `\$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `\$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_pmux'. Generating RTLIL representation for module `\_90_demux'. Generating RTLIL representation for module `\_90_lut'. Successfully finished Verilog frontend. 24.42.16.2. Continuing TECHMAP pass. No more expansions possible. <suppressed ~180 debug messages> 24.42.17. Executing OPT pass (performing simple optimizations). 24.42.17.1. Executing OPT_EXPR pass (perform const folding). Optimizing module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4. Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. Optimizing module $paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4. Optimizing module $paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4. Optimizing module $paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4. Optimizing module $paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4. Optimizing module $paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4. Optimizing module $paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4. Optimizing module $paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4. Optimizing module $paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4. 24.42.17.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4'. Removed a total of 0 cells. 24.42.17.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 24.42.17.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4. Optimizing cells in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. Optimizing cells in module $paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4. Optimizing cells in module $paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4. Optimizing cells in module $paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4. Optimizing cells in module $paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4. Optimizing cells in module $paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4. Optimizing cells in module $paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4. Optimizing cells in module $paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4. Optimizing cells in module $paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4. Performed a total of 0 changes. 24.42.17.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4'. Removed a total of 0 cells. 24.42.17.6. Executing OPT_DFF pass (perform DFF optimizations). 24.42.17.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.. 24.42.17.8. Executing OPT_EXPR pass (perform const folding). Optimizing module $paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4. Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. Optimizing module $paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4. Optimizing module $paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4. Optimizing module $paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4. Optimizing module $paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4. Optimizing module $paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4. Optimizing module $paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4. Optimizing module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4. Optimizing module $paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4. 24.42.17.9. Finished OPT passes. (There is nothing left to do.) 24.42.18. Executing TECHMAP pass (map to technology primitives). 24.42.18.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/abc9_map.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/abc9_map.v' to AST representation. Successfully finished Verilog frontend. 24.42.18.2. Continuing TECHMAP pass. Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. Using template $paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4 for cells of type $paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4. Using template $paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4 for cells of type $paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4. Using template $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4 for cells of type $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4. Using template $paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4 for cells of type $paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4. Using template $paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4 for cells of type $paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4. Using template $paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4 for cells of type $paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4. Using template $paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4 for cells of type $paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4. Using template $paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4 for cells of type $paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4. Using template $paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4 for cells of type $paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4. No more expansions possible. <suppressed ~320 debug messages> 24.42.19. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/abc9_model.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/abc9_model.v' to AST representation. Generating RTLIL representation for module `$__ABC9_DELAY'. Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'. Generating RTLIL representation for module `$__DFF_N__$abc9_flop'. Generating RTLIL representation for module `$__DFF_P__$abc9_flop'. Successfully finished Verilog frontend. 24.42.20. Executing ABC9_OPS pass (helper functions for ABC9). <suppressed ~2 debug messages> 24.42.21. Executing ABC9_OPS pass (helper functions for ABC9). 24.42.22. Executing ABC9_OPS pass (helper functions for ABC9). <suppressed ~2 debug messages> 24.42.23. Executing TECHMAP pass (map to technology primitives). 24.42.23.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/techmap.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu_brent_kung'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `\$__div_mod_u'. Generating RTLIL representation for module `\$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `\$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_pmux'. Generating RTLIL representation for module `\_90_demux'. Generating RTLIL representation for module `\_90_lut'. Successfully finished Verilog frontend. 24.42.23.2. Continuing TECHMAP pass. Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C. Using extmapper simplemap for cells of type $not. Using extmapper simplemap for cells of type $or. Using extmapper simplemap for cells of type $and. Using template $paramod\LUT4\INIT=16'1001011010101010 for cells of type LUT4. Using template $paramod\LUT2\INIT=4'1010 for cells of type LUT2. Using extmapper simplemap for cells of type $xor. Using extmapper simplemap for cells of type $mux. No more expansions possible. <suppressed ~219 debug messages> 24.42.24. Executing OPT pass (performing simple optimizations). 24.42.24.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~18 debug messages> 24.42.24.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~6 debug messages> Removed a total of 2 cells. 24.42.24.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 24.42.24.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 24.42.24.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 24.42.24.6. Executing OPT_DFF pass (perform DFF optimizations). 24.42.24.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 55 unused wires. <suppressed ~1 debug messages> 24.42.24.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 24.42.24.9. Rerunning OPT passes. (Maybe there is more to do..) 24.42.24.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 24.42.24.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 24.42.24.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 24.42.24.13. Executing OPT_DFF pass (perform DFF optimizations). 24.42.24.14. Executing OPT_CLEAN pass (remove unused cells and wires). ****** Vivado v2023.2 (64-bit) **** SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023 **** IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023 **** SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023 ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. ** Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. source run.tcl # read_verilog "main.v" Finding unused cells or wires in module \top.. 24.42.24.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 24.42.24.16. Finished OPT passes. (There is nothing left to do.) 24.42.25. Executing AIGMAP pass (map logic to AIG). Module top: replaced 18 cells with 120 new cells, skipped 39 cells. replaced 3 cell types: 2 $_OR_ 2 $_XOR_ 14 $_MUX_ not replaced 3 cell types: 31 $specify2 4 $_NOT_ 4 $_AND_ 24.42.26. Executing AIGMAP pass (map logic to AIG). Module top: replaced 4572 cells with 27300 new cells, skipped 3388 cells. replaced 4 cell types: 1564 $_OR_ 138 $_XOR_ 3 $_ORNOT_ 2867 $_MUX_ not replaced 27 cell types: 32 $scopeinfo 432 $_NOT_ 1075 $_AND_ 6 $_TBUF_ 1026 TRELLIS_FF 1 $paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4 1 $paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4 1 $paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4 24 $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4 1 $paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4 276 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 24 $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4 1 $__ABC9_SCC_BREAKER 1 $paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4 1 $paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4 1 $paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4 200 $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C 1 $paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4_$abc9_byp 276 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4_$abc9_byp 24.42.26.1. Executing ABC9_OPS pass (helper functions for ABC9). 24.42.26.2. Executing ABC9_OPS pass (helper functions for ABC9). 24.42.26.3. Executing XAIGER backend. <suppressed ~11 debug messages> Extracted 11657 AND gates and 33452 wires from module `top' to a netlist network with 2274 inputs and 896 outputs. 24.42.26.4. Executing ABC9_EXE pass (technology mapping using ABC9). 24.42.26.5. Executing ABC9. read_verilog: Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1318.062 ; gain = 0.023 ; free physical = 1863 ; free virtual = 25396 # read_verilog ../../debug/reset.v # read_verilog ../../src/core/alu_control.v # read_verilog ../../src/core/alu.v # read_verilog ../../src/core/control_unit.v # read_verilog ../../src/core/core.v # read_verilog ../../src/core/immediate_generator.v # read_verilog ../../src/core/mux.v # read_verilog ../../src/core/pc.v # read_verilog ../../src/core/registers.v # read_verilog ../../src/core/csr_unit.v # read_verilog ../../src/core/mdu.v # read_verilog ../../src/peripheral/bus.v # read_verilog ../../src/peripheral/gpio.v # read_verilog ../../src/peripheral/gpios.v # read_verilog ../../src/peripheral/leds.v # read_verilog ../../src/peripheral/memory.v # read_verilog ../../src/peripheral/soc.v # read_verilog ../../src/peripheral/uart_rx.v # read_verilog ../../src/peripheral/uart_tx.v # read_verilog ../../src/peripheral/uart.v # read_verilog ../../src/peripheral/fifo.v # read_verilog ../../src/peripheral/pwm.v # read_xdc "digilent_nexys4_ddr.xdc" # set_property PROCESSING_ORDER EARLY [get_files digilent_nexys4_ddr.xdc] # synth_design -top "top" -part "xc7a100tcsg324-1" Command: synth_design -top top -part xc7a100tcsg324-1 Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7a100t' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a100t' Running ABC command: "<yosys-exe-dir>/yosys-abc" -s -f <abc-temp-dir>/abc.script 2>&1 ABC: ABC command line: "source <abc-temp-dir>/abc.script". ABC: ABC: + read_lut <abc-temp-dir>/input.lut ABC: + read_box <abc-temp-dir>/input.box ABC: + &read <abc-temp-dir>/input.xaig ABC: + &ps ABC: <abc-temp-dir>/input : i/o = 2274/ 896 and = 10101 lev = 53 (3.73) mem = 0.26 MB box = 508 bb = 308 ABC: + &scorr ABC: Warning: The network is combinational. ABC: + &sweep ABC: + &dc2 ABC: + &dch -f ABC: + &ps ABC: <abc-temp-dir>/input : i/o = 2274/ 896 and = 12565 lev = 57 (3.03) mem = 0.29 MB ch = 1358 box = 508 bb = 308 ABC: + &if -W 300 -v ABC: K = 7. Memory (bytes): Truth = 0. Cut = 64. Obj = 148. Set = 672. CutMin = no ABC: Node = 12565. Ch = 1158. Total mem = 3.41 MB. Peak cut mem = 0.26 MB. ABC: P: Del = 6339.00. Ar = 14850.0. Edge = 16337. Cut = 162493. T = 0.05 sec ABC: P: Del = 6321.00. Ar = 15399.0. Edge = 16738. Cut = 157582. T = 0.04 sec ABC: P: Del = 6321.00. Ar = 7316.0. Edge = 13434. Cut = 409261. T = 0.10 sec ABC: F: Del = 6321.00. Ar = 5218.0. Edge = 11826. Cut = 305987. T = 0.08 sec ABC: A: Del = 6321.00. Ar = 4761.0. Edge = 10812. Cut = 286133. T = 0.11 sec ABC: A: Del = 6321.00. Ar = 4709.0. Edge = 10738. Cut = 293020. T = 0.11 sec ABC: Total time = 0.49 sec ABC: + &write -n <abc-temp-dir>/output.aig ABC: + &mfs ABC: + &ps -l ABC: <abc-temp-dir>/input : i/o = 2274/ 896 and = 11296 lev = 37 (3.49) mem = 0.27 MB box = 508 bb = 308 ABC: Mapping (K=7) : lut = 2634 edge = 10339 lev = 13 (1.67) Boxes are not in a topological order. Switching to level computation without boxes. ABC: levB = 37 mem = 0.14 MB ABC: LUT = 2634 : 2=298 11.3 % 3=615 23.3 % 4=1155 43.8 % 5=286 10.9 % 6=112 4.3 % 7=168 6.4 % Ave = 3.93 ABC: + &write -n <abc-temp-dir>/output.aig ABC: + time ABC: elapse: 7.50 seconds, total: 7.50 seconds 24.42.26.6. Executing AIGER frontend. <suppressed ~6352 debug messages> Removed 16818 unused cells and 27675 unused wires. 24.42.26.7. Executing ABC9_OPS pass (helper functions for ABC9). ABC RESULTS: $lut cells: 2663 ABC RESULTS: $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4_$abc9_byp cells: 24 ABC RESULTS: $paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C cells: 200 ABC RESULTS: $paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp cells: 276 ABC RESULTS: $paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: input signals: 364 ABC RESULTS: output signals: 162 Removing temp directory. 24.42.27. Executing TECHMAP pass (map to technology primitives). 24.42.27.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/abc9_unmap.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/abc9_unmap.v' to AST representation. Generating RTLIL representation for module `\$__DFF_x__$abc9_flop'. Generating RTLIL representation for module `\$__ABC9_SCC_BREAKER'. Successfully finished Verilog frontend. 24.42.27.2. Continuing TECHMAP pass. Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C. Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4 for cells of type $paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4. Using template $paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4 for cells of type $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4. Using template $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod\$__ABC9_SCC_BREAKER\WIDTH=32'00000000000000000000000000000111 for cells of type $__ABC9_SCC_BREAKER. Using template $paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4 for cells of type $paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4. Using template $paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4 for cells of type $paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4. Using template $paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4 for cells of type $paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4. Using template $paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4 for cells of type $paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4. Using template $paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4 for cells of type $paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4. Using template $paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4 for cells of type $paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4. Using template $paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4 for cells of type $paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4. Using template $paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4_$abc9_byp. No more expansions possible. <suppressed ~854 debug messages> Removed 166 unused cells and 39205 unused wires. 24.43. Executing TECHMAP pass (map to technology primitives). 24.43.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v' to AST representation. Generating RTLIL representation for module `\$_DFF_N_'. Generating RTLIL representation for module `\$_DFF_P_'. Generating RTLIL representation for module `\$_DFFE_NN_'. Generating RTLIL representation for module `\$_DFFE_PN_'. Generating RTLIL representation for module `\$_DFFE_NP_'. Generating RTLIL representation for module `\$_DFFE_PP_'. Generating RTLIL representation for module `\$_DFF_NP0_'. Generating RTLIL representation for module `\$_DFF_NP1_'. Generating RTLIL representation for module `\$_DFF_PP0_'. Generating RTLIL representation for module `\$_DFF_PP1_'. Generating RTLIL representation for module `\$_SDFF_NP0_'. Generating RTLIL representation for module `\$_SDFF_NP1_'. Generating RTLIL representation for module `\$_SDFF_PP0_'. Generating RTLIL representation for module `\$_SDFF_PP1_'. Generating RTLIL representation for module `\$_DFFE_NP0P_'. Generating RTLIL representation for module `\$_DFFE_NP1P_'. Generating RTLIL representation for module `\$_DFFE_PP0P_'. Generating RTLIL representation for module `\$_DFFE_PP1P_'. Generating RTLIL representation for module `\$_DFFE_NP0N_'. Generating RTLIL representation for module `\$_DFFE_NP1N_'. Generating RTLIL representation for module `\$_DFFE_PP0N_'. Generating RTLIL representation for module `\$_DFFE_PP1N_'. Generating RTLIL representation for module `\$_SDFFE_NP0P_'. Generating RTLIL representation for module `\$_SDFFE_NP1P_'. Generating RTLIL representation for module `\$_SDFFE_PP0P_'. Generating RTLIL representation for module `\$_SDFFE_PP1P_'. Generating RTLIL representation for module `\$_SDFFE_NP0N_'. Generating RTLIL representation for module `\$_SDFFE_NP1N_'. Generating RTLIL representation for module `\$_SDFFE_PP0N_'. Generating RTLIL representation for module `\$_SDFFE_PP1N_'. Generating RTLIL representation for module `\$_ALDFF_NP_'. Generating RTLIL representation for module `\$_ALDFF_PP_'. Generating RTLIL representation for module `\$_ALDFFE_NPN_'. Generating RTLIL representation for module `\$_ALDFFE_NPP_'. Generating RTLIL representation for module `\$_ALDFFE_PPN_'. Generating RTLIL representation for module `\$_ALDFFE_PPP_'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Generating RTLIL representation for module `\$lut'. Successfully finished Verilog frontend. 24.43.2. Continuing TECHMAP pass. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0010 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100000 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0001 for cells of type $lut. Using template $paramod$0c8ca179830091c5e617fa87fec5eda52bbb802e\$lut for cells of type $lut. Using template $paramod$8e44661def013b6bf9fe6f8b049ef2c838d749f9\$lut for cells of type $lut. Using template $paramod$272652f6c6fbe9a75eff76e45cc7e2788835518b\$lut for cells of type $lut. Using template $paramod$63114da772fb28945ba24699e32f1e30ca7142f4\$lut for cells of type $lut. Using template $paramod$11ec7271d8e6e5aeaace08c13e4c601f10e31038\$lut for cells of type $lut. Using template $paramod$df196ed0a1da5c4a58c5e08a1dac304fd3fccaab\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000111 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001010 for cells of type $lut. Using template $paramod$b45e5cb971154e30a797eecb0461619c3eeae12d\$lut for cells of type $lut. Using template $paramod$8b24407096beec47292ddeb1567a058197a320b9\$lut for cells of type $lut. Using template $paramod$873c285bdccf0ac2b60d2304ea5cd14bf211d2a6\$lut for cells of type $lut. Using template $paramod$e49f6e3576ef1a6d2f58c54414dbb786af8cc869\$lut for cells of type $lut. Using template $paramod$8fd8efe0a495790cc9ddc97266933ea8a8cd7b45\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101010 for cells of type $lut. Using template $paramod$6e238df02989b317f10820a22773676e71120644\$lut for cells of type $lut. Using template $paramod$f9813472aa48e533b3838c6f2316dc2e78c66111\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010000 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1110 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000010 for cells of type $lut. Using template $paramod$373d637619c29cb9150902df9528107e5f3b8288\$lut for cells of type $lut. Using template $paramod$6d6beead1425af15cf78b27fd9b11b41b5d4bce8\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000100 for cells of type $lut. Using template $paramod$e51a8a571bee774247b38f52d6e85fd62ae52cea\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101000 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0111 for cells of type $lut. Using template $paramod$364c9ffbffac467d60dfec81bba4e18476c15602\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101100 for cells of type $lut. Using template $paramod$f87bcf1791971b4eaa30f3f28437044fef878a04\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000001 for cells of type $lut. Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10011100 for cells of type $lut. Using template $paramod$c28a8b7ce0535d090c4cfb52e9c74affd52b110c\$lut for cells of type $lut. Using template $paramod$f8f63b209b7230e81958663ff24fef1613156af7\$lut for cells of type $lut. Using template $paramod$529baf23c57d5ed871d62e547aaaa8bb53e364ce\$lut for cells of type $lut. Using template $paramod$bba54c1ef87367812b4c15f4aed5ac70773df775\$lut for cells of type $lut. Using template $paramod$498daa9936ffa1c0b12d774cacc95a35d14b818e\$lut for cells of type $lut. Using template $paramod$ffc2ea81a65101fbef8a332deddf112494d27163\$lut for cells of type $lut. Using template $paramod$059968be1ef12c596bb5d360a749040b6777bf4a\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001000 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111101 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111000 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11011011 for cells of type $lut. Using template $paramod$02a5a80d4eef56492e4edc7b5b102e47b6626300\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010100 for cells of type $lut. Using template $paramod$af98aba0de24e3f98f1b791dc07b2a4510a2fcf8\$lut for cells of type $lut. Using template $paramod$a95f2cc9c87e3874f0d72f5d140e772a071be0f3\$lut for cells of type $lut. Using template $paramod$a8b7516c4ccadf4ab65906113028f2819d14ea8b\$lut for cells of type $lut. Using template $paramod$183ec76ed3429a430a8be24b57f3de734985f568\$lut for cells of type $lut. Using template $paramod$3c6be0cecca529b904c273ae6983e0f6d0361b11\$lut for cells of type $lut. Using template $paramod$774a669204184147b38453b69c15da44a7cf748f\$lut for cells of type $lut. Using template $paramod$101238f3d8d49ab12a9b49a2f01cd503b26e9c61\$lut for cells of type $lut. Using template $paramod$a706847f6879882480d389e1befb7d6ea334cebe\$lut for cells of type $lut. Using template $paramod$fd46bf23b073c16e0381117194754f10a840f124\$lut for cells of type $lut. Using template $paramod$de5074a80e0a92a065a2ccd0d26c618282111f8c\$lut for cells of type $lut. Using template $paramod$d300dbf869151e5625fd998a1b1ec1ceb033bf30\$lut for cells of type $lut. Using template $paramod$75f6f0be508fd5e89f0b6f7cde2eae58888fb999\$lut for cells of type $lut. Using template $paramod$df5c8730c0a53792c3f54c2192a2221c27162fb5\$lut for cells of type $lut. Using template $paramod$30305e55a780880b9c824fe3509a4d981acb0f2b\$lut for cells of type $lut. Using template $paramod$f7cbd8f5974233f70d25c33ef6a692898e4f6377\$lut for cells of type $lut. Using template $paramod$2f8906d92ae1098c2572f7229f96d57e5f523e47\$lut for cells of type $lut. Using template $paramod$7c052c0b1024cd2dc284019efd4e103ffd43c5e8\$lut for cells of type $lut. Using template $paramod$8233fe5f3e32016e38f9f385f1fbeb88df751ed2\$lut for cells of type $lut. Using template $paramod$c078756a5eee24746ec1cfb3824decc1ad0554b7\$lut for cells of type $lut. Using template $paramod$d7816c8fe91c91c2deadbc0f27110529e1999027\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1001 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001010 for cells of type $lut. Using template $paramod$99d4cc9a89c6761bf48a9ab2ab4120b1fc9e831e\$lut for cells of type $lut. Using template $paramod$8e931b44474f4cdf083cc19b54ab720c8f78b716\$lut for cells of type $lut. Using template $paramod$ffc80aea4aa44f0166b2d4713ba5912f56e92991\$lut for cells of type $lut. Using template $paramod$0fa1c6e5d65a4e509c15b676a94b9aed076b9f4d\$lut for cells of type $lut. Using template $paramod$94e65f323749ab2f501acf5577af42456678fff9\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01101100 for cells of type $lut. Using template $paramod$6e2b27a23561eba4d5d7a3612a01502854865858\$lut for cells of type $lut. Using template $paramod$595068676881f8f0ed67ef7157dfe63b0222f2b8\$lut for cells of type $lut. Using template $paramod$d54ca69d08183848eda3cee258c095f420071713\$lut for cells of type $lut. Using template $paramod$822ee66f10c0722a3c10f8859d68af94a9eb6713\$lut for cells of type $lut. Using template $paramod$b2a4860cd839ff40d9dca4c3f237b2b534267028\$lut for cells of type $lut. Using template $paramod$014f438feb630e2ee10e1dc7f5f10c5f5e88c2b1\$lut for cells of type $lut. Using template $paramod$40122785a6a92bbbd8718a6d42ae75685d47b531\$lut for cells of type $lut. Using template $paramod$b18a3edb490ff3a49fefc94182a05f36efbdbba2\$lut for cells of type $lut. Using template $paramod$3a75385b1beb239786b9fcdc898b53110e63595f\$lut for cells of type $lut. Using template $paramod$f940b3836b816258cf0bf1afa7ea5d3b0e7a8025\$lut for cells of type $lut. Using template $paramod$75913ee5f15a4f63132b736d4556f0d154807878\$lut for cells of type $lut. Using template $paramod$32fe9cbac14888d92290708eff255016c65b5cab\$lut for cells of type $lut. Using template $paramod$5636998c7ce0b77a9e79012d4ef0c6d0a5a30e63\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00110101 for cells of type $lut. Using template $paramod$b2e76819bcc0479d1ccb1b440eb619596fe92918\$lut for cells of type $lut. Using template $paramod$effd3e173150aea719ae75dc8dbf934e727e88ba\$lut for cells of type $lut. Using template $paramod$fde0101c87c794ccc02d9979638c7a9059f028ed\$lut for cells of type $lut. Using template $paramod$b0969e4b829aa2286ccce660aa055f1c4b1825bb\$lut for cells of type $lut. Using template $paramod$4a0808c66205f5068665ff0f3029068c8de9e3f7\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01010011 for cells of type $lut. Using template $paramod$e744c098b4bb1ecf3afd28345f294469d8b4fa2c\$lut for cells of type $lut. Using template $paramod$497aa714ffa399423aed5fe789a8dd35df92638a\$lut for cells of type $lut. Using template $paramod$2ea69c779d6c1b79ac5a87b0d1523c67d5628dba\$lut for cells of type $lut. Using template $paramod$9f6e771b947f00627d1e824d9c57e5bcb080209e\$lut for cells of type $lut. Using template $paramod$6d05ee5be4fbc817e6482b590e1831ddde15ffbe\$lut for cells of type $lut. Using template $paramod$a08fe2462bdcdc30db8a81758ff51b6fe69add33\$lut for cells of type $lut. Using template $paramod$1fba9dc1e6c93ee9cdbcb7fc719adf6648f1e190\$lut for cells of type $lut. Using template $paramod$056d5a9438b208d5710860d404f760cee6ed2e40\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110000 for cells of type $lut. Using template $paramod$7eb69b4a100452c0bfb101b4a1ae1581c12c28a2\$lut for cells of type $lut. Using template $paramod$cfa4b1dbf69daad51d2c591c8fb4f83532132170\$lut for cells of type $lut. Using template $paramod$75666cd83f95cd3810dc34cfd303359c5f9c7bb4\$lut for cells of type $lut. Using template $paramod$c7e66f45868fa4e2bd89e75b7d5261390f2843d9\$lut for cells of type $lut. Using template $paramod$15881039f9110a1e9f78134d495f1442e5e043fe\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100000 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001000 for cells of type $lut. Using template $paramod$eabde4761c91679426ef5401ae1b2c95bf56e107\$lut for cells of type $lut. Using template $paramod$70d51b1d579bb02a269254058dfd0c880691fdcd\$lut for cells of type $lut. Using template $paramod$bb2031685dacce6ff6ed170259091a379bce71ec\$lut for cells of type $lut. Using template $paramod$13f0f581c42a157265afed68d410e9a3e7200c82\$lut for cells of type $lut. Using template $paramod$d99a5f38831281ff4d02067d2eb0a956cb6f0120\$lut for cells of type $lut. Using template $paramod$61e1779f98a03fbfda4ac0554ec0a827779000bf\$lut for cells of type $lut. Using template $paramod$5e523f9f3b8eb6118feb70ffae97a1b87170ee66\$lut for cells of type $lut. Using template $paramod$a41fc11e54f72cca2250b75df87d96513733390b\$lut for cells of type $lut. Using template $paramod$a6e128b38cfa79799619909b12c3ee56045e9d4e\$lut for cells of type $lut. Using template $paramod$2014354416722209de7d48370ab008bc2278a034\$lut for cells of type $lut. Using template $paramod$2f60579bf356129f19db3ead3dd6cc1bf15e5017\$lut for cells of type $lut. Using template $paramod$280adc3d65115ec482e1b15979ea31e2f857b588\$lut for cells of type $lut. Using template $paramod$9bfe1886af55ab8065e0fb6a586fb9a29caf058d\$lut for cells of type $lut. Using template $paramod$64ec3fca119f7a5796f4732c65816e8e3029750f\$lut for cells of type $lut. Using template $paramod$11b737f19e883ca1b181f5e2f1645badd999d0b5\$lut for cells of type $lut. Using template $paramod$8feda2504ab37188ca041e37a96d51463bbecb45\$lut for cells of type $lut. Using template $paramod$d790a05e278f008dbc6abe4a699affdaba125e87\$lut for cells of type $lut. Using template $paramod$d87fd6508d10d8ed9307b7313a68e0865774250f\$lut for cells of type $lut. Using template $paramod$02e55836878a22873310c70e8a2ed14028fabfa5\$lut for cells of type $lut. Using template $paramod$e510e287973222665a7428648d6babe4e83959f6\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100010 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001011 for cells of type $lut. Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9\$lut for cells of type $lut. Using template $paramod$5348912da867a611a8088b6b8b27a62d65f1de6e\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10110000 for cells of type $lut. Using template $paramod$ccd3e15dc00d71b9284dff48e88ccef5be7362c8\$lut for cells of type $lut. Using template $paramod$fb7bbfbe62f17d1abd6f8eaee546f5a966c46c29\$lut for cells of type $lut. Using template $paramod$2844c7fef2a755a9af80c70990cd830291c4b71c\$lut for cells of type $lut. Using template $paramod$2595fa2bdd403bc1b89d7bb3b33bd300a9dae135\$lut for cells of type $lut. Using template $paramod$b4f85a6321a00b090afc4e21d68e7b99eb94d149\$lut for cells of type $lut. Using template $paramod$0fcb06ed76df01e8d45bc2b9e6c8a9b43fa42cb4\$lut for cells of type $lut. Using template $paramod$a50bbaf70b48eb6d78317eddf4f7e11e8988acec\$lut for cells of type $lut. Using template $paramod$547ac4d3aa2d0cc2dd61462e70e48b5e3e336609\$lut for cells of type $lut. Using template $paramod$82b4a585d1edcb5c6e755dc9bd3392228a1c1304\$lut for cells of type $lut. Using template $paramod$ac5e2c9cf0c38f76c17e4610a0244e743447ef19\$lut for cells of type $lut. Using template $paramod$7ed3d685a887e531dc8f4f21b9907d4766cf861f\$lut for cells of type $lut. Using template $paramod$413d040dcd860cd74ca61a70644516a95d328ae7\$lut for cells of type $lut. Using template $paramod$5e17a4c266c6912bc9a1c5d215123444ffce8aae\$lut for cells of type $lut. Using template $paramod$dff8e7e8854dc948604d9ed7dea9d198697a573d\$lut for cells of type $lut. Using template $paramod$9cc51547ab44a72dd506ee5bb84a864365a103da\$lut for cells of type $lut. Using template $paramod$f3a9cb4a6dcd55c9015bfb659b637a7c07b996c0\$lut for cells of type $lut. Using template $paramod$191987e4132f69ca46dd53dfa3f15f72d990cc0a\$lut for cells of type $lut. Using template $paramod$47a8214374025465e226fa66bee690ff33268a25\$lut for cells of type $lut. Using template $paramod$bacdb2105cbfbe75cfbcc2fb021fd3aba864526b\$lut for cells of type $lut. Using template $paramod$0487181f3e5daed4d221a2e3f2a63fe9cd198807\$lut for cells of type $lut. Using template $paramod$8494168726d27c2200605afcf1fb7470bf987857\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10100010 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0110 for cells of type $lut. Using template $paramod$ba7b4568c306470a7f204c239212739869e234a1\$lut for cells of type $lut. Using template $paramod$4834046533425f54583d6bd31e49deb63455e1a5\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01100000 for cells of type $lut. Using template $paramod$2497a87a8b02f147192f3d3899c1e3cd7fba6f01\$lut for cells of type $lut. Using template $paramod$8cc13fab11ed939f0e40808b82d4ee5fa0f31080\$lut for cells of type $lut. Using template $paramod$4116600cc1d4ec10c50cda98f7d086b1d09ff1df\$lut for cells of type $lut. Using template $paramod$b6d7b8802225d3fe3444a1b7fbd727be1d62f151\$lut for cells of type $lut. Using template $paramod$a5516fc31d1e552de2435200bb732b4d4ad63a9c\$lut for cells of type $lut. Using template $paramod$d3f42722705cec5c7214523ffe8ab49f6734469b\$lut for cells of type $lut. Using template $paramod$a6597eda4608f36e684c1dd07ed552fcbec112b2\$lut for cells of type $lut. Using template $paramod$7b809938766c3068dc017c276033f224fcfb7189\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01010110 for cells of type $lut. Using template $paramod$f45429e380905f064bb0bad3a8bdb941708e63a7\$lut for cells of type $lut. Using template $paramod$ca1d48527df516f209cb40a6149324209c84bc69\$lut for cells of type $lut. Using template $paramod$8829675bb8c52553aed9f101ec0d5ef0c865e5c7\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01100101 for cells of type $lut. Using template $paramod$8512f4fb47fa9596f76cdbe5b407a5b54df368e7\$lut for cells of type $lut. Using template $paramod$879bf9f89af81e215ecdbd0ecbeae74349673921\$lut for cells of type $lut. Using template $paramod$8545389b02a7d1f8b3b033f01b168e67cb15be78\$lut for cells of type $lut. Using template $paramod$edc5a73130589b9210f4bdf92e14bdcacac8945d\$lut for cells of type $lut. Using template $paramod$a067ca065a0e8fdac308d6893e69914865d54ec4\$lut for cells of type $lut. Using template $paramod$525425bfbe66d72ee88210d059d9a74f55ab8de8\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010011 for cells of type $lut. Using template $paramod$f258f431a7c2fc52205873e71cd6683fdc689824\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01010001 for cells of type $lut. Using template $paramod$626c926c090c24ceb89df275614206a0a54168a8\$lut for cells of type $lut. Using template $paramod$0a22748909ba4ddbae54c16a4f7c552bb8270c8d\$lut for cells of type $lut. Using template $paramod$4b815e6c998e04ad0d0242e44b0c58a7a9d0b3b6\$lut for cells of type $lut. Using template $paramod$5a4927a018e8013be27635297370eddd48c3da9d\$lut for cells of type $lut. Using template $paramod$20d76b8deb3530e72461aafa0917e952ed06d0b7\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100100 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11011000 for cells of type $lut. Using template $paramod$ec77ef2f39e0c5347eaada9711f26fca6a276050\$lut for cells of type $lut. Using template $paramod$9e0d5e3cbbbadb2b139aaae0b912cff38011856c\$lut for cells of type $lut. Using template $paramod$ad55c0c44402400cc43bb299f86257a8ef03997c\$lut for cells of type $lut. Using template $paramod$b55f45c6dc20e6c434e3ecfaac16a92e424cd4fe\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110010 for cells of type $lut. Using template $paramod$0c822c65361ce832091b6c90f1a02f1ee0b109d4\$lut for cells of type $lut. Using template $paramod$221832ea6a41a3208cd6f3411a952b5811695f4c\$lut for cells of type $lut. Using template $paramod$973818279bc95792902f3c09371fd2407d04a2a5\$lut for cells of type $lut. Using template $paramod$dd0930bc3f95e455098f587e94d781217b7c4455\$lut for cells of type $lut. Using template $paramod$097592bb16245531f0716c5ddb18d7090f9c7d9d\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1011 for cells of type $lut. Using template $paramod$f58e0d90afc57a738914697b6a4a7319b30d7e7e\$lut for cells of type $lut. Using template $paramod$d79e8c7f0cb3bd049a34d82ec5fe688d444e5a52\$lut for cells of type $lut. Using template $paramod$dcc80413e595f6068225523669e63de7a140a290\$lut for cells of type $lut. Using template $paramod$d4322991da61c273f587e6246ec4b4ad91e983f0\$lut for cells of type $lut. Using template $paramod$73ea26144a7b2990251f47a11e967735b03bcbe6\$lut for cells of type $lut. Using template $paramod$eeed37ce45abdda29d3e180f2d1dfc0c4c376530\$lut for cells of type $lut. Using template $paramod$ebb7fc765547d4ee3b96ad1162602b1d05f7aa94\$lut for cells of type $lut. Using template $paramod$a1522875362ebcc26f7effea4d2e5fdd80b2cc18\$lut for cells of type $lut. Using template $paramod$49a46b940c7cfd81e9aefe1faa7779efe5cad163\$lut for cells of type $lut. Using template $paramod$ac969d9398eb9421a30a342d303d11422783b5d2\$lut for cells of type $lut. Using template $paramod$018d71a0fe325d6362687fe53ac13dd6340e400d\$lut for cells of type $lut. Using template $paramod$5a4aa946ddef553bf035383155a67aba5f9dc115\$lut for cells of type $lut. Using template $paramod$fa45f28daf300aaa781ee4b9baa5ce968b1d8c66\$lut for cells of type $lut. Using template $paramod$3ec5e45cb3e54de9dbe908707155b5f9917c9370\$lut for cells of type $lut. Using template $paramod$3702268f692b8bf258e428f65d3bca4e1f76d98b\$lut for cells of type $lut. Using template $paramod$a05170b3f2d3fcb0bf88d37e810984e864962880\$lut for cells of type $lut. Using template $paramod$f747d54e1c552a8e1ec84eeba290de53b40d2baf\$lut for cells of type $lut. Using template $paramod$6bcd405cb0e5af7d8fd7d6c479341287c3bee423\$lut for cells of type $lut. Using template $paramod$da52757a531f227ad8085ca9d964754a4124a5a0\$lut for cells of type $lut. Using template $paramod$e4b832d686d12318ec0715f027fe549b42e45c20\$lut for cells of type $lut. Using template $paramod$7c329d6461da3322bc872b7712a3b81795022421\$lut for cells of type $lut. Using template $paramod$e4e8ac6ab447d6fc1add82a90e666ac3e0ad3e11\$lut for cells of type $lut. Using template $paramod$d315acbf930db7c20b3f4ac2dad3b7982b1f437c\$lut for cells of type $lut. Using template $paramod$060b19b867a35b5a43d3acaba4d8a8ec98ac604c\$lut for cells of type $lut. Using template $paramod$5c269c7ae8ebe8ae616b450420108fd8f1bac4c4\$lut for cells of type $lut. Using template $paramod$cd05caaf261e4148f336c0ecc488c806e4433d99\$lut for cells of type $lut. Using template $paramod$e8456af1de81b89b1d1b569e4ff4293afab2804a\$lut for cells of type $lut. Using template $paramod$b2b6fce78782dddd9d4121a732ed42ec7581b938\$lut for cells of type $lut. Using template $paramod$b01d7f38b3b27eb28cdc4c96c9d43e6b4803ff8a\$lut for cells of type $lut. Using template $paramod$5acc4341b16e48bc84b74027776d6d9e9b7f3a99\$lut for cells of type $lut. Using template $paramod$c0e5aa029594cd87101127a49c7b96105f4d8a4a\$lut for cells of type $lut. Using template $paramod$53d802be753f20765720d6b13f27c78b02e4888c\$lut for cells of type $lut. Using template $paramod$3418c99d5e4dcf94373956703fa75ab2bb3fdc84\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001000 for cells of type $lut. Using template $paramod$57e9679fb6ac67018036911602f0966b5f780d50\$lut for cells of type $lut. Using template $paramod$7929d818ff6cdab401756b40b10229878e94bd76\$lut for cells of type $lut. Using template $paramod$d82e3ce0992c2c9ee304d5e3733d06acec3d4e5a\$lut for cells of type $lut. Using template $paramod$af5330eeff6be7ec404d71572c9c2e2852c0a198\$lut for cells of type $lut. Using template $paramod$a59854b679c443f21a6748ea460109b8241cb007\$lut for cells of type $lut. Using template $paramod$56e6d8a28a52006bb4e50e077743f0a2163235af\$lut for cells of type $lut. Using template $paramod$d9697c27edeeedf1e70e6c3f23a895a810d0e470\$lut for cells of type $lut. Using template $paramod$26d876869d6ab003366d0470e095daef2ccfcbd7\$lut for cells of type $lut. Using template $paramod$961043886a66a2d7623ddfd6cee77d2ff5d365ce\$lut for cells of type $lut. Using template $paramod$5488a2b09d077d65ef597672bc7454706900e094\$lut for cells of type $lut. Using template $paramod$3128ede2c998148b098fc8ae777015bb2ba1835f\$lut for cells of type $lut. Using template $paramod$5e9374f44a27c3f8a1c38af244ec43ceb4fb8d4f\$lut for cells of type $lut. Using template $paramod$58df2c605746858c7e53492c8f57d6f1fafa12d2\$lut for cells of type $lut. Using template $paramod$c7eaad6a588218ef0ba5a17502d003bdff2bbd3e\$lut for cells of type $lut. Using template $paramod$11459c282341f7ea2a324ce23bcd2b846f81c85a\$lut for cells of type $lut. Using template $paramod$f5f41ee5d60dede31a2b59f58ec46b167939d713\$lut for cells of type $lut. Using template $paramod$d3185319b5c99da719afc2e6b2580a0af7d6917b\$lut for cells of type $lut. Using template $paramod$f90e2ec6b7a4c6db6f7a3682dfa870e7c33a78da\$lut for cells of type $lut. Using template $paramod$6b85005f52472512b211286b920c973a28f5655b\$lut for cells of type $lut. Using template $paramod$8d64e576629e8d7c655e0c65958ea61e649cd93e\$lut for cells of type $lut. Using template $paramod$9e776ec1b34d86f88d5c27558aea8207655d0a2b\$lut for cells of type $lut. Using template $paramod$113ce73995f65f4ab30c731543ee7ef849b7d713\$lut for cells of type $lut. Using template $paramod$868e858f7825b992db8b875fb73eac482f890054\$lut for cells of type $lut. Using template $paramod$24e8e45e1f616576290998a80e943342bb13ffc5\$lut for cells of type $lut. Using template $paramod$fffceb4d6b1f2097835ac93992c22fe6056375fb\$lut for cells of type $lut. Using template $paramod$11b5c28e72aff080e7e0c2d32c1771373651f3c4\$lut for cells of type $lut. Using template $paramod$f7a6eac5bfd7cc7c4c99abf3e1ef6130612e0664\$lut for cells of type $lut. Using template $paramod$52341f6017db69268706bfd5a5ad5f208704cdde\$lut for cells of type $lut. Using template $paramod$01e92061986b32babd4df547521634b11a27dfa2\$lut for cells of type $lut. Using template $paramod$4f475258bcee6b5e6ab09927a7443bdf9dae7411\$lut for cells of type $lut. Using template $paramod$77b566652a2449bae604a937e67f0c9bd49bb4a7\$lut for cells of type $lut. Using template $paramod$397ab08a025ffa0fdf392a0c9a750682e97f89d9\$lut for cells of type $lut. Using template $paramod$c362ad8dedc7d166ed978091aca319ab1e81a2d4\$lut for cells of type $lut. Using template $paramod$4f09540800ac966d6e31a7ccf5f32a559a8ce57a\$lut for cells of type $lut. Using template $paramod$758c1f387a474cd81674de8227563598a835ad3c\$lut for cells of type $lut. Using template $paramod$796520cb7ec6807336506391ddb3b3896e463af0\$lut for cells of type $lut. Using template $paramod$06af8e98b1ee32760d0eff675cf4988d49cbfdfa\$lut for cells of type $lut. Using template $paramod$5002424fb13e71fe3d63c5ae16358968d083bd9b\$lut for cells of type $lut. Using template $paramod$39edba5b0b5aad7ce7719fffe4a98b9e82b0e804\$lut for cells of type $lut. Using template $paramod$4f0992e853620c1b6bdec4e0ad852db5490f409d\$lut for cells of type $lut. Using template $paramod$ae9b8688208bc968e066759f867620e9ddf86c4d\$lut for cells of type $lut. Using template $paramod$01a774932a7360a620e4704477ccb3c7e23ece02\$lut for cells of type $lut. Using template $paramod$57db67c9b4c7c49765c11cfa5912d38cd9a5ad67\$lut for cells of type $lut. Using template $paramod$3e5ece585495a03246739c68e98604e944f8b582\$lut for cells of type $lut. Using template $paramod$af15d200e3605f2c4c42beab3430842bc93f1158\$lut for cells of type $lut. Using template $paramod$c758cf8aee7c6f51f0f08a610e549e87b7c5efaf\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11010000 for cells of type $lut. Using template $paramod$67a7ae540a7abc215c4e0ac06ac3b047221d8e8f\$lut for cells of type $lut. Using template $paramod$d7f56753654ac6d225893b00fbc35a2408a482b7\$lut for cells of type $lut. Using template $paramod$f1e653228fd65c9e6dbf31be5aff449649c761eb\$lut for cells of type $lut. Using template $paramod$a1d323730045824cfc84bb9f4ee8031f1c4dcc9e\$lut for cells of type $lut. Using template $paramod$390ab503081c27220758f809afca20dea00ee13b\$lut for cells of type $lut. Using template $paramod$219b71aec9a19e7a27754ed85a7d6cdad9e5ec96\$lut for cells of type $lut. Using template $paramod$127d42c61791e2b6b8fd39133e126a67cbdb52bc\$lut for cells of type $lut. Using template $paramod$b7685cb0c8a6753256bc84bc31d36a443c15fab7\$lut for cells of type $lut. Using template $paramod$a977fb3a4e30b200887394f8ff6c3df1befab9e3\$lut for cells of type $lut. Using template $paramod$d546db88fc169832512e499a9cdf9a41b89ab74e\$lut for cells of type $lut. Using template $paramod$ab5f6cbda813df0763ad05c5e0cfe5a674acf259\$lut for cells of type $lut. Using template $paramod$a466678992feb44cf6749703c13a9fa3f3b5c308\$lut for cells of type $lut. Using template $paramod$653640a6ab19815122ca8006667d53466bf03163\$lut for cells of type $lut. Using template $paramod$462d32da163b9fe56a501bc98db9986e07be47f1\$lut for cells of type $lut. Using template $paramod$f462624619cf0a2d6f0c31648d390037e6d23d7c\$lut for cells of type $lut. Using template $paramod$8b2d4da05a775f7705e7bcda27120d70b71d57db\$lut for cells of type $lut. Using template $paramod$8aeee140d2ae9f358f8fe61c5400dbb6eeb83fd2\$lut for cells of type $lut. Using template $paramod$9f940528886e4436555e49aadfc3973afc89a325\$lut for cells of type $lut. Using template $paramod$741a56e1ab0c59116c24b6bba53915f87e59cde0\$lut for cells of type $lut. Using template $paramod$df29fe9e6d6d694a9cc5697e4251bf7d8cd4d8e4\$lut for cells of type $lut. Using template $paramod$9e2b188711e0c12c2fe86e0510cd6df11f513c14\$lut for cells of type $lut. Using template $paramod$b10362b71f0fae22c5be855d27fcefe2e81551bf\$lut for cells of type $lut. Using template $paramod$2414775a920c78244d3b73d56a9177516a8dafff\$lut for cells of type $lut. Using template $paramod$e5f53fb2cb3e702c9422ebddd3ba952e5a8f3401\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11101111 for cells of type $lut. Using template $paramod$9dfe2a25d99d8640a9f67a2438aaca85b684d257\$lut for cells of type $lut. Using template $paramod$64b84593fae19d6c4d7d26333a195e5cc6b30160\$lut for cells of type $lut. Using template $paramod$2d07c1a6c53c7b878509360922c4fa5ebedc3011\$lut for cells of type $lut. Using template $paramod$2382b0dd4cb27fd4312681c40a6dd179c2a7a26a\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10010000 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1101 for cells of type $lut. Using template $paramod$cae45ff85b946d8cfe295bf4feda7db55ee71cea\$lut for cells of type $lut. Using template $paramod$f34232779a0569d5ac41d2d692536961128467b0\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00110001 for cells of type $lut. Using template $paramod$181733d3e31dcdcea8c52d0a4fc252b3aa453564\$lut for cells of type $lut. Using template $paramod$4ebbf381cf64b08e3304ae8194da41d0cd1eaa92\$lut for cells of type $lut. Using template $paramod$baa939b0bd5b3e0c8760492528669bd58f640542\$lut for cells of type $lut. Using template $paramod$ca38b4deb8400d082d8b40f50a5122655719c7aa\$lut for cells of type $lut. Using template $paramod$0721052c0877e4dc4a65769ffe372fb9eecc24c1\$lut for cells of type $lut. Using template $paramod$57400e123f0147f905d2ec980ae5b64230fc0a43\$lut for cells of type $lut. Using template $paramod$a8b2b0f3a3fd7b01c99e8d61bb72f602bd41af54\$lut for cells of type $lut. Using template $paramod$eba7de026ff587370e320127e266317dae097a89\$lut for cells of type $lut. Using template $paramod$25003f26a78bb2f583f23824f1e0b8cc16b88761\$lut for cells of type $lut. Using template $paramod$c1a19a87ccbbb03d43a72335db63f692ddf82cc1\$lut for cells of type $lut. Using template $paramod$f6419acf37716c6266d111b8ace61651cab00c08\$lut for cells of type $lut. Using template $paramod$8adf7fbd410d2cc654c288d5be5f7508ee8809b0\$lut for cells of type $lut. Using template $paramod$16b79a5eba6e0c11d0283a95b16674705257a0eb\$lut for cells of type $lut. Using template $paramod$b70f6d644b8a52b516c4ce5ffb3655ea8e60a955\$lut for cells of type $lut. Using template $paramod$c600b4b1adc22857e1c1ba3b6aeb516fabe09da0\$lut for cells of type $lut. Using template $paramod$68333ba85565e16101ab8af69fddc9a0d05bfda5\$lut for cells of type $lut. Using template $paramod$fe285f2cd171c10ad8655977bef8843a68f96041\$lut for cells of type $lut. Using template $paramod$053f34c7337c703bac391af9e006c7f4d7011c4b\$lut for cells of type $lut. Using template $paramod$65c625408491be27ddc50cde597ced7caa7e3e35\$lut for cells of type $lut. Using template $paramod$12b93181fde40368887ce43b59fecaa09cb41fa7\$lut for cells of type $lut. Using template $paramod$faf4b69e2195a9ce52b7c3bce83fa5ea343bc378\$lut for cells of type $lut. Using template $paramod$b587e1dcd8f8a9800d395e4aeecac52c55d6f585\$lut for cells of type $lut. Using template $paramod$f626b575273537b3090dbe5d04b27b283ec9a192\$lut for cells of type $lut. Using template $paramod$93b474cc03318a79e4643a3a3ea212704a47025b\$lut for cells of type $lut. Using template $paramod$7b733f5b3466ec911060896fccc5c2626cbe3d64\$lut for cells of type $lut. Using template $paramod$cdc5bba2585477f1744fd1f869bebc8beb23d707\$lut for cells of type $lut. Using template $paramod$7f4670b933e9d0d313fe2dbe752fa82b1cf04d5c\$lut for cells of type $lut. Using template $paramod$000fa2164e1f538c16460571efee2b6209a086cc\$lut for cells of type $lut. Using template $paramod$f3ada871809f362efd8eb0c4fb952bb5c98f0750\$lut for cells of type $lut. Using template $paramod$18b66a2dc66be2a0d172c3d50ba03932f5924e22\$lut for cells of type $lut. Using template $paramod$9fc14cb0ba5120a1da0c687a9fb19472f206fdfe\$lut for cells of type $lut. Using template $paramod$11c86b7a6cb6e98dcfb16c5f4d4cc1052b93d8a4\$lut for cells of type $lut. Using template $paramod$84c5cfa8d7481774250caab0fcdd6d249a376a31\$lut for cells of type $lut. Using template $paramod$ddace04fba544e6adc4cdda6a50048ddd7c111af\$lut for cells of type $lut. Using template $paramod$865395c0228487a64a8e4011cecafc2c64b79f2b\$lut for cells of type $lut. Using template $paramod$66caeb00a39d236782a97659e3bd99621b74681b\$lut for cells of type $lut. Using template $paramod$7491e7206ae8c682d288373efe06a43b67c277cf\$lut for cells of type $lut. Using template $paramod$1a10df59f43f252ae2ee713b788731ad5d18c6f5\$lut for cells of type $lut. Using template $paramod$68a25441a4bae0d0c849cc98a765b52d3c284acb\$lut for cells of type $lut. Using template $paramod$5502a85110dbca29ac631107f0b0635e7fade476\$lut for cells of type $lut. Using template $paramod$a50be0e6fa3a01511bb234559cb74fb8bd3e2061\$lut for cells of type $lut. Using template $paramod$3ae9f1cda205b669870c653a21d45eee50078e98\$lut for cells of type $lut. Using template $paramod$d7ec878ecfa8f5f7604d3e91692b5d4c2ee758ad\$lut for cells of type $lut. Using template $paramod$8ae5e24171bca0b8d12d43741a6723f274290f92\$lut for cells of type $lut. Using template $paramod$0970e85cdc747dab949eb3dd0e62f11c3828dc7d\$lut for cells of type $lut. Using template $paramod$db08fd84fb3c4d6a41eaec6adfffe445fb7eb17f\$lut for cells of type $lut. Using template $paramod$98f046219fcb6214b75e755687ac5c88eed225b9\$lut for cells of type $lut. Using template $paramod$47d363ae7b1a0e81207e02fe31af85b6bf36a2ac\$lut for cells of type $lut. Using template $paramod$655e7cdf1fce9923e771969f28446489197085e2\$lut for cells of type $lut. Using template $paramod$beb2a19325ee1ad97b5d00f26c00864fd5366f0f\$lut for cells of type $lut. Using template $paramod$b93d1ea7a612a32c185108f67a153d44ffb9aac2\$lut for cells of type $lut. Using template $paramod$adce9c89515a4e83641fc3471eb3c01ec7b082ff\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001100 for cells of type $lut. Using template $paramod$21ce7bd4c9c58a58784d7d482453272837db1acd\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001111 for cells of type $lut. Using template $paramod$f7a897257decedfb6cc642e53d65fef7fc0df390\$lut for cells of type $lut. Using template $paramod$f32bdd7cc07438f72cd437b3c5a28e8ae84afc03\$lut for cells of type $lut. Using template $paramod$ee700feb78d1f78a2275689013e0e783764ce7f3\$lut for cells of type $lut. Using template $paramod$53ce561f80f32d4298a3beadc88b6c5c78293221\$lut for cells of type $lut. Using template $paramod$01b636f2759ab594c2741266b3c22685988e291c\$lut for cells of type $lut. Using template $paramod$66658cbed86a8310f9b7ba1190d35eff90ee749b\$lut for cells of type $lut. Using template $paramod$39b624085d541d640f20e75b5bef913f25a96429\$lut for cells of type $lut. Using template $paramod$cc0454b50e7a4bac6495b6e30a58ceb8dfd032c5\$lut for cells of type $lut. Using template $paramod$712505941a295086314c22735153725461a87f4a\$lut for cells of type $lut. Using template $paramod$1c4a5fb48d7dfe60e67a1a249551f33b87b0f2f3\$lut for cells of type $lut. Using template $paramod$d61ed33262f5520dcebd685520368064d7278297\$lut for cells of type $lut. Using template $paramod$179512a187da069f3b79ef6612a41e494e7d54b6\$lut for cells of type $lut. Using template $paramod$234997bee759301806c8ada31f0c044884c8f8c5\$lut for cells of type $lut. Using template $paramod$b15d9bfef5644085826544ce6c62dc7d407673ec\$lut for cells of type $lut. Using template $paramod$a6b2d4693fada6bebbe4480262641915d709d280\$lut for cells of type $lut. Using template $paramod$8a14c147789974582009243c8f6f60c968cc6777\$lut for cells of type $lut. Using template $paramod$a76afe794e55ba422468b9db09d48da3f250b812\$lut for cells of type $lut. Using template $paramod$20ba583962918fa0136fc97b1558cc45cc91cc29\$lut for cells of type $lut. Using template $paramod$1f313f85ef575d13bac75382f04905a8c8be8f57\$lut for cells of type $lut. Using template $paramod$9e354de8d358bf081aa0c089488ea3bc5b7c2fd9\$lut for cells of type $lut. Using template $paramod$de04cb9fed08da92a34d101e5e82912c17d40d8e\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010101 for cells of type $lut. Using template $paramod$92392f7e0125ad8ca1de78d92e39c252afd15cdf\$lut for cells of type $lut. Using template $paramod$4d7f17f71543a1e7fc1835bd79c4827a43f2e844\$lut for cells of type $lut. Using template $paramod$e54349d9a634ecff5f53629ed023a0262d334efb\$lut for cells of type $lut. Using template $paramod$78b4324556f6321a85bd440441a5392f271ea218\$lut for cells of type $lut. Using template $paramod$beae4210b922fc9ba2fcc4008a7474b475e38c50\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111001 for cells of type $lut. Using template $paramod$e03cd8e8a49e77c888661124604e34849b676141\$lut for cells of type $lut. Using template $paramod$6f527ad842b6bfe0b6a4f71c5f351694f4beb3d7\$lut for cells of type $lut. Using template $paramod$b600d182ae966d09f33a746441e104587fe7a58f\$lut for cells of type $lut. Using template $paramod$87cad75e5228984b6c2387055450005570b7eea8\$lut for cells of type $lut. Using template $paramod$650649997bf7e5f1ea588e401d59f9091021f47e\$lut for cells of type $lut. Using template $paramod$fb5ee0bdef1c4e74aaf1fd8efae98b46a2f5e564\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111101 for cells of type $lut. Using template $paramod$1b4dd6457d07f8f165ec99061b8d6c5023635c5b\$lut for cells of type $lut. Using template $paramod$5307f40f1b453046eb68ee1a10c3f82d605af6fc\$lut for cells of type $lut. Using template $paramod$619b7c9a4d44585e10b42f7fb79b16304cca97c5\$lut for cells of type $lut. Using template $paramod$651e836885d95717c36e69441422c3fe04ee5f4d\$lut for cells of type $lut. Using template $paramod$aa9cf2f501984f3d23676491f808fe20bb38f6a7\$lut for cells of type $lut. Using template $paramod$4d256fbdc9e64053bf8437c1c851d487119b6909\$lut for cells of type $lut. Using template $paramod$432f26b811c14bf54c5e87c8670ec65cbcaf38ac\$lut for cells of type $lut. Using template $paramod$0328e568d609989242dcb98a1c5328d4372a6e9c\$lut for cells of type $lut. Using template $paramod$ee82f1504b2c48e70160208feb4e1f2a1b612b8d\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111000 for cells of type $lut. Using template $paramod$5b4b4ed558983d9f3ab4c896a7a011d129b0db9a\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01010111 for cells of type $lut. Using template $paramod$66a21d6ecac0a869f10dfeecf6235898a47b3b78\$lut for cells of type $lut. Using template $paramod$8b5cd3db939d1b72145e634c68ab25658458fb1a\$lut for cells of type $lut. Using template $paramod$4721519bef85e75f87d1f147d88c627c84abf942\$lut for cells of type $lut. Using template $paramod$769bdbbde83614df0f4ab5f54e777ded51bb10ce\$lut for cells of type $lut. Using template $paramod$6e4a86e6f1a5dc8f826898a131e83cdba4a4fc9e\$lut for cells of type $lut. Using template $paramod$bff60da521de773f8caf46fbc0845c3d7d3e2310\$lut for cells of type $lut. Using template $paramod$684b54388be6489c38743e4efd4f9fa13e760a4a\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01101010 for cells of type $lut. Using template $paramod$0379de7331749c8fff95d21832911292af4fff21\$lut for cells of type $lut. Using template $paramod$486e9253c65fbb8e04c0c19bc627fa9f3113c6b6\$lut for cells of type $lut. Using template $paramod$fb5496753f4cd235e71c284b2ffee9d41a960ca2\$lut for cells of type $lut. Using template $paramod$1843b3c15f2447d117e2d5de9b00f791ef5f9fa3\$lut for cells of type $lut. Using template $paramod$19f4fa446d94767b8a3977abee599cf6b53b2330\$lut for cells of type $lut. Using template $paramod$00dfa99b7aecc2e72490719b192118cbd6549a2c\$lut for cells of type $lut. Using template $paramod$658d8ae8f10d8bd0c2aa5487f4823315bd52b0e0\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111110 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11110010 for cells of type $lut. Using template $paramod$223a1a0bfc3038108c8c5d096bc8fdc50fd540b0\$lut for cells of type $lut. No more expansions possible. <suppressed ~8488 debug messages> 24.44. Executing OPT_LUT_INS pass (discard unused LUT inputs). Optimizing LUTs in top. Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81779.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81779.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81779.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81779.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81779.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81733.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$15343.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$15046.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$15046.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$14532.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$14401.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$14374.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$14374.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$13751.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$13124.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$13124.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$13124.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$13124.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$13124.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$13124.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$13118.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$13118.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$13093.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$81649$lut$auto$rtlil.cc:2582:Mux$4491[15].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$12037.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$11816.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$11816.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$11800.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$11602.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$11457.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$11421.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$10556.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$10556.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$10556.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$10556.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$10556.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$10537.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$10524.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$10524.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81781.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81781.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81780.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81780.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$10505.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$10492.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$10485.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$10485.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$10485.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$10473.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$10473.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$10473.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$10473.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$10473.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$10473.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$10432.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$10432.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$10384.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81783.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$10254.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$10254.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$10249.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$10227.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$10222.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$10222.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$10222.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$10198.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$10198.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$10198.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$10198.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$10198.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$10198.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$10192.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$10127.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$10127.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$10127.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$10116.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$10116.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$10090.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81784.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81784.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81784.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81784.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81784.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81784.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81785.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$9896.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$9896.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$9896.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$9887.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$9887.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$9887.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$9867.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$9867.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$9867.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$9867.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$9867.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$9854.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$9854.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$9854.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$9854.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$9854.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$9854.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$9843.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$9843.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$9843.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$9843.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$9843.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$9843.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$9843.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81653.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81653.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81653.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81653.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81653.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81653.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81652.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81652.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81652.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81652.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81652.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81652.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$9810.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$9810.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$9755.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$9755.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$9755.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$9755.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$9741.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81655.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81655.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$9627.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$9627.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$9627.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$9627.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$9627.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$9603.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$9583.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$9583.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$9583.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$9583.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$9583.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$9583.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$9583.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$9534.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$9508.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$9508.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$9508.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$9646.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$9646.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$9646.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$9646.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$9646.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81657.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$9474.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$9468.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$9468.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$9468.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$9428.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$9428.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$9423.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$9423.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$9412.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$9412.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$9412.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$9412.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$9412.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$9412.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$9412.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$9400.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$9400.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$9400.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$9381.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$9359.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$9328.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$9322.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$9322.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$9322.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$9313.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$9313.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$9313.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$9342.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$9342.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$9342.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$9342.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$9342.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$9342.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$9303.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$9303.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$9303.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$9303.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$9303.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$9303.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$9291.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$9291.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$10066.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$9264.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$9264.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$9255.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$9255.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$9255.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$9437.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$9437.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81786.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$9983.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$9983.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$9969.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$9969.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$9969.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$9969.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$9969.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$9969.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$9969.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$9960.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$9960.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$9960.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$9945.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$9945.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$9945.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$9834.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$9834.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$9834.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$10010.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$10010.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$10010.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$10010.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$9990.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$9990.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$9990.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$9917.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$9917.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$9876.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$9876.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$9876.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$9999.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$9999.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$9999.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$6943.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$6943.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$6943.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$6281.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$6281.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$5414.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$5414.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$8860.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$8860.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$8860.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$8860.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$8860.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$8665.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$8665.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$8665.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$8665.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$8665.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$8611.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$8369.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$8315.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$8267.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$8267.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$8267.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$8267.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$8267.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$8267.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$8398.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81798.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81798.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81798.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81798.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81798.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$5739.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$5699.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$5668.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$5668.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$8222.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$8222.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$8222.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$8222.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$8222.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$8213.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$8173.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$8142.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$8142.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$9543.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$9543.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$9543.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$5405.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$5405.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$5405.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$5405.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$5405.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$5405.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$5396.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$5386.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$5386.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$5386.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$5386.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$5356.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$5356.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$5356.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$5356.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$5325.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$5325.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$5325.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$5325.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$5325.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$5301.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$5301.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$5301.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$5301.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$5301.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$5292.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$5282.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$5282.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$5282.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$5282.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$5252.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$5252.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$5252.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$5252.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$5221.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$5221.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$5221.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$5221.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$5221.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$5197.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$5197.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$5197.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$5197.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$5197.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$5188.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$5178.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$5178.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$5178.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$5178.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$5148.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$5148.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$5148.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$5148.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$5117.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$5117.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$5117.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$5117.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$5117.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$4849.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$4849.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$4849.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$4849.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$4849.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$4840.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$4830.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$4830.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$4830.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$4830.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$4800.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$4800.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$4800.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$4800.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$4769.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$4769.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$4769.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$4769.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$4769.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$7792.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$7792.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$7792.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$7792.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$7792.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$7783.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$7773.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$7773.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$7773.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$7773.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$7743.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$7743.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$7743.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$7743.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$7712.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$7712.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$7712.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$7712.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$7712.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$4742.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$4742.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$4742.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$4742.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$4742.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$4733.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$4723.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$4723.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$4723.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$4723.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$4693.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$4693.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$4693.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$4693.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$4662.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$4662.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$4662.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$4662.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$4662.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81792.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81792.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81792.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81792.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$4944.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$4934.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$4934.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$4934.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$4934.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$4904.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$4904.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$4904.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$4904.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$4873.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$4873.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$4873.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$4873.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$4873.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$4638.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$4638.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$4638.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$4638.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$4638.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$4629.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$4619.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$4619.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$4619.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$4619.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$4589.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$4589.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$4589.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$4589.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$4558.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$4558.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$4558.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$4558.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$4558.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$9681.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$9681.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81794.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81794.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81794.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81794.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81794.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$6160.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$6150.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$6150.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$6150.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$6150.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$6120.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$6120.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$6120.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$6120.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$6089.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$6089.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$6089.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$6089.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$6089.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81793.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81793.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81793.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81793.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$5085.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$5075.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$5075.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$5075.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$5075.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$5045.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$5045.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$5045.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$5045.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$5014.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$5014.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$5014.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$5014.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$5014.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$6272.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$6272.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$6272.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$6272.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$6272.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$6263.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$6253.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$6253.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$6253.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$6253.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$6223.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$6223.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$6223.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$6223.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$6192.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$6192.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$6192.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$6192.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$6192.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$6065.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$6065.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$6065.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$6065.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$6065.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$6056.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$6046.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$6046.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$6046.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$6046.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$6016.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$6016.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$6016.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$6016.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$5985.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$5985.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$5985.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$5985.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$5985.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81796.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81796.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81796.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81796.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$5530.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$5520.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$5520.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$5520.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$5520.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$5490.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$5490.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$5490.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$5490.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$5459.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$5459.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$5459.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$5459.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$5459.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81795.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81795.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81795.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81795.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$5633.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$5623.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$5623.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$5623.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$5623.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$5593.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$5593.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$5593.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$5593.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$5562.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$5562.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$5562.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$5562.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$5562.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$5961.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$5961.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$5961.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$5961.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$5961.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$5952.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$5942.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$5942.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$5942.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$5942.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$5912.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$5912.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$5912.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$5912.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$5881.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$5881.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$5881.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$5881.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$5881.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$9667.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$9667.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$9667.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$9667.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$9667.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$9667.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$5851.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$5851.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$5851.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$5851.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$5851.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$5851.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$5842.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$5802.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$5802.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$5802.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$5802.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$5771.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$5771.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$9653.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81797.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81797.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81797.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81797.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81797.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81797.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$8106.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$8106.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$8106.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$8106.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$8106.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$8097.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$8087.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$8087.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$8087.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$8087.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$8057.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$8057.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$8057.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$8057.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$8026.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$8026.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$8026.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$8026.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$8026.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$7368.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$7368.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$7368.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$7368.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$7368.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$7359.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$7349.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$7349.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$7349.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$7349.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$7319.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$7319.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$7319.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$7319.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$7288.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$7288.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$7288.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$7288.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$7288.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$9559.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$9559.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81790.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81790.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81790.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81790.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81790.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$7463.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$7453.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$7453.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$7453.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$7453.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$7423.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$7423.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$7423.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$7423.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$7392.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$7392.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$7392.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$7392.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$7392.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81789.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81789.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81789.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81789.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$6615.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$6605.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$6605.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$6605.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$6605.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$6575.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$6575.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$6575.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$6575.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$6544.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$6544.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$6544.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$6544.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$6544.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$7682.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$7682.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$7682.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$7682.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$7682.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$7673.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$7663.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$7663.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$7663.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$7663.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$7633.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$7633.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$7633.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$7633.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$7602.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$7602.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$7602.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$7602.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$7602.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$7578.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$7578.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$7578.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$7578.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$7578.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$7569.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$7559.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$7559.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$7559.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$7559.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$7529.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$7529.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$7529.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$7529.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$7498.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$7498.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$7498.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$7498.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$7498.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81791.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81791.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81791.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81791.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$7994.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$7984.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$7984.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$7984.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$7984.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$7954.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$7954.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$7954.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$7954.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$7923.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$7923.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$7923.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$7923.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$7923.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$7896.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$7896.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$7896.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$7896.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$7896.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$7887.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$7877.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$7877.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$7877.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$7877.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$7847.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$7847.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$7847.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$7847.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$7816.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$7816.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$7816.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$7816.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$7816.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81787.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81787.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81787.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81787.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$7246.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$7236.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$7236.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$7236.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$7236.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$7206.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$7206.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$7206.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$7206.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$7175.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$7175.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$7175.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$7175.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$7175.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$7151.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$7151.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$7151.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$7151.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$7151.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$7142.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$7132.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$7132.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$7132.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$7132.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$7102.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$7102.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$7102.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$7102.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$7071.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$7071.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$7071.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$7071.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$7071.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$9524.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$9524.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81788.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81788.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81788.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81788.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81788.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$6718.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$6708.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$6708.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$6708.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$6708.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$6678.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$6678.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$6678.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$6678.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$6647.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$6647.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$6647.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$6647.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$6647.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$7047.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$7047.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$7047.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$7047.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$7047.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$7038.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$7028.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$7028.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$7028.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$7028.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$6998.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$6998.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$6998.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$6998.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$6967.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$6967.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$6967.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$6967.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$6967.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$6934.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$6934.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$6934.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$6934.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$6934.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$6925.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$6915.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$6915.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$6915.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$6915.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$6885.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$6885.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$6885.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$6885.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$6854.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$6854.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$6854.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$6854.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$6854.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$6830.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$6830.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$6830.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$6830.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$6830.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$6821.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$6811.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$6811.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$6811.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$6811.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$6781.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$6781.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$6781.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$6781.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$6750.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$6750.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$6750.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$6750.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$6750.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$4162.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$4987.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$4987.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$4987.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$4987.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$4987.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$4987.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$4534.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$4534.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$4494.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$4494.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$4494.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$4494.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$6415.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$6415.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$6348.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$6348.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$6348.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$6348.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$6348.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$6348.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$6322.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$6322.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$6322.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$6322.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$6322.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$6322.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$6297.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$6481.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$6477.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$4972.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$6466.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$6466.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$4469.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$4469.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$6461.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$6461.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$6461.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$6461.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$6461.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$6454.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$4520.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$4464.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$4464.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$4464.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$4464.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$4449.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$4449.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$4424.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$4424.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$4424.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$4424.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$4424.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$4424.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$4375.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$81649$lut$auto$rtlil.cc:2582:Mux$4491[11].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$10010.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$10010.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81786.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$9437.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$10047.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$9264.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$9342.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$10079.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$10090.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$10090.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$10116.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$10116.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$10127.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$10145.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$10178.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$10192.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$10198.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$10222.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$10249.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$10254.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$10305.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$10354.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$10361.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$10399.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$10414.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$10418.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$10432.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$10467.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$10473.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$10477.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$10485.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$10492.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$10501.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$10533.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$10541.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$10556.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$10556.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$10635.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$10678.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$10693.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$10751.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$10958.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$10969.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$11083.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$11126.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$11118.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$11254.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$11297.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$11289.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$11337.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$11378.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$11413.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$11463.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$11551.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$11586.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$11594.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$11606.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$81649$lut$auto$rtlil.cc:2582:Mux$4491[4].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$11650.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$11741.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$11776.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$11800.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$11810.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$11896.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$11931.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$11963.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$11990.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$12041.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$81649$lut$auto$rtlil.cc:2582:Mux$4491[7].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$12074.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$12089.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$12089.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$12118.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$12153.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$12188.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$12255.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$12290.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$12302.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$12320.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$12325.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$12325.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$12405.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$12427.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$12434.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$12439.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$12439.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$12473.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$12553.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$12588.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$12592.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$12675.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$12707.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$12712.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$12712.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$12785.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$12820.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$12894.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$12899.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$12899.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$13071.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$13078.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$13093.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$13104.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$13118.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$13124.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$13243.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$13262.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$13275.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$13321.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$13353.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$13377.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$13396.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$13494.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$13524.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$13616.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$13647.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$13652.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$13751.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$13782.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$13881.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$13902.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$13912.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$14031.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$14051.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$14101.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$14133.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$14143.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$14180.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$14231.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$14263.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$14273.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$14314.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$14374.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$14374.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$14401.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$14401.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$14532.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$14532.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$14556.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$14608.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$14643.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$14663.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$14752.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$14776.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$14876.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$14925.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$15005.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$15023.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$15027.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$15046.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$15084.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$15218.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$15306.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$15339.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$15366.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$4520.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$4162.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$4375.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$4396.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$4424.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$4469.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$4473.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$4972.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$4494.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$4506.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$4494.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$4528.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$4534.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$9681.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$4558.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$4629.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$4638.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$4662.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$4733.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$4742.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$8860.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$4769.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$4840.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$4849.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$4638.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$4873.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$4944.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$4972.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$4987.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$6272.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$5014.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$5085.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$4849.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$5117.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$5188.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$5197.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$5197.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$5221.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$5292.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$5301.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$5301.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$5325.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$5396.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$5405.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$5414.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$5414.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$5459.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$5530.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$5961.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$5562.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$5633.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$8222.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$5699.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$5739.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$5842.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$5851.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$5881.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$5952.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$5961.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$5985.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$6056.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$6065.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$6089.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$6160.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$6065.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$6192.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$6263.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$6272.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$6281.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$6281.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$6297.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$6301.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$6311.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$6322.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$6322.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$6348.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$6397.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$6397.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$6415.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$6425.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$6438.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$6461.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$6466.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$6438.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$6513.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$6513.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$6520.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$7682.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$6544.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$6615.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$7047.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$6647.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$6718.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$6750.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$6821.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$6830.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$6830.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$6854.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$6925.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$6934.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$6943.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$6934.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$6967.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$7038.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$7047.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$9524.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$7071.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$7142.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$7151.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$7151.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$7175.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$7246.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$7261.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$7261.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$9559.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$7288.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$7359.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$7368.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81789.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$7392.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$7463.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$7498.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$7569.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$7578.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$7578.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$7602.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$7673.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$7682.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$4742.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$7712.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$7783.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$7792.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$7816.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$7887.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$7896.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$7896.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$7923.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$7994.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$7368.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$8026.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$8097.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$8106.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$8173.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$8213.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$8222.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$8267.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$8267.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$8277.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$8322.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$8345.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$8362.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$8377.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$8398.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$8398.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$8405.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$8473.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$8479.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$8524.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$8539.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$8555.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$8570.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$8603.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$8615.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$8638.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$8665.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$8665.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$8694.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$8709.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$8717.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$8750.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$8766.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$8791.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$8800.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$8809.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$8819.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$8848.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$8860.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$8877.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$8881.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$8915.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$8919.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$8941.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$9144.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$9149.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$9155.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$9176.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81793.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81792.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81795.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81796.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81791.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$7792.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$10192.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$9255.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$9264.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$9291.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$9291.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$9303.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$9313.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$9322.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$9303.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$9342.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$9328.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$9347.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$9359.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$9359.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$9381.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$9381.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$9390.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$9400.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$9412.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$9423.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$9428.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$9437.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$9468.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$9474.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81657.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$9489.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$9646.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$9508.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$9524.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81787.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$9543.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$9559.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$8106.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$9577.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$9612.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$9627.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$9646.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$9653.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$9667.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$9681.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$9489.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$9755.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$9755.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$9762.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$9805.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$9810.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$9834.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$9843.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$9854.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$9854.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$9867.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$81649$lut$aiger81648$9876.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$9867.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$9887.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$9896.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$9904.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$9908.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$9917.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$9917.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81651.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$9945.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$9960.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$9969.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$9978.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$9983.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$81649$lut$aiger81648$9990.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$9999.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$81649$lut$auto$fsm_map.cc:170:map_fsm$3959[1].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$13751.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$81649$lut$auto$rtlil.cc:2582:Mux$4491[25].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$81649$lut$auto$rtlil.cc:2582:Mux$4491[10].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$81649$lut$auto$rtlil.cc:2582:Mux$4491[18].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$81649$lut$auto$rtlil.cc:2582:Mux$4491[5].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$81649$lut$auto$rtlil.cc:2582:Mux$4491[6].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$81649$lut$auto$rtlil.cc:2582:Mux$4491[9].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$81649$lut$auto$rtlil.cc:2582:Mux$4491[13].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$81649$lut$auto$rtlil.cc:2582:Mux$4491[3].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$81649$lut$auto$fsm_map.cc:170:map_fsm$3959[3].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$81649$lut$aiger81648$11784.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81654.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81736.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$81649$lut$aiger81648$14318.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$81649$lut$auto$rtlil.cc:2582:Mux$4491[28].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81652.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81653.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81655.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81656.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81657.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81666.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81672.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81679.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81680.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81682.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81685.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81686.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81689.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81696.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81700.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81703.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81707.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81708.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81719.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81722.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81723.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81726.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81732.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81734.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81759.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81762.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81664.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81779.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81779.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81780.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81781.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81782.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81784.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81786.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81787.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81788.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81789.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81790.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81791.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81792.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81793.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81794.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) OpINFO: [Device 21-403] Loading part xc7a100tcsg324-1 timizing lut $auto$abc9_ops.cc:1550:reintegrate$81795.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81796.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81797.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$81798.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Removed 0 unused cells and 7193 unused wires. 24.45. Executing AUTONAME pass. Renamed 508047 objects in module top (252 iterations). <suppressed ~13110 debug messages> 24.46. Executing HIERARCHY pass (managing design hierarchy). 24.46.1. Analyzing design hierarchy.. Top module: \top 24.46.2. Analyzing design hierarchy.. Top module: \top Removed 0 unused modules. 24.47. Printing statistics. === top === Number of wires: 5913 Number of wire bits: 15082 Number of public wires: 5913 Number of public wire bits: 15082 Number of ports: 6 Number of port bits: 18 Number of memories: 0 Number of memory bits: 0 Number of processes: 0 Number of cells: 7813 $_TBUF_ 6 $scopeinfo 32 CCU2C 196 L6MUX21 616 LUT4 4455 PFUMX 1182 TRELLIS_DPR16X4 308 TRELLIS_FF 1018 24.48. Executing CHECK pass (checking for obvious problems). Checking module top... Found and reported 0 problems. 24.49. Executing JSON backend. Warnings: 2 unique messages, 3 total End of script. Logfile hash: 0bb8f8ce31, CPU: user 9.22s system 0.08s, MEM: 242.47 MB peak Yosys 0.42+15 (git sha1 74a1dd99a, clang++ 14.0.0-1ubuntu1.1 -fPIC -Os) Time spent: 44% 1x abc9_exe (7 sec), 9% 11x techmap (1 sec), ... [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (NextPNR) [Pipeline] sh + /eda/oss-cad-suite/bin/nextpnr-ecp5 --json ./build/out.json --write ./build/out_pnr.json --45k --lpf Risco-5/fpga/ecp5/pinout.lpf --textcfg ./build/out.config --package CABGA381 --speed 6 --lpf-allow-unconstrained Info: constraining clock net 'clk' to 25.00 MHz Info: Logic utilisation before packing: Info: Total LUT4s: 6695/43848 15% Info: logic LUTs: 4455/43848 10% Info: carry LUTs: 392/43848 0% Info: RAM LUTs: 1232/ 5481 22% Info: RAMW LUTs: 616/10962 5% Info: Total DFFs: 1018/43848 2% Info: Packing IOs.. Info: $gpios[5]$iobuf_i: gpios_$_TBUF__Y.Y Info: pin 'gpios[5]$tr_io' constrained to Bel 'X9/Y71/PIOB'. Info: $gpios[4]$iobuf_i: gpios_$_TBUF__Y_1.Y Info: pin 'gpios[4]$tr_io' constrained to Bel 'X4/Y71/PIOB'. Info: $gpios[3]$iobuf_i: gpios_$_TBUF__Y_2.Y Info: pin 'gpios[3]$tr_io' constrained to Bel 'X0/Y65/PIOB'. Info: $gpios[2]$iobuf_i: gpios_$_TBUF__Y_3.Y Info: pin 'gpios[2]$tr_io' constrained to Bel 'X9/Y71/PIOA'. Info: $gpios[1]$iobuf_i: gpios_$_TBUF__Y_4.Y Info: pin 'gpios[1]$tr_io' constrained to Bel 'X6/Y71/PIOA'. Info: $gpios[0]$iobuf_i: gpios_$_TBUF__Y_5.Y Info: pin 'gpios[0]$tr_io' constrained to Bel 'X4/Y71/PIOA'. Info: pin 'tx$tr_io' constrained to Bel 'X90/Y20/PIOC'. Info: pin 'rx$tr_io' constrained to Bel 'X90/Y20/PIOA'. Info: pin 'reset$tr_io' constrained to Bel 'X0/Y29/PIOA'. Info: pin 'led[7]$tr_io' constrained to Bel 'X90/Y20/PIOD'. Info: pin 'led[6]$tr_io' constrained to Bel 'X0/Y44/PIOD'. Info: pin 'led[5]$tr_io' constrained to Bel 'X0/Y59/PIOA'. Info: pin 'led[4]$tr_io' constrained to Bel 'X15/Y71/PIOB'. Info: pin 'led[3]$tr_io' constrained to Bel 'X90/Y29/PIOC'. Info: pin 'led[2]$tr_io' constrained to Bel 'X90/Y44/PIOB'. Info: pin 'led[1]$tr_io' constrained to Bel 'X0/Y44/PIOC'. Info: pin 'led[0]$tr_io' constrained to Bel 'X0/Y59/PIOC'. Info: pin 'clk$tr_io' constrained to Bel 'X0/Y68/PIOC'. Info: Packing constants.. Info: Packing carries... Info: Packing LUTs... Info: Packing LUT5-7s... Info: Packing FFs... Info: 462 FFs paired with LUTs. Info: Generating derived timing constraints... Info: Promoting globals... Info: promoting clock net clk$TRELLIS_IO_IN to global network INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes. INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes INFO: [Synth 8-7075] Helper process launched with PID 694044 Info: Checksum: 0x802a4dda Info: Device utilisation: Info: TRELLIS_IO: 18/ 245 7% Info: DCCA: 1/ 56 1% Info: DP16KD: 0/ 108 0% Info: MULT18X18D: 0/ 72 0% Info: ALU54B: 0/ 36 0% Info: EHXPLLL: 0/ 4 0% Info: EXTREFB: 0/ 2 0% Info: DCUA: 0/ 2 0% Info: PCSCLKDIV: 0/ 2 0% Info: IOLOGIC: 0/ 160 0% Info: SIOLOGIC: 0/ 85 0% Info: GSR: 0/ 1 0% Info: JTAGG: 0/ 1 0% Info: OSCG: 0/ 1 0% Info: SEDGA: 0/ 1 0% Info: DTR: 0/ 1 0% Info: USRMCLK: 0/ 1 0% Info: CLKDIVF: 0/ 4 0% Info: ECLKSYNCB: 0/ 10 0% Info: DLLDELD: 0/ 8 0% Info: DDRDLL: 0/ 4 0% Info: DQSBUFM: 0/ 10 0% Info: TRELLIS_ECLKBUF: 0/ 8 0% Info: ECLKBRIDGECS: 0/ 2 0% Info: DCSC: 0/ 2 0% Info: TRELLIS_FF: 1018/ 43848 2% Info: TRELLIS_COMB: 6787/ 43848 15% Info: TRELLIS_RAMW: 308/ 5481 5% Info: Placed 18 cells based on constraints. Info: Creating initial analytic placement for 3550 cells, random placement wirelen = 306820. Info: at initial placer iter 0, wirelen = 2600 Info: at initial placer iter 1, wirelen = 1663 Info: at initial placer iter 2, wirelen = 1761 Info: at initial placer iter 3, wirelen = 1814 Info: Running main analytical placer, max placement attempts per cell = 8266178. Info: at iteration #1, type ALL: wirelen solved = 1790, spread = 43229, legal = 43923; time = 0.28s Info: at iteration #2, type ALL: wirelen solved = 4027, spread = 35769, legal = 36458; time = 0.28s Info: at iteration #3, type ALL: wirelen solved = 6539, spread = 34211, legal = 34855; time = 0.28s Info: at iteration #4, type ALL: wirelen solved = 9150, spread = 32431, legal = 33204; time = 0.25s Info: at iteration #5, type ALL: wirelen solved = 10822, spread = 31824, legal = 32538; time = 0.18s Info: at iteration #6, type ALL: wirelen solved = 12374, spread = 29616, legal = 30434; time = 0.23s Info: at iteration #7, type ALL: wirelen solved = 12967, spread = 29613, legal = 30475; time = 0.25s Info: at iteration #8, type ALL: wirelen solved = 14565, spread = 27987, legal = 28877; time = 0.24s Info: at iteration #9, type ALL: wirelen solved = 14931, spread = 26942, legal = 27760; time = 0.17s Info: at iteration #10, type ALL: wirelen solved = 15634, spread = 27042, legal = 27774; time = 0.17s Info: at iteration #11, type ALL: wirelen solved = 15580, spread = 26956, legal = 27908; time = 0.17s Info: at iteration #12, type ALL: wirelen solved = 16574, spread = 26247, legal = 27086; time = 0.17s --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2028.754 ; gain = 403.715 ; free physical = 757 ; free virtual = 24299 --------------------------------------------------------------------------------- Info: at iteration #13, type ALL: wirelen solved = 17452, spread = 25134, legal = 26052; time = 0.17s Info: at iteration #14, type ALL: wirelen solved = 16885, spread = 25187, legal = 26166; time = 0.17s Info: at iteration #15, type ALL: wirelen solved = 17291, spread = 25053, legal = 26082; time = 0.16s INFO: [Synth 8-11241] undeclared symbol 'pc_source', assumed default net type 'wire' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:168] WARNING: [Synth 8-9400] empty statement in sequential block [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v:54] INFO: [Synth 8-6157] synthesizing module 'top' [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/main.v:1] INFO: [Synth 8-6157] synthesizing module 'ResetBootSystem' [/var/lib/jenkins/workspace/Risco_5/Risco-5/debug/reset.v:1] Parameter CYCLES bound to: 20 - type: integer INFO: [Synth 8-6155] done synthesizing module 'ResetBootSystem' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/debug/reset.v:1] WARNING: [Synth 8-7071] port 'resetn_o' of module 'ResetBootSystem' is unconnected for instance 'ResetBootSystem' [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/main.v:24] WARNING: [Synth 8-7023] instance 'ResetBootSystem' of module 'ResetBootSystem' has 3 connections declared, but only 2 given [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/main.v:24] INFO: [Synth 8-6157] synthesizing module 'Risco_5_SOC' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:1] Parameter CLOCK_FREQ bound to: 50000000 - type: integer Parameter BIT_RATE bound to: 115200 - type: integer Parameter MEMORY_SIZE bound to: 2048 - type: integer Parameter MEMORY_FILE bound to: ../../software/memory/teste_uart_fpga.hex - type: string Parameter GPIO_WIDHT bound to: 8 - type: integer Parameter UART_BUFFER_SIZE bound to: 16 - type: integer INFO: [Synth 8-6157] synthesizing module 'Core' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:2] Parameter BOOT_ADDRESS bound to: 0 - type: integer INFO: [Synth 8-6157] synthesizing module 'PC' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/pc.v:1] INFO: [Synth 8-6155] done synthesizing module 'PC' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/pc.v:1] INFO: [Synth 8-6157] synthesizing module 'MUX' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/mux.v:1] INFO: [Synth 8-6155] done synthesizing module 'MUX' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/mux.v:1] INFO: [Synth 8-6157] synthesizing module 'Registers' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/registers.v:1] INFO: [Synth 8-6155] done synthesizing module 'Registers' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/registers.v:1] INFO: [Synth 8-6157] synthesizing module 'Control_Unit' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v:2] INFO: [Synth 8-155] case statement is not full and has no default [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v:166] INFO: [Synth 8-155] case statement is not full and has no default [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v:363] INFO: [Synth 8-6155] done synthesizing module 'Control_Unit' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v:2] INFO: [Synth 8-6157] synthesizing module 'ALU_Control' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v:1] INFO: [Synth 8-226] default block is never used [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v:34] INFO: [Synth 8-155] case statement is not full and has no default [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v:11] INFO: [Synth 8-6155] done synthesizing module 'ALU_Control' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v:1] INFO: [Synth 8-6157] synthesizing module 'Alu' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu.v:1] INFO: [Synth 8-6155] done synthesizing module 'Alu' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu.v:1] INFO: [Synth 8-6157] synthesizing module 'Immediate_Generator' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/immediate_generator.v:1] INFO: [Synth 8-6155] done synthesizing module 'Immediate_Generator' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/immediate_generator.v:1] INFO: [Synth 8-6157] synthesizing module 'CSR_Unit' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/csr_unit.v:1] INFO: [Synth 8-155] case statement is not full and has no default [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/csr_unit.v:117] INFO: [Synth 8-6155] done synthesizing module 'CSR_Unit' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/csr_unit.v:1] INFO: [Synth 8-6155] done synthesizing module 'Core' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:2] WARNING: [Synth 8-7071] port 'halt' of module 'Core' is unconnected for instance 'Core' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:33] WARNING: [Synth 8-7071] port 'interruption_request_external' of module 'Core' is unconnected for instance 'Core' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:33] WARNING: [Synth 8-7071] port 'interruption_request_timer' of module 'Core' is unconnected for instance 'Core' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:33] WARNING: [Synth 8-7071] port 'interruption_request_software' of module 'Core' is unconnected for instance 'Core' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:33] WARNING: [Synth 8-7071] port 'interruption_request_fast' of module 'Core' is unconnected for instance 'Core' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:33] WARNING: [Synth 8-7023] instance 'Core' of module 'Core' has 14 connections declared, but only 9 given [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:33] INFO: [Synth 8-6157] synthesizing module 'Memory' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v:1] Parameter MEMORY_FILE bound to: ../../software/memory/teste_uart_fpga.hex - type: string Parameter MEMORY_SIZE bound to: 2048 - type: integer INFO: [Synth 8-3876] $readmem data file '../../software/memory/teste_uart_fpga.hex' is read successfully [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v:35] INFO: [Synth 8-6155] done synthesizing module 'Memory' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v:1] INFO: [Synth 8-6157] synthesizing module 'BUS' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/bus.v:1] INFO: [Synth 8-6155] done synthesizing module 'BUS' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/bus.v:1] INFO: [Synth 8-6157] synthesizing module 'LEDs' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/leds.v:1] INFO: [Synth 8-6155] done synthesizing module 'LEDs' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/leds.v:1] INFO: [Synth 8-6157] synthesizing module 'UART' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart.v:1] Parameter CLK_FREQ bound to: 50000000 - type: integer Parameter BIT_RATE bound to: 115200 - type: integer Parameter BUFFER_SIZE bound to: 16 - type: integer INFO: [Synth 8-6157] synthesizing module 'FIFO' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/fifo.v:1] Parameter DEPTH bound to: 16 - type: integer Parameter WIDTH bound to: 8 - type: integer INFO: [Synth 8-6155] done synthesizing module 'FIFO' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/fifo.v:1] INFO: [Synth 8-6157] synthesizing module 'uart_tool_rx' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_rx.v:10] Parameter BIT_RATE bound to: 115200 - type: integer Parameter CLK_HZ bound to: 50000000 - type: integer Parameter PAYLOAD_BITS bound to: 8 - type: integer INFO: [Synth 8-6155] done synthesizing module 'uart_tool_rx' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_rx.v:10] INFO: [Synth 8-6157] synthesizing module 'uart_tool_tx' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_tx.v:10] Parameter BIT_RATE bound to: 115200 - type: integer Parameter CLK_HZ bound to: 50000000 - type: integer Parameter PAYLOAD_BITS bound to: 8 - type: integer INFO: [Synth 8-6155] done synthesizing module 'uart_tool_tx' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_tx.v:10] INFO: [Synth 8-6155] done synthesizing module 'UART' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart.v:1] INFO: [Synth 8-6157] synthesizing module 'GPIOS' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v:1] Parameter WIDHT bound to: 8 - type: integer INFO: [Synth 8-6157] synthesizing module 'GPIO' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpio.v:1] INFO: [Synth 8-6155] done synthesizing module 'GPIO' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpio.v:1] INFO: [Synth 8-6157] synthesizing module 'PWM' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/pwm.v:1] INFO: [Synth 8-6155] done synthesizing module 'PWM' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/pwm.v:1] INFO: [Synth 8-155] case statement is not full and has no default [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v:66] INFO: [Synth 8-6155] done synthesizing module 'GPIOS' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v:1] INFO: [Synth 8-6155] done synthesizing module 'Risco_5_SOC' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:1] INFO: [Synth 8-6155] done synthesizing module 'top' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/main.v:1] Info: at iteration #16, type ALL: wirelen solved = 17839, spread = 24598, legal = 25786; time = 0.17s WARNING: [Synth 8-3848] Net mdu_done in module/entity Core does not have driver. [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:55] WARNING: [Synth 8-6014] Unused sequential element tx_fifo_read_reg was removed. [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart.v:160] Info: at iteration #17, type ALL: wirelen solved = 18047, spread = 24350, legal = 25253; time = 0.24s WARNING: [Synth 8-7129] Port address[31] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[30] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[29] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[28] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[27] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[26] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[25] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[24] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[23] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[22] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[21] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[20] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[19] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[18] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[17] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[16] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[15] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[14] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[13] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[12] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[11] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[10] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[9] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[8] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[31] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[30] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[29] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[28] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[27] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[26] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[25] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[24] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[23] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[22] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[21] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[20] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[19] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[18] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[17] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[31] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[30] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[29] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[28] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[27] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[26] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[25] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[24] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[23] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[22] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[21] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[20] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[19] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[18] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[17] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[16] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[15] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[14] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[13] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[12] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[11] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[10] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[9] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[8] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[7] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[6] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[5] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[1] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[0] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[31] in module LEDs is either unconnected or has no load WARNING: [Synth 8-7129] Port address[30] in module LEDs is either unconnected or has no load WARNING: [Synth 8-7129] Port address[29] in module LEDs is either unconnected or has no load WARNING: [Synth 8-7129] Port address[28] in module LEDs is either unconnected or has no load WARNING: [Synth 8-7129] Port address[27] in module LEDs is either unconnected or has no load WARNING: [Synth 8-7129] Port address[26] in module LEDs is either unconnected or has no load WARNING: [Synth 8-7129] Port address[25] in module LEDs is either unconnected or has no load WARNING: [Synth 8-7129] Port address[24] in module LEDs is either unconnected or has no load WARNING: [Synth 8-7129] Port address[23] in module LEDs is either unconnected or has no load WARNING: [Synth 8-7129] Port address[22] in module LEDs is either unconnected or has no load WARNING: [Synth 8-7129] Port address[21] in module LEDs is either unconnected or has no load WARNING: [Synth 8-7129] Port address[20] in module LEDs is either unconnected or has no load WARNING: [Synth 8-7129] Port address[19] in module LEDs is either unconnected or has no load WARNING: [Synth 8-7129] Port address[18] in module LEDs is either unconnected or has no load WARNING: [Synth 8-7129] Port address[17] in module LEDs is either unconnected or has no load WARNING: [Synth 8-7129] Port address[16] in module LEDs is either unconnected or has no load WARNING: [Synth 8-7129] Port address[15] in module LEDs is either unconnected or has no load WARNING: [Synth 8-7129] Port address[14] in module LEDs is either unconnected or has no load WARNING: [Synth 8-7129] Port address[13] in module LEDs is either unconnected or has no load WARNING: [Synth 8-7129] Port address[12] in module LEDs is either unconnected or has no load WARNING: [Synth 8-7129] Port address[11] in module LEDs is either unconnected or has no load WARNING: [Synth 8-7129] Port address[10] in module LEDs is either unconnected or has no load WARNING: [Synth 8-7129] Port address[9] in module LEDs is either unconnected or has no load WARNING: [Synth 8-7129] Port address[8] in module LEDs is either unconnected or has no load WARNING: [Synth 8-7129] Port address[7] in module LEDs is either unconnected or has no load WARNING: [Synth 8-7129] Port address[6] in module LEDs is either unconnected or has no load WARNING: [Synth 8-7129] Port address[5] in module LEDs is either unconnected or has no load WARNING: [Synth 8-7129] Port address[4] in module LEDs is either unconnected or has no load WARNING: [Synth 8-7129] Port address[3] in module LEDs is either unconnected or has no load WARNING: [Synth 8-7129] Port address[2] in module LEDs is either unconnected or has no load WARNING: [Synth 8-7129] Port address[1] in module LEDs is either unconnected or has no load WARNING: [Synth 8-7129] Port address[0] in module LEDs is either unconnected or has no load INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2117.723 ; gain = 492.684 ; free physical = 645 ; free virtual = 24187 --------------------------------------------------------------------------------- Info: at iteration #18, type ALL: wirelen solved = 18227, spread = 24532, legal = 25567; time = 0.24s --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2135.535 ; gain = 510.496 ; free physical = 637 ; free virtual = 24179 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2135.535 ; gain = 510.496 ; free physical = 637 ; free virtual = 24179 --------------------------------------------------------------------------------- Info: at iteration #19, type ALL: wirelen solved = 18861, spread = 24596, legal = 25614; time = 0.22s Netlist sorting complete. Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2135.535 ; gain = 0.000 ; free physical = 644 ; free virtual = 24187 Info: at iteration #20, type ALL: wirelen solved = 18795, spread = 24577, legal = 25624; time = 0.17s Info: at iteration #21, type ALL: wirelen solved = 19170, spread = 24419, legal = 25525; time = 0.16s Info: at iteration #22, type ALL: wirelen solved = 19303, spread = 24269, legal = 25683; time = 0.16s Info: HeAP Placer Time: 7.20s Info: of which solving equations: 4.54s Info: of which spreading cells: 0.50s Info: of which strict legalisation: 0.17s Info: Running simulated annealing placer for refinement. Info: at iteration #1: temp = 0.000000, timing cost = 4313, wirelen = 25253 INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine Parsing XDC File [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc] Finished Parsing XDC File [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc] INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Completed Processing XDC Constraints Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2283.285 ; gain = 0.000 ; free physical = 579 ; free virtual = 24122 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2283.320 ; gain = 0.000 ; free physical = 583 ; free virtual = 24126 Info: at iteration #5: temp = 0.000000, timing cost = 5981, wirelen = 22882 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 2283.320 ; gain = 658.281 ; free physical = 560 ; free virtual = 24105 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7a100tcsg324-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 2283.320 ; gain = 658.281 ; free physical = 559 ; free virtual = 24104 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 2283.320 ; gain = 658.281 ; free physical = 557 ; free virtual = 24102 --------------------------------------------------------------------------------- INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'ResetBootSystem' INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'Control_Unit' INFO: [Synth 8-802] inferred FSM for state register 'fsm_state_reg' in module 'uart_tool_rx' INFO: [Synth 8-802] inferred FSM for state register 'fsm_state_reg' in module 'uart_tool_tx' INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'UART' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- RESET_COUNTER | 00 | 01 IDLE | 01 | 10 INIT | 10 | 00 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'ResetBootSystem' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- FETCH | 00000000000000000000000000000000000000000000001 | 000000 VALIDATE_FETCH | 00000000000000000000000000000000000000000000010 | 101110 DECODE | 00000000000000000000000000000000000000000000100 | 000001 MEMADR | 00000000000000000000000000000000000000000001000 | 000010 MEMREAD_UNALIGNED | 00000000000000000000000000000000000000000010000 | 010110 LOAD_FIRST_BLOCK | 00000000000000000000000000000000000000000100000 | 010000 SAVE_FIRST_BLOCK | 00000000000000000000000000000000000000001000000 | 010001 CALC_NEXT_ADDRESS | 00000000000000000000000000000000000000010000000 | 010010 READ_SECOND_BLOCK | 00000000000000000000000000000000000000100000000 | 010011 LOAD_SECOND_BLOCK | 00000000000000000000000000000000000001000000000 | 010100 MERGE_BLOCKS | 00000000000000000000000000000000000010000000000 | 010101 FILTER_ALU_WB | 00000000000000000000000000000000000100000000000 | 010111 MEMREAD | 00000000000000000000000000000000001000000000000 | 000011 MEMWB | 00000000000000000000000000000000010000000000000 | 000100 MEMWRITE_UNALIGNED | 00000000000000000000000000000000100000000000000 | 011000 GEN_FIRST_BLOCK_PART_1 | 00000000000000000000000000000001000000000000000 | 011001 GEN_FIRST_BLOCK_PART_2 | 00000000000000000000000000000010000000000000000 | 011010 GEN_SECOND_BLOCK_PART_1 | 00000000000000000000000000000100000000000000000 | 011011 GEN_SECOND_BLOCK_PART_2 | 00000000000000000000000000001000000000000000000 | 011100 MERGE_WRITE_BLOCKS | 00000000000000000000000000010000000000000000000 | 011101 SWAP_VALUE_DIRECTION | 00000000000000000000000000100000000000000000000 | 011110 CLEAR_VALUE_HALF_BYTE_ONE_BLOCK | 00000000000000000000000001000000000000000000000 | 100010 CLEAR_VALUE_HALF_BYTE_ONE_BLOCK_2 | 00000000000000000000000010000000000000000000000 | 100011 CLEAR_VALUE_HALF_BYTE_ONE_BLOCK_3 | 00000000000000000000000100000000000000000000000 | 100100 CLEAR_VALUE | 00000000000000000000001000000000000000000000000 | 011111 MERGE_WRITE_VALUE_1 | 00000000000000000000010000000000000000000000000 | 100000 WRITE_VALUE_1 | 00000000000000000000100000000000000000000000000 | 100001 CALC_SECOND_BLOCK_ADDRESS_TO_WRITE | 00000000000000000001000000000000000000000000000 | 100101 READ_SECOND_BLOCK_TO_WRITE | 00000000000000000010000000000000000000000000000 | 100110 LOAD_SECOND_BLOCK_TO_WRITE | 00000000000000000100000000000000000000000000000 | 100111 LOAD_SECOND_BLOCK_TO_WRITE_2 | 00000000000000001000000000000000000000000000000 | 101000 SWAP_VALUE_DIRECTION_2 | 00000000000000010000000000000000000000000000000 | 101001 CLEAR_VALUE_PART_2 | 00000000000000100000000000000000000000000000000 | 101010 CLEAR_VALUE_PART_2_1 | 00000000000001000000000000000000000000000000000 | 101011 MERGE_WRITE_VALUE_2 | 00000000000010000000000000000000000000000000000 | 101100 WRITE_VALUE_2 | 00000000000100000000000000000000000000000000000 | 101101 MEMWRITE | 00000000001000000000000000000000000000000000000 | 000101 EXECUTER | 00000000010000000000000000000000000000000000000 | 000110 EXECUTEI | 00000000100000000000000000000000000000000000000 | 001000 JAL | 00000001000000000000000000000000000000000000000 | 001001 BRANCH | 00000010000000000000000000000000000000000000000 | 001010 AUIPC | 00000100000000000000000000000000000000000000000 | 001100 LUI | 00001000000000000000000000000000000000000000000 | 001101 JALR_PC | 00010000000000000000000000000000000000000000000 | 001110 JALR | 00100000000000000000000000000000000000000000000 | 001011 ALUWB | 01000000000000000000000000000000000000000000000 | 000111 EXECUTECSR | 10000000000000000000000000000000000000000000000 | 001111 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'Control_Unit' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- FSM_IDLE | 00 | 000 FSM_START | 11 | 001 FSM_RECV | 10 | 010 FSM_STOP | 01 | 011 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'fsm_state_reg' using encoding 'sequential' in module 'uart_tool_rx' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- FSM_IDLE | 00 | 000 FSM_START | 11 | 001 FSM_SEND | 10 | 010 FSM_STOP | 01 | 011 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'fsm_state_reg' using encoding 'sequential' in module 'uart_tool_tx' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- IDLE | 0000 | 0000 COPY_WRITE_BUFFER | 0001 | 0100 WRITE | 0010 | 0010 READ | 0011 | 0001 READ_RX_FIFO_EMPTY | 0100 | 0110 READ_TX_FIFO_EMPTY | 0101 | 0111 READ_RX_FIFO_FULL | 0110 | 1000 READ_TX_FIFO_FULL | 0111 | 1001 WB | 1000 | 0101 FINISH | 1001 | 0011 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'UART' --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 2283.320 ; gain = 658.281 ; free physical = 518 ; free virtual = 24065 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Adders : 2 Input 32 Bit Adders := 1 3 Input 32 Bit Adders := 1 2 Input 10 Bit Adders := 2 2 Input 6 Bit Adders := 6 2 Input 5 Bit Adders := 1 2 Input 4 Bit Adders := 2 2 Input 3 Bit Adders := 2 2 Input 2 Bit Adders := 1 +---XORs : 2 Input 32 Bit XORs := 1 +---XORs : 2 Bit Wide XORs := 1 +---Registers : 64 Bit Registers := 2 32 Bit Registers := 51 16 Bit Registers := 4 10 Bit Registers := 2 8 Bit Registers := 8 6 Bit Registers := 5 4 Bit Registers := 2 3 Bit Registers := 1 2 Bit Registers := 1 1 Bit Registers := 15 +---RAMs : 16K Bit (512 X 32 bit) RAMs := 1 128 Bit (16 X 8 bit) RAMs := 2 +---Muxes : 4 Input 64 Bit Muxes := 1 47 Input 47 Bit Muxes := 1 2 Input 47 Bit Muxes := 17 11 Input 47 Bit Muxes := 1 2 Input 32 Bit Muxes := 8 8 Input 32 Bit Muxes := 1 15 Input 32 Bit Muxes := 1 6 Input 32 Bit Muxes := 1 4 Input 32 Bit Muxes := 1 10 Input 32 Bit Muxes := 2 2 Input 8 Bit Muxes := 3 3 Input 6 Bit Muxes := 1 2 Input 6 Bit Muxes := 4 2 Input 5 Bit Muxes := 1 47 Input 4 Bit Muxes := 1 9 Input 4 Bit Muxes := 1 10 Input 4 Bit Muxes := 2 23 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 3 6 Input 4 Bit Muxes := 1 5 Input 3 Bit Muxes := 1 2 Input 3 Bit Muxes := 3 4 Input 3 Bit Muxes := 2 47 Input 3 Bit Muxes := 3 10 Input 3 Bit Muxes := 2 3 Input 2 Bit Muxes := 1 2 Input 2 Bit Muxes := 16 47 Input 2 Bit Muxes := 2 4 Input 2 Bit Muxes := 4 3 Input 1 Bit Muxes := 6 2 Input 1 Bit Muxes := 77 47 Input 1 Bit Muxes := 12 6 Input 1 Bit Muxes := 12 4 Input 1 Bit Muxes := 2 10 Input 1 Bit Muxes := 8 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 240 (col length:80) BRAMs: 270 (col length: RAMB18 80 RAMB36 40) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Info: at iteration #10: temp = 0.000000, timing cost = 6559, wirelen = 22156 [80%] Tech-Mapping Phase 3 completed [90%] Tech-Mapping Phase 4 completed WARN (NL0002) : The module "ALU_Control" instantiated to "ALU_Control" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":238) WARN (NL0002) : The module "Immediate_Generator" instantiated to "Immediate_Generator" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":255) WARN (NL0002) : The module "MUX" instantiated to "PCSourceMUX" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":178) WARN (NL0002) : The module "GPIO" instantiated to "Gpios[0]" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":43) WARN (NL0002) : The module "GPIO" instantiated to "Gpios[1]" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":43) WARN (NL0002) : The module "GPIO" instantiated to "Gpios[2]" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":43) WARN (NL0002) : The module "GPIO" instantiated to "Gpios[3]" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":43) WARN (NL0002) : The module "GPIO" instantiated to "Gpios[4]" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":43) [95%] Generate netlist file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/gwsynthesis/project.vg" completed [100%] Generate report file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/gwsynthesis/project_syn.rpt.html" completed GowinSynthesis finish Reading netlist file: "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/gwsynthesis/project.vg" Parsing netlist file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/gwsynthesis/project.vg" completed Processing netlist completed Reading constraint file: "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/pinout.cst" Physical Constraint parsed completed Running placement...... --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- WARNING: [Synth 8-7080] Parallel synthesis criteria is not met INFO: [Synth 8-6851] RAM (SOC/Memory/memory_reg) has partial Byte Wide Write Enable pattern, however no output register found in fanout of RAM. Recommended to use supported Byte Wide Write Enable template. Info: at iteration #15: temp = 0.000000, timing cost = 6149, wirelen = 21883 [10%] Placement Phase 0 completed Info: at iteration #20: temp = 0.000000, timing cost = 5628, wirelen = 21807 [20%] Placement Phase 1 completed Info: at iteration #23: temp = 0.000000, timing cost = 5598, wirelen = 21792 Info: SA placement time 18.99s Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 41.75 MHz (PASS at 25.00 MHz) Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 8.01 ns Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 10.20 ns Info: Slack histogram: Info: legend: * represents 53 endpoint(s) Info: + represents [1,53) endpoint(s) Info: [ 16049, 17209) |+ Info: [ 17209, 18369) |+ Info: [ 18369, 19529) |+ Info: [ 19529, 20689) |*+ Info: [ 20689, 21849) |*****+ Info: [ 21849, 23009) |*******+ Info: [ 23009, 24169) |*********+ Info: [ 24169, 25329) |***********+ Info: [ 25329, 26489) |*****+ Info: [ 26489, 27649) |***+ Info: [ 27649, 28809) |*****+ Info: [ 28809, 29969) |*****************************+ Info: [ 29969, 31129) |************************************************************ Info: [ 31129, 32289) |************+ Info: [ 32289, 33449) |***+ Info: [ 33449, 34609) |********+ Info: [ 34609, 35769) |******+ Info: [ 35769, 36929) |*****+ Info: [ 36929, 38089) |*******+ Info: [ 38089, 39249) |*****+ Info: Checksum: 0x41178a46 Info: Routing globals... Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0 Info: Routing.. Info: Setting up routing queue. Info: Routing 32648 arcs. Info: | (re-)routed arcs | delta | remaining| time spent | Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)| Info: 1000 | 420 579 | 420 579 | 32179| 0.68 0.68| Info: 2000 | 894 1105 | 474 526 | 31780| 0.31 0.99| Info: 3000 | 1354 1645 | 460 540 | 31323| 0.26 1.25| Info: 4000 | 1829 2170 | 475 525 | 30862| 0.26 1.51| Info: 5000 | 2227 2772 | 398 602 | 30399| 0.26 1.77| Info: 6000 | 2709 3290 | 482 518 | 29995| 0.25 2.02| Info: 7000 | 3030 3969 | 321 679 | 29499| 0.26 2.28| Info: 8000 | 3387 4612 | 357 643 | 29001| 0.26 2.54| Info: 9000 | 3793 5206 | 406 594 | 28495| 0.24 2.78| --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:30 ; elapsed = 00:00:30 . Memory (MB): peak = 2283.320 ; gain = 658.281 ; free physical = 388 ; free virtual = 23941 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- Distributed RAM: Preliminary Mapping Report (see note below) +------------+-----------------------------+-----------+----------------------+-----------------+ |Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | +------------+-----------------------------+-----------+----------------------+-----------------+ |top | SOC/Memory/memory_reg | Implied | 512 x 32 | RAM256X1S x 64 | |top | SOC/Uart/RX_FIFO/memory_reg | Implied | 16 x 8 | RAM32M x 2 | |top | SOC/Uart/TX_FIFO/memory_reg | Implied | 16 x 8 | RAM32M x 2 | +------------+-----------------------------+-----------+----------------------+-----------------+ Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once. --------------------------------------------------------------------------------- Finished ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- Info: 10000 | 4078 5921 | 285 715 | 27847| 0.25 3.03| Info: 11000 | 4403 6596 | 325 675 | 27400| 0.25 3.28| Info: 12000 | 4732 7267 | 329 671 | 26820| 0.25 3.53| Info: 13000 | 5023 7976 | 291 709 | 26328| 0.26 3.79| Info: 14000 | 5348 8651 | 325 675 | 25913| 0.29 4.08| Info: 15000 | 5611 9388 | 263 737 | 25264| 0.27 4.35| Info: 16000 | 5770 10229 | 159 841 | 24912| 0.24 4.59| Info: 17000 | 6033 10966 | 263 737 | 24607| 0.26 4.85| Info: 18000 | 6301 11698 | 268 732 | 24068| 0.29 5.14| Info: 19000 | 6611 12388 | 310 690 | 23553| 0.26 5.39| Info: 20000 | 6937 13062 | 326 674 | 22973| 0.27 5.67| Info: 21000 | 7042 13957 | 105 895 | 22909| 0.26 5.93| Info: 22000 | 7364 14635 | 322 678 | 22394| 0.27 6.20| Info: 23000 | 7697 15302 | 333 667 | 21850| 0.30 6.50| Info: 24000 | 8050 15949 | 353 647 | 21460| 0.30 6.80| Info: 25000 | 8366 16633 | 316 684 | 20945| 0.31 7.12| Info: 26000 | 8650 17349 | 284 716 | 20352| 0.31 7.43| Info: 27000 | 8935 18064 | 285 715 | 19877| 0.30 7.73| --------------------------------------------------------------------------------- Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:35 ; elapsed = 00:00:35 . Memory (MB): peak = 2283.320 ; gain = 658.281 ; free physical = 385 ; free virtual = 23939 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- Info: 28000 | 9307 18692 | 372 628 | 19359| 0.33 8.06| Info: 29000 | 9565 19434 | 258 742 | 18751| 0.32 8.38| Info: 30000 | 9833 20166 | 268 732 | 18204| 0.33 8.71| Info: 31000 | 10154 20845 | 321 679 | 17896| 0.37 9.08| Info: 32000 | 10489 21510 | 335 665 | 17386| 0.37 9.45| Info: 33000 | 10730 22269 | 241 759 | 16902| 0.34 9.79| Info: 34000 | 11015 22984 | 285 715 | 16364| 0.33 10.12| Info: 35000 | 11391 23608 | 376 624 | 15880| 0.35 10.47| --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:38 ; elapsed = 00:00:38 . Memory (MB): peak = 2283.320 ; gain = 658.281 ; free physical = 384 ; free virtual = 23937 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- Distributed RAM: Final Mapping Report +------------+-----------------------------+-----------+----------------------+-----------------+ |Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | +------------+-----------------------------+-----------+----------------------+-----------------+ |top | SOC/Memory/memory_reg | Implied | 512 x 32 | RAM256X1S x 64 | |top | SOC/Uart/RX_FIFO/memory_reg | Implied | 16 x 8 | RAM32M x 2 | |top | SOC/Uart/TX_FIFO/memory_reg | Implied | 16 x 8 | RAM32M x 2 | +------------+-----------------------------+-----------+----------------------+-----------------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Info: 36000 | 11692 24307 | 301 699 | 15487| 0.34 10.82| Info: 37000 | 12021 24978 | 329 671 | 14969| 0.36 11.18| Info: 38000 | 12417 25582 | 396 604 | 14586| 0.33 11.51| Info: 39000 | 12922 26077 | 505 495 | 14285| 0.37 11.88| Info: 40000 | 13358 26641 | 436 564 | 13882| 0.34 12.21| Info: 41000 | 13800 27199 | 442 558 | 13502| 0.34 12.55| Info: 42000 | 14176 27823 | 376 624 | 13067| 0.35 12.90| --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 2283.320 ; gain = 658.281 ; free physical = 385 ; free virtual = 23938 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Info: 43000 | 14547 28452 | 371 629 | 12611| 0.36 13.26| Info: 44000 | 14850 29123 | 303 671 | 12325| 0.34 13.60| Info: 45000 | 15073 29756 | 223 633 | 11661| 0.25 13.85| Info: 46000 | 15319 30322 | 246 566 | 10984| 0.21 14.07| Info: 47000 | 15586 30865 | 267 543 | 10306| 0.20 14.27| Info: 48000 | 15873 31411 | 287 546 | 9685| 0.26 14.53| Info: 49000 | 16231 32002 | 358 591 | 9383| 0.42 14.95| Info: 50000 | 16557 32646 | 326 644 | 9006| 0.39 15.34| [30%] Placement Phase 2 completed Info: 51000 | 16922 33244 | 365 598 | 8440| 0.30 15.64| Info: 52000 | 17228 33892 | 306 648 | 7815| 0.25 15.89| Info: 53000 | 17526 34550 | 298 658 | 7195| 0.26 16.15| Info: 54000 | 17995 35058 | 469 508 | 6741| 0.34 16.48| Info: 55000 | 18338 35695 | 343 637 | 6130| 0.30 16.78| Info: 56000 | 18396 36625 | 58 930 | 5214| 0.14 16.93| Info: 57000 | 18410 37610 | 14 985 | 4230| 0.10 17.03| Info: 58000 | 18437 38580 | 27 970 | 3259| 0.10 17.13| --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:45 ; elapsed = 00:00:45 . Memory (MB): peak = 2283.320 ; gain = 658.281 ; free physical = 332 ; free virtual = 23885 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:45 ; elapsed = 00:00:45 . Memory (MB): peak = 2283.320 ; gain = 658.281 ; free physical = 332 ; free virtual = 23885 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- Info: 59000 | 18508 39472 | 71 892 | 2338| 0.20 17.33| --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:45 ; elapsed = 00:00:45 . Memory (MB): peak = 2283.320 ; gain = 658.281 ; free physical = 310 ; free virtual = 23864 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:45 ; elapsed = 00:00:45 . Memory (MB): peak = 2283.320 ; gain = 658.281 ; free physical = 329 ; free virtual = 23882 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:45 ; elapsed = 00:00:45 . Memory (MB): peak = 2283.320 ; gain = 658.281 ; free physical = 324 ; free virtual = 23877 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:45 ; elapsed = 00:00:45 . Memory (MB): peak = 2283.320 ; gain = 658.281 ; free physical = 323 ; free virtual = 23876 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+----------+------+ | |Cell |Count | +------+----------+------+ |1 |BUFG | 2| |2 |CARRY4 | 71| |3 |LUT1 | 19| |4 |LUT2 | 185| |5 |LUT3 | 258| |6 |LUT4 | 308| |7 |LUT5 | 260| |8 |LUT6 | 1515| |9 |MUXF7 | 458| |10 |MUXF8 | 15| |11 |RAM256X1S | 64| |12 |RAM32M | 2| |13 |RAM32X1D | 4| |14 |FDRE | 2091| |15 |FDSE | 4| |16 |IBUF | 3| |17 |IOBUF | 8| |18 |OBUF | 9| +------+----------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:45 ; elapsed = 00:00:45 . Memory (MB): peak = 2283.320 ; gain = 658.281 ; free physical = 322 ; free virtual = 23875 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 63 warnings. Info: 60000 | 18652 40255 | 144 783 | 1492| 0.30 17.63| Synthesis Optimization Runtime : Time (s): cpu = 00:00:43 ; elapsed = 00:00:43 . Memory (MB): peak = 2283.320 ; gain = 510.496 ; free physical = 321 ; free virtual = 23875 Synthesis Optimization Complete : Time (s): cpu = 00:00:45 ; elapsed = 00:00:45 . Memory (MB): peak = 2283.320 ; gain = 658.281 ; free physical = 320 ; free virtual = 23874 INFO: [Project 1-571] Translating synthesized netlist Info: 61000 | 18745 41099 | 93 844 | 604| 0.35 17.98| Info: 61620 | 18759 41441 | 14 342 | 0| 0.15 18.13| Info: Routing complete. Info: Router1 time 18.13s Info: Checksum: 0xcbf7c795 Netlist sorting complete. Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2283.320 ; gain = 0.000 ; free physical = 602 ; free virtual = 24155 INFO: [Netlist 29-17] Analyzing 622 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge): Info: curr total Info: 0.5 0.5 Source SOC.Core.Control_Unit.state_TRELLIS_FF_Q_3.Q Info: 1.8 2.4 Net SOC.Leds.write_LUT4_Z_C_LUT4_Z_B[1] (20,33) -> (23,42) Info: Sink SOC.Core.Control_Unit.nextstate_LUT4_Z_4_B_LUT4_D_B_LUT4_Z.B Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.2 2.6 Source SOC.Core.Control_Unit.nextstate_LUT4_Z_4_B_LUT4_D_B_LUT4_Z.F Info: 0.6 3.2 Net SOC.Core.Control_Unit.nextstate_LUT4_Z_4_B[1] (23,42) -> (23,42) Info: Sink SOC.Core.Control_Unit.nextstate_LUT4_Z_4_B_LUT4_D_B_LUT4_D.D Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.2 3.5 Source SOC.Core.Control_Unit.nextstate_LUT4_Z_4_B_LUT4_D_B_LUT4_D.F Info: 0.8 4.2 Net SOC.Core.Control_Unit.nextstate_LUT4_Z_4_B_LUT4_D_B_LUT4_D_Z[3] (23,42) -> (22,41) Info: Sink SOC.Core.Control_Unit.nextstate_LUT4_Z_4_B_LUT4_D_B_LUT4_D_Z_LUT4_C_1.D Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.2 4.5 Source SOC.Core.Control_Unit.nextstate_LUT4_Z_4_B_LUT4_D_B_LUT4_D_Z_LUT4_C_1.F Info: 0.4 4.9 Net SOC.Leds.write_LUT4_Z_C[1] (22,41) -> (22,41) Info: Sink SOC.Leds.write_LUT4_Z_C_LUT4_C.D Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.2 5.1 Source SOC.Leds.write_LUT4_Z_C_LUT4_C.F Info: 1.3 6.4 Net SOC.Leds.write_LUT4_Z_C_LUT4_C_Z[2] (22,41) -> (19,44) Info: Sink SOC.GPIOS.address_LUT4_Z.D Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.2 6.6 Source SOC.GPIOS.address_LUT4_Z.F Info: 2.3 8.9 Net SOC.address[5] (19,44) -> (9,51) Info: Sink SOC.Memory.memory.0.81$DPRAM_COMB3.A Info: Defined in: Info: Risco-5/src/peripheral/soc.v:23.5-23.18 Info: 0.2 9.2 Source SOC.Memory.memory.0.81$DPRAM_COMB3.F Info: 0.8 10.0 Net SOC.Memory.memory.0.73_DO[0] (9,51) -> (10,51) Info: Sink SOC.Memory.memory.0.65_DO_LUT4_Z_2.A Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.2 10.3 Source SOC.Memory.memory.0.65_DO_LUT4_Z_2.F Info: 0.7 11.0 Net SOC.Memory.memory.0.65_DO[4] (10,51) -> (10,50) Info: Sink SOC.Memory.memory.0.193_DO_LUT4_A_Z_PFUMX_Z_BLUT_LUT4_Z.M Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.3 11.2 Source SOC.Memory.memory.0.193_DO_LUT4_A_Z_PFUMX_Z_BLUT_LUT4_Z.OFX Info: 0.4 11.7 Net SOC.Memory.memory.0.193_DO_LUT4_A_Z[3] (10,50) -> (12,50) Info: Sink SOC.Memory.memory.0.225_DO_LUT4_A_Z_LUT4_Z_1.D Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.2 11.9 Source SOC.Memory.memory.0.225_DO_LUT4_A_Z_LUT4_Z_1.F Info: 1.3 13.2 Net SOC.Memory.memory.0.225_DO_LUT4_A_Z[4] (12,50) -> (15,47) Info: Sink SOC.GPIOS.Gpios[0].data_in_LUT4_C_Z_LUT4_Z_1_D_LUT4_Z_C_LUT4_B_Z_PFUMX_Z_BLUT_LUT4_Z.M Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.3 13.4 Source SOC.GPIOS.Gpios[0].data_in_LUT4_C_Z_LUT4_Z_1_D_LUT4_Z_C_LUT4_B_Z_PFUMX_Z_BLUT_LUT4_Z.OFX Info: 1.0 14.4 Net SOC.Core.read_data_PFUMX_Z_BLUT_LUT4_Z_D[4] (15,47) -> (16,44) Info: Sink SOC.Memory.memory.0.67_DO_2_LUT4_A_Z_PFUMX_C0_Z_PFUMX_Z_1_BLUT_LUT4_Z.M Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.3 14.6 Source SOC.Memory.memory.0.67_DO_2_LUT4_A_Z_PFUMX_C0_Z_PFUMX_Z_1_BLUT_LUT4_Z.OFX Info: 2.3 16.9 Net SOC.Core.read_data_LUT4_Z_10_B[2] (16,44) -> (32,36) Info: Sink SOC.Core.read_data_LUT4_Z_22.B Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.2 17.2 Source SOC.Core.read_data_LUT4_Z_22.F Info: 0.8 17.9 Net SOC.read_data[26] (32,36) -> (32,35) Info: Sink SOC.Core.instruction_register_TRELLIS_FF_Q_5.M Info: Defined in: Info: Risco-5/src/peripheral/soc.v:22.34-22.43 Info: 0.0 17.9 Setup SOC.Core.instruction_register_TRELLIS_FF_Q_5.M Info: 3.4 ns logic, 14.5 ns routing Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN': Info: curr total Info: 0.0 0.0 Source gpios[5]$tr_io.O Info: 2.2 2.2 Net gpios[5]$TRELLIS_IO_IN (9,71) -> (9,54) Info: Sink SOC.GPIOS.Gpios[5].data_in_LUT4_B.A Info: Defined in: Info: Risco-5/fpga/ecp5/main.v:7.16-7.21 Info: 0.2 2.5 Source SOC.GPIOS.Gpios[5].data_in_LUT4_B.F Info: 1.4 3.9 Net SOC.GPIOS.Gpios[5].data_in_LUT4_B_Z[4] (9,54) -> (10,44) Info: Sink SOC.GPIOS.Gpios[5].data_in_LUT4_B_Z_PFUMX_C0_BLUT_LUT4_Z.M Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.3 4.1 Source SOC.GPIOS.Gpios[5].data_in_LUT4_B_Z_PFUMX_C0_BLUT_LUT4_Z.OFX Info: 1.0 5.1 Net SOC.GPIOS.Gpios[5].data_in_LUT4_B_Z_PFUMX_C0_Z[1] (10,44) -> (12,44) Info: Sink SOC.Core.read_data_LUT4_Z_5.B Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.2 5.3 Source SOC.Core.read_data_LUT4_Z_5.F Info: 1.4 6.7 Net SOC.read_data[5] (12,44) -> (13,38) Info: Sink SOC.Core.instruction_register_TRELLIS_FF_Q_25.M Info: Defined in: Info: Risco-5/src/peripheral/soc.v:22.34-22.43 Info: 0.0 6.7 Setup SOC.Core.instruction_register_TRELLIS_FF_Q_25.M Info: 0.7 ns logic, 6.0 ns routing Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>': Info: curr total Info: 0.5 0.5 Source SOC.Leds.data_TRELLIS_FF_Q_24.Q Info: 3.1 3.6 Net SOC.Leds.data[7] (25,41) -> (56,26) Info: Sink led_LUT4_Z_2.D Info: Defined in: Info: Risco-5/src/peripheral/leds.v:15.12-15.16 Info: 0.2 3.9 Source led_LUT4_Z_2.F Info: 2.7 6.6 Net led[7]$TRELLIS_IO_OUT (56,26) -> (90,20) Info: Sink led[7]$tr_io.I Info: Defined in: Info: Risco-5/fpga/ecp5/main.v:6.22-6.25 Info: 0.8 ns logic, 5.8 ns routing Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 55.79 MHz (PASS at 25.00 MHz) Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 6.69 ns Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 6.56 ns Info: Slack histogram: Info: legend: * represents 48 endpoint(s) Info: + represents [1,48) endpoint(s) Info: [ 22076, 22925) |+ Info: [ 22925, 23774) |*+ Info: [ 23774, 24623) |*********+ Info: [ 24623, 25472) |***+ Info: [ 25472, 26321) |*+ Info: [ 26321, 27170) |*****+ Info: [ 27170, 28019) |***************+ Info: [ 28019, 28868) |***********+ Info: [ 28868, 29717) |*+ Info: [ 29717, 30566) |*******+ Info: [ 30566, 31415) |************************************+ Info: [ 31415, 32264) |************************************************************ Info: [ 32264, 33113) |*********+ Info: [ 33113, 33962) |****+ Info: [ 33962, 34811) |***+ Info: [ 34811, 35660) |***+ Info: [ 35660, 36509) |********+ Info: [ 36509, 37358) |*******+ Info: [ 37358, 38207) |*********+ Info: [ 38207, 39056) |*****+ Parsing XDC File [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc] Finished Parsing XDC File [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc] INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2347.316 ; gain = 0.000 ; free physical = 536 ; free virtual = 24106 INFO: [Project 1-111] Unisim Transformation Summary: A total of 78 instances were transformed. IOBUF => IOBUF (IBUF, OBUFT): 8 instances RAM256X1S => RAM256X1S (MUXF7(x2), MUXF8, RAMS64E(x4)): 64 instances RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 2 instances RAM32X1D => RAM32X1D (RAMD32(x2)): 4 instances Info: Program finished normally. Synth Design complete | Checksum: 4323e98b INFO: [Common 17-83] Releasing license: Synthesis 79 Infos, 112 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:55 ; elapsed = 00:00:52 . Memory (MB): peak = 2347.352 ; gain = 1029.289 ; free physical = 870 ; free virtual = 24443 INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 2024.216; main = 1745.663; forked = 422.461 INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3220.926; main = 2347.320; forked = 969.652 # opt_design Command: opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' Running DRC as a precondition to command opt_design Starting DRC Task [Pipeline] } INFO: [DRC 23-27] Running DRC with 8 threads [Pipeline] // stage [Pipeline] stage [Pipeline] { (ECPPACK) INFO: [Project 1-461] DRC finished with 0 Errors INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.7 . Memory (MB): peak = 2411.348 ; gain = 63.996 ; free physical = 863 ; free virtual = 24436 Starting Cache Timing Information Task [Pipeline] sh + /eda/oss-cad-suite/bin/ecppack --compress --input ./build/out.config --bit ./build/out.bit [Pipeline] } [Pipeline] // stage [Pipeline] } [Pipeline] // stage [Pipeline] } INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Cache Timing Information Task | Checksum: 146decbe9 Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2521.160 ; gain = 109.812 ; free physical = 802 ; free virtual = 24376 Starting Logic Optimization Task Phase 1 Initialization Phase 1.1 Core Generation And Design Setup Phase 1.1 Core Generation And Design Setup | Checksum: 146decbe9 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2771.066 ; gain = 0.000 ; free physical = 532 ; free virtual = 24106 Phase 1.2 Setup Constraints And Sort Netlist Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 146decbe9 Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2771.066 ; gain = 0.000 ; free physical = 532 ; free virtual = 24106 Phase 1 Initialization | Checksum: 146decbe9 Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2771.066 ; gain = 0.000 ; free physical = 532 ; free virtual = 24106 Phase 2 Timer Update And Timing Data Collection Phase 2.1 Timer Update Phase 2.1 Timer Update | Checksum: 146decbe9 Time (s): cpu = 00:00:00.18 ; elapsed = 00:00:00.06 . Memory (MB): peak = 2771.066 ; gain = 0.000 ; free physical = 532 ; free virtual = 24106 Phase 2.2 Timing Data Collection Phase 2.2 Timing Data Collection | Checksum: 146decbe9 Time (s): cpu = 00:00:00.19 ; elapsed = 00:00:00.07 . Memory (MB): peak = 2771.066 ; gain = 0.000 ; free physical = 532 ; free virtual = 24106 Phase 2 Timer Update And Timing Data Collection | Checksum: 146decbe9 Time (s): cpu = 00:00:00.19 ; elapsed = 00:00:00.07 . Memory (MB): peak = 2771.066 ; gain = 0.000 ; free physical = 532 ; free virtual = 24106 Phase 3 Retarget INFO: [Opt 31-1566] Pulled 5 inverters resulting in an inversion of 15 pins INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Opt 31-49] Retargeted 0 cell(s). Phase 3 Retarget | Checksum: 1823b20f2 Time (s): cpu = 00:00:00.3 ; elapsed = 00:00:00.15 . Memory (MB): peak = 2771.066 ; gain = 0.000 ; free physical = 532 ; free virtual = 24106 Retarget | Checksum: 1823b20f2 INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 5 cells Phase 4 Constant propagation INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 4 Constant propagation | Checksum: 1823b20f2 Time (s): cpu = 00:00:00.34 ; elapsed = 00:00:00.19 . Memory (MB): peak = 2771.066 ; gain = 0.000 ; free physical = 532 ; free virtual = 24106 Constant propagation | Checksum: 1823b20f2 INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells Phase 5 Sweep Phase 5 Sweep | Checksum: 20fd107b2 Time (s): cpu = 00:00:00.38 ; elapsed = 00:00:00.24 . Memory (MB): peak = 2771.066 ; gain = 0.000 ; free physical = 531 ; free virtual = 24105 Sweep | Checksum: 20fd107b2 INFO: [Opt 31-389] Phase Sweep created 8 cells and removed 0 cells Phase 6 BUFG optimization Phase 6 BUFG optimization | Checksum: 20fd107b2 Time (s): cpu = 00:00:00.47 ; elapsed = 00:00:00.28 . Memory (MB): peak = 2803.082 ; gain = 32.016 ; free physical = 531 ; free virtual = 24105 BUFG optimization | Checksum: 20fd107b2 INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. Phase 7 Shift Register Optimization INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs Phase 7 Shift Register Optimization | Checksum: 20fd107b2 Time (s): cpu = 00:00:00.48 ; elapsed = 00:00:00.29 . Memory (MB): peak = 2803.082 ; gain = 32.016 ; free physical = 531 ; free virtual = 24105 Shift Register Optimization | Checksum: 20fd107b2 INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells Phase 8 Post Processing Netlist Phase 8 Post Processing Netlist | Checksum: 1b2306da5 Time (s): cpu = 00:00:00.49 ; elapsed = 00:00:00.3 . Memory (MB): peak = 2803.082 ; gain = 32.016 ; free physical = 531 ; free virtual = 24105 Post Processing Netlist | Checksum: 1b2306da5 INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells Phase 9 Finalization Phase 9.1 Finalizing Design Cores and Updating Shapes Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 13af42843 Time (s): cpu = 00:00:00.57 ; elapsed = 00:00:00.35 . Memory (MB): peak = 2803.082 ; gain = 32.016 ; free physical = 531 ; free virtual = 24105 Phase 9.2 Verifying Netlist Connectivity Starting Connectivity Check Task Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2803.082 ; gain = 0.000 ; free physical = 531 ; free virtual = 24105 Phase 9.2 Verifying Netlist Connectivity | Checksum: 13af42843 Time (s): cpu = 00:00:00.58 ; elapsed = 00:00:00.36 . Memory (MB): peak = 2803.082 ; gain = 32.016 ; free physical = 531 ; free virtual = 24105 Phase 9 Finalization | Checksum: 13af42843 Time (s): cpu = 00:00:00.58 ; elapsed = 00:00:00.36 . Memory (MB): peak = 2803.082 ; gain = 32.016 ; free physical = 531 ; free virtual = 24105 Opt_design Change Summary ========================= ------------------------------------------------------------------------------------------------------------------------- | Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | ------------------------------------------------------------------------------------------------------------------------- | Retarget | 0 | 5 | 0 | | Constant propagation | 0 | 0 | 0 | | Sweep | 8 | 0 | 0 | | BUFG optimization | 0 | 0 | 0 | | Shift Register Optimization | 0 | 0 | 0 | | Post Processing Netlist | 0 | 0 | 0 | ------------------------------------------------------------------------------------------------------------------------- Ending Logic Optimization Task | Checksum: 13af42843 Time (s): cpu = 00:00:00.58 ; elapsed = 00:00:00.36 . Memory (MB): peak = 2803.082 ; gain = 32.016 ; free physical = 531 ; free virtual = 24105 INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8 Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2803.082 ; gain = 0.000 ; free physical = 531 ; free virtual = 24105 Starting Power Optimization Task INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. Ending Power Optimization Task | Checksum: 13af42843 Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2803.082 ; gain = 0.000 ; free physical = 531 ; free virtual = 24105 Starting Final Cleanup Task Ending Final Cleanup Task | Checksum: 13af42843 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2803.082 ; gain = 0.000 ; free physical = 531 ; free virtual = 24105 Starting Netlist Obfuscation Task Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2803.082 ; gain = 0.000 ; free physical = 531 ; free virtual = 24105 Ending Netlist Obfuscation Task | Checksum: 13af42843 Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2803.082 ; gain = 0.000 ; free physical = 531 ; free virtual = 24105 INFO: [Common 17-83] Releasing license: Implementation 19 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. opt_design completed successfully opt_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 2803.082 ; gain = 455.730 ; free physical = 531 ; free virtual = 24105 # place_design Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' INFO: [Common 17-83] Releasing license: Implementation INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Starting Placer Task Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2835.098 ; gain = 0.000 ; free physical = 528 ; free virtual = 24102 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: c04d5782 Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2835.098 ; gain = 0.000 ; free physical = 528 ; free virtual = 24102 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2835.098 ; gain = 0.000 ; free physical = 528 ; free virtual = 24102 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: bad7e1af Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.79 . Memory (MB): peak = 2835.098 ; gain = 0.000 ; free physical = 531 ; free virtual = 24106 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: bdb759a9 Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2842.125 ; gain = 7.027 ; free physical = 531 ; free virtual = 24105 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: bdb759a9 Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2842.125 ; gain = 7.027 ; free physical = 531 ; free virtual = 24105 Phase 1 Placer Initialization | Checksum: bdb759a9 Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2842.125 ; gain = 7.027 ; free physical = 531 ; free virtual = 24105 Phase 2 Global Placement Phase 2.1 Floorplanning Phase 2.1 Floorplanning | Checksum: d65f425b Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 2842.125 ; gain = 7.027 ; free physical = 528 ; free virtual = 24102 Phase 2.2 Update Timing before SLR Path Opt Phase 2.2 Update Timing before SLR Path Opt | Checksum: 15c583a28 Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 2842.125 ; gain = 7.027 ; free physical = 528 ; free virtual = 24102 Phase 2.3 Post-Processing in Floorplanning Phase 2.3 Post-Processing in Floorplanning | Checksum: 15c583a28 Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 2842.125 ; gain = 7.027 ; free physical = 528 ; free virtual = 24102 Phase 2.4 Global Placement Core Phase 2.4.1 UpdateTiming Before Physical Synthesis Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 13270fcb8 Time (s): cpu = 00:00:15 ; elapsed = 00:00:04 . Memory (MB): peak = 2842.125 ; gain = 7.027 ; free physical = 523 ; free virtual = 24097 Phase 2.4.2 Physical Synthesis In Placer INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 89 LUT instances to create LUTNM shape INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0 INFO: [Physopt 32-1138] End 1 Pass. Optimized 34 nets or LUTs. Breaked 0 LUT, combined 34 existing LUTs and moved 0 existing LUT INFO: [Physopt 32-65] No nets found for high-fanout optimization. INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed. INFO: [Physopt 32-670] No setup violation found. Shift Register to Pipeline Optimization was not performed. INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed. INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed. INFO: [Physopt 32-670] No setup violation found. URAM Register Optimization was not performed. INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2842.125 ; gain = 0.000 ; free physical = 523 ; free virtual = 24097 Summary of Physical Synthesis Optimizations ============================================ ----------------------------------------------------------------------------------------------------------------------------------------------------------- | Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ----------------------------------------------------------------------------------------------------------------------------------------------------------- | LUT Combining | 0 | 34 | 34 | 0 | 1 | 00:00:00 | | Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | Shift Register to Pipeline | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | URAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Total | 0 | 34 | 34 | 0 | 4 | 00:00:00 | ----------------------------------------------------------------------------------------------------------------------------------------------------------- Phase 2.4.2 Physical Synthesis In Placer | Checksum: 1456691e6 Time (s): cpu = 00:00:15 ; elapsed = 00:00:05 . Memory (MB): peak = 2842.125 ; gain = 7.027 ; free physical = 523 ; free virtual = 24097 Phase 2.4 Global Placement Core | Checksum: 11d0214de Time (s): cpu = 00:00:20 ; elapsed = 00:00:05 . Memory (MB): peak = 2842.125 ; gain = 7.027 ; free physical = 523 ; free virtual = 24097 Phase 2 Global Placement | Checksum: 11d0214de Time (s): cpu = 00:00:20 ; elapsed = 00:00:05 . Memory (MB): peak = 2842.125 ; gain = 7.027 ; free physical = 523 ; free virtual = 24097 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 1a95a0775 Time (s): cpu = 00:00:20 ; elapsed = 00:00:05 . Memory (MB): peak = 2842.125 ; gain = 7.027 ; free physical = 523 ; free virtual = 24097 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 123e0a448 Time (s): cpu = 00:00:20 ; elapsed = 00:00:05 . Memory (MB): peak = 2842.125 ; gain = 7.027 ; free physical = 523 ; free virtual = 24097 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 15c081164 Time (s): cpu = 00:00:20 ; elapsed = 00:00:05 . Memory (MB): peak = 2842.125 ; gain = 7.027 ; free physical = 523 ; free virtual = 24097 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 104d545db Time (s): cpu = 00:00:20 ; elapsed = 00:00:05 . Memory (MB): peak = 2842.125 ; gain = 7.027 ; free physical = 523 ; free virtual = 24097 Phase 3.5 Small Shape Detail Placement Phase 3.5 Small Shape Detail Placement | Checksum: 150d95eed Time (s): cpu = 00:00:22 ; elapsed = 00:00:07 . Memory (MB): peak = 2842.125 ; gain = 7.027 ; free physical = 524 ; free virtual = 24098 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: fe87775e Time (s): cpu = 00:00:22 ; elapsed = 00:00:07 . Memory (MB): peak = 2842.125 ; gain = 7.027 ; free physical = 524 ; free virtual = 24098 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 1575cc3c3 Time (s): cpu = 00:00:22 ; elapsed = 00:00:07 . Memory (MB): peak = 2842.125 ; gain = 7.027 ; free physical = 524 ; free virtual = 24098 Phase 3 Detail Placement | Checksum: 1575cc3c3 Time (s): cpu = 00:00:22 ; elapsed = 00:00:07 . Memory (MB): peak = 2842.125 ; gain = 7.027 ; free physical = 524 ; free virtual = 24098 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 4.1.1 Post Placement Optimization Post Placement Optimization Initialization | Checksum: 12b1c98e3 Phase 4.1.1.1 BUFG Insertion Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=9.081 | TNS=0.000 | Phase 1 Physical Synthesis Initialization | Checksum: 1722e4068 Time (s): cpu = 00:00:00.22 ; elapsed = 00:00:00.08 . Memory (MB): peak = 2842.125 ; gain = 0.000 ; free physical = 524 ; free virtual = 24098 INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0. Ending Physical Synthesis Task | Checksum: 1722e4068 Time (s): cpu = 00:00:00.27 ; elapsed = 00:00:00.13 . Memory (MB): peak = 2842.125 ; gain = 0.000 ; free physical = 524 ; free virtual = 24098 Phase 4.1.1.1 BUFG Insertion | Checksum: 12b1c98e3 Time (s): cpu = 00:00:25 ; elapsed = 00:00:08 . Memory (MB): peak = 2842.125 ; gain = 7.027 ; free physical = 524 ; free virtual = 24098 Phase 4.1.1.2 Post Placement Timing Optimization INFO: [Place 30-746] Post Placement Timing Summary WNS=9.081. For the most accurate timing information please run report_timing. Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 12ce860c2 Time (s): cpu = 00:00:25 ; elapsed = 00:00:08 . Memory (MB): peak = 2842.125 ; gain = 7.027 ; free physical = 524 ; free virtual = 24098 Time (s): cpu = 00:00:25 ; elapsed = 00:00:08 . Memory (MB): peak = 2842.125 ; gain = 7.027 ; free physical = 524 ; free virtual = 24098 Phase 4.1 Post Commit Optimization | Checksum: 12ce860c2 Time (s): cpu = 00:00:25 ; elapsed = 00:00:08 . Memory (MB): peak = 2842.125 ; gain = 7.027 ; free physical = 524 ; free virtual = 24098 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 12ce860c2 Time (s): cpu = 00:00:25 ; elapsed = 00:00:08 . Memory (MB): peak = 2842.125 ; gain = 7.027 ; free physical = 524 ; free virtual = 24098 Phase 4.3 Placer Reporting Phase 4.3.1 Print Estimated Congestion INFO: [Place 30-612] Post-Placement Estimated Congestion ____________________________________________________ | | Global Congestion | Short Congestion | | Direction | Region Size | Region Size | |___________|___________________|___________________| | North| 1x1| 2x2| |___________|___________________|___________________| | South| 1x1| 1x1| |___________|___________________|___________________| | East| 1x1| 1x1| |___________|___________________|___________________| | West| 1x1| 1x1| |___________|___________________|___________________| Phase 4.3.1 Print Estimated Congestion | Checksum: 12ce860c2 Time (s): cpu = 00:00:26 ; elapsed = 00:00:08 . Memory (MB): peak = 2842.125 ; gain = 7.027 ; free physical = 524 ; free virtual = 24098 Phase 4.3 Placer Reporting | Checksum: 12ce860c2 Time (s): cpu = 00:00:26 ; elapsed = 00:00:08 . Memory (MB): peak = 2842.125 ; gain = 7.027 ; free physical = 524 ; free virtual = 24098 Phase 4.4 Final Placement Cleanup Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2842.125 ; gain = 0.000 ; free physical = 524 ; free virtual = 24098 Time (s): cpu = 00:00:26 ; elapsed = 00:00:08 . Memory (MB): peak = 2842.125 ; gain = 7.027 ; free physical = 524 ; free virtual = 24098 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 862fa997 Time (s): cpu = 00:00:26 ; elapsed = 00:00:08 . Memory (MB): peak = 2842.125 ; gain = 7.027 ; free physical = 524 ; free virtual = 24098 Ending Placer Task | Checksum: 50ceb87c Time (s): cpu = 00:00:26 ; elapsed = 00:00:08 . Memory (MB): peak = 2842.125 ; gain = 7.027 ; free physical = 524 ; free virtual = 24098 29 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:27 ; elapsed = 00:00:09 . Memory (MB): peak = 2842.125 ; gain = 39.043 ; free physical = 524 ; free virtual = 24098 # report_utilization -hierarchical -file digilent_nexys4ddr_utilization_hierarchical_place.rpt # report_utilization -file digilent_nexys4ddr_utilization_place.rpt # report_io -file digilent_nexys4ddr_io.rpt report_io: Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.16 . Memory (MB): peak = 2842.125 ; gain = 0.000 ; free physical = 515 ; free virtual = 24089 # report_control_sets -verbose -file digilent_nexys4ddr_control_sets.rpt report_control_sets: Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.1 . Memory (MB): peak = 2842.125 ; gain = 0.000 ; free physical = 523 ; free virtual = 24097 # report_clock_utilization -file digilent_nexys4ddr_clock_utilization.rpt # route_design Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' Running DRC as a precondition to command route_design INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Phase 1 Build RT Design Checksum: PlaceDB: 20ab9d53 ConstDB: 0 ShapeSum: 30231b29 RouteDB: 0 [50%] Placement Phase 3 completed Running routing...... [60%] Routing Phase 0 completed [70%] Routing Phase 1 completed [80%] Routing Phase 2 completed Post Restoration Checksum: NetGraph: 38316509 | NumContArr: 4ed83706 | Constraints: c2a8fa9d | Timing: c2a8fa9d Phase 1 Build RT Design | Checksum: 20c5b9149 Time (s): cpu = 00:00:33 ; elapsed = 00:00:27 . Memory (MB): peak = 2842.125 ; gain = 0.000 ; free physical = 433 ; free virtual = 24007 Phase 2 Router Initialization Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 20c5b9149 Time (s): cpu = 00:00:33 ; elapsed = 00:00:27 . Memory (MB): peak = 2842.125 ; gain = 0.000 ; free physical = 433 ; free virtual = 24007 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 20c5b9149 Time (s): cpu = 00:00:33 ; elapsed = 00:00:27 . Memory (MB): peak = 2842.125 ; gain = 0.000 ; free physical = 433 ; free virtual = 24007 Number of Nodes with overlaps = 0 Phase 2.3 Update Timing Phase 2.3 Update Timing | Checksum: 2a589208d Time (s): cpu = 00:00:37 ; elapsed = 00:00:28 . Memory (MB): peak = 2842.125 ; gain = 0.000 ; free physical = 405 ; free virtual = 23979 INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.996 | TNS=0.000 | WHS=-0.066 | THS=-0.066 | Router Utilization Summary Global Vertical Routing Utilization = 8.70436e-05 % Global Horizontal Routing Utilization = 7.10429e-05 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 3835 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 3834 Number of Partially Routed Nets = 1 Number of Node Overlaps = 0 Phase 2 Router Initialization | Checksum: 2dc8ebc9d Time (s): cpu = 00:00:39 ; elapsed = 00:00:29 . Memory (MB): peak = 2842.125 ; gain = 0.000 ; free physical = 398 ; free virtual = 23972 Phase 3 Initial Routing Phase 3.1 Global Routing Phase 3.1 Global Routing | Checksum: 2dc8ebc9d Time (s): cpu = 00:00:39 ; elapsed = 00:00:29 . Memory (MB): peak = 2842.125 ; gain = 0.000 ; free physical = 398 ; free virtual = 23972 Phase 3.2 Initial Net Routing Phase 3.2 Initial Net Routing | Checksum: 216aa9269 Time (s): cpu = 00:00:41 ; elapsed = 00:00:29 . Memory (MB): peak = 2842.125 ; gain = 0.000 ; free physical = 391 ; free virtual = 23966 Phase 3 Initial Routing | Checksum: 216aa9269 Time (s): cpu = 00:00:41 ; elapsed = 00:00:29 . Memory (MB): peak = 2842.125 ; gain = 0.000 ; free physical = 400 ; free virtual = 23974 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Number of Nodes with overlaps = 570 Number of Nodes with overlaps = 3 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.788 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 4.1 Global Iteration 0 | Checksum: 1fcf7f3f8 Time (s): cpu = 00:00:44 ; elapsed = 00:00:30 . Memory (MB): peak = 2842.125 ; gain = 0.000 ; free physical = 395 ; free virtual = 23970 Phase 4 Rip-up And Reroute | Checksum: 1fcf7f3f8 Time (s): cpu = 00:00:44 ; elapsed = 00:00:30 . Memory (MB): peak = 2842.125 ; gain = 0.000 ; free physical = 395 ; free virtual = 23970 Phase 5 Delay and Skew Optimization Phase 5.1 Delay CleanUp Phase 5.1 Delay CleanUp | Checksum: 1fcf7f3f8 Time (s): cpu = 00:00:44 ; elapsed = 00:00:30 . Memory (MB): peak = 2842.125 ; gain = 0.000 ; free physical = 395 ; free virtual = 23970 Phase 5.2 Clock Skew Optimization Phase 5.2 Clock Skew Optimization | Checksum: 1fcf7f3f8 Time (s): cpu = 00:00:44 ; elapsed = 00:00:30 . Memory (MB): peak = 2842.125 ; gain = 0.000 ; free physical = 395 ; free virtual = 23970 Phase 5 Delay and Skew Optimization | Checksum: 1fcf7f3f8 Time (s): cpu = 00:00:44 ; elapsed = 00:00:30 . Memory (MB): peak = 2842.125 ; gain = 0.000 ; free physical = 395 ; free virtual = 23970 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1.1 Update Timing Phase 6.1.1 Update Timing | Checksum: 22b9bb45d Time (s): cpu = 00:00:44 ; elapsed = 00:00:30 . Memory (MB): peak = 2842.125 ; gain = 0.000 ; free physical = 395 ; free virtual = 23970 INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.884 | TNS=0.000 | WHS=0.247 | THS=0.000 | Phase 6.1 Hold Fix Iter | Checksum: 22b9bb45d Time (s): cpu = 00:00:44 ; elapsed = 00:00:30 . Memory (MB): peak = 2842.125 ; gain = 0.000 ; free physical = 395 ; free virtual = 23970 Phase 6 Post Hold Fix | Checksum: 22b9bb45d Time (s): cpu = 00:00:44 ; elapsed = 00:00:30 . Memory (MB): peak = 2842.125 ; gain = 0.000 ; free physical = 395 ; free virtual = 23970 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.781825 % Global Horizontal Routing Utilization = 0.994317 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 7 Route finalize | Checksum: 22b9bb45d Time (s): cpu = 00:00:44 ; elapsed = 00:00:30 . Memory (MB): peak = 2842.125 ; gain = 0.000 ; free physical = 395 ; free virtual = 23970 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 22b9bb45d Time (s): cpu = 00:00:44 ; elapsed = 00:00:30 . Memory (MB): peak = 2842.125 ; gain = 0.000 ; free physical = 395 ; free virtual = 23970 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 20bb02aaf Time (s): cpu = 00:00:45 ; elapsed = 00:00:31 . Memory (MB): peak = 2842.125 ; gain = 0.000 ; free physical = 395 ; free virtual = 23970 Phase 10 Post Router Timing INFO: [Route 35-57] Estimated Timing Summary | WNS=8.884 | TNS=0.000 | WHS=0.247 | THS=0.000 | INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary. Phase 10 Post Router Timing | Checksum: 20bb02aaf Time (s): cpu = 00:00:45 ; elapsed = 00:00:31 . Memory (MB): peak = 2842.125 ; gain = 0.000 ; free physical = 395 ; free virtual = 23970 INFO: [Route 35-16] Router Completed Successfully Phase 11 Post-Route Event Processing Phase 11 Post-Route Event Processing | Checksum: 12a061842 Time (s): cpu = 00:00:45 ; elapsed = 00:00:31 . Memory (MB): peak = 2842.125 ; gain = 0.000 ; free physical = 395 ; free virtual = 23970 Ending Routing Task | Checksum: 12a061842 Time (s): cpu = 00:00:45 ; elapsed = 00:00:31 . Memory (MB): peak = 2842.125 ; gain = 0.000 ; free physical = 395 ; free virtual = 23970 Routing Is Done. INFO: [Common 17-83] Releasing license: Implementation 12 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:47 ; elapsed = 00:00:32 . Memory (MB): peak = 2842.125 ; gain = 0.000 ; free physical = 395 ; free virtual = 23970 # report_timing_summary -no_header -no_detailed_paths INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs ------------------------------------------------------------------------------------------------ | Timer Settings | -------------- ------------------------------------------------------------------------------------------------ Enable Multi Corner Analysis : Yes Enable Pessimism Removal : Yes Pessimism Removal Resolution : Nearest Common Node Enable Input Delay Default Clock : No Enable Preset / Clear Arcs : No Disable Flight Delays : No Ignore I/O Paths : No Timing Early Launch at Borrowing Latches : No Borrow Time for Max Delay Exceptions : Yes Merge Timing Exceptions : Yes Inter-SLR Compensation : Conservative Corner Analyze Analyze Name Max Paths Min Paths ------ --------- --------- Slow Yes Yes Fast Yes Yes ------------------------------------------------------------------------------------------------ | Report Methodology | ------------------ ------------------------------------------------------------------------------------------------ No report available as report_methodology has not been run prior. Run report_methodology on the current design for the summary of methodology violations. check_timing report Table of Contents ----------------- 1. checking no_clock (2381) 2. checking constant_clock (0) 3. checking pulse_width_clock (0) 4. checking unconstrained_internal_endpoints (7609) 5. checking no_input_delay (10) 6. checking no_output_delay (17) 7. checking multiple_clock (0) 8. checking generated_clocks (0) 9. checking loops (0) 10. checking partial_input_delay (0) 11. checking partial_output_delay (0) 12. checking latch_loops (0) 1. checking no_clock (2381) --------------------------- There are 2381 register/latch pins with no clock driven by root clock pin: clk_o_reg/Q (HIGH) 2. checking constant_clock (0) ------------------------------ There are 0 register/latch pins with constant_clock. 3. checking pulse_width_clock (0) --------------------------------- There are 0 register/latch pins which need pulse_width check 4. checking unconstrained_internal_endpoints (7609) --------------------------------------------------- There are 7609 pins that are not constrained for maximum delay. (HIGH) There are 0 pins that are not constrained for maximum delay due to constant clock. 5. checking no_input_delay (10) ------------------------------- There are 10 input ports with no input delay specified. (HIGH) There are 0 input ports with no input delay but user has a false path constraint. 6. checking no_output_delay (17) -------------------------------- There are 17 ports with no output delay specified. (HIGH) There are 0 ports with no output delay but user has a false path constraint There are 0 ports with no output delay but with a timing clock defined on it or propagating through it 7. checking multiple_clock (0) ------------------------------ There are 0 register/latch pins with multiple clocks. 8. checking generated_clocks (0) -------------------------------- There are 0 generated clocks that are not connected to a clock source. 9. checking loops (0) --------------------- There are 0 combinational loops in the design. 10. checking partial_input_delay (0) ------------------------------------ There are 0 input ports with partial input delay specified. 11. checking partial_output_delay (0) ------------------------------------- There are 0 ports with partial output delay specified. 12. checking latch_loops (0) ---------------------------- There are 0 combinational latch loops in the design through latch input ------------------------------------------------------------------------------------------------ | Design Timing Summary | --------------------- ------------------------------------------------------------------------------------------------ WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- 8.908 0.000 0 1 0.263 0.000 0 1 4.500 0.000 0 3 All user specified timing constraints are met. ------------------------------------------------------------------------------------------------ | Clock Summary | ------------- ------------------------------------------------------------------------------------------------ Clock Waveform(ns) Period(ns) Frequency(MHz) ----- ------------ ---------- -------------- sys_clk_pin {0.000 5.000} 10.000 100.000 ------------------------------------------------------------------------------------------------ | Intra Clock Table | ----------------- ------------------------------------------------------------------------------------------------ Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- sys_clk_pin 8.908 0.000 0 1 0.263 0.000 0 1 4.500 0.000 0 3 ------------------------------------------------------------------------------------------------ | Inter Clock Table | ----------------- ------------------------------------------------------------------------------------------------ From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- ------------------------------------------------------------------------------------------------ | Other Path Groups Table | ----------------------- ------------------------------------------------------------------------------------------------ Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- # report_route_status -file digilent_nexys4ddr_route_status.rpt # report_drc -file digilent_nexys4ddr_drc.rpt Command: report_drc -file digilent_nexys4ddr_drc.rpt INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/eda/vivado/Vivado/2023.2/data/ip'. INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado_Tcl 2-168] The results of DRC are in file /var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4ddr_drc.rpt. report_drc completed successfully # report_timing_summary -datasheet -max_paths 10 -file digilent_nexys4ddr_timing.rpt INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs # report_power -file digilent_nexys4ddr_power.rpt Command: report_power -file digilent_nexys4ddr_power.rpt Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis. Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report. 0 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. report_power completed successfully # write_bitstream -force "./build/out.bit" Command: write_bitstream -force ./build/out.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' Running DRC as a precondition to command write_bitstream INFO: [IP_Flow 19-1839] IP Catalog is up to date. WARN (PR1014) : Generic routing resource will be used to clock signal 'clk_d' by the specified constraint. And then it may lead to the excessive delay or skew [90%] Routing Phase 3 completed Running timing analysis...... [95%] Timing analysis completed Placement and routing completed Bitstream generation in progress...... Bitstream generation completed Running power analysis...... [100%] Power analysis completed Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.power.html" completed Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.pin.html" completed Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.rpt.html" completed Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.rpt.txt" completed Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.tr.html" completed Sun Jun 23 15:04:35 2024 [Pipeline] } [Pipeline] // stage [Pipeline] } INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: set_property CFGBVS value1 [current_design] #where value1 is either VCCO or GND set_property CONFIG_VOLTAGE value2 [current_design] #where value2 is the voltage provided to configuration bank 0 Refer to the device configuration user guide for more information. INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... Loading site data... Loading route data... Processing options... Creating bitmap... Creating bitstream... Writing bitstream ./build/out.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-1876] WebTalk data collection is mandatory when using a ULT device. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Common 17-83] Releasing license: Implementation 9 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 3156.148 ; gain = 250.113 ; free physical = 370 ; free virtual = 23957 INFO: [Common 17-206] Exiting Vivado at Sun Jun 23 15:04:45 2024... [Pipeline] } [Pipeline] // stage [Pipeline] } [Pipeline] // parallel [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (FPGA Flash) [Pipeline] parallel [Pipeline] { (Branch: openFPGAloader ECP5) [Pipeline] { (Branch: openFPGAloader Tangnano 20k) [Pipeline] { (Branch: openFPGAloader Nexys 4 DDR) [Pipeline] stage [Pipeline] { (openFPGAloader ECP5) [Pipeline] stage [Pipeline] { (openFPGAloader Tangnano 20k) [Pipeline] stage [Pipeline] { (openFPGAloader Nexys 4 DDR) [Pipeline] script [Pipeline] { [Pipeline] script [Pipeline] { [Pipeline] script [Pipeline] { [Pipeline] lock Trying to acquire lock on [ecp5] Resource [ecp5] did not exist. Created. Lock acquired on [ecp5] [Pipeline] { [Pipeline] lock Trying to acquire lock on [tangnano20k] Resource [tangnano20k] did not exist. Created. Lock acquired on [tangnano20k] [Pipeline] { [Pipeline] lock Trying to acquire lock on [nexys4] Resource [nexys4] did not exist. Created. Lock acquired on [nexys4] [Pipeline] { [Pipeline] echo FPGA ECP5 Broqueada [Pipeline] sh [Pipeline] echo FPGA TangNano Broqueada + /eda/oss-cad-suite/bin/openFPGALoader -b colorlight-i9 ./build/out.bit empty Found 1 compatible device: 0x0d28 0x0204 0x3 DAPLink CMSIS-DAP Open file: DONE b3bdffff Parse file: DONE Enable configuration: DONE SRAM erase: DONE [Pipeline] sh [Pipeline] echo FPGA Nexys 4 Broqueada + echo gravando na tang nano gravando na tang nano [Pipeline] sh + cd Risco-5/fpga/nexys4_ddr + /eda/oss-cad-suite/bin/openFPGALoader -b nexys_a7_100 ./build/out.bit empty Jtag frequency : requested 6.00MHz -> real 6.00MHz Open file DONE Parse file DONE load program [Pipeline] } Lock released on resource [tangnano20k] [Pipeline] // lock Loading: [====== ] 10.89%[Pipeline] } [Pipeline] // script Load SRAM: [========= ] 18.00%[Pipeline] } [Pipeline] // stage [Pipeline] } Loading: [=========== ] 21.78% Load SRAM: [=================== ] 38.00% Loading: [================= ] 32.68% Load SRAM: [============================= ] 58.00% Loading: [====================== ] 43.57% Load SRAM: [======================================= ] 78.00% Loading: [============================ ] 54.46% Load SRAM: [================================================= ] 98.00% Load SRAM: [===================================================] 100.00% Done Shift IR 35 ir: 1 isc_done 1 isc_ena 0 init 1 done 1 [Pipeline] } Lock released on resource [nexys4] Loading: [================================= ] 65.35%[Pipeline] // lock [Pipeline] } [Pipeline] // script [Pipeline] } Loading: [======================================= ] 76.25%[Pipeline] // stage [Pipeline] } Loading: [============================================ ] 87.14% Loading: [==================================================] 98.03% Loading: [==================================================] 100.00% Done Disable configuration: DONE [Pipeline] } Lock released on resource [ecp5] [Pipeline] // lock [Pipeline] } [Pipeline] // script [Pipeline] } [Pipeline] // stage [Pipeline] } [Pipeline] // parallel [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Testes) [Pipeline] parallel [Pipeline] { (Branch: ECP5 - Testes) [Pipeline] { (Branch: TangNano - Testes) [Pipeline] { (Branch: Nexys 4 - Testes) [Pipeline] stage [Pipeline] { (ECP5 - Testes) [Pipeline] stage [Pipeline] { (TangNano - Testes) [Pipeline] stage [Pipeline] { (Nexys 4 - Testes) [Pipeline] script [Pipeline] { [Pipeline] script [Pipeline] { [Pipeline] script [Pipeline] { [Pipeline] echo Rodando teste na ECP5 [Pipeline] lock Trying to acquire lock on [ecp5] Resource [ecp5] did not exist. Created. Lock acquired on [ecp5] [Pipeline] { [Pipeline] echo Rodando teste na tang nano [Pipeline] lock Trying to acquire lock on [tangnano20k] Resource [tangnano20k] did not exist. Created. Lock acquired on [tangnano20k] [Pipeline] { [Pipeline] echo Rodando teste na Nexys 4 [Pipeline] lock Trying to acquire lock on [nexys4] Resource [nexys4] did not exist. Created. Lock acquired on [nexys4] [Pipeline] { [Pipeline] echo FPGA ECP5 Broqueada [Pipeline] sh [Pipeline] echo FPGA TangNano Broqueada + echo testando na ecp5 testando na ecp5 [Pipeline] sh [Pipeline] echo FPGA Nexys 4 Broqueada + echo testando na tang nano testando na tang nano [Pipeline] sh + echo testando na tang nano testando na tang nano [Pipeline] } Lock released on resource [ecp5] [Pipeline] } Lock released on resource [tangnano20k] [Pipeline] // lock [Pipeline] // lock [Pipeline] echo ECP5 liberada [Pipeline] } [Pipeline] echo TangNano liberada [Pipeline] } [Pipeline] } Lock released on resource [nexys4] [Pipeline] // script [Pipeline] // script [Pipeline] // lock [Pipeline] } [Pipeline] } [Pipeline] echo TangNano liberada [Pipeline] } [Pipeline] // stage [Pipeline] // stage [Pipeline] // script [Pipeline] } [Pipeline] } [Pipeline] } [Pipeline] // stage [Pipeline] } [Pipeline] // parallel [Pipeline] } [Pipeline] // stage [Pipeline] } [Pipeline] // node [Pipeline] End of Pipeline Finished: SUCCESS