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INFO: [Synth 8-6157] synthesizing module 'Alu' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu.v:1]
INFO: [Synth 8-6155] done synthesizing module 'Alu' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu.v:1]
INFO: [Synth 8-6157] synthesizing module 'Immediate_Generator' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/immediate_generator.v:1]
INFO: [Synth 8-6155] done synthesizing module 'Immediate_Generator' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/immediate_generator.v:1]
INFO: [Synth 8-6157] synthesizing module 'CSR_Unit' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/csr_unit.v:1]
INFO: [Synth 8-155] case statement is not full and has no default [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/csr_unit.v:117]
INFO: [Synth 8-6155] done synthesizing module 'CSR_Unit' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/csr_unit.v:1]
INFO: [Synth 8-6155] done synthesizing module 'Core' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:2]
WARNING: [Synth 8-7071] port 'halt' of module 'Core' is unconnected for instance 'Core' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:33]
WARNING: [Synth 8-7071] port 'interruption_request_external' of module 'Core' is unconnected for instance 'Core' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:33]
WARNING: [Synth 8-7071] port 'interruption_request_timer' of module 'Core' is unconnected for instance 'Core' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:33]
WARNING: [Synth 8-7071] port 'interruption_request_software' of module 'Core' is unconnected for instance 'Core' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:33]
WARNING: [Synth 8-7071] port 'interruption_request_fast' of module 'Core' is unconnected for instance 'Core' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:33]
WARNING: [Synth 8-7023] instance 'Core' of module 'Core' has 14 connections declared, but only 9 given [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:33]
INFO: [Synth 8-6157] synthesizing module 'Memory' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v:1]
Parameter MEMORY_FILE bound to: ../../software/memory/teste_uart_fpga.hex - type: string
Parameter MEMORY_SIZE bound to: 2048 - type: integer
INFO: [Synth 8-3876] $readmem data file '../../software/memory/teste_uart_fpga.hex' is read successfully [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v:35]
INFO: [Synth 8-6155] done synthesizing module 'Memory' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v:1]
INFO: [Synth 8-6157] synthesizing module 'BUS' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/bus.v:1]
INFO: [Synth 8-6155] done synthesizing module 'BUS' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/bus.v:1]
INFO: [Synth 8-6157] synthesizing module 'LEDs' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/leds.v:1]
INFO: [Synth 8-6155] done synthesizing module 'LEDs' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/leds.v:1]
INFO: [Synth 8-6157] synthesizing module 'UART' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart.v:1]
Parameter CLK_FREQ bound to: 50000000 - type: integer
Parameter BIT_RATE bound to: 115200 - type: integer
Parameter BUFFER_SIZE bound to: 16 - type: integer
INFO: [Synth 8-6157] synthesizing module 'FIFO' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/fifo.v:1]
Parameter DEPTH bound to: 16 - type: integer
Parameter WIDTH bound to: 8 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'FIFO' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/fifo.v:1]
INFO: [Synth 8-6157] synthesizing module 'uart_tool_rx' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_rx.v:10]
Parameter BIT_RATE bound to: 115200 - type: integer
Parameter CLK_HZ bound to: 50000000 - type: integer
Parameter PAYLOAD_BITS bound to: 8 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'uart_tool_rx' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_rx.v:10]
INFO: [Synth 8-6157] synthesizing module 'uart_tool_tx' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_tx.v:10]
Parameter BIT_RATE bound to: 115200 - type: integer
Parameter CLK_HZ bound to: 50000000 - type: integer
Parameter PAYLOAD_BITS bound to: 8 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'uart_tool_tx' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_tx.v:10]
INFO: [Synth 8-6155] done synthesizing module 'UART' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart.v:1]
INFO: [Synth 8-6157] synthesizing module 'GPIOS' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v:1]
Parameter WIDHT bound to: 8 - type: integer
INFO: [Synth 8-6157] synthesizing module 'GPIO' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpio.v:1]
INFO: [Synth 8-6155] done synthesizing module 'GPIO' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpio.v:1]
INFO: [Synth 8-6157] synthesizing module 'PWM' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/pwm.v:1]
INFO: [Synth 8-6155] done synthesizing module 'PWM' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/pwm.v:1]
INFO: [Synth 8-155] case statement is not full and has no default [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v:66]
INFO: [Synth 8-6155] done synthesizing module 'GPIOS' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v:1]
INFO: [Synth 8-6155] done synthesizing module 'Risco_5_SOC' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:1]
INFO: [Synth 8-6155] done synthesizing module 'top' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/main.v:1]
Info: at iteration #16, type ALL: wirelen solved = 17839, spread = 24598, legal = 25786; time = 0.17s
WARNING: [Synth 8-3848] Net mdu_done in module/entity Core does not have driver. [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:55]
WARNING: [Synth 8-6014] Unused sequential element tx_fifo_read_reg was removed. [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart.v:160]
Info: at iteration #17, type ALL: wirelen solved = 18047, spread = 24350, legal = 25253; time = 0.24s
WARNING: [Synth 8-7129] Port address[31] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[30] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[29] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[28] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[27] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[26] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[25] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[24] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[23] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[22] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[21] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[20] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[19] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[18] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[17] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[16] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[15] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[14] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[13] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[12] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[11] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[10] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[9] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[8] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[31] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[30] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[29] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[28] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[27] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[26] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[25] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[24] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[23] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[22] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[21] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[20] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[19] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[18] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[17] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[31] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[30] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[29] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[28] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[27] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[26] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[25] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[24] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[23] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[22] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[21] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[20] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[19] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[18] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[17] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[16] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[15] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[14] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[13] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[12] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[11] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[10] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[9] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[8] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[7] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[6] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[5] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[1] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[0] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[31] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[30] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[29] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[28] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[27] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[26] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[25] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[24] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[23] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[22] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[21] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[20] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[19] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[18] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[17] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[16] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[15] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[14] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[13] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[12] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[11] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[10] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[9] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[8] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[7] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[6] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[5] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[4] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[3] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[2] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[1] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[0] in module LEDs is either unconnected or has no load
INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2117.723 ; gain = 492.684 ; free physical = 645 ; free virtual = 24187
---------------------------------------------------------------------------------
Info: at iteration #18, type ALL: wirelen solved = 18227, spread = 24532, legal = 25567; time = 0.24s
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2135.535 ; gain = 510.496 ; free physical = 637 ; free virtual = 24179
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2135.535 ; gain = 510.496 ; free physical = 637 ; free virtual = 24179
---------------------------------------------------------------------------------
Info: at iteration #19, type ALL: wirelen solved = 18861, spread = 24596, legal = 25614; time = 0.22s
Netlist sorting complete. Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2135.535 ; gain = 0.000 ; free physical = 644 ; free virtual = 24187
Info: at iteration #20, type ALL: wirelen solved = 18795, spread = 24577, legal = 25624; time = 0.17s
Info: at iteration #21, type ALL: wirelen solved = 19170, spread = 24419, legal = 25525; time = 0.16s
Info: at iteration #22, type ALL: wirelen solved = 19303, spread = 24269, legal = 25683; time = 0.16s
Info: HeAP Placer Time: 7.20s
Info: of which solving equations: 4.54s
Info: of which spreading cells: 0.50s
Info: of which strict legalisation: 0.17s
Info: Running simulated annealing placer for refinement.
Info: at iteration #1: temp = 0.000000, timing cost = 4313, wirelen = 25253
INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints
Initializing timing engine
Parsing XDC File [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc]
Finished Parsing XDC File [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc]
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Completed Processing XDC Constraints
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2283.285 ; gain = 0.000 ; free physical = 579 ; free virtual = 24122
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2283.320 ; gain = 0.000 ; free physical = 583 ; free virtual = 24126
Info: at iteration #5: temp = 0.000000, timing cost = 5981, wirelen = 22882
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 2283.320 ; gain = 658.281 ; free physical = 560 ; free virtual = 24105
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Start Loading Part and Timing Information
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Loading part: xc7a100tcsg324-1
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Finished Loading Part and Timing Information : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 2283.320 ; gain = 658.281 ; free physical = 559 ; free virtual = 24104
---------------------------------------------------------------------------------
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Start Applying 'set_property' XDC Constraints
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Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 2283.320 ; gain = 658.281 ; free physical = 557 ; free virtual = 24102
---------------------------------------------------------------------------------
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'ResetBootSystem'
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'Control_Unit'
INFO: [Synth 8-802] inferred FSM for state register 'fsm_state_reg' in module 'uart_tool_rx'
INFO: [Synth 8-802] inferred FSM for state register 'fsm_state_reg' in module 'uart_tool_tx'
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'UART'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
RESET_COUNTER | 00 | 01
IDLE | 01 | 10
INIT | 10 | 00
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'ResetBootSystem'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
FETCH | 00000000000000000000000000000000000000000000001 | 000000
VALIDATE_FETCH | 00000000000000000000000000000000000000000000010 | 101110
DECODE | 00000000000000000000000000000000000000000000100 | 000001
MEMADR | 00000000000000000000000000000000000000000001000 | 000010
MEMREAD_UNALIGNED | 00000000000000000000000000000000000000000010000 | 010110
LOAD_FIRST_BLOCK | 00000000000000000000000000000000000000000100000 | 010000
SAVE_FIRST_BLOCK | 00000000000000000000000000000000000000001000000 | 010001
CALC_NEXT_ADDRESS | 00000000000000000000000000000000000000010000000 | 010010
READ_SECOND_BLOCK | 00000000000000000000000000000000000000100000000 | 010011
LOAD_SECOND_BLOCK | 00000000000000000000000000000000000001000000000 | 010100
MERGE_BLOCKS | 00000000000000000000000000000000000010000000000 | 010101
FILTER_ALU_WB | 00000000000000000000000000000000000100000000000 | 010111
MEMREAD | 00000000000000000000000000000000001000000000000 | 000011
MEMWB | 00000000000000000000000000000000010000000000000 | 000100
MEMWRITE_UNALIGNED | 00000000000000000000000000000000100000000000000 | 011000
GEN_FIRST_BLOCK_PART_1 | 00000000000000000000000000000001000000000000000 | 011001
GEN_FIRST_BLOCK_PART_2 | 00000000000000000000000000000010000000000000000 | 011010
GEN_SECOND_BLOCK_PART_1 | 00000000000000000000000000000100000000000000000 | 011011
GEN_SECOND_BLOCK_PART_2 | 00000000000000000000000000001000000000000000000 | 011100
MERGE_WRITE_BLOCKS | 00000000000000000000000000010000000000000000000 | 011101
SWAP_VALUE_DIRECTION | 00000000000000000000000000100000000000000000000 | 011110
CLEAR_VALUE_HALF_BYTE_ONE_BLOCK | 00000000000000000000000001000000000000000000000 | 100010
CLEAR_VALUE_HALF_BYTE_ONE_BLOCK_2 | 00000000000000000000000010000000000000000000000 | 100011
CLEAR_VALUE_HALF_BYTE_ONE_BLOCK_3 | 00000000000000000000000100000000000000000000000 | 100100
CLEAR_VALUE | 00000000000000000000001000000000000000000000000 | 011111
MERGE_WRITE_VALUE_1 | 00000000000000000000010000000000000000000000000 | 100000
WRITE_VALUE_1 | 00000000000000000000100000000000000000000000000 | 100001
CALC_SECOND_BLOCK_ADDRESS_TO_WRITE | 00000000000000000001000000000000000000000000000 | 100101
READ_SECOND_BLOCK_TO_WRITE | 00000000000000000010000000000000000000000000000 | 100110
LOAD_SECOND_BLOCK_TO_WRITE | 00000000000000000100000000000000000000000000000 | 100111
LOAD_SECOND_BLOCK_TO_WRITE_2 | 00000000000000001000000000000000000000000000000 | 101000
SWAP_VALUE_DIRECTION_2 | 00000000000000010000000000000000000000000000000 | 101001
CLEAR_VALUE_PART_2 | 00000000000000100000000000000000000000000000000 | 101010
CLEAR_VALUE_PART_2_1 | 00000000000001000000000000000000000000000000000 | 101011
MERGE_WRITE_VALUE_2 | 00000000000010000000000000000000000000000000000 | 101100
WRITE_VALUE_2 | 00000000000100000000000000000000000000000000000 | 101101
MEMWRITE | 00000000001000000000000000000000000000000000000 | 000101
EXECUTER | 00000000010000000000000000000000000000000000000 | 000110
EXECUTEI | 00000000100000000000000000000000000000000000000 | 001000
JAL | 00000001000000000000000000000000000000000000000 | 001001
BRANCH | 00000010000000000000000000000000000000000000000 | 001010
AUIPC | 00000100000000000000000000000000000000000000000 | 001100
LUI | 00001000000000000000000000000000000000000000000 | 001101
JALR_PC | 00010000000000000000000000000000000000000000000 | 001110
JALR | 00100000000000000000000000000000000000000000000 | 001011
ALUWB | 01000000000000000000000000000000000000000000000 | 000111
EXECUTECSR | 10000000000000000000000000000000000000000000000 | 001111
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'Control_Unit'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
FSM_IDLE | 00 | 000
FSM_START | 11 | 001
FSM_RECV | 10 | 010
FSM_STOP | 01 | 011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'fsm_state_reg' using encoding 'sequential' in module 'uart_tool_rx'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
FSM_IDLE | 00 | 000
FSM_START | 11 | 001
FSM_SEND | 10 | 010
FSM_STOP | 01 | 011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'fsm_state_reg' using encoding 'sequential' in module 'uart_tool_tx'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
IDLE | 0000 | 0000
COPY_WRITE_BUFFER | 0001 | 0100
WRITE | 0010 | 0010
READ | 0011 | 0001
READ_RX_FIFO_EMPTY | 0100 | 0110
READ_TX_FIFO_EMPTY | 0101 | 0111
READ_RX_FIFO_FULL | 0110 | 1000
READ_TX_FIFO_FULL | 0111 | 1001
WB | 1000 | 0101
FINISH | 1001 | 0011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'UART'
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 2283.320 ; gain = 658.281 ; free physical = 518 ; free virtual = 24065
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Component Statistics
---------------------------------------------------------------------------------
Detailed RTL Component Info :
+---Adders :
2 Input 32 Bit Adders := 1
3 Input 32 Bit Adders := 1
2 Input 10 Bit Adders := 2
2 Input 6 Bit Adders := 6
2 Input 5 Bit Adders := 1
2 Input 4 Bit Adders := 2
2 Input 3 Bit Adders := 2
2 Input 2 Bit Adders := 1
+---XORs :
2 Input 32 Bit XORs := 1
+---XORs :
2 Bit Wide XORs := 1
+---Registers :
64 Bit Registers := 2
32 Bit Registers := 51
16 Bit Registers := 4
10 Bit Registers := 2
8 Bit Registers := 8
6 Bit Registers := 5
4 Bit Registers := 2
3 Bit Registers := 1
2 Bit Registers := 1
1 Bit Registers := 15
+---RAMs :
16K Bit (512 X 32 bit) RAMs := 1
128 Bit (16 X 8 bit) RAMs := 2
+---Muxes :
4 Input 64 Bit Muxes := 1
47 Input 47 Bit Muxes := 1
2 Input 47 Bit Muxes := 17
11 Input 47 Bit Muxes := 1
2 Input 32 Bit Muxes := 8
8 Input 32 Bit Muxes := 1
15 Input 32 Bit Muxes := 1
6 Input 32 Bit Muxes := 1
4 Input 32 Bit Muxes := 1
10 Input 32 Bit Muxes := 2
2 Input 8 Bit Muxes := 3
3 Input 6 Bit Muxes := 1
2 Input 6 Bit Muxes := 4
2 Input 5 Bit Muxes := 1
47 Input 4 Bit Muxes := 1
9 Input 4 Bit Muxes := 1
10 Input 4 Bit Muxes := 2
23 Input 4 Bit Muxes := 1
2 Input 4 Bit Muxes := 3
6 Input 4 Bit Muxes := 1
5 Input 3 Bit Muxes := 1
2 Input 3 Bit Muxes := 3
4 Input 3 Bit Muxes := 2
47 Input 3 Bit Muxes := 3
10 Input 3 Bit Muxes := 2
3 Input 2 Bit Muxes := 1
2 Input 2 Bit Muxes := 16
47 Input 2 Bit Muxes := 2
4 Input 2 Bit Muxes := 4
3 Input 1 Bit Muxes := 6
2 Input 1 Bit Muxes := 77
47 Input 1 Bit Muxes := 12
6 Input 1 Bit Muxes := 12
4 Input 1 Bit Muxes := 2
10 Input 1 Bit Muxes := 8
---------------------------------------------------------------------------------
Finished RTL Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 240 (col length:80)
BRAMs: 270 (col length: RAMB18 80 RAMB36 40)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
Info: at iteration #10: temp = 0.000000, timing cost = 6559, wirelen = 22156
[80%] Tech-Mapping Phase 3 completed
[90%] Tech-Mapping Phase 4 completed
WARN (NL0002) : The module "ALU_Control" instantiated to "ALU_Control" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":238)
WARN (NL0002) : The module "Immediate_Generator" instantiated to "Immediate_Generator" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":255)
WARN (NL0002) : The module "MUX" instantiated to "PCSourceMUX" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":178)
WARN (NL0002) : The module "GPIO" instantiated to "Gpios[0]" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":43)
WARN (NL0002) : The module "GPIO" instantiated to "Gpios[1]" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":43)
WARN (NL0002) : The module "GPIO" instantiated to "Gpios[2]" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":43)
WARN (NL0002) : The module "GPIO" instantiated to "Gpios[3]" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":43)
WARN (NL0002) : The module "GPIO" instantiated to "Gpios[4]" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":43)
[95%] Generate netlist file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/gwsynthesis/project.vg" completed
[100%] Generate report file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/gwsynthesis/project_syn.rpt.html" completed
GowinSynthesis finish
Reading netlist file: "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/gwsynthesis/project.vg"
Parsing netlist file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/gwsynthesis/project.vg" completed
Processing netlist completed
Reading constraint file: "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/pinout.cst"
Physical Constraint parsed completed
Running placement......
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
INFO: [Synth 8-6851] RAM (SOC/Memory/memory_reg) has partial Byte Wide Write Enable pattern, however no output register found in fanout of RAM. Recommended to use supported Byte Wide Write Enable template.
Info: at iteration #15: temp = 0.000000, timing cost = 6149, wirelen = 21883
[10%] Placement Phase 0 completed
Info: at iteration #20: temp = 0.000000, timing cost = 5628, wirelen = 21807
[20%] Placement Phase 1 completed
Info: at iteration #23: temp = 0.000000, timing cost = 5598, wirelen = 21792
Info: SA placement time 18.99s
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 41.75 MHz (PASS at 25.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 8.01 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 10.20 ns
Info: Slack histogram:
Info: legend: * represents 53 endpoint(s)
Info: + represents [1,53) endpoint(s)
Info: [ 16049, 17209) |+
Info: [ 17209, 18369) |+
Info: [ 18369, 19529) |+
Info: [ 19529, 20689) |*+
Info: [ 20689, 21849) |*****+
Info: [ 21849, 23009) |*******+
Info: [ 23009, 24169) |*********+
Info: [ 24169, 25329) |***********+
Info: [ 25329, 26489) |*****+
Info: [ 26489, 27649) |***+
Info: [ 27649, 28809) |*****+
Info: [ 28809, 29969) |*****************************+
Info: [ 29969, 31129) |************************************************************
Info: [ 31129, 32289) |************+
Info: [ 32289, 33449) |***+
Info: [ 33449, 34609) |********+
Info: [ 34609, 35769) |******+
Info: [ 35769, 36929) |*****+
Info: [ 36929, 38089) |*******+
Info: [ 38089, 39249) |*****+
Info: Checksum: 0x41178a46
Info: Routing globals...
Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
Info: Routing..
Info: Setting up routing queue.
Info: Routing 32648 arcs.
Info: | (re-)routed arcs | delta | remaining| time spent |
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
Info: 1000 | 420 579 | 420 579 | 32179| 0.68 0.68|
Info: 2000 | 894 1105 | 474 526 | 31780| 0.31 0.99|
Info: 3000 | 1354 1645 | 460 540 | 31323| 0.26 1.25|
Info: 4000 | 1829 2170 | 475 525 | 30862| 0.26 1.51|
Info: 5000 | 2227 2772 | 398 602 | 30399| 0.26 1.77|
Info: 6000 | 2709 3290 | 482 518 | 29995| 0.25 2.02|
Info: 7000 | 3030 3969 | 321 679 | 29499| 0.26 2.28|
Info: 8000 | 3387 4612 | 357 643 | 29001| 0.26 2.54|
Info: 9000 | 3793 5206 | 406 594 | 28495| 0.24 2.78|
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:30 ; elapsed = 00:00:30 . Memory (MB): peak = 2283.320 ; gain = 658.281 ; free physical = 388 ; free virtual = 23941
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
Distributed RAM: Preliminary Mapping Report (see note below)
+------------+-----------------------------+-----------+----------------------+-----------------+
|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
+------------+-----------------------------+-----------+----------------------+-----------------+
|top | SOC/Memory/memory_reg | Implied | 512 x 32 | RAM256X1S x 64 |
|top | SOC/Uart/RX_FIFO/memory_reg | Implied | 16 x 8 | RAM32M x 2 |
|top | SOC/Uart/TX_FIFO/memory_reg | Implied | 16 x 8 | RAM32M x 2 |
+------------+-----------------------------+-----------+----------------------+-----------------+
Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once.
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
Info: 10000 | 4078 5921 | 285 715 | 27847| 0.25 3.03|
Info: 11000 | 4403 6596 | 325 675 | 27400| 0.25 3.28|
Info: 12000 | 4732 7267 | 329 671 | 26820| 0.25 3.53|
Info: 13000 | 5023 7976 | 291 709 | 26328| 0.26 3.79|
Info: 14000 | 5348 8651 | 325 675 | 25913| 0.29 4.08|
Info: 15000 | 5611 9388 | 263 737 | 25264| 0.27 4.35|
Info: 16000 | 5770 10229 | 159 841 | 24912| 0.24 4.59|
Info: 17000 | 6033 10966 | 263 737 | 24607| 0.26 4.85|
Info: 18000 | 6301 11698 | 268 732 | 24068| 0.29 5.14|
Info: 19000 | 6611 12388 | 310 690 | 23553| 0.26 5.39|
Info: 20000 | 6937 13062 | 326 674 | 22973| 0.27 5.67|
Info: 21000 | 7042 13957 | 105 895 | 22909| 0.26 5.93|
Info: 22000 | 7364 14635 | 322 678 | 22394| 0.27 6.20|
Info: 23000 | 7697 15302 | 333 667 | 21850| 0.30 6.50|
Info: 24000 | 8050 15949 | 353 647 | 21460| 0.30 6.80|
Info: 25000 | 8366 16633 | 316 684 | 20945| 0.31 7.12|
Info: 26000 | 8650 17349 | 284 716 | 20352| 0.31 7.43|
Info: 27000 | 8935 18064 | 285 715 | 19877| 0.30 7.73|
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:35 ; elapsed = 00:00:35 . Memory (MB): peak = 2283.320 ; gain = 658.281 ; free physical = 385 ; free virtual = 23939
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
Info: 28000 | 9307 18692 | 372 628 | 19359| 0.33 8.06|
Info: 29000 | 9565 19434 | 258 742 | 18751| 0.32 8.38|
Info: 30000 | 9833 20166 | 268 732 | 18204| 0.33 8.71|
Info: 31000 | 10154 20845 | 321 679 | 17896| 0.37 9.08|
Info: 32000 | 10489 21510 | 335 665 | 17386| 0.37 9.45|
Info: 33000 | 10730 22269 | 241 759 | 16902| 0.34 9.79|
Info: 34000 | 11015 22984 | 285 715 | 16364| 0.33 10.12|
Info: 35000 | 11391 23608 | 376 624 | 15880| 0.35 10.47|
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:00:38 ; elapsed = 00:00:38 . Memory (MB): peak = 2283.320 ; gain = 658.281 ; free physical = 384 ; free virtual = 23937
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
Distributed RAM: Final Mapping Report
+------------+-----------------------------+-----------+----------------------+-----------------+
|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
+------------+-----------------------------+-----------+----------------------+-----------------+
|top | SOC/Memory/memory_reg | Implied | 512 x 32 | RAM256X1S x 64 |
|top | SOC/Uart/RX_FIFO/memory_reg | Implied | 16 x 8 | RAM32M x 2 |
|top | SOC/Uart/TX_FIFO/memory_reg | Implied | 16 x 8 | RAM32M x 2 |
+------------+-----------------------------+-----------+----------------------+-----------------+
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
Info: 36000 | 11692 24307 | 301 699 | 15487| 0.34 10.82|
Info: 37000 | 12021 24978 | 329 671 | 14969| 0.36 11.18|
Info: 38000 | 12417 25582 | 396 604 | 14586| 0.33 11.51|
Info: 39000 | 12922 26077 | 505 495 | 14285| 0.37 11.88|
Info: 40000 | 13358 26641 | 436 564 | 13882| 0.34 12.21|
Info: 41000 | 13800 27199 | 442 558 | 13502| 0.34 12.55|
Info: 42000 | 14176 27823 | 376 624 | 13067| 0.35 12.90|
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 2283.320 ; gain = 658.281 ; free physical = 385 ; free virtual = 23938
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
Info: 43000 | 14547 28452 | 371 629 | 12611| 0.36 13.26|
Info: 44000 | 14850 29123 | 303 671 | 12325| 0.34 13.60|
Info: 45000 | 15073 29756 | 223 633 | 11661| 0.25 13.85|
Info: 46000 | 15319 30322 | 246 566 | 10984| 0.21 14.07|
Info: 47000 | 15586 30865 | 267 543 | 10306| 0.20 14.27|
Info: 48000 | 15873 31411 | 287 546 | 9685| 0.26 14.53|
Info: 49000 | 16231 32002 | 358 591 | 9383| 0.42 14.95|
Info: 50000 | 16557 32646 | 326 644 | 9006| 0.39 15.34|
[30%] Placement Phase 2 completed
Info: 51000 | 16922 33244 | 365 598 | 8440| 0.30 15.64|
Info: 52000 | 17228 33892 | 306 648 | 7815| 0.25 15.89|
Info: 53000 | 17526 34550 | 298 658 | 7195| 0.26 16.15|
Info: 54000 | 17995 35058 | 469 508 | 6741| 0.34 16.48|
Info: 55000 | 18338 35695 | 343 637 | 6130| 0.30 16.78|
Info: 56000 | 18396 36625 | 58 930 | 5214| 0.14 16.93|
Info: 57000 | 18410 37610 | 14 985 | 4230| 0.10 17.03|
Info: 58000 | 18437 38580 | 27 970 | 3259| 0.10 17.13|
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:00:45 ; elapsed = 00:00:45 . Memory (MB): peak = 2283.320 ; gain = 658.281 ; free physical = 332 ; free virtual = 23885
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:00:45 ; elapsed = 00:00:45 . Memory (MB): peak = 2283.320 ; gain = 658.281 ; free physical = 332 ; free virtual = 23885
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
Info: 59000 | 18508 39472 | 71 892 | 2338| 0.20 17.33|
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:45 ; elapsed = 00:00:45 . Memory (MB): peak = 2283.320 ; gain = 658.281 ; free physical = 310 ; free virtual = 23864
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:00:45 ; elapsed = 00:00:45 . Memory (MB): peak = 2283.320 ; gain = 658.281 ; free physical = 329 ; free virtual = 23882
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:45 ; elapsed = 00:00:45 . Memory (MB): peak = 2283.320 ; gain = 658.281 ; free physical = 324 ; free virtual = 23877
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:00:45 ; elapsed = 00:00:45 . Memory (MB): peak = 2283.320 ; gain = 658.281 ; free physical = 323 ; free virtual = 23876
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------
Report BlackBoxes:
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+
Report Cell Usage:
+------+----------+------+
| |Cell |Count |
+------+----------+------+
|1 |BUFG | 2|
|2 |CARRY4 | 71|
|3 |LUT1 | 19|
|4 |LUT2 | 185|
|5 |LUT3 | 258|
|6 |LUT4 | 308|
|7 |LUT5 | 260|
|8 |LUT6 | 1515|
|9 |MUXF7 | 458|
|10 |MUXF8 | 15|
|11 |RAM256X1S | 64|
|12 |RAM32M | 2|
|13 |RAM32X1D | 4|
|14 |FDRE | 2091|
|15 |FDSE | 4|
|16 |IBUF | 3|
|17 |IOBUF | 8|
|18 |OBUF | 9|
+------+----------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:45 ; elapsed = 00:00:45 . Memory (MB): peak = 2283.320 ; gain = 658.281 ; free physical = 322 ; free virtual = 23875
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 63 warnings.
Info: 60000 | 18652 40255 | 144 783 | 1492| 0.30 17.63|
Synthesis Optimization Runtime : Time (s): cpu = 00:00:43 ; elapsed = 00:00:43 . Memory (MB): peak = 2283.320 ; gain = 510.496 ; free physical = 321 ; free virtual = 23875
Synthesis Optimization Complete : Time (s): cpu = 00:00:45 ; elapsed = 00:00:45 . Memory (MB): peak = 2283.320 ; gain = 658.281 ; free physical = 320 ; free virtual = 23874
INFO: [Project 1-571] Translating synthesized netlist
Info: 61000 | 18745 41099 | 93 844 | 604| 0.35 17.98|
Info: 61620 | 18759 41441 | 14 342 | 0| 0.15 18.13|
Info: Routing complete.
Info: Router1 time 18.13s
Info: Checksum: 0xcbf7c795
Netlist sorting complete. Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2283.320 ; gain = 0.000 ; free physical = 602 ; free virtual = 24155
INFO: [Netlist 29-17] Analyzing 622 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
Info: curr total
Info: 0.5 0.5 Source SOC.Core.Control_Unit.state_TRELLIS_FF_Q_3.Q
Info: 1.8 2.4 Net SOC.Leds.write_LUT4_Z_C_LUT4_Z_B[1] (20,33) -> (23,42)
Info: Sink SOC.Core.Control_Unit.nextstate_LUT4_Z_4_B_LUT4_D_B_LUT4_Z.B
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 2.6 Source SOC.Core.Control_Unit.nextstate_LUT4_Z_4_B_LUT4_D_B_LUT4_Z.F
Info: 0.6 3.2 Net SOC.Core.Control_Unit.nextstate_LUT4_Z_4_B[1] (23,42) -> (23,42)
Info: Sink SOC.Core.Control_Unit.nextstate_LUT4_Z_4_B_LUT4_D_B_LUT4_D.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 3.5 Source SOC.Core.Control_Unit.nextstate_LUT4_Z_4_B_LUT4_D_B_LUT4_D.F
Info: 0.8 4.2 Net SOC.Core.Control_Unit.nextstate_LUT4_Z_4_B_LUT4_D_B_LUT4_D_Z[3] (23,42) -> (22,41)
Info: Sink SOC.Core.Control_Unit.nextstate_LUT4_Z_4_B_LUT4_D_B_LUT4_D_Z_LUT4_C_1.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 4.5 Source SOC.Core.Control_Unit.nextstate_LUT4_Z_4_B_LUT4_D_B_LUT4_D_Z_LUT4_C_1.F
Info: 0.4 4.9 Net SOC.Leds.write_LUT4_Z_C[1] (22,41) -> (22,41)
Info: Sink SOC.Leds.write_LUT4_Z_C_LUT4_C.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 5.1 Source SOC.Leds.write_LUT4_Z_C_LUT4_C.F
Info: 1.3 6.4 Net SOC.Leds.write_LUT4_Z_C_LUT4_C_Z[2] (22,41) -> (19,44)
Info: Sink SOC.GPIOS.address_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 6.6 Source SOC.GPIOS.address_LUT4_Z.F
Info: 2.3 8.9 Net SOC.address[5] (19,44) -> (9,51)
Info: Sink SOC.Memory.memory.0.81$DPRAM_COMB3.A
Info: Defined in:
Info: Risco-5/src/peripheral/soc.v:23.5-23.18
Info: 0.2 9.2 Source SOC.Memory.memory.0.81$DPRAM_COMB3.F
Info: 0.8 10.0 Net SOC.Memory.memory.0.73_DO[0] (9,51) -> (10,51)
Info: Sink SOC.Memory.memory.0.65_DO_LUT4_Z_2.A
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 10.3 Source SOC.Memory.memory.0.65_DO_LUT4_Z_2.F
Info: 0.7 11.0 Net SOC.Memory.memory.0.65_DO[4] (10,51) -> (10,50)
Info: Sink SOC.Memory.memory.0.193_DO_LUT4_A_Z_PFUMX_Z_BLUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 11.2 Source SOC.Memory.memory.0.193_DO_LUT4_A_Z_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: 0.4 11.7 Net SOC.Memory.memory.0.193_DO_LUT4_A_Z[3] (10,50) -> (12,50)
Info: Sink SOC.Memory.memory.0.225_DO_LUT4_A_Z_LUT4_Z_1.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 11.9 Source SOC.Memory.memory.0.225_DO_LUT4_A_Z_LUT4_Z_1.F
Info: 1.3 13.2 Net SOC.Memory.memory.0.225_DO_LUT4_A_Z[4] (12,50) -> (15,47)
Info: Sink SOC.GPIOS.Gpios[0].data_in_LUT4_C_Z_LUT4_Z_1_D_LUT4_Z_C_LUT4_B_Z_PFUMX_Z_BLUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 13.4 Source SOC.GPIOS.Gpios[0].data_in_LUT4_C_Z_LUT4_Z_1_D_LUT4_Z_C_LUT4_B_Z_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: 1.0 14.4 Net SOC.Core.read_data_PFUMX_Z_BLUT_LUT4_Z_D[4] (15,47) -> (16,44)
Info: Sink SOC.Memory.memory.0.67_DO_2_LUT4_A_Z_PFUMX_C0_Z_PFUMX_Z_1_BLUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 14.6 Source SOC.Memory.memory.0.67_DO_2_LUT4_A_Z_PFUMX_C0_Z_PFUMX_Z_1_BLUT_LUT4_Z.OFX
Info: 2.3 16.9 Net SOC.Core.read_data_LUT4_Z_10_B[2] (16,44) -> (32,36)
Info: Sink SOC.Core.read_data_LUT4_Z_22.B
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 17.2 Source SOC.Core.read_data_LUT4_Z_22.F
Info: 0.8 17.9 Net SOC.read_data[26] (32,36) -> (32,35)
Info: Sink SOC.Core.instruction_register_TRELLIS_FF_Q_5.M
Info: Defined in:
Info: Risco-5/src/peripheral/soc.v:22.34-22.43
Info: 0.0 17.9 Setup SOC.Core.instruction_register_TRELLIS_FF_Q_5.M
Info: 3.4 ns logic, 14.5 ns routing
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
Info: curr total
Info: 0.0 0.0 Source gpios[5]$tr_io.O
Info: 2.2 2.2 Net gpios[5]$TRELLIS_IO_IN (9,71) -> (9,54)
Info: Sink SOC.GPIOS.Gpios[5].data_in_LUT4_B.A
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:7.16-7.21
Info: 0.2 2.5 Source SOC.GPIOS.Gpios[5].data_in_LUT4_B.F
Info: 1.4 3.9 Net SOC.GPIOS.Gpios[5].data_in_LUT4_B_Z[4] (9,54) -> (10,44)
Info: Sink SOC.GPIOS.Gpios[5].data_in_LUT4_B_Z_PFUMX_C0_BLUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 4.1 Source SOC.GPIOS.Gpios[5].data_in_LUT4_B_Z_PFUMX_C0_BLUT_LUT4_Z.OFX
Info: 1.0 5.1 Net SOC.GPIOS.Gpios[5].data_in_LUT4_B_Z_PFUMX_C0_Z[1] (10,44) -> (12,44)
Info: Sink SOC.Core.read_data_LUT4_Z_5.B
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 5.3 Source SOC.Core.read_data_LUT4_Z_5.F
Info: 1.4 6.7 Net SOC.read_data[5] (12,44) -> (13,38)
Info: Sink SOC.Core.instruction_register_TRELLIS_FF_Q_25.M
Info: Defined in:
Info: Risco-5/src/peripheral/soc.v:22.34-22.43
Info: 0.0 6.7 Setup SOC.Core.instruction_register_TRELLIS_FF_Q_25.M
Info: 0.7 ns logic, 6.0 ns routing
Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
Info: curr total
Info: 0.5 0.5 Source SOC.Leds.data_TRELLIS_FF_Q_24.Q
Info: 3.1 3.6 Net SOC.Leds.data[7] (25,41) -> (56,26)
Info: Sink led_LUT4_Z_2.D
Info: Defined in:
Info: Risco-5/src/peripheral/leds.v:15.12-15.16
Info: 0.2 3.9 Source led_LUT4_Z_2.F
Info: 2.7 6.6 Net led[7]$TRELLIS_IO_OUT (56,26) -> (90,20)
Info: Sink led[7]$tr_io.I
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:6.22-6.25
Info: 0.8 ns logic, 5.8 ns routing
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 55.79 MHz (PASS at 25.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 6.69 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 6.56 ns
Info: Slack histogram:
Info: legend: * represents 48 endpoint(s)
Info: + represents [1,48) endpoint(s)
Info: [ 22076, 22925) |+
Info: [ 22925, 23774) |*+
Info: [ 23774, 24623) |*********+
Info: [ 24623, 25472) |***+
Info: [ 25472, 26321) |*+
Info: [ 26321, 27170) |*****+
Info: [ 27170, 28019) |***************+
Info: [ 28019, 28868) |***********+
Info: [ 28868, 29717) |*+
Info: [ 29717, 30566) |*******+
Info: [ 30566, 31415) |************************************+
Info: [ 31415, 32264) |************************************************************
Info: [ 32264, 33113) |*********+
Info: [ 33113, 33962) |****+
Info: [ 33962, 34811) |***+
Info: [ 34811, 35660) |***+
Info: [ 35660, 36509) |********+
Info: [ 36509, 37358) |*******+
Info: [ 37358, 38207) |*********+
Info: [ 38207, 39056) |*****+
Parsing XDC File [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc]
Finished Parsing XDC File [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2347.316 ; gain = 0.000 ; free physical = 536 ; free virtual = 24106
INFO: [Project 1-111] Unisim Transformation Summary:
A total of 78 instances were transformed.
IOBUF => IOBUF (IBUF, OBUFT): 8 instances
RAM256X1S => RAM256X1S (MUXF7(x2), MUXF8, RAMS64E(x4)): 64 instances
RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 2 instances
RAM32X1D => RAM32X1D (RAMD32(x2)): 4 instances
Info: Program finished normally.
Synth Design complete | Checksum: 4323e98b
INFO: [Common 17-83] Releasing license: Synthesis
79 Infos, 112 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:55 ; elapsed = 00:00:52 . Memory (MB): peak = 2347.352 ; gain = 1029.289 ; free physical = 870 ; free virtual = 24443
INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 2024.216; main = 1745.663; forked = 422.461
INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3220.926; main = 2347.320; forked = 969.652
# opt_design
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command opt_design
Starting DRC Task
[Pipeline] }
INFO: [DRC 23-27] Running DRC with 8 threads
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (ECPPACK)
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.7 . Memory (MB): peak = 2411.348 ; gain = 63.996 ; free physical = 863 ; free virtual = 24436
Starting Cache Timing Information Task
[Pipeline] sh
+ /eda/oss-cad-suite/bin/ecppack --compress --input ./build/out.config --bit ./build/out.bit
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
INFO: [Timing 38-35] Done setting XDC timing constraints.
Ending Cache Timing Information Task | Checksum: 146decbe9
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2521.160 ; gain = 109.812 ; free physical = 802 ; free virtual = 24376
Starting Logic Optimization Task
Phase 1 Initialization
Phase 1.1 Core Generation And Design Setup
Phase 1.1 Core Generation And Design Setup | Checksum: 146decbe9
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2771.066 ; gain = 0.000 ; free physical = 532 ; free virtual = 24106
Phase 1.2 Setup Constraints And Sort Netlist
Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 146decbe9
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2771.066 ; gain = 0.000 ; free physical = 532 ; free virtual = 24106
Phase 1 Initialization | Checksum: 146decbe9
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2771.066 ; gain = 0.000 ; free physical = 532 ; free virtual = 24106
Phase 2 Timer Update And Timing Data Collection
Phase 2.1 Timer Update
Phase 2.1 Timer Update | Checksum: 146decbe9
Time (s): cpu = 00:00:00.18 ; elapsed = 00:00:00.06 . Memory (MB): peak = 2771.066 ; gain = 0.000 ; free physical = 532 ; free virtual = 24106
Phase 2.2 Timing Data Collection
Phase 2.2 Timing Data Collection | Checksum: 146decbe9
Time (s): cpu = 00:00:00.19 ; elapsed = 00:00:00.07 . Memory (MB): peak = 2771.066 ; gain = 0.000 ; free physical = 532 ; free virtual = 24106
Phase 2 Timer Update And Timing Data Collection | Checksum: 146decbe9
Time (s): cpu = 00:00:00.19 ; elapsed = 00:00:00.07 . Memory (MB): peak = 2771.066 ; gain = 0.000 ; free physical = 532 ; free virtual = 24106
Phase 3 Retarget
INFO: [Opt 31-1566] Pulled 5 inverters resulting in an inversion of 15 pins
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 3 Retarget | Checksum: 1823b20f2
Time (s): cpu = 00:00:00.3 ; elapsed = 00:00:00.15 . Memory (MB): peak = 2771.066 ; gain = 0.000 ; free physical = 532 ; free virtual = 24106
Retarget | Checksum: 1823b20f2
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 5 cells
Phase 4 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 4 Constant propagation | Checksum: 1823b20f2
Time (s): cpu = 00:00:00.34 ; elapsed = 00:00:00.19 . Memory (MB): peak = 2771.066 ; gain = 0.000 ; free physical = 532 ; free virtual = 24106
Constant propagation | Checksum: 1823b20f2
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
Phase 5 Sweep
Phase 5 Sweep | Checksum: 20fd107b2
Time (s): cpu = 00:00:00.38 ; elapsed = 00:00:00.24 . Memory (MB): peak = 2771.066 ; gain = 0.000 ; free physical = 531 ; free virtual = 24105
Sweep | Checksum: 20fd107b2
INFO: [Opt 31-389] Phase Sweep created 8 cells and removed 0 cells
Phase 6 BUFG optimization
Phase 6 BUFG optimization | Checksum: 20fd107b2
Time (s): cpu = 00:00:00.47 ; elapsed = 00:00:00.28 . Memory (MB): peak = 2803.082 ; gain = 32.016 ; free physical = 531 ; free virtual = 24105
BUFG optimization | Checksum: 20fd107b2
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
Phase 7 Shift Register Optimization
INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
Phase 7 Shift Register Optimization | Checksum: 20fd107b2
Time (s): cpu = 00:00:00.48 ; elapsed = 00:00:00.29 . Memory (MB): peak = 2803.082 ; gain = 32.016 ; free physical = 531 ; free virtual = 24105
Shift Register Optimization | Checksum: 20fd107b2
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
Phase 8 Post Processing Netlist
Phase 8 Post Processing Netlist | Checksum: 1b2306da5
Time (s): cpu = 00:00:00.49 ; elapsed = 00:00:00.3 . Memory (MB): peak = 2803.082 ; gain = 32.016 ; free physical = 531 ; free virtual = 24105
Post Processing Netlist | Checksum: 1b2306da5
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
Phase 9 Finalization
Phase 9.1 Finalizing Design Cores and Updating Shapes
Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 13af42843
Time (s): cpu = 00:00:00.57 ; elapsed = 00:00:00.35 . Memory (MB): peak = 2803.082 ; gain = 32.016 ; free physical = 531 ; free virtual = 24105
Phase 9.2 Verifying Netlist Connectivity
Starting Connectivity Check Task
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2803.082 ; gain = 0.000 ; free physical = 531 ; free virtual = 24105
Phase 9.2 Verifying Netlist Connectivity | Checksum: 13af42843
Time (s): cpu = 00:00:00.58 ; elapsed = 00:00:00.36 . Memory (MB): peak = 2803.082 ; gain = 32.016 ; free physical = 531 ; free virtual = 24105
Phase 9 Finalization | Checksum: 13af42843
Time (s): cpu = 00:00:00.58 ; elapsed = 00:00:00.36 . Memory (MB): peak = 2803.082 ; gain = 32.016 ; free physical = 531 ; free virtual = 24105
Opt_design Change Summary
=========================
-------------------------------------------------------------------------------------------------------------------------
| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
-------------------------------------------------------------------------------------------------------------------------
| Retarget | 0 | 5 | 0 |
| Constant propagation | 0 | 0 | 0 |
| Sweep | 8 | 0 | 0 |
| BUFG optimization | 0 | 0 | 0 |
| Shift Register Optimization | 0 | 0 | 0 |
| Post Processing Netlist | 0 | 0 | 0 |
-------------------------------------------------------------------------------------------------------------------------
Ending Logic Optimization Task | Checksum: 13af42843
Time (s): cpu = 00:00:00.58 ; elapsed = 00:00:00.36 . Memory (MB): peak = 2803.082 ; gain = 32.016 ; free physical = 531 ; free virtual = 24105
INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8
Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2803.082 ; gain = 0.000 ; free physical = 531 ; free virtual = 24105
Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
Ending Power Optimization Task | Checksum: 13af42843
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2803.082 ; gain = 0.000 ; free physical = 531 ; free virtual = 24105
Starting Final Cleanup Task
Ending Final Cleanup Task | Checksum: 13af42843
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2803.082 ; gain = 0.000 ; free physical = 531 ; free virtual = 24105
Starting Netlist Obfuscation Task
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2803.082 ; gain = 0.000 ; free physical = 531 ; free virtual = 24105
Ending Netlist Obfuscation Task | Checksum: 13af42843
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2803.082 ; gain = 0.000 ; free physical = 531 ; free virtual = 24105
INFO: [Common 17-83] Releasing license: Implementation
19 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 2803.082 ; gain = 455.730 ; free physical = 531 ; free virtual = 24105
# place_design
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-83] Releasing license: Implementation
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs
Starting Placer Task
Phase 1 Placer Initialization
Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2835.098 ; gain = 0.000 ; free physical = 528 ; free virtual = 24102
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: c04d5782
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2835.098 ; gain = 0.000 ; free physical = 528 ; free virtual = 24102
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2835.098 ; gain = 0.000 ; free physical = 528 ; free virtual = 24102
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: bad7e1af
Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.79 . Memory (MB): peak = 2835.098 ; gain = 0.000 ; free physical = 531 ; free virtual = 24106
Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: bdb759a9
Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2842.125 ; gain = 7.027 ; free physical = 531 ; free virtual = 24105
Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: bdb759a9
Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2842.125 ; gain = 7.027 ; free physical = 531 ; free virtual = 24105
Phase 1 Placer Initialization | Checksum: bdb759a9
Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2842.125 ; gain = 7.027 ; free physical = 531 ; free virtual = 24105
Phase 2 Global Placement
Phase 2.1 Floorplanning
Phase 2.1 Floorplanning | Checksum: d65f425b
Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 2842.125 ; gain = 7.027 ; free physical = 528 ; free virtual = 24102
Phase 2.2 Update Timing before SLR Path Opt
Phase 2.2 Update Timing before SLR Path Opt | Checksum: 15c583a28
Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 2842.125 ; gain = 7.027 ; free physical = 528 ; free virtual = 24102
Phase 2.3 Post-Processing in Floorplanning
Phase 2.3 Post-Processing in Floorplanning | Checksum: 15c583a28
Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 2842.125 ; gain = 7.027 ; free physical = 528 ; free virtual = 24102
Phase 2.4 Global Placement Core
Phase 2.4.1 UpdateTiming Before Physical Synthesis
Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 13270fcb8
Time (s): cpu = 00:00:15 ; elapsed = 00:00:04 . Memory (MB): peak = 2842.125 ; gain = 7.027 ; free physical = 523 ; free virtual = 24097
Phase 2.4.2 Physical Synthesis In Placer
INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 89 LUT instances to create LUTNM shape
INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0
INFO: [Physopt 32-1138] End 1 Pass. Optimized 34 nets or LUTs. Breaked 0 LUT, combined 34 existing LUTs and moved 0 existing LUT
INFO: [Physopt 32-65] No nets found for high-fanout optimization.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found. Shift Register to Pipeline Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found. URAM Register Optimization was not performed.
INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2842.125 ; gain = 0.000 ; free physical = 523 ; free virtual = 24097
Summary of Physical Synthesis Optimizations
============================================
-----------------------------------------------------------------------------------------------------------------------------------------------------------
| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |
-----------------------------------------------------------------------------------------------------------------------------------------------------------
| LUT Combining | 0 | 34 | 34 | 0 | 1 | 00:00:00 |
| Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| Shift Register to Pipeline | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| URAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| Total | 0 | 34 | 34 | 0 | 4 | 00:00:00 |
-----------------------------------------------------------------------------------------------------------------------------------------------------------
Phase 2.4.2 Physical Synthesis In Placer | Checksum: 1456691e6
Time (s): cpu = 00:00:15 ; elapsed = 00:00:05 . Memory (MB): peak = 2842.125 ; gain = 7.027 ; free physical = 523 ; free virtual = 24097
Phase 2.4 Global Placement Core | Checksum: 11d0214de
Time (s): cpu = 00:00:20 ; elapsed = 00:00:05 . Memory (MB): peak = 2842.125 ; gain = 7.027 ; free physical = 523 ; free virtual = 24097
Phase 2 Global Placement | Checksum: 11d0214de
Time (s): cpu = 00:00:20 ; elapsed = 00:00:05 . Memory (MB): peak = 2842.125 ; gain = 7.027 ; free physical = 523 ; free virtual = 24097
Phase 3 Detail Placement
Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: 1a95a0775
Time (s): cpu = 00:00:20 ; elapsed = 00:00:05 . Memory (MB): peak = 2842.125 ; gain = 7.027 ; free physical = 523 ; free virtual = 24097
Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 123e0a448
Time (s): cpu = 00:00:20 ; elapsed = 00:00:05 . Memory (MB): peak = 2842.125 ; gain = 7.027 ; free physical = 523 ; free virtual = 24097
Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 15c081164
Time (s): cpu = 00:00:20 ; elapsed = 00:00:05 . Memory (MB): peak = 2842.125 ; gain = 7.027 ; free physical = 523 ; free virtual = 24097
Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: 104d545db
Time (s): cpu = 00:00:20 ; elapsed = 00:00:05 . Memory (MB): peak = 2842.125 ; gain = 7.027 ; free physical = 523 ; free virtual = 24097
Phase 3.5 Small Shape Detail Placement
Phase 3.5 Small Shape Detail Placement | Checksum: 150d95eed
Time (s): cpu = 00:00:22 ; elapsed = 00:00:07 . Memory (MB): peak = 2842.125 ; gain = 7.027 ; free physical = 524 ; free virtual = 24098
Phase 3.6 Re-assign LUT pins
Phase 3.6 Re-assign LUT pins | Checksum: fe87775e
Time (s): cpu = 00:00:22 ; elapsed = 00:00:07 . Memory (MB): peak = 2842.125 ; gain = 7.027 ; free physical = 524 ; free virtual = 24098
Phase 3.7 Pipeline Register Optimization
Phase 3.7 Pipeline Register Optimization | Checksum: 1575cc3c3
Time (s): cpu = 00:00:22 ; elapsed = 00:00:07 . Memory (MB): peak = 2842.125 ; gain = 7.027 ; free physical = 524 ; free virtual = 24098
Phase 3 Detail Placement | Checksum: 1575cc3c3
Time (s): cpu = 00:00:22 ; elapsed = 00:00:07 . Memory (MB): peak = 2842.125 ; gain = 7.027 ; free physical = 524 ; free virtual = 24098
Phase 4 Post Placement Optimization and Clean-Up
Phase 4.1 Post Commit Optimization
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 4.1.1 Post Placement Optimization
Post Placement Optimization Initialization | Checksum: 12b1c98e3
Phase 4.1.1.1 BUFG Insertion
Starting Physical Synthesis Task
Phase 1 Physical Synthesis Initialization
INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=9.081 | TNS=0.000 |
Phase 1 Physical Synthesis Initialization | Checksum: 1722e4068
Time (s): cpu = 00:00:00.22 ; elapsed = 00:00:00.08 . Memory (MB): peak = 2842.125 ; gain = 0.000 ; free physical = 524 ; free virtual = 24098
INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0.
Ending Physical Synthesis Task | Checksum: 1722e4068
Time (s): cpu = 00:00:00.27 ; elapsed = 00:00:00.13 . Memory (MB): peak = 2842.125 ; gain = 0.000 ; free physical = 524 ; free virtual = 24098
Phase 4.1.1.1 BUFG Insertion | Checksum: 12b1c98e3
Time (s): cpu = 00:00:25 ; elapsed = 00:00:08 . Memory (MB): peak = 2842.125 ; gain = 7.027 ; free physical = 524 ; free virtual = 24098
Phase 4.1.1.2 Post Placement Timing Optimization
INFO: [Place 30-746] Post Placement Timing Summary WNS=9.081. For the most accurate timing information please run report_timing.
Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 12ce860c2
Time (s): cpu = 00:00:25 ; elapsed = 00:00:08 . Memory (MB): peak = 2842.125 ; gain = 7.027 ; free physical = 524 ; free virtual = 24098
Time (s): cpu = 00:00:25 ; elapsed = 00:00:08 . Memory (MB): peak = 2842.125 ; gain = 7.027 ; free physical = 524 ; free virtual = 24098
Phase 4.1 Post Commit Optimization | Checksum: 12ce860c2
Time (s): cpu = 00:00:25 ; elapsed = 00:00:08 . Memory (MB): peak = 2842.125 ; gain = 7.027 ; free physical = 524 ; free virtual = 24098
Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: 12ce860c2
Time (s): cpu = 00:00:25 ; elapsed = 00:00:08 . Memory (MB): peak = 2842.125 ; gain = 7.027 ; free physical = 524 ; free virtual = 24098
Phase 4.3 Placer Reporting
Phase 4.3.1 Print Estimated Congestion
INFO: [Place 30-612] Post-Placement Estimated Congestion
____________________________________________________
| | Global Congestion | Short Congestion |
| Direction | Region Size | Region Size |
|___________|___________________|___________________|
| North| 1x1| 2x2|
|___________|___________________|___________________|
| South| 1x1| 1x1|
|___________|___________________|___________________|
| East| 1x1| 1x1|
|___________|___________________|___________________|
| West| 1x1| 1x1|
|___________|___________________|___________________|
Phase 4.3.1 Print Estimated Congestion | Checksum: 12ce860c2
Time (s): cpu = 00:00:26 ; elapsed = 00:00:08 . Memory (MB): peak = 2842.125 ; gain = 7.027 ; free physical = 524 ; free virtual = 24098
Phase 4.3 Placer Reporting | Checksum: 12ce860c2
Time (s): cpu = 00:00:26 ; elapsed = 00:00:08 . Memory (MB): peak = 2842.125 ; gain = 7.027 ; free physical = 524 ; free virtual = 24098
Phase 4.4 Final Placement Cleanup
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2842.125 ; gain = 0.000 ; free physical = 524 ; free virtual = 24098
Time (s): cpu = 00:00:26 ; elapsed = 00:00:08 . Memory (MB): peak = 2842.125 ; gain = 7.027 ; free physical = 524 ; free virtual = 24098
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 862fa997
Time (s): cpu = 00:00:26 ; elapsed = 00:00:08 . Memory (MB): peak = 2842.125 ; gain = 7.027 ; free physical = 524 ; free virtual = 24098
Ending Placer Task | Checksum: 50ceb87c
Time (s): cpu = 00:00:26 ; elapsed = 00:00:08 . Memory (MB): peak = 2842.125 ; gain = 7.027 ; free physical = 524 ; free virtual = 24098
29 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
place_design: Time (s): cpu = 00:00:27 ; elapsed = 00:00:09 . Memory (MB): peak = 2842.125 ; gain = 39.043 ; free physical = 524 ; free virtual = 24098
# report_utilization -hierarchical -file digilent_nexys4ddr_utilization_hierarchical_place.rpt
# report_utilization -file digilent_nexys4ddr_utilization_place.rpt
# report_io -file digilent_nexys4ddr_io.rpt
report_io: Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.16 . Memory (MB): peak = 2842.125 ; gain = 0.000 ; free physical = 515 ; free virtual = 24089
# report_control_sets -verbose -file digilent_nexys4ddr_control_sets.rpt
report_control_sets: Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.1 . Memory (MB): peak = 2842.125 ; gain = 0.000 ; free physical = 523 ; free virtual = 24097
# report_clock_utilization -file digilent_nexys4ddr_clock_utilization.rpt
# route_design
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command route_design
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs
Phase 1 Build RT Design
Checksum: PlaceDB: 20ab9d53 ConstDB: 0 ShapeSum: 30231b29 RouteDB: 0
[50%] Placement Phase 3 completed
Running routing......
[60%] Routing Phase 0 completed
[70%] Routing Phase 1 completed
[80%] Routing Phase 2 completed
Post Restoration Checksum: NetGraph: 38316509 | NumContArr: 4ed83706 | Constraints: c2a8fa9d | Timing: c2a8fa9d
Phase 1 Build RT Design | Checksum: 20c5b9149
Time (s): cpu = 00:00:33 ; elapsed = 00:00:27 . Memory (MB): peak = 2842.125 ; gain = 0.000 ; free physical = 433 ; free virtual = 24007
Phase 2 Router Initialization
Phase 2.1 Fix Topology Constraints
Phase 2.1 Fix Topology Constraints | Checksum: 20c5b9149
Time (s): cpu = 00:00:33 ; elapsed = 00:00:27 . Memory (MB): peak = 2842.125 ; gain = 0.000 ; free physical = 433 ; free virtual = 24007
Phase 2.2 Pre Route Cleanup
Phase 2.2 Pre Route Cleanup | Checksum: 20c5b9149
Time (s): cpu = 00:00:33 ; elapsed = 00:00:27 . Memory (MB): peak = 2842.125 ; gain = 0.000 ; free physical = 433 ; free virtual = 24007
Number of Nodes with overlaps = 0
Phase 2.3 Update Timing
Phase 2.3 Update Timing | Checksum: 2a589208d
Time (s): cpu = 00:00:37 ; elapsed = 00:00:28 . Memory (MB): peak = 2842.125 ; gain = 0.000 ; free physical = 405 ; free virtual = 23979
INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.996 | TNS=0.000 | WHS=-0.066 | THS=-0.066 |
Router Utilization Summary
Global Vertical Routing Utilization = 8.70436e-05 %
Global Horizontal Routing Utilization = 7.10429e-05 %
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
Number of Failed Nets = 3835
(Failed Nets is the sum of unrouted and partially routed nets)
Number of Unrouted Nets = 3834
Number of Partially Routed Nets = 1
Number of Node Overlaps = 0
Phase 2 Router Initialization | Checksum: 2dc8ebc9d
Time (s): cpu = 00:00:39 ; elapsed = 00:00:29 . Memory (MB): peak = 2842.125 ; gain = 0.000 ; free physical = 398 ; free virtual = 23972
Phase 3 Initial Routing
Phase 3.1 Global Routing
Phase 3.1 Global Routing | Checksum: 2dc8ebc9d
Time (s): cpu = 00:00:39 ; elapsed = 00:00:29 . Memory (MB): peak = 2842.125 ; gain = 0.000 ; free physical = 398 ; free virtual = 23972
Phase 3.2 Initial Net Routing
Phase 3.2 Initial Net Routing | Checksum: 216aa9269
Time (s): cpu = 00:00:41 ; elapsed = 00:00:29 . Memory (MB): peak = 2842.125 ; gain = 0.000 ; free physical = 391 ; free virtual = 23966
Phase 3 Initial Routing | Checksum: 216aa9269
Time (s): cpu = 00:00:41 ; elapsed = 00:00:29 . Memory (MB): peak = 2842.125 ; gain = 0.000 ; free physical = 400 ; free virtual = 23974
Phase 4 Rip-up And Reroute
Phase 4.1 Global Iteration 0
Number of Nodes with overlaps = 570
Number of Nodes with overlaps = 3
Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.788 | TNS=0.000 | WHS=N/A | THS=N/A |
Phase 4.1 Global Iteration 0 | Checksum: 1fcf7f3f8
Time (s): cpu = 00:00:44 ; elapsed = 00:00:30 . Memory (MB): peak = 2842.125 ; gain = 0.000 ; free physical = 395 ; free virtual = 23970
Phase 4 Rip-up And Reroute | Checksum: 1fcf7f3f8
Time (s): cpu = 00:00:44 ; elapsed = 00:00:30 . Memory (MB): peak = 2842.125 ; gain = 0.000 ; free physical = 395 ; free virtual = 23970
Phase 5 Delay and Skew Optimization
Phase 5.1 Delay CleanUp
Phase 5.1 Delay CleanUp | Checksum: 1fcf7f3f8
Time (s): cpu = 00:00:44 ; elapsed = 00:00:30 . Memory (MB): peak = 2842.125 ; gain = 0.000 ; free physical = 395 ; free virtual = 23970
Phase 5.2 Clock Skew Optimization
Phase 5.2 Clock Skew Optimization | Checksum: 1fcf7f3f8
Time (s): cpu = 00:00:44 ; elapsed = 00:00:30 . Memory (MB): peak = 2842.125 ; gain = 0.000 ; free physical = 395 ; free virtual = 23970
Phase 5 Delay and Skew Optimization | Checksum: 1fcf7f3f8
Time (s): cpu = 00:00:44 ; elapsed = 00:00:30 . Memory (MB): peak = 2842.125 ; gain = 0.000 ; free physical = 395 ; free virtual = 23970
Phase 6 Post Hold Fix
Phase 6.1 Hold Fix Iter
Phase 6.1.1 Update Timing
Phase 6.1.1 Update Timing | Checksum: 22b9bb45d
Time (s): cpu = 00:00:44 ; elapsed = 00:00:30 . Memory (MB): peak = 2842.125 ; gain = 0.000 ; free physical = 395 ; free virtual = 23970
INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.884 | TNS=0.000 | WHS=0.247 | THS=0.000 |
Phase 6.1 Hold Fix Iter | Checksum: 22b9bb45d
Time (s): cpu = 00:00:44 ; elapsed = 00:00:30 . Memory (MB): peak = 2842.125 ; gain = 0.000 ; free physical = 395 ; free virtual = 23970
Phase 6 Post Hold Fix | Checksum: 22b9bb45d
Time (s): cpu = 00:00:44 ; elapsed = 00:00:30 . Memory (MB): peak = 2842.125 ; gain = 0.000 ; free physical = 395 ; free virtual = 23970
Phase 7 Route finalize
Router Utilization Summary
Global Vertical Routing Utilization = 0.781825 %
Global Horizontal Routing Utilization = 0.994317 %
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
Number of Failed Nets = 0
(Failed Nets is the sum of unrouted and partially routed nets)
Number of Unrouted Nets = 0
Number of Partially Routed Nets = 0
Number of Node Overlaps = 0
Phase 7 Route finalize | Checksum: 22b9bb45d
Time (s): cpu = 00:00:44 ; elapsed = 00:00:30 . Memory (MB): peak = 2842.125 ; gain = 0.000 ; free physical = 395 ; free virtual = 23970
Phase 8 Verifying routed nets
Verification completed successfully
Phase 8 Verifying routed nets | Checksum: 22b9bb45d
Time (s): cpu = 00:00:44 ; elapsed = 00:00:30 . Memory (MB): peak = 2842.125 ; gain = 0.000 ; free physical = 395 ; free virtual = 23970
Phase 9 Depositing Routes
Phase 9 Depositing Routes | Checksum: 20bb02aaf
Time (s): cpu = 00:00:45 ; elapsed = 00:00:31 . Memory (MB): peak = 2842.125 ; gain = 0.000 ; free physical = 395 ; free virtual = 23970
Phase 10 Post Router Timing
INFO: [Route 35-57] Estimated Timing Summary | WNS=8.884 | TNS=0.000 | WHS=0.247 | THS=0.000 |
INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
Phase 10 Post Router Timing | Checksum: 20bb02aaf
Time (s): cpu = 00:00:45 ; elapsed = 00:00:31 . Memory (MB): peak = 2842.125 ; gain = 0.000 ; free physical = 395 ; free virtual = 23970
INFO: [Route 35-16] Router Completed Successfully
Phase 11 Post-Route Event Processing
Phase 11 Post-Route Event Processing | Checksum: 12a061842
Time (s): cpu = 00:00:45 ; elapsed = 00:00:31 . Memory (MB): peak = 2842.125 ; gain = 0.000 ; free physical = 395 ; free virtual = 23970
Ending Routing Task | Checksum: 12a061842
Time (s): cpu = 00:00:45 ; elapsed = 00:00:31 . Memory (MB): peak = 2842.125 ; gain = 0.000 ; free physical = 395 ; free virtual = 23970
Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
12 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:00:47 ; elapsed = 00:00:32 . Memory (MB): peak = 2842.125 ; gain = 0.000 ; free physical = 395 ; free virtual = 23970
# report_timing_summary -no_header -no_detailed_paths
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------
Enable Multi Corner Analysis : Yes
Enable Pessimism Removal : Yes
Pessimism Removal Resolution : Nearest Common Node
Enable Input Delay Default Clock : No
Enable Preset / Clear Arcs : No
Disable Flight Delays : No
Ignore I/O Paths : No
Timing Early Launch at Borrowing Latches : No
Borrow Time for Max Delay Exceptions : Yes
Merge Timing Exceptions : Yes
Inter-SLR Compensation : Conservative
Corner Analyze Analyze
Name Max Paths Min Paths
------ --------- ---------
Slow Yes Yes
Fast Yes Yes
------------------------------------------------------------------------------------------------
| Report Methodology
| ------------------
------------------------------------------------------------------------------------------------
No report available as report_methodology has not been run prior. Run report_methodology on the current design for the summary of methodology violations.
check_timing report
Table of Contents
-----------------
1. checking no_clock (2381)
2. checking constant_clock (0)
3. checking pulse_width_clock (0)
4. checking unconstrained_internal_endpoints (7609)
5. checking no_input_delay (10)
6. checking no_output_delay (17)
7. checking multiple_clock (0)
8. checking generated_clocks (0)
9. checking loops (0)
10. checking partial_input_delay (0)
11. checking partial_output_delay (0)
12. checking latch_loops (0)
1. checking no_clock (2381)
---------------------------
There are 2381 register/latch pins with no clock driven by root clock pin: clk_o_reg/Q (HIGH)
2. checking constant_clock (0)
------------------------------
There are 0 register/latch pins with constant_clock.
3. checking pulse_width_clock (0)
---------------------------------
There are 0 register/latch pins which need pulse_width check
4. checking unconstrained_internal_endpoints (7609)
---------------------------------------------------
There are 7609 pins that are not constrained for maximum delay. (HIGH)
There are 0 pins that are not constrained for maximum delay due to constant clock.
5. checking no_input_delay (10)
-------------------------------
There are 10 input ports with no input delay specified. (HIGH)
There are 0 input ports with no input delay but user has a false path constraint.
6. checking no_output_delay (17)
--------------------------------
There are 17 ports with no output delay specified. (HIGH)
There are 0 ports with no output delay but user has a false path constraint
There are 0 ports with no output delay but with a timing clock defined on it or propagating through it
7. checking multiple_clock (0)
------------------------------
There are 0 register/latch pins with multiple clocks.
8. checking generated_clocks (0)
--------------------------------
There are 0 generated clocks that are not connected to a clock source.
9. checking loops (0)
---------------------
There are 0 combinational loops in the design.
10. checking partial_input_delay (0)
------------------------------------
There are 0 input ports with partial input delay specified.
11. checking partial_output_delay (0)
-------------------------------------
There are 0 ports with partial output delay specified.
12. checking latch_loops (0)
----------------------------
There are 0 combinational latch loops in the design through latch input
------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------
WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
8.908 0.000 0 1 0.263 0.000 0 1 4.500 0.000 0 3
All user specified timing constraints are met.
------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------
Clock Waveform(ns) Period(ns) Frequency(MHz)
----- ------------ ---------- --------------
sys_clk_pin {0.000 5.000} 10.000 100.000
------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------
Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
sys_clk_pin 8.908 0.000 0 1 0.263 0.000 0 1 4.500 0.000 0 3
------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------
From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------
Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
# report_route_status -file digilent_nexys4ddr_route_status.rpt
# report_drc -file digilent_nexys4ddr_drc.rpt
Command: report_drc -file digilent_nexys4ddr_drc.rpt
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/eda/vivado/Vivado/2023.2/data/ip'.
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 2-168] The results of DRC are in file /var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4ddr_drc.rpt.
report_drc completed successfully
# report_timing_summary -datasheet -max_paths 10 -file digilent_nexys4ddr_timing.rpt
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
# report_power -file digilent_nexys4ddr_power.rpt
Command: report_power -file digilent_nexys4ddr_power.rpt
Running Vector-less Activity Propagation...
Finished Running Vector-less Activity Propagation
WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis.
Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report.
0 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
# write_bitstream -force "./build/out.bit"
Command: write_bitstream -force ./build/out.bit
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command write_bitstream
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
WARN (PR1014) : Generic routing resource will be used to clock signal 'clk_d' by the specified constraint. And then it may lead to the excessive delay or skew
[90%] Routing Phase 3 completed
Running timing analysis......
[95%] Timing analysis completed
Placement and routing completed
Bitstream generation in progress......
Bitstream generation completed
Running power analysis......
[100%] Power analysis completed
Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.power.html" completed
Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.pin.html" completed
Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.rpt.html" completed
Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.rpt.txt" completed
Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.tr.html" completed
Sun Jun 23 15:04:35 2024
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
INFO: [DRC 23-27] Running DRC with 8 threads
WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
set_property CFGBVS value1 [current_design]
#where value1 is either VCCO or GND
set_property CONFIG_VOLTAGE value2 [current_design]
#where value2 is the voltage provided to configuration bank 0
Refer to the device configuration user guide for more information.
INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
INFO: [Designutils 20-2272] Running write_bitstream with 8 threads.
Loading data files...
Loading site data...
Loading route data...
Processing options...
Creating bitmap...
Creating bitstream...
Writing bitstream ./build/out.bit...
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
INFO: [Project 1-1876] WebTalk data collection is mandatory when using a ULT device. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
INFO: [Common 17-83] Releasing license: Implementation
9 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
write_bitstream completed successfully
write_bitstream: Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 3156.148 ; gain = 250.113 ; free physical = 370 ; free virtual = 23957
INFO: [Common 17-206] Exiting Vivado at Sun Jun 23 15:04:45 2024...
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (FPGA Flash)
[Pipeline] parallel
[Pipeline] { (Branch: openFPGAloader ECP5)
[Pipeline] { (Branch: openFPGAloader Tangnano 20k)
[Pipeline] { (Branch: openFPGAloader Nexys 4 DDR)
[Pipeline] stage
[Pipeline] { (openFPGAloader ECP5)
[Pipeline] stage
[Pipeline] { (openFPGAloader Tangnano 20k)
[Pipeline] stage
[Pipeline] { (openFPGAloader Nexys 4 DDR)
[Pipeline] script
[Pipeline] {
[Pipeline] script
[Pipeline] {
[Pipeline] script
[Pipeline] {
[Pipeline] lock
Trying to acquire lock on [ecp5]
Resource [ecp5] did not exist. Created.
Lock acquired on [ecp5]
[Pipeline] {
[Pipeline] lock
Trying to acquire lock on [tangnano20k]
Resource [tangnano20k] did not exist. Created.
Lock acquired on [tangnano20k]
[Pipeline] {
[Pipeline] lock
Trying to acquire lock on [nexys4]
Resource [nexys4] did not exist. Created.
Lock acquired on [nexys4]
[Pipeline] {
[Pipeline] echo
FPGA ECP5 Broqueada
[Pipeline] sh
[Pipeline] echo
FPGA TangNano Broqueada
+ /eda/oss-cad-suite/bin/openFPGALoader -b colorlight-i9 ./build/out.bit
empty
Found 1 compatible device:
0x0d28 0x0204 0x3 DAPLink CMSIS-DAP
Open file: DONE
b3bdffff
Parse file: DONE
Enable configuration: DONE
SRAM erase: DONE
[Pipeline] sh
[Pipeline] echo
FPGA Nexys 4 Broqueada
+ echo gravando na tang nano
gravando na tang nano
[Pipeline] sh
+ cd Risco-5/fpga/nexys4_ddr
+ /eda/oss-cad-suite/bin/openFPGALoader -b nexys_a7_100 ./build/out.bit
empty
Jtag frequency : requested 6.00MHz -> real 6.00MHz
Open file DONE
Parse file DONE
load program
[Pipeline] }
Lock released on resource [tangnano20k]
[Pipeline] // lock
Loading: [====== ] 10.89%[Pipeline] }
[Pipeline] // script
Load SRAM: [========= ] 18.00%[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Loading: [=========== ] 21.78%
Load SRAM: [=================== ] 38.00%
Loading: [================= ] 32.68%
Load SRAM: [============================= ] 58.00%
Loading: [====================== ] 43.57%
Load SRAM: [======================================= ] 78.00%
Loading: [============================ ] 54.46%
Load SRAM: [================================================= ] 98.00%
Load SRAM: [===================================================] 100.00%
Done
Shift IR 35
ir: 1 isc_done 1 isc_ena 0 init 1 done 1
[Pipeline] }
Lock released on resource [nexys4]
Loading: [================================= ] 65.35%[Pipeline] // lock
[Pipeline] }
[Pipeline] // script
[Pipeline] }
Loading: [======================================= ] 76.25%[Pipeline] // stage
[Pipeline] }
Loading: [============================================ ] 87.14%
Loading: [==================================================] 98.03%
Loading: [==================================================] 100.00%
Done
Disable configuration: DONE
[Pipeline] }
Lock released on resource [ecp5]
[Pipeline] // lock
[Pipeline] }
[Pipeline] // script
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Testes)
[Pipeline] parallel
[Pipeline] { (Branch: ECP5 - Testes)
[Pipeline] { (Branch: TangNano - Testes)
[Pipeline] { (Branch: Nexys 4 - Testes)
[Pipeline] stage
[Pipeline] { (ECP5 - Testes)
[Pipeline] stage
[Pipeline] { (TangNano - Testes)
[Pipeline] stage
[Pipeline] { (Nexys 4 - Testes)
[Pipeline] script
[Pipeline] {
[Pipeline] script
[Pipeline] {
[Pipeline] script
[Pipeline] {
[Pipeline] echo
Rodando teste na ECP5
[Pipeline] lock
Trying to acquire lock on [ecp5]
Resource [ecp5] did not exist. Created.
Lock acquired on [ecp5]
[Pipeline] {
[Pipeline] echo
Rodando teste na tang nano
[Pipeline] lock
Trying to acquire lock on [tangnano20k]
Resource [tangnano20k] did not exist. Created.
Lock acquired on [tangnano20k]
[Pipeline] {
[Pipeline] echo
Rodando teste na Nexys 4
[Pipeline] lock
Trying to acquire lock on [nexys4]
Resource [nexys4] did not exist. Created.
Lock acquired on [nexys4]
[Pipeline] {
[Pipeline] echo
FPGA ECP5 Broqueada
[Pipeline] sh
[Pipeline] echo
FPGA TangNano Broqueada
+ echo testando na ecp5
testando na ecp5
[Pipeline] sh
[Pipeline] echo
FPGA Nexys 4 Broqueada
+ echo testando na tang nano
testando na tang nano
[Pipeline] sh
+ echo testando na tang nano
testando na tang nano
[Pipeline] }
Lock released on resource [ecp5]
[Pipeline] }
Lock released on resource [tangnano20k]
[Pipeline] // lock
[Pipeline] // lock
[Pipeline] echo
ECP5 liberada
[Pipeline] }
[Pipeline] echo
TangNano liberada
[Pipeline] }
[Pipeline] }
Lock released on resource [nexys4]
[Pipeline] // script
[Pipeline] // script
[Pipeline] // lock
[Pipeline] }
[Pipeline] }
[Pipeline] echo
TangNano liberada
[Pipeline] }
[Pipeline] // stage
[Pipeline] // stage
[Pipeline] // script
[Pipeline] }
[Pipeline] }
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // node
[Pipeline] End of Pipeline
Finished: SUCCESS
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