Console Output
+ /eda/oss-cad-suite/bin/nextpnr-ecp5 --json ./build/out.json --write ./build/out_pnr.json --45k --lpf Risco-5/fpga/ecp5/pinout.lpf --textcfg ./build/out.config --package CABGA381 --speed 6 --lpf-allow-unconstrained
Info: constraining clock net 'clk' to 25.00 MHz
Info: Logic utilisation before packing:
Info: Total LUT4s: 6695/43848 15%
Info: logic LUTs: 4455/43848 10%
Info: carry LUTs: 392/43848 0%
Info: RAM LUTs: 1232/ 5481 22%
Info: RAMW LUTs: 616/10962 5%
Info: Total DFFs: 1018/43848 2%
Info: Packing IOs..
Info: $gpios[5]$iobuf_i: gpios_$_TBUF__Y.Y
Info: pin 'gpios[5]$tr_io' constrained to Bel 'X9/Y71/PIOB'.
Info: $gpios[4]$iobuf_i: gpios_$_TBUF__Y_1.Y
Info: pin 'gpios[4]$tr_io' constrained to Bel 'X4/Y71/PIOB'.
Info: $gpios[3]$iobuf_i: gpios_$_TBUF__Y_2.Y
Info: pin 'gpios[3]$tr_io' constrained to Bel 'X0/Y65/PIOB'.
Info: $gpios[2]$iobuf_i: gpios_$_TBUF__Y_3.Y
Info: pin 'gpios[2]$tr_io' constrained to Bel 'X9/Y71/PIOA'.
Info: $gpios[1]$iobuf_i: gpios_$_TBUF__Y_4.Y
Info: pin 'gpios[1]$tr_io' constrained to Bel 'X6/Y71/PIOA'.
Info: $gpios[0]$iobuf_i: gpios_$_TBUF__Y_5.Y
Info: pin 'gpios[0]$tr_io' constrained to Bel 'X4/Y71/PIOA'.
Info: pin 'tx$tr_io' constrained to Bel 'X90/Y20/PIOC'.
Info: pin 'rx$tr_io' constrained to Bel 'X90/Y20/PIOA'.
Info: pin 'reset$tr_io' constrained to Bel 'X0/Y29/PIOA'.
Info: pin 'led[7]$tr_io' constrained to Bel 'X90/Y20/PIOD'.
Info: pin 'led[6]$tr_io' constrained to Bel 'X0/Y44/PIOD'.
Info: pin 'led[5]$tr_io' constrained to Bel 'X0/Y59/PIOA'.
Info: pin 'led[4]$tr_io' constrained to Bel 'X15/Y71/PIOB'.
Info: pin 'led[3]$tr_io' constrained to Bel 'X90/Y29/PIOC'.
Info: pin 'led[2]$tr_io' constrained to Bel 'X90/Y44/PIOB'.
Info: pin 'led[1]$tr_io' constrained to Bel 'X0/Y44/PIOC'.
Info: pin 'led[0]$tr_io' constrained to Bel 'X0/Y59/PIOC'.
Info: pin 'clk$tr_io' constrained to Bel 'X0/Y68/PIOC'.
Info: Packing constants..
Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info: 462 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info: Promoting globals...
Info: promoting clock net clk$TRELLIS_IO_IN to global network
Info: Checksum: 0x802a4dda
Info: Device utilisation:
Info: TRELLIS_IO: 18/ 245 7%
Info: DCCA: 1/ 56 1%
Info: DP16KD: 0/ 108 0%
Info: MULT18X18D: 0/ 72 0%
Info: ALU54B: 0/ 36 0%
Info: EHXPLLL: 0/ 4 0%
Info: EXTREFB: 0/ 2 0%
Info: DCUA: 0/ 2 0%
Info: PCSCLKDIV: 0/ 2 0%
Info: IOLOGIC: 0/ 160 0%
Info: SIOLOGIC: 0/ 85 0%
Info: GSR: 0/ 1 0%
Info: JTAGG: 0/ 1 0%
Info: OSCG: 0/ 1 0%
Info: SEDGA: 0/ 1 0%
Info: DTR: 0/ 1 0%
Info: USRMCLK: 0/ 1 0%
Info: CLKDIVF: 0/ 4 0%
Info: ECLKSYNCB: 0/ 10 0%
Info: DLLDELD: 0/ 8 0%
Info: DDRDLL: 0/ 4 0%
Info: DQSBUFM: 0/ 10 0%
Info: TRELLIS_ECLKBUF: 0/ 8 0%
Info: ECLKBRIDGECS: 0/ 2 0%
Info: DCSC: 0/ 2 0%
Info: TRELLIS_FF: 1018/ 43848 2%
Info: TRELLIS_COMB: 6787/ 43848 15%
Info: TRELLIS_RAMW: 308/ 5481 5%
Info: Placed 18 cells based on constraints.
Info: Creating initial analytic placement for 3550 cells, random placement wirelen = 306820.
Info: at initial placer iter 0, wirelen = 2600
Info: at initial placer iter 1, wirelen = 1663
Info: at initial placer iter 2, wirelen = 1761
Info: at initial placer iter 3, wirelen = 1814
Info: Running main analytical placer, max placement attempts per cell = 8266178.
Info: at iteration #1, type ALL: wirelen solved = 1790, spread = 43229, legal = 43923; time = 0.28s
Info: at iteration #2, type ALL: wirelen solved = 4027, spread = 35769, legal = 36458; time = 0.28s
Info: at iteration #3, type ALL: wirelen solved = 6539, spread = 34211, legal = 34855; time = 0.28s
Info: at iteration #4, type ALL: wirelen solved = 9150, spread = 32431, legal = 33204; time = 0.25s
Info: at iteration #5, type ALL: wirelen solved = 10822, spread = 31824, legal = 32538; time = 0.18s
Info: at iteration #6, type ALL: wirelen solved = 12374, spread = 29616, legal = 30434; time = 0.23s
Info: at iteration #7, type ALL: wirelen solved = 12967, spread = 29613, legal = 30475; time = 0.25s
Info: at iteration #8, type ALL: wirelen solved = 14565, spread = 27987, legal = 28877; time = 0.24s
Info: at iteration #9, type ALL: wirelen solved = 14931, spread = 26942, legal = 27760; time = 0.17s
Info: at iteration #10, type ALL: wirelen solved = 15634, spread = 27042, legal = 27774; time = 0.17s
Info: at iteration #11, type ALL: wirelen solved = 15580, spread = 26956, legal = 27908; time = 0.17s
Info: at iteration #12, type ALL: wirelen solved = 16574, spread = 26247, legal = 27086; time = 0.17s
Info: at iteration #13, type ALL: wirelen solved = 17452, spread = 25134, legal = 26052; time = 0.17s
Info: at iteration #14, type ALL: wirelen solved = 16885, spread = 25187, legal = 26166; time = 0.17s
Info: at iteration #15, type ALL: wirelen solved = 17291, spread = 25053, legal = 26082; time = 0.16s
Info: at iteration #16, type ALL: wirelen solved = 17839, spread = 24598, legal = 25786; time = 0.17s
Info: at iteration #17, type ALL: wirelen solved = 18047, spread = 24350, legal = 25253; time = 0.24s
Info: at iteration #18, type ALL: wirelen solved = 18227, spread = 24532, legal = 25567; time = 0.24s
Info: at iteration #19, type ALL: wirelen solved = 18861, spread = 24596, legal = 25614; time = 0.22s
Info: at iteration #20, type ALL: wirelen solved = 18795, spread = 24577, legal = 25624; time = 0.17s
Info: at iteration #21, type ALL: wirelen solved = 19170, spread = 24419, legal = 25525; time = 0.16s
Info: at iteration #22, type ALL: wirelen solved = 19303, spread = 24269, legal = 25683; time = 0.16s
Info: HeAP Placer Time: 7.20s
Info: of which solving equations: 4.54s
Info: of which spreading cells: 0.50s
Info: of which strict legalisation: 0.17s
Info: Running simulated annealing placer for refinement.
Info: at iteration #1: temp = 0.000000, timing cost = 4313, wirelen = 25253
Info: at iteration #5: temp = 0.000000, timing cost = 5981, wirelen = 22882
Info: at iteration #10: temp = 0.000000, timing cost = 6559, wirelen = 22156
Info: at iteration #15: temp = 0.000000, timing cost = 6149, wirelen = 21883
Info: at iteration #20: temp = 0.000000, timing cost = 5628, wirelen = 21807
Info: at iteration #23: temp = 0.000000, timing cost = 5598, wirelen = 21792
Info: SA placement time 18.99s
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 41.75 MHz (PASS at 25.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 8.01 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 10.20 ns
Info: Slack histogram:
Info: legend: * represents 53 endpoint(s)
Info: + represents [1,53) endpoint(s)
Info: [ 16049, 17209) |+
Info: [ 17209, 18369) |+
Info: [ 18369, 19529) |+
Info: [ 19529, 20689) |*+
Info: [ 20689, 21849) |*****+
Info: [ 21849, 23009) |*******+
Info: [ 23009, 24169) |*********+
Info: [ 24169, 25329) |***********+
Info: [ 25329, 26489) |*****+
Info: [ 26489, 27649) |***+
Info: [ 27649, 28809) |*****+
Info: [ 28809, 29969) |*****************************+
Info: [ 29969, 31129) |************************************************************
Info: [ 31129, 32289) |************+
Info: [ 32289, 33449) |***+
Info: [ 33449, 34609) |********+
Info: [ 34609, 35769) |******+
Info: [ 35769, 36929) |*****+
Info: [ 36929, 38089) |*******+
Info: [ 38089, 39249) |*****+
Info: Checksum: 0x41178a46
Info: Routing globals...
Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
Info: Routing..
Info: Setting up routing queue.
Info: Routing 32648 arcs.
Info: | (re-)routed arcs | delta | remaining| time spent |
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
Info: 1000 | 420 579 | 420 579 | 32179| 0.68 0.68|
Info: 2000 | 894 1105 | 474 526 | 31780| 0.31 0.99|
Info: 3000 | 1354 1645 | 460 540 | 31323| 0.26 1.25|
Info: 4000 | 1829 2170 | 475 525 | 30862| 0.26 1.51|
Info: 5000 | 2227 2772 | 398 602 | 30399| 0.26 1.77|
Info: 6000 | 2709 3290 | 482 518 | 29995| 0.25 2.02|
Info: 7000 | 3030 3969 | 321 679 | 29499| 0.26 2.28|
Info: 8000 | 3387 4612 | 357 643 | 29001| 0.26 2.54|
Info: 9000 | 3793 5206 | 406 594 | 28495| 0.24 2.78|
Info: 10000 | 4078 5921 | 285 715 | 27847| 0.25 3.03|
Info: 11000 | 4403 6596 | 325 675 | 27400| 0.25 3.28|
Info: 12000 | 4732 7267 | 329 671 | 26820| 0.25 3.53|
Info: 13000 | 5023 7976 | 291 709 | 26328| 0.26 3.79|
Info: 14000 | 5348 8651 | 325 675 | 25913| 0.29 4.08|
Info: 15000 | 5611 9388 | 263 737 | 25264| 0.27 4.35|
Info: 16000 | 5770 10229 | 159 841 | 24912| 0.24 4.59|
Info: 17000 | 6033 10966 | 263 737 | 24607| 0.26 4.85|
Info: 18000 | 6301 11698 | 268 732 | 24068| 0.29 5.14|
Info: 19000 | 6611 12388 | 310 690 | 23553| 0.26 5.39|
Info: 20000 | 6937 13062 | 326 674 | 22973| 0.27 5.67|
Info: 21000 | 7042 13957 | 105 895 | 22909| 0.26 5.93|
Info: 22000 | 7364 14635 | 322 678 | 22394| 0.27 6.20|
Info: 23000 | 7697 15302 | 333 667 | 21850| 0.30 6.50|
Info: 24000 | 8050 15949 | 353 647 | 21460| 0.30 6.80|
Info: 25000 | 8366 16633 | 316 684 | 20945| 0.31 7.12|
Info: 26000 | 8650 17349 | 284 716 | 20352| 0.31 7.43|
Info: 27000 | 8935 18064 | 285 715 | 19877| 0.30 7.73|
Info: 28000 | 9307 18692 | 372 628 | 19359| 0.33 8.06|
Info: 29000 | 9565 19434 | 258 742 | 18751| 0.32 8.38|
Info: 30000 | 9833 20166 | 268 732 | 18204| 0.33 8.71|
Info: 31000 | 10154 20845 | 321 679 | 17896| 0.37 9.08|
Info: 32000 | 10489 21510 | 335 665 | 17386| 0.37 9.45|
Info: 33000 | 10730 22269 | 241 759 | 16902| 0.34 9.79|
Info: 34000 | 11015 22984 | 285 715 | 16364| 0.33 10.12|
Info: 35000 | 11391 23608 | 376 624 | 15880| 0.35 10.47|
Info: 36000 | 11692 24307 | 301 699 | 15487| 0.34 10.82|
Info: 37000 | 12021 24978 | 329 671 | 14969| 0.36 11.18|
Info: 38000 | 12417 25582 | 396 604 | 14586| 0.33 11.51|
Info: 39000 | 12922 26077 | 505 495 | 14285| 0.37 11.88|
Info: 40000 | 13358 26641 | 436 564 | 13882| 0.34 12.21|
Info: 41000 | 13800 27199 | 442 558 | 13502| 0.34 12.55|
Info: 42000 | 14176 27823 | 376 624 | 13067| 0.35 12.90|
Info: 43000 | 14547 28452 | 371 629 | 12611| 0.36 13.26|
Info: 44000 | 14850 29123 | 303 671 | 12325| 0.34 13.60|
Info: 45000 | 15073 29756 | 223 633 | 11661| 0.25 13.85|
Info: 46000 | 15319 30322 | 246 566 | 10984| 0.21 14.07|
Info: 47000 | 15586 30865 | 267 543 | 10306| 0.20 14.27|
Info: 48000 | 15873 31411 | 287 546 | 9685| 0.26 14.53|
Info: 49000 | 16231 32002 | 358 591 | 9383| 0.42 14.95|
Info: 50000 | 16557 32646 | 326 644 | 9006| 0.39 15.34|
Info: 51000 | 16922 33244 | 365 598 | 8440| 0.30 15.64|
Info: 52000 | 17228 33892 | 306 648 | 7815| 0.25 15.89|
Info: 53000 | 17526 34550 | 298 658 | 7195| 0.26 16.15|
Info: 54000 | 17995 35058 | 469 508 | 6741| 0.34 16.48|
Info: 55000 | 18338 35695 | 343 637 | 6130| 0.30 16.78|
Info: 56000 | 18396 36625 | 58 930 | 5214| 0.14 16.93|
Info: 57000 | 18410 37610 | 14 985 | 4230| 0.10 17.03|
Info: 58000 | 18437 38580 | 27 970 | 3259| 0.10 17.13|
Info: 59000 | 18508 39472 | 71 892 | 2338| 0.20 17.33|
Info: 60000 | 18652 40255 | 144 783 | 1492| 0.30 17.63|
Info: 61000 | 18745 41099 | 93 844 | 604| 0.35 17.98|
Info: 61620 | 18759 41441 | 14 342 | 0| 0.15 18.13|
Info: Routing complete.
Info: Router1 time 18.13s
Info: Checksum: 0xcbf7c795
Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
Info: curr total
Info: 0.5 0.5 Source SOC.Core.Control_Unit.state_TRELLIS_FF_Q_3.Q
Info: 1.8 2.4 Net SOC.Leds.write_LUT4_Z_C_LUT4_Z_B[1] (20,33) -> (23,42)
Info: Sink SOC.Core.Control_Unit.nextstate_LUT4_Z_4_B_LUT4_D_B_LUT4_Z.B
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 2.6 Source SOC.Core.Control_Unit.nextstate_LUT4_Z_4_B_LUT4_D_B_LUT4_Z.F
Info: 0.6 3.2 Net SOC.Core.Control_Unit.nextstate_LUT4_Z_4_B[1] (23,42) -> (23,42)
Info: Sink SOC.Core.Control_Unit.nextstate_LUT4_Z_4_B_LUT4_D_B_LUT4_D.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 3.5 Source SOC.Core.Control_Unit.nextstate_LUT4_Z_4_B_LUT4_D_B_LUT4_D.F
Info: 0.8 4.2 Net SOC.Core.Control_Unit.nextstate_LUT4_Z_4_B_LUT4_D_B_LUT4_D_Z[3] (23,42) -> (22,41)
Info: Sink SOC.Core.Control_Unit.nextstate_LUT4_Z_4_B_LUT4_D_B_LUT4_D_Z_LUT4_C_1.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 4.5 Source SOC.Core.Control_Unit.nextstate_LUT4_Z_4_B_LUT4_D_B_LUT4_D_Z_LUT4_C_1.F
Info: 0.4 4.9 Net SOC.Leds.write_LUT4_Z_C[1] (22,41) -> (22,41)
Info: Sink SOC.Leds.write_LUT4_Z_C_LUT4_C.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 5.1 Source SOC.Leds.write_LUT4_Z_C_LUT4_C.F
Info: 1.3 6.4 Net SOC.Leds.write_LUT4_Z_C_LUT4_C_Z[2] (22,41) -> (19,44)
Info: Sink SOC.GPIOS.address_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 6.6 Source SOC.GPIOS.address_LUT4_Z.F
Info: 2.3 8.9 Net SOC.address[5] (19,44) -> (9,51)
Info: Sink SOC.Memory.memory.0.81$DPRAM_COMB3.A
Info: Defined in:
Info: Risco-5/src/peripheral/soc.v:23.5-23.18
Info: 0.2 9.2 Source SOC.Memory.memory.0.81$DPRAM_COMB3.F
Info: 0.8 10.0 Net SOC.Memory.memory.0.73_DO[0] (9,51) -> (10,51)
Info: Sink SOC.Memory.memory.0.65_DO_LUT4_Z_2.A
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 10.3 Source SOC.Memory.memory.0.65_DO_LUT4_Z_2.F
Info: 0.7 11.0 Net SOC.Memory.memory.0.65_DO[4] (10,51) -> (10,50)
Info: Sink SOC.Memory.memory.0.193_DO_LUT4_A_Z_PFUMX_Z_BLUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 11.2 Source SOC.Memory.memory.0.193_DO_LUT4_A_Z_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: 0.4 11.7 Net SOC.Memory.memory.0.193_DO_LUT4_A_Z[3] (10,50) -> (12,50)
Info: Sink SOC.Memory.memory.0.225_DO_LUT4_A_Z_LUT4_Z_1.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 11.9 Source SOC.Memory.memory.0.225_DO_LUT4_A_Z_LUT4_Z_1.F
Info: 1.3 13.2 Net SOC.Memory.memory.0.225_DO_LUT4_A_Z[4] (12,50) -> (15,47)
Info: Sink SOC.GPIOS.Gpios[0].data_in_LUT4_C_Z_LUT4_Z_1_D_LUT4_Z_C_LUT4_B_Z_PFUMX_Z_BLUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 13.4 Source SOC.GPIOS.Gpios[0].data_in_LUT4_C_Z_LUT4_Z_1_D_LUT4_Z_C_LUT4_B_Z_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: 1.0 14.4 Net SOC.Core.read_data_PFUMX_Z_BLUT_LUT4_Z_D[4] (15,47) -> (16,44)
Info: Sink SOC.Memory.memory.0.67_DO_2_LUT4_A_Z_PFUMX_C0_Z_PFUMX_Z_1_BLUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 14.6 Source SOC.Memory.memory.0.67_DO_2_LUT4_A_Z_PFUMX_C0_Z_PFUMX_Z_1_BLUT_LUT4_Z.OFX
Info: 2.3 16.9 Net SOC.Core.read_data_LUT4_Z_10_B[2] (16,44) -> (32,36)
Info: Sink SOC.Core.read_data_LUT4_Z_22.B
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 17.2 Source SOC.Core.read_data_LUT4_Z_22.F
Info: 0.8 17.9 Net SOC.read_data[26] (32,36) -> (32,35)
Info: Sink SOC.Core.instruction_register_TRELLIS_FF_Q_5.M
Info: Defined in:
Info: Risco-5/src/peripheral/soc.v:22.34-22.43
Info: 0.0 17.9 Setup SOC.Core.instruction_register_TRELLIS_FF_Q_5.M
Info: 3.4 ns logic, 14.5 ns routing
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
Info: curr total
Info: 0.0 0.0 Source gpios[5]$tr_io.O
Info: 2.2 2.2 Net gpios[5]$TRELLIS_IO_IN (9,71) -> (9,54)
Info: Sink SOC.GPIOS.Gpios[5].data_in_LUT4_B.A
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:7.16-7.21
Info: 0.2 2.5 Source SOC.GPIOS.Gpios[5].data_in_LUT4_B.F
Info: 1.4 3.9 Net SOC.GPIOS.Gpios[5].data_in_LUT4_B_Z[4] (9,54) -> (10,44)
Info: Sink SOC.GPIOS.Gpios[5].data_in_LUT4_B_Z_PFUMX_C0_BLUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 4.1 Source SOC.GPIOS.Gpios[5].data_in_LUT4_B_Z_PFUMX_C0_BLUT_LUT4_Z.OFX
Info: 1.0 5.1 Net SOC.GPIOS.Gpios[5].data_in_LUT4_B_Z_PFUMX_C0_Z[1] (10,44) -> (12,44)
Info: Sink SOC.Core.read_data_LUT4_Z_5.B
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 5.3 Source SOC.Core.read_data_LUT4_Z_5.F
Info: 1.4 6.7 Net SOC.read_data[5] (12,44) -> (13,38)
Info: Sink SOC.Core.instruction_register_TRELLIS_FF_Q_25.M
Info: Defined in:
Info: Risco-5/src/peripheral/soc.v:22.34-22.43
Info: 0.0 6.7 Setup SOC.Core.instruction_register_TRELLIS_FF_Q_25.M
Info: 0.7 ns logic, 6.0 ns routing
Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
Info: curr total
Info: 0.5 0.5 Source SOC.Leds.data_TRELLIS_FF_Q_24.Q
Info: 3.1 3.6 Net SOC.Leds.data[7] (25,41) -> (56,26)
Info: Sink led_LUT4_Z_2.D
Info: Defined in:
Info: Risco-5/src/peripheral/leds.v:15.12-15.16
Info: 0.2 3.9 Source led_LUT4_Z_2.F
Info: 2.7 6.6 Net led[7]$TRELLIS_IO_OUT (56,26) -> (90,20)
Info: Sink led[7]$tr_io.I
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:6.22-6.25
Info: 0.8 ns logic, 5.8 ns routing
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 55.79 MHz (PASS at 25.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 6.69 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 6.56 ns
Info: Slack histogram:
Info: legend: * represents 48 endpoint(s)
Info: + represents [1,48) endpoint(s)
Info: [ 22076, 22925) |+
Info: [ 22925, 23774) |*+
Info: [ 23774, 24623) |*********+
Info: [ 24623, 25472) |***+
Info: [ 25472, 26321) |*+
Info: [ 26321, 27170) |*****+
Info: [ 27170, 28019) |***************+
Info: [ 28019, 28868) |***********+
Info: [ 28868, 29717) |*+
Info: [ 29717, 30566) |*******+
Info: [ 30566, 31415) |************************************+
Info: [ 31415, 32264) |************************************************************
Info: [ 32264, 33113) |*********+
Info: [ 33113, 33962) |****+
Info: [ 33962, 34811) |***+
Info: [ 34811, 35660) |***+
Info: [ 35660, 36509) |********+
Info: [ 36509, 37358) |*******+
Info: [ 37358, 38207) |*********+
Info: [ 38207, 39056) |*****+
Info: Program finished normally.
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