Console Output
+ /eda/oss-cad-suite/bin/nextpnr-ecp5 --json ./build/out.json --write ./build/out_pnr.json --45k --lpf Risco-5/fpga/ecp5/pinout.lpf --textcfg ./build/out.config --package CABGA381 --speed 6 --lpf-allow-unconstrained
Info: constraining clock net 'clk' to 25.00 MHz
Info: Logic utilisation before packing:
Info: Total LUT4s: 7116/43848 16%
Info: logic LUTs: 4578/43848 10%
Info: carry LUTs: 690/43848 1%
Info: RAM LUTs: 1232/ 5481 22%
Info: RAMW LUTs: 616/10962 5%
Info: Total DFFs: 1344/43848 3%
Info: Packing IOs..
Info: $gpios[5]$iobuf_i: gpios_$_TBUF__Y.Y
Info: pin 'gpios[5]$tr_io' constrained to Bel 'X9/Y71/PIOB'.
Info: $gpios[4]$iobuf_i: gpios_$_TBUF__Y_1.Y
Info: pin 'gpios[4]$tr_io' constrained to Bel 'X4/Y71/PIOB'.
Info: $gpios[3]$iobuf_i: gpios_$_TBUF__Y_2.Y
Info: pin 'gpios[3]$tr_io' constrained to Bel 'X0/Y65/PIOB'.
Info: $gpios[2]$iobuf_i: gpios_$_TBUF__Y_3.Y
Info: pin 'gpios[2]$tr_io' constrained to Bel 'X9/Y71/PIOA'.
Info: $gpios[1]$iobuf_i: gpios_$_TBUF__Y_4.Y
Info: pin 'gpios[1]$tr_io' constrained to Bel 'X6/Y71/PIOA'.
Info: $gpios[0]$iobuf_i: gpios_$_TBUF__Y_5.Y
Info: pin 'gpios[0]$tr_io' constrained to Bel 'X4/Y71/PIOA'.
Info: pin 'tx$tr_io' constrained to Bel 'X90/Y20/PIOC'.
Info: pin 'rx$tr_io' constrained to Bel 'X90/Y20/PIOA'.
Info: pin 'reset$tr_io' constrained to Bel 'X0/Y29/PIOA'.
Info: pin 'led[7]$tr_io' constrained to Bel 'X90/Y20/PIOD'.
Info: pin 'led[6]$tr_io' constrained to Bel 'X0/Y44/PIOD'.
Info: pin 'led[5]$tr_io' constrained to Bel 'X0/Y59/PIOA'.
Info: pin 'led[4]$tr_io' constrained to Bel 'X15/Y71/PIOB'.
Info: pin 'led[3]$tr_io' constrained to Bel 'X90/Y29/PIOC'.
Info: pin 'led[2]$tr_io' constrained to Bel 'X90/Y44/PIOB'.
Info: pin 'led[1]$tr_io' constrained to Bel 'X0/Y44/PIOC'.
Info: pin 'led[0]$tr_io' constrained to Bel 'X0/Y59/PIOC'.
Info: pin 'clk$tr_io' constrained to Bel 'X0/Y68/PIOC'.
Info: Packing constants..
Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info: 661 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info: Promoting globals...
Info: promoting clock net clk$TRELLIS_IO_IN to global network
Info: Checksum: 0xc38d19a9
Info: Device utilisation:
Info: TRELLIS_IO: 18/ 245 7%
Info: DCCA: 1/ 56 1%
Info: DP16KD: 0/ 108 0%
Info: MULT18X18D: 4/ 72 5%
Info: ALU54B: 0/ 36 0%
Info: EHXPLLL: 0/ 4 0%
Info: EXTREFB: 0/ 2 0%
Info: DCUA: 0/ 2 0%
Info: PCSCLKDIV: 0/ 2 0%
Info: IOLOGIC: 0/ 160 0%
Info: SIOLOGIC: 0/ 85 0%
Info: GSR: 0/ 1 0%
Info: JTAGG: 0/ 1 0%
Info: OSCG: 0/ 1 0%
Info: SEDGA: 0/ 1 0%
Info: DTR: 0/ 1 0%
Info: USRMCLK: 0/ 1 0%
Info: CLKDIVF: 0/ 4 0%
Info: ECLKSYNCB: 0/ 10 0%
Info: DLLDELD: 0/ 8 0%
Info: DDRDLL: 0/ 4 0%
Info: DQSBUFM: 0/ 10 0%
Info: TRELLIS_ECLKBUF: 0/ 8 0%
Info: ECLKBRIDGECS: 0/ 2 0%
Info: DCSC: 0/ 2 0%
Info: TRELLIS_FF: 1344/ 43848 3%
Info: TRELLIS_COMB: 7240/ 43848 16%
Info: TRELLIS_RAMW: 308/ 5481 5%
Info: Placed 18 cells based on constraints.
Info: Creating initial analytic placement for 4016 cells, random placement wirelen = 360996.
Info: at initial placer iter 0, wirelen = 2952
Info: at initial placer iter 1, wirelen = 2211
Info: at initial placer iter 2, wirelen = 2359
Info: at initial placer iter 3, wirelen = 2410
Info: Running main analytical placer, max placement attempts per cell = 9934653.
Info: at iteration #1, type ALL: wirelen solved = 2283, spread = 57656, legal = 57006; time = 0.21s
Info: at iteration #2, type ALL: wirelen solved = 5997, spread = 45267, legal = 46151; time = 0.22s
Info: at iteration #3, type ALL: wirelen solved = 8731, spread = 42162, legal = 44043; time = 0.21s
Info: at iteration #4, type ALL: wirelen solved = 11528, spread = 41115, legal = 43595; time = 0.20s
Info: at iteration #5, type ALL: wirelen solved = 13618, spread = 39076, legal = 41443; time = 0.20s
Info: at iteration #6, type ALL: wirelen solved = 15799, spread = 35520, legal = 38431; time = 0.20s
Info: at iteration #7, type ALL: wirelen solved = 15209, spread = 35600, legal = 38270; time = 0.24s
Info: at iteration #8, type ALL: wirelen solved = 16886, spread = 33189, legal = 35473; time = 0.28s
Info: at iteration #9, type ALL: wirelen solved = 18279, spread = 33338, legal = 35234; time = 0.25s
Info: at iteration #10, type ALL: wirelen solved = 18375, spread = 32649, legal = 34394; time = 0.19s
Info: at iteration #11, type ALL: wirelen solved = 19413, spread = 31987, legal = 33631; time = 0.19s
Info: at iteration #12, type ALL: wirelen solved = 19762, spread = 32207, legal = 33677; time = 0.19s
Info: at iteration #13, type ALL: wirelen solved = 20642, spread = 31652, legal = 33654; time = 0.19s
Info: at iteration #14, type ALL: wirelen solved = 20871, spread = 32068, legal = 33893; time = 0.18s
Info: at iteration #15, type ALL: wirelen solved = 21534, spread = 31018, legal = 33107; time = 0.19s
Info: at iteration #16, type ALL: wirelen solved = 21906, spread = 31238, legal = 33296; time = 0.19s
Info: at iteration #17, type ALL: wirelen solved = 22408, spread = 31740, legal = 33723; time = 0.27s
Info: at iteration #18, type ALL: wirelen solved = 23450, spread = 30637, legal = 32930; time = 0.27s
Info: at iteration #19, type ALL: wirelen solved = 22790, spread = 31229, legal = 33949; time = 0.19s
Info: at iteration #20, type ALL: wirelen solved = 23776, spread = 30902, legal = 33510; time = 0.19s
Info: at iteration #21, type ALL: wirelen solved = 23790, spread = 30556, legal = 33997; time = 0.19s
Info: at iteration #22, type ALL: wirelen solved = 23660, spread = 30938, legal = 34183; time = 0.19s
Info: at iteration #23, type ALL: wirelen solved = 23889, spread = 30542, legal = 33836; time = 0.19s
Info: HeAP Placer Time: 7.72s
Info: of which solving equations: 4.61s
Info: of which spreading cells: 0.59s
Info: of which strict legalisation: 0.24s
Info: Running simulated annealing placer for refinement.
Info: at iteration #1: temp = 0.000000, timing cost = 4577, wirelen = 32930
Info: at iteration #5: temp = 0.000000, timing cost = 4228, wirelen = 29524
Info: at iteration #10: temp = 0.000000, timing cost = 5167, wirelen = 28655
Info: at iteration #15: temp = 0.000000, timing cost = 5159, wirelen = 28217
Info: at iteration #20: temp = 0.000000, timing cost = 5185, wirelen = 28100
Info: at iteration #23: temp = 0.000000, timing cost = 5144, wirelen = 28067
Info: SA placement time 20.34s
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 44.25 MHz (PASS at 25.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 11.21 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 10.44 ns
Info: Slack histogram:
Info: legend: * represents 39 endpoint(s)
Info: + represents [1,39) endpoint(s)
Info: [ 17401, 18493) |+
Info: [ 18493, 19585) |+
Info: [ 19585, 20677) |*+
Info: [ 20677, 21769) |***+
Info: [ 21769, 22861) |***********+
Info: [ 22861, 23953) |********+
Info: [ 23953, 25045) |**************+
Info: [ 25045, 26137) |************+
Info: [ 26137, 27229) |**********+
Info: [ 27229, 28321) |************+
Info: [ 28321, 29413) |*************+
Info: [ 29413, 30505) |*****************************************+
Info: [ 30505, 31597) |************************************************************
Info: [ 31597, 32689) |*************************+
Info: [ 32689, 33781) |*****+
Info: [ 33781, 34873) |*************+
Info: [ 34873, 35965) |************+
Info: [ 35965, 37057) |**********+
Info: [ 37057, 38149) |*********+
Info: [ 38149, 39241) |********+
Info: Checksum: 0x56558f2c
Info: Routing globals...
Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
Info: Routing..
Info: Setting up routing queue.
Info: Routing 33986 arcs.
Info: | (re-)routed arcs | delta | remaining| time spent |
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
Info: 1000 | 145 854 | 145 854 | 33147| 0.83 0.83|
Info: 2000 | 332 1667 | 187 813 | 32633| 0.31 1.14|
Info: 3000 | 463 2536 | 131 869 | 31931| 0.27 1.42|
Info: 4000 | 658 3341 | 195 805 | 31217| 0.28 1.70|
Info: 5000 | 866 4133 | 208 792 | 30592| 0.33 2.02|
Info: 6000 | 1137 4862 | 271 729 | 30098| 0.32 2.35|
Info: 7000 | 1409 5590 | 272 728 | 29664| 0.30 2.64|
Info: 8000 | 1741 6258 | 332 668 | 29215| 0.30 2.95|
Info: 9000 | 2108 6891 | 367 633 | 28721| 0.25 3.20|
Info: 10000 | 2506 7493 | 398 602 | 28272| 0.29 3.48|
Info: 11000 | 2785 8214 | 279 721 | 27679| 0.29 3.77|
Info: 12000 | 3048 8951 | 263 737 | 27087| 0.29 4.07|
Info: 13000 | 3403 9596 | 355 645 | 26586| 0.30 4.37|
Info: 14000 | 3795 10204 | 392 608 | 26121| 0.32 4.69|
Info: 15000 | 4101 10898 | 306 694 | 25605| 0.30 4.99|
Info: 16000 | 4417 11582 | 316 684 | 25300| 0.31 5.30|
Info: 17000 | 4755 12244 | 338 662 | 24757| 0.32 5.61|
Info: 18000 | 5074 12925 | 319 681 | 24329| 0.35 5.96|
Info: 19000 | 5385 13614 | 311 689 | 23793| 0.35 6.31|
Info: 20000 | 5719 14280 | 334 666 | 23424| 0.37 6.68|
Info: 21000 | 5991 15008 | 272 728 | 22886| 0.33 7.01|
Info: 22000 | 6277 15722 | 286 714 | 22371| 0.34 7.35|
Info: 23000 | 6588 16411 | 311 689 | 22068| 0.34 7.68|
Info: 24000 | 6916 17083 | 328 672 | 21540| 0.39 8.07|
Info: 25000 | 7241 17758 | 325 675 | 20985| 0.35 8.42|
Info: 26000 | 7565 18434 | 324 676 | 20456| 0.32 8.74|
Info: 27000 | 7996 19003 | 431 569 | 20190| 0.36 9.10|
Info: 28000 | 8371 19628 | 375 625 | 19725| 0.34 9.44|
Info: 29000 | 8752 20247 | 381 619 | 19252| 0.33 9.77|
Info: 30000 | 9175 20824 | 423 577 | 18858| 0.35 10.12|
Info: 31000 | 9547 21452 | 372 628 | 18336| 0.32 10.45|
Info: 32000 | 9843 22156 | 296 704 | 17858| 0.38 10.83|
Info: 33000 | 10039 22960 | 196 804 | 17762| 0.32 11.15|
Info: 34000 | 10255 23744 | 216 784 | 17538| 0.41 11.55|
Info: 35000 | 10683 24316 | 428 572 | 17083| 0.38 11.93|
Info: 36000 | 11078 24921 | 395 605 | 16645| 0.34 12.27|
Info: 37000 | 11414 25585 | 336 664 | 16191| 0.34 12.61|
Info: 38000 | 11823 26176 | 409 591 | 15823| 0.38 12.98|
Info: 39000 | 12222 26777 | 399 601 | 15452| 0.37 13.35|
Info: 40000 | 12683 27316 | 461 539 | 15077| 0.37 13.72|
Info: 41000 | 13151 27848 | 468 532 | 14653| 0.38 14.10|
Info: 42000 | 13592 28407 | 441 559 | 14252| 0.37 14.46|
Info: 43000 | 13941 29058 | 349 651 | 13917| 0.39 14.85|
Info: 44000 | 14338 29640 | 397 582 | 13540| 0.42 15.27|
Info: 45000 | 14673 30211 | 335 571 | 13014| 0.35 15.62|
Info: 46000 | 14990 30736 | 317 525 | 12424| 0.29 15.91|
Info: 47000 | 15276 31279 | 286 543 | 11818| 0.27 16.18|
Info: 48000 | 15577 31849 | 301 570 | 11300| 0.28 16.46|
Info: 49000 | 15913 32385 | 336 536 | 10708| 0.26 16.72|
Info: 50000 | 16238 33003 | 325 618 | 10154| 0.29 17.01|
Info: 51000 | 16548 33658 | 310 655 | 9564| 0.33 17.34|
Info: 52000 | 16903 34264 | 355 606 | 8985| 0.31 17.64|
Info: 53000 | 17293 34843 | 390 579 | 8520| 0.42 18.06|
Info: 54000 | 17618 35505 | 325 662 | 7897| 0.32 18.39|
Info: 55000 | 17771 36291 | 153 786 | 7102| 0.34 18.73|
Info: 56000 | 17845 37212 | 74 921 | 6496| 0.31 19.04|
Info: 57000 | 17866 38190 | 21 978 | 5517| 0.11 19.15|
Info: 58000 | 17900 39122 | 34 932 | 4577| 0.12 19.27|
Info: 59000 | 17954 40047 | 54 925 | 3657| 0.17 19.44|
Info: 60000 | 18085 40811 | 131 764 | 2825| 0.27 19.70|
Info: 61000 | 18366 41524 | 281 713 | 2680| 1.40 21.10|
Info: 62000 | 18519 42299 | 153 775 | 1916| 0.70 21.80|
Info: 63000 | 18600 43154 | 81 855 | 1025| 0.27 22.07|
Info: 64000 | 18713 43881 | 113 727 | 316| 0.27 22.34|
Info: 64320 | 18718 44093 | 5 212 | 0| 0.12 22.46|
Info: Routing complete.
Info: Router1 time 22.46s
Info: Checksum: 0x69b4ddf2
Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
Info: curr total
Info: 0.5 0.5 Source SOC.Core.Control_Unit.state_TRELLIS_FF_Q_3.Q
Info: 1.4 2.0 Net SOC.Memory.memory_response_LUT4_B_Z_LUT4_Z_D[1] (22,23) -> (23,26)
Info: Sink SOC.Core.Mdu.div_done_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_LUT4_D_Z_LUT4_Z_2_D_LUT4_Z.B
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 2.2 Source SOC.Core.Mdu.div_done_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_LUT4_D_Z_LUT4_Z_2_D_LUT4_Z.F
Info: 1.0 3.2 Net SOC.Core.Mdu.div_done_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_LUT4_D_Z_LUT4_Z_2_D[1] (23,26) -> (24,30)
Info: Sink SOC.Core.Mdu.div_done_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_LUT4_D_Z_LUT4_Z_2_D_LUT4_C.C
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 3.4 Source SOC.Core.Mdu.div_done_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_LUT4_D_Z_LUT4_Z_2_D_LUT4_C.F
Info: 0.6 4.0 Net SOC.Core.Mdu.div_done_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_LUT4_D_Z_LUT4_Z_2_D_LUT4_C_Z[1] (24,30) -> (24,30)
Info: Sink SOC.Leds.write_LUT4_Z_B_LUT4_Z_1.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 4.3 Source SOC.Leds.write_LUT4_Z_B_LUT4_Z_1.F
Info: 0.9 5.2 Net SOC.Leds.write_LUT4_Z_B[0] (24,30) -> (21,29)
Info: Sink SOC.Memory.memory_response_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_LUT4_D.C
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 5.4 Source SOC.Memory.memory_response_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_LUT4_D.F
Info: 0.9 6.3 Net SOC.Memory.memory_response_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_LUT4_D_Z[2] (21,29) -> (19,29)
Info: Sink SOC.GPIOS.address_LUT4_Z_1.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 6.6 Source SOC.GPIOS.address_LUT4_Z_1.F
Info: 1.9 8.5 Net SOC.address[4] (19,29) -> (11,20)
Info: Sink SOC.Memory.memory.0.121$DPRAM_COMB3.C
Info: Defined in:
Info: Risco-5/src/peripheral/soc.v:23.5-23.18
Info: 0.2 8.7 Source SOC.Memory.memory.0.121$DPRAM_COMB3.F
Info: 0.8 9.5 Net SOC.Memory.memory.0.97_DO[0] (11,20) -> (11,20)
Info: Sink SOC.Memory.memory.0.97_DO_LUT4_A.A
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 9.8 Source SOC.Memory.memory.0.97_DO_LUT4_A.F
Info: 0.9 10.7 Net SOC.Memory.memory.0.97_DO_LUT4_A_Z[2] (11,20) -> (11,21)
Info: Sink SOC.Memory.memory.0.193_DO_LUT4_A_Z_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 10.9 Source SOC.Memory.memory.0.193_DO_LUT4_A_Z_LUT4_Z.F
Info: 0.9 11.8 Net SOC.Memory.memory.0.193_DO_LUT4_A_Z[3] (11,21) -> (11,23)
Info: Sink SOC.Memory.memory.0.193_DO_LUT4_A_Z_LUT4_B.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 12.0 Source SOC.Memory.memory.0.193_DO_LUT4_A_Z_LUT4_B.F
Info: 1.0 13.0 Net SOC.Core.read_data_LUT4_Z_7_B_LUT4_Z_1_C[0] (11,23) -> (15,25)
Info: Sink SOC.Memory.memory.0.194_DO_3_LUT4_A_Z_PFUMX_C0_Z_LUT4_Z_1.B
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 13.3 Source SOC.Memory.memory.0.194_DO_3_LUT4_A_Z_PFUMX_C0_Z_LUT4_Z_1.F
Info: 1.3 14.6 Net SOC.Core.read_data_LUT4_Z_10_C_LUT4_Z_1_B[3] (15,25) -> (20,28)
Info: Sink SOC.Memory.memory.0.167_DO_LUT4_A_Z_LUT4_C_Z_LUT4_A_Z_LUT4_Z_2.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 14.8 Source SOC.Memory.memory.0.167_DO_LUT4_A_Z_LUT4_C_Z_LUT4_A_Z_LUT4_Z_2.F
Info: 1.2 16.0 Net SOC.Core.read_data_LUT4_Z_15_B[3] (20,28) -> (29,28)
Info: Sink SOC.Core.read_data_PFUMX_Z_13_BLUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 16.3 Source SOC.Core.read_data_PFUMX_Z_13_BLUT_LUT4_Z.OFX
Info: 2.0 18.3 Net SOC.read_data[29] (29,28) -> (28,6)
Info: Sink SOC.Core.instruction_register_TRELLIS_FF_Q_2.M
Info: Defined in:
Info: Risco-5/src/peripheral/soc.v:22.34-22.43
Info: 0.0 18.3 Setup SOC.Core.instruction_register_TRELLIS_FF_Q_2.M
Info: 3.4 ns logic, 14.9 ns routing
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
Info: curr total
Info: 0.0 0.0 Source gpios[3]$tr_io.O
Info: 3.6 3.6 Net gpios[3]$TRELLIS_IO_IN (0,65) -> (6,30)
Info: Sink SOC.GPIOS.Gpios[3].data_in_LUT4_C.A
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:7.16-7.21
Info: 0.2 3.9 Source SOC.GPIOS.Gpios[3].data_in_LUT4_C.F
Info: 1.3 5.2 Net SOC.GPIOS.Gpios[3].data_in_LUT4_C_Z[4] (6,30) -> (7,20)
Info: Sink SOC.GPIOS.Gpios[3].data_in_LUT4_C_Z_PFUMX_C0_BLUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 5.4 Source SOC.GPIOS.Gpios[3].data_in_LUT4_C_Z_PFUMX_C0_BLUT_LUT4_Z.OFX
Info: 0.6 6.0 Net SOC.GPIOS.Gpios[3].data_in_LUT4_C_Z_PFUMX_C0_Z[1] (7,20) -> (7,20)
Info: Sink SOC.Core.read_data_LUT4_Z_3.B
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 6.2 Source SOC.Core.read_data_LUT4_Z_3.F
Info: 2.2 8.5 Net SOC.read_data[3] (7,20) -> (18,5)
Info: Sink SOC.Core.instruction_register_TRELLIS_FF_Q_27.M
Info: Defined in:
Info: Risco-5/src/peripheral/soc.v:22.34-22.43
Info: 0.0 8.5 Setup SOC.Core.instruction_register_TRELLIS_FF_Q_27.M
Info: 0.7 ns logic, 7.7 ns routing
Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
Info: curr total
Info: 0.5 0.5 Source SOC.Leds.data_TRELLIS_FF_Q_29.Q
Info: 4.1 4.7 Net SOC.Leds.data[2] (17,27) -> (75,31)
Info: Sink led_LUT4_Z.D
Info: Defined in:
Info: Risco-5/src/peripheral/leds.v:15.12-15.16
Info: 0.2 4.9 Source led_LUT4_Z.F
Info: 2.2 7.1 Net led[2]$TRELLIS_IO_OUT (75,31) -> (90,44)
Info: Sink led[2]$tr_io.I
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:6.22-6.25
Info: 0.8 ns logic, 6.3 ns routing
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 54.64 MHz (PASS at 25.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 8.46 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 7.09 ns
Info: Slack histogram:
Info: legend: * represents 48 endpoint(s)
Info: + represents [1,48) endpoint(s)
Info: [ 21698, 22566) |+
Info: [ 22566, 23434) |*+
Info: [ 23434, 24302) |*****+
Info: [ 24302, 25170) |*******+
Info: [ 25170, 26038) |******+
Info: [ 26038, 26906) |******+
Info: [ 26906, 27774) |**************+
Info: [ 27774, 28642) |******+
Info: [ 28642, 29510) |*******+
Info: [ 29510, 30378) |********+
Info: [ 30378, 31246) |***************************+
Info: [ 31246, 32114) |************************************************************
Info: [ 32114, 32982) |*******************+
Info: [ 32982, 33850) |***+
Info: [ 33850, 34718) |*****+
Info: [ 34718, 35586) |*****+
Info: [ 35586, 36454) |***********+
Info: [ 36454, 37322) |********+
Info: [ 37322, 38190) |********+
Info: [ 38190, 39058) |*******+
Info: Program finished normally.
![[Jenkins]](/jenkins/static/b6fe011e/images/svgs/logo.svg){kind=logo}
