Console Output
+ /eda/oss-cad-suite/bin/nextpnr-ecp5 --json ./build/out.json --write ./build/out_pnr.json --45k --lpf Risco-5/fpga/ecp5/pinout.lpf --textcfg ./build/out.config --package CABGA381 --speed 6 --lpf-allow-unconstrained
Info: constraining clock net 'clk' to 25.00 MHz
Info: Logic utilisation before packing:
Info: Total LUT4s: 7122/43848 16%
Info: logic LUTs: 4584/43848 10%
Info: carry LUTs: 690/43848 1%
Info: RAM LUTs: 1232/ 5481 22%
Info: RAMW LUTs: 616/10962 5%
Info: Total DFFs: 1344/43848 3%
Info: Packing IOs..
Info: $gpios[5]$iobuf_i: gpios_$_TBUF__Y.Y
Info: pin 'gpios[5]$tr_io' constrained to Bel 'X9/Y71/PIOB'.
Info: $gpios[4]$iobuf_i: gpios_$_TBUF__Y_1.Y
Info: pin 'gpios[4]$tr_io' constrained to Bel 'X4/Y71/PIOB'.
Info: $gpios[3]$iobuf_i: gpios_$_TBUF__Y_2.Y
Info: pin 'gpios[3]$tr_io' constrained to Bel 'X0/Y65/PIOB'.
Info: $gpios[2]$iobuf_i: gpios_$_TBUF__Y_3.Y
Info: pin 'gpios[2]$tr_io' constrained to Bel 'X9/Y71/PIOA'.
Info: $gpios[1]$iobuf_i: gpios_$_TBUF__Y_4.Y
Info: pin 'gpios[1]$tr_io' constrained to Bel 'X6/Y71/PIOA'.
Info: $gpios[0]$iobuf_i: gpios_$_TBUF__Y_5.Y
Info: pin 'gpios[0]$tr_io' constrained to Bel 'X4/Y71/PIOA'.
Info: pin 'tx$tr_io' constrained to Bel 'X90/Y20/PIOC'.
Info: pin 'rx$tr_io' constrained to Bel 'X90/Y20/PIOA'.
Info: pin 'reset$tr_io' constrained to Bel 'X0/Y29/PIOA'.
Info: pin 'led[7]$tr_io' constrained to Bel 'X90/Y20/PIOD'.
Info: pin 'led[6]$tr_io' constrained to Bel 'X0/Y44/PIOD'.
Info: pin 'led[5]$tr_io' constrained to Bel 'X0/Y59/PIOA'.
Info: pin 'led[4]$tr_io' constrained to Bel 'X15/Y71/PIOB'.
Info: pin 'led[3]$tr_io' constrained to Bel 'X90/Y29/PIOC'.
Info: pin 'led[2]$tr_io' constrained to Bel 'X90/Y44/PIOB'.
Info: pin 'led[1]$tr_io' constrained to Bel 'X0/Y44/PIOC'.
Info: pin 'led[0]$tr_io' constrained to Bel 'X0/Y59/PIOC'.
Info: pin 'clk$tr_io' constrained to Bel 'X0/Y68/PIOC'.
Info: Packing constants..
Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info: 662 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info: Promoting globals...
Info: promoting clock net clk$TRELLIS_IO_IN to global network
Info: Checksum: 0xa311e89a
Info: Device utilisation:
Info: TRELLIS_IO: 18/ 245 7%
Info: DCCA: 1/ 56 1%
Info: DP16KD: 0/ 108 0%
Info: MULT18X18D: 4/ 72 5%
Info: ALU54B: 0/ 36 0%
Info: EHXPLLL: 0/ 4 0%
Info: EXTREFB: 0/ 2 0%
Info: DCUA: 0/ 2 0%
Info: PCSCLKDIV: 0/ 2 0%
Info: IOLOGIC: 0/ 160 0%
Info: SIOLOGIC: 0/ 85 0%
Info: GSR: 0/ 1 0%
Info: JTAGG: 0/ 1 0%
Info: OSCG: 0/ 1 0%
Info: SEDGA: 0/ 1 0%
Info: DTR: 0/ 1 0%
Info: USRMCLK: 0/ 1 0%
Info: CLKDIVF: 0/ 4 0%
Info: ECLKSYNCB: 0/ 10 0%
Info: DLLDELD: 0/ 8 0%
Info: DDRDLL: 0/ 4 0%
Info: DQSBUFM: 0/ 10 0%
Info: TRELLIS_ECLKBUF: 0/ 8 0%
Info: ECLKBRIDGECS: 0/ 2 0%
Info: DCSC: 0/ 2 0%
Info: TRELLIS_FF: 1344/ 43848 3%
Info: TRELLIS_COMB: 7246/ 43848 16%
Info: TRELLIS_RAMW: 308/ 5481 5%
Info: Placed 18 cells based on constraints.
Info: Creating initial analytic placement for 4028 cells, random placement wirelen = 364787.
Info: at initial placer iter 0, wirelen = 3497
Info: at initial placer iter 1, wirelen = 2756
Info: at initial placer iter 2, wirelen = 2302
Info: at initial placer iter 3, wirelen = 2334
Info: Running main analytical placer, max placement attempts per cell = 9948030.
Info: at iteration #1, type ALL: wirelen solved = 2458, spread = 56377, legal = 53578; time = 0.20s
Info: at iteration #2, type ALL: wirelen solved = 5502, spread = 47363, legal = 48275; time = 0.23s
Info: at iteration #3, type ALL: wirelen solved = 9261, spread = 40099, legal = 42605; time = 0.22s
Info: at iteration #4, type ALL: wirelen solved = 10664, spread = 39539, legal = 42218; time = 0.22s
Info: at iteration #5, type ALL: wirelen solved = 12973, spread = 39228, legal = 41675; time = 0.19s
Info: at iteration #6, type ALL: wirelen solved = 14128, spread = 37242, legal = 39256; time = 0.20s
Info: at iteration #7, type ALL: wirelen solved = 15815, spread = 36618, legal = 38520; time = 0.19s
Info: at iteration #8, type ALL: wirelen solved = 16487, spread = 35033, legal = 36842; time = 0.19s
Info: at iteration #9, type ALL: wirelen solved = 17617, spread = 33822, legal = 35541; time = 0.18s
Info: at iteration #10, type ALL: wirelen solved = 18114, spread = 33581, legal = 34872; time = 0.18s
Info: at iteration #11, type ALL: wirelen solved = 18845, spread = 32403, legal = 34057; time = 0.19s
Info: at iteration #12, type ALL: wirelen solved = 19672, spread = 31569, legal = 33184; time = 0.19s
Info: at iteration #13, type ALL: wirelen solved = 20154, spread = 32510, legal = 33826; time = 0.19s
Info: at iteration #14, type ALL: wirelen solved = 20783, spread = 32016, legal = 33356; time = 0.18s
Info: at iteration #15, type ALL: wirelen solved = 21617, spread = 31680, legal = 33154; time = 0.18s
Info: at iteration #16, type ALL: wirelen solved = 21924, spread = 31729, legal = 33474; time = 0.18s
Info: at iteration #17, type ALL: wirelen solved = 22624, spread = 33694, legal = 35093; time = 0.18s
Info: at iteration #18, type ALL: wirelen solved = 23803, spread = 31847, legal = 33797; time = 0.19s
Info: at iteration #19, type ALL: wirelen solved = 23639, spread = 32057, legal = 33939; time = 0.18s
Info: at iteration #20, type ALL: wirelen solved = 23757, spread = 31689, legal = 34261; time = 0.18s
Info: HeAP Placer Time: 6.28s
Info: of which solving equations: 3.62s
Info: of which spreading cells: 0.50s
Info: of which strict legalisation: 0.20s
Info: Running simulated annealing placer for refinement.
Info: at iteration #1: temp = 0.000000, timing cost = 7343, wirelen = 33154
Info: at iteration #5: temp = 0.000000, timing cost = 5472, wirelen = 29409
Info: at iteration #10: temp = 0.000000, timing cost = 4988, wirelen = 28445
Info: at iteration #15: temp = 0.000000, timing cost = 4441, wirelen = 28031
Info: at iteration #20: temp = 0.000000, timing cost = 5342, wirelen = 27869
Info: at iteration #25: temp = 0.000000, timing cost = 5325, wirelen = 27812
Info: at iteration #28: temp = 0.000000, timing cost = 5319, wirelen = 27804
Info: SA placement time 24.60s
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 39.33 MHz (PASS at 25.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 9.05 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 9.40 ns
Info: Slack histogram:
Info: legend: * represents 51 endpoint(s)
Info: + represents [1,51) endpoint(s)
Info: [ 14576, 15810) |+
Info: [ 15810, 17044) |+
Info: [ 17044, 18278) |+
Info: [ 18278, 19512) |**+
Info: [ 19512, 20746) |*****************+
Info: [ 20746, 21980) |**************+
Info: [ 21980, 23214) |*****+
Info: [ 23214, 24448) |*+
Info: [ 24448, 25682) |*+
Info: [ 25682, 26916) |****************************+
Info: [ 26916, 28150) |************************************************************
Info: [ 28150, 29384) |********************+
Info: [ 29384, 30618) |****+
Info: [ 30618, 31852) |*+
Info: [ 31852, 33086) |****+
Info: [ 33086, 34320) |**********+
Info: [ 34320, 35554) |*************+
Info: [ 35554, 36788) |*****+
Info: [ 36788, 38022) |*****+
Info: [ 38022, 39256) |********+
Info: Checksum: 0xcf26cda4
Info: Routing globals...
Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
Info: Routing..
Info: Setting up routing queue.
Info: Routing 34071 arcs.
Info: | (re-)routed arcs | delta | remaining| time spent |
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
Info: 1000 | 235 764 | 235 764 | 33491| 0.97 0.97|
Info: 2000 | 450 1549 | 215 785 | 32797| 0.28 1.25|
Info: 3000 | 641 2358 | 191 809 | 32060| 0.28 1.53|
Info: 4000 | 836 3163 | 195 805 | 31499| 0.27 1.80|
Info: 5000 | 1087 3912 | 251 749 | 30866| 0.26 2.06|
Info: 6000 | 1315 4684 | 228 772 | 30324| 0.29 2.35|
Info: 7000 | 1600 5399 | 285 715 | 29709| 0.28 2.62|
Info: 8000 | 1888 6111 | 288 712 | 29194| 0.28 2.90|
Info: 9000 | 2022 6977 | 134 866 | 29045| 0.29 3.19|
Info: 10000 | 2222 7777 | 200 800 | 28606| 0.28 3.47|
Info: 11000 | 2492 8507 | 270 730 | 27986| 0.26 3.73|
Info: 12000 | 2671 9328 | 179 821 | 27742| 0.27 4.00|
Info: 13000 | 2879 10120 | 208 792 | 27208| 0.26 4.26|
Info: 14000 | 3223 10776 | 344 656 | 26760| 0.27 4.53|
Info: 15000 | 3475 11524 | 252 748 | 26399| 0.26 4.79|
Info: 16000 | 3768 12231 | 293 707 | 25826| 0.31 5.10|
Info: 17000 | 4012 12987 | 244 756 | 25443| 0.31 5.42|
Info: 18000 | 4246 13753 | 234 766 | 24819| 0.33 5.74|
Info: 19000 | 4502 14497 | 256 744 | 24166| 0.31 6.06|
Info: 20000 | 4818 15181 | 316 684 | 23667| 0.31 6.36|
Info: 21000 | 5148 15851 | 330 670 | 23123| 0.30 6.66|
Info: 22000 | 5408 16591 | 260 740 | 22514| 0.35 7.01|
Info: 23000 | 5703 17296 | 295 705 | 22015| 0.34 7.35|
Info: 24000 | 5974 18025 | 271 729 | 21924| 0.34 7.69|
Info: 25000 | 6204 18795 | 230 770 | 21295| 0.35 8.04|
Info: 26000 | 6496 19503 | 292 708 | 20751| 0.34 8.39|
Info: 27000 | 6781 20218 | 285 715 | 20144| 0.36 8.74|
Info: 28000 | 7094 20905 | 313 687 | 19619| 0.34 9.08|
Info: 29000 | 7249 21750 | 155 845 | 19523| 0.40 9.48|
Info: 30000 | 7463 22536 | 214 786 | 18857| 0.36 9.84|
Info: 31000 | 7810 23189 | 347 653 | 18322| 0.40 10.24|
Info: 32000 | 8230 23769 | 420 580 | 17895| 0.42 10.65|
Info: 33000 | 8560 24439 | 330 670 | 17393| 0.37 11.03|
Info: 34000 | 8903 25096 | 343 657 | 16890| 0.37 11.40|
Info: 35000 | 9274 25725 | 371 629 | 16389| 0.39 11.79|
Info: 36000 | 9696 26303 | 422 578 | 15957| 0.39 12.18|
Info: 37000 | 10173 26826 | 477 523 | 15576| 0.34 12.52|
Info: 38000 | 10607 27392 | 434 566 | 15181| 0.36 12.88|
Info: 39000 | 11047 27952 | 440 560 | 14745| 0.36 13.24|
Info: 40000 | 11506 28493 | 459 541 | 14279| 0.37 13.61|
Info: 41000 | 11900 29099 | 394 606 | 13894| 0.37 13.98|
Info: 42000 | 12208 29791 | 308 692 | 13684| 0.42 14.40|
Info: 43000 | 12491 30508 | 283 717 | 13540| 0.41 14.81|
Info: 44000 | 12768 31202 | 277 694 | 13196| 0.38 15.19|
Info: 45000 | 13140 31761 | 372 559 | 12726| 0.33 15.52|
Info: 46000 | 13495 32272 | 355 511 | 12157| 0.27 15.79|
Info: 47000 | 13780 32807 | 285 535 | 11485| 0.32 16.11|
Info: 48000 | 13994 33349 | 214 542 | 10723| 0.22 16.33|
Info: 49000 | 14252 33947 | 258 598 | 10013| 0.27 16.60|
Info: 50000 | 14549 34599 | 297 652 | 9327| 0.25 16.85|
Info: 51000 | 14972 35154 | 423 555 | 8884| 0.34 17.19|
Info: 52000 | 15390 35726 | 418 572 | 8458| 0.41 17.61|
Info: 53000 | 15779 36317 | 389 591 | 7907| 0.34 17.95|
Info: 54000 | 15874 37148 | 95 831 | 7056| 0.26 18.21|
Info: 55000 | 15931 38086 | 57 938 | 6130| 0.19 18.40|
Info: 56000 | 15985 39030 | 54 944 | 5249| 0.13 18.53|
Info: 57000 | 16024 39983 | 39 953 | 4296| 0.14 18.67|
Info: 58000 | 16120 40808 | 96 825 | 3399| 0.35 19.02|
Info: 59000 | 16252 41581 | 132 773 | 2552| 0.40 19.42|
Info: 60000 | 16406 42359 | 154 778 | 1748| 0.41 19.83|
Info: 61000 | 16491 43211 | 85 852 | 869| 0.35 20.18|
Info: 61910 | 16530 43873 | 39 662 | 0| 0.21 20.39|
Info: Routing complete.
Info: Router1 time 20.39s
Info: Checksum: 0x28550c85
Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
Info: curr total
Info: 0.5 0.5 Source SOC.Core.Control_Unit.state_TRELLIS_FF_Q_1.Q
Info: 1.4 2.0 Net SOC.Core.Control_Unit.state[4] (27,20) -> (35,18)
Info: Sink SOC.Core.Mdu.mul_done_LUT4_A_Z_LUT4_Z_D_LUT4_C_Z_LUT4_Z_D_LUT4_B_C_LUT4_D_Z_LUT4_Z_D_LUT4_C_Z_LUT4_Z_1.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 2.2 Source SOC.Core.Mdu.mul_done_LUT4_A_Z_LUT4_Z_D_LUT4_C_Z_LUT4_Z_D_LUT4_B_C_LUT4_D_Z_LUT4_Z_D_LUT4_C_Z_LUT4_Z_1.F
Info: 1.4 3.6 Net SOC.Core.Control_Unit.nextstate_LUT4_Z_1_C_LUT4_D_B[0] (35,18) -> (40,23)
Info: Sink SOC.Core.Mdu.mul_done_LUT4_A_Z_LUT4_Z_D_LUT4_D_Z_LUT4_Z_D_LUT4_Z_D_LUT4_C.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 3.8 Source SOC.Core.Mdu.mul_done_LUT4_A_Z_LUT4_Z_D_LUT4_D_Z_LUT4_Z_D_LUT4_Z_D_LUT4_C.F
Info: 0.4 4.2 Net SOC.Uart.response_LUT4_B_Z[0] (40,23) -> (40,23)
Info: Sink SOC.Leds.write_LUT4_Z_B_LUT4_Z.C
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 4.5 Source SOC.Leds.write_LUT4_Z_B_LUT4_Z.F
Info: 1.9 6.4 Net SOC.GPIOS.gpio_direction_LUT4_C_Z_LUT4_Z_D_LUT4_Z_C_LUT4_Z_D[0] (40,23) -> (25,30)
Info: Sink SOC.GPIOS.gpio_direction_LUT4_C_Z_LUT4_Z_D_LUT4_Z_C_LUT4_Z_D_LUT4_D.C
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 6.6 Source SOC.GPIOS.gpio_direction_LUT4_C_Z_LUT4_Z_D_LUT4_Z_C_LUT4_Z_D_LUT4_D.F
Info: 0.8 7.4 Net SOC.GPIOS.gpio_direction_LUT4_C_Z_LUT4_Z_D_LUT4_Z_C_LUT4_Z_D_LUT4_D_Z[2] (25,30) -> (25,36)
Info: Sink SOC.GPIOS.address_LUT4_Z_2.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 7.7 Source SOC.GPIOS.address_LUT4_Z_2.F
Info: 2.1 9.8 Net SOC.address[3] (25,36) -> (10,39)
Info: Sink SOC.Memory.memory.0.201$DPRAM_COMB3.B
Info: Defined in:
Info: Risco-5/src/peripheral/soc.v:23.5-23.18
Info: 0.2 10.0 Source SOC.Memory.memory.0.201$DPRAM_COMB3.F
Info: 0.9 10.9 Net SOC.Memory.memory.0.201_DO[1] (10,39) -> (10,40)
Info: Sink SOC.Memory.memory.0.201_DO_LUT4_A.B
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 11.1 Source SOC.Memory.memory.0.201_DO_LUT4_A.F
Info: 0.7 11.8 Net SOC.Memory.memory.0.193_DO_LUT4_A_Z[1] (10,40) -> (9,40)
Info: Sink SOC.Memory.memory.0.65_DO_LUT4_A_Z_LUT4_Z.C
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 12.0 Source SOC.Memory.memory.0.65_DO_LUT4_A_Z_LUT4_Z.F
Info: 0.6 12.6 Net SOC.Memory.memory.0.65_DO_LUT4_A_Z[3] (9,40) -> (7,40)
Info: Sink SOC.Memory.memory.0.129_DO_LUT4_A_Z_LUT4_C_Z_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 12.9 Source SOC.Memory.memory.0.129_DO_LUT4_A_Z_LUT4_C_Z_LUT4_Z.F
Info: 1.4 14.2 Net SOC.Memory.memory.0.129_DO_LUT4_A_Z_LUT4_C_Z[3] (7,40) -> (6,31)
Info: Sink SOC.Memory.memory.0.129_DO_LUT4_A_Z_LUT4_C_Z_LUT4_A.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 14.4 Source SOC.Memory.memory.0.129_DO_LUT4_A_Z_LUT4_C_Z_LUT4_A.F
Info: 0.0 14.4 Net SOC.Memory.memory.0.129_DO_LUT4_A_Z_LUT4_C_Z_LUT4_A_Z (6,31) -> (6,31)
Info: Sink SOC.Memory.memory.0.129_DO_LUT4_A_Z_LUT4_C_Z_PFUMX_C0_BLUT_LUT4_Z.F1
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:133.22-133.24
Info: 0.2 14.6 Source SOC.Memory.memory.0.129_DO_LUT4_A_Z_LUT4_C_Z_PFUMX_C0_BLUT_LUT4_Z.OFX
Info: 1.3 15.9 Net SOC.Core.read_data_LUT4_Z_10_C_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_C[4] (6,31) -> (22,31)
Info: Sink SOC.Memory.memory.0.231_DO_1_LUT4_A_Z_LUT4_C_Z_LUT4_B_Z_LUT4_Z_1.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 16.1 Source SOC.Memory.memory.0.231_DO_1_LUT4_A_Z_LUT4_C_Z_LUT4_B_Z_LUT4_Z_1.F
Info: 1.1 17.2 Net SOC.Core.read_data_PFUMX_Z_10_C0[3] (22,31) -> (20,35)
Info: Sink SOC.Core.read_data_PFUMX_Z_BLUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 17.5 Source SOC.Core.read_data_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: 1.9 19.3 Net SOC.read_data[8] (20,35) -> (20,17)
Info: Sink SOC.Core.instruction_register_TRELLIS_FF_Q_22.M
Info: Defined in:
Info: Risco-5/src/peripheral/soc.v:22.34-22.43
Info: 0.0 19.3 Setup SOC.Core.instruction_register_TRELLIS_FF_Q_22.M
Info: 3.5 ns logic, 15.8 ns routing
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
Info: curr total
Info: 0.0 0.0 Source gpios[1]$tr_io.O
Info: 2.7 2.7 Net gpios[1]$TRELLIS_IO_IN (6,71) -> (6,40)
Info: Sink SOC.GPIOS.Gpios[1].data_in_LUT4_C.A
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 2.9 Source SOC.GPIOS.Gpios[1].data_in_LUT4_C.F
Info: 1.6 4.5 Net SOC.GPIOS.Gpios[1].data_in_LUT4_C_Z[4] (6,40) -> (10,32)
Info: Sink SOC.GPIOS.Gpios[1].data_in_LUT4_C_Z_PFUMX_C0_BLUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 4.7 Source SOC.GPIOS.Gpios[1].data_in_LUT4_C_Z_PFUMX_C0_BLUT_LUT4_Z.OFX
Info: 0.7 5.5 Net SOC.GPIOS.Gpios[1].data_in_LUT4_C_Z_PFUMX_C0_Z[1] (10,32) -> (10,28)
Info: Sink SOC.Core.read_data_LUT4_Z_1.B
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 5.7 Source SOC.Core.read_data_LUT4_Z_1.F
Info: 1.0 6.7 Net SOC.read_data[1] (10,28) -> (10,23)
Info: Sink SOC.Core.instruction_register_TRELLIS_FF_Q_29.M
Info: Defined in:
Info: Risco-5/src/peripheral/soc.v:22.34-22.43
Info: 0.0 6.7 Setup SOC.Core.instruction_register_TRELLIS_FF_Q_29.M
Info: 0.7 ns logic, 6.0 ns routing
Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
Info: curr total
Info: 0.5 0.5 Source SOC.Leds.data_TRELLIS_FF_Q_24.Q
Info: 3.5 4.0 Net SOC.Leds.data[7] (22,27) -> (65,26)
Info: Sink led_LUT4_Z_2.D
Info: Defined in:
Info: Risco-5/src/peripheral/leds.v:15.12-15.16
Info: 0.2 4.2 Source led_LUT4_Z_2.F
Info: 2.1 6.4 Net led[7]$TRELLIS_IO_OUT (65,26) -> (90,20)
Info: Sink led[7]$tr_io.I
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:6.22-6.25
Info: 0.8 ns logic, 5.6 ns routing
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 51.72 MHz (PASS at 25.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 6.74 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 6.39 ns
Info: Slack histogram:
Info: legend: * represents 52 endpoint(s)
Info: + represents [1,52) endpoint(s)
Info: [ 20664, 21584) |+
Info: [ 21584, 22504) |+
Info: [ 22504, 23424) |***+
Info: [ 23424, 24344) |************+
Info: [ 24344, 25264) |*********+
Info: [ 25264, 26184) |*************+
Info: [ 26184, 27104) |****+
Info: [ 27104, 28024) |**+
Info: [ 28024, 28944) |***+
Info: [ 28944, 29864) |******************+
Info: [ 29864, 30784) |************************************************************
Info: [ 30784, 31704) |********************+
Info: [ 31704, 32624) |*****+
Info: [ 32624, 33544) |****+
Info: [ 33544, 34464) |****+
Info: [ 34464, 35384) |*****+
Info: [ 35384, 36304) |************+
Info: [ 36304, 37224) |*********+
Info: [ 37224, 38144) |*****+
Info: [ 38144, 39064) |*******+
Info: Program finished normally.
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