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Started by timer [Pipeline] Start of Pipeline [Pipeline] node Running on Jenkins in /var/lib/jenkins/workspace/Risco_5 [Pipeline] { [Pipeline] stage [Pipeline] { (Git Clone) [Pipeline] sh + rm -Rf Risco-5/ build/ [Pipeline] sh + git clone https://github.com/JN513/Risco-5 Cloning into 'Risco-5'... [Pipeline] sh + cd Risco-5 [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (IVerilog) [Pipeline] sh + mkdir -p build [Pipeline] sh + cp Risco-5/software/memory/add.hex Risco-5/software/memory/generic.hex [Pipeline] sh + /eda/oss-cad-suite/bin/iverilog -o build/soc_test.o -s soc_tb -I Risco-5/src/ Risco-5/src/core/alu.v Risco-5/src/core/alu_control.v Risco-5/src/core/control_unit.v Risco-5/src/core/core.v Risco-5/src/core/csr_unit.v Risco-5/src/core/immediate_generator.v Risco-5/src/core/mdu.v Risco-5/src/core/mux.v Risco-5/src/core/pc.v Risco-5/src/core/registers.v Risco-5/src/peripheral/bus.v Risco-5/src/peripheral/fifo.v Risco-5/src/peripheral/gpio.v Risco-5/src/peripheral/gpios.v Risco-5/src/peripheral/leds.v Risco-5/src/peripheral/memory.v Risco-5/src/peripheral/pwm.v Risco-5/src/peripheral/soc.v Risco-5/src/peripheral/uart.v Risco-5/src/peripheral/uart_rx.v Risco-5/src/peripheral/uart_tx.v Risco-5/tests/soc_test.v [Pipeline] sh + /eda/oss-cad-suite/bin/vvp build/soc_test.o ERROR: Risco-5/src/peripheral/memory.v:35: $readmemh: Unable to open software/memory/generic.hex for reading. VCD info: dumpfile build/soc.vcd opened for output. Risco-5/tests/soc_test.v:42: $finish called at 3606 (1s) [Pipeline] sh + rm -f Risco-5/software/memory/generic.hex [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Síntese) [Pipeline] parallel [Pipeline] { (Branch: OSS-Cad-Suite) [Pipeline] { (Branch: Gowin) [Pipeline] { (Branch: Vivado) [Pipeline] stage [Pipeline] { (OSS-Cad-Suite) [Pipeline] stage [Pipeline] { (Gowin) [Pipeline] stage [Pipeline] { (Vivado) [Pipeline] stage [Pipeline] { (Yosys) [Pipeline] sh [Pipeline] sh + rm -rf Risco-5/impl/pnr [Pipeline] sh + cd Risco-5/fpga/nexys4_ddr + mkdir build + /eda/vivado/Vivado/2023.2/bin/vivado -mode batch -nolog -nojournal -source run.tcl + /eda/oss-cad-suite/bin/yosys -p read_verilog Risco-5/fpga/ecp5/*.v; read_verilog Risco-5/debug/reset.v; read_verilog Risco-5/src/core/*.v; read_verilog Risco-5/src/peripheral/*.v; synth_ecp5 -json ./build/out.json -abc9 /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2024 Claire Xenia Wolf <claire@yosyshq.com> | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.42+36 (git sha1 07daf61ae, clang++ 14.0.0-1ubuntu1.1 -fPIC -Os) -- Running command ` read_verilog Risco-5/fpga/ecp5/*.v; read_verilog Risco-5/debug/reset.v; read_verilog Risco-5/src/core/*.v; read_verilog Risco-5/src/peripheral/*.v; synth_ecp5 -json ./build/out.json -abc9 ' -- 1. Executing Verilog-2005 frontend: Risco-5/fpga/ecp5/main.v Parsing Verilog input from `Risco-5/fpga/ecp5/main.v' to AST representation. Generating RTLIL representation for module `\top'. Successfully finished Verilog frontend. 2. Executing Verilog-2005 frontend: Risco-5/debug/reset.v Parsing Verilog input from `Risco-5/debug/reset.v' to AST representation. Generating RTLIL representation for module `\ResetBootSystem'. Successfully finished Verilog frontend. 3. Executing Verilog-2005 frontend: Risco-5/src/core/alu.v Parsing Verilog input from `Risco-5/src/core/alu.v' to AST representation. Generating RTLIL representation for module `\Alu'. Successfully finished Verilog frontend. 4. Executing Verilog-2005 frontend: Risco-5/src/core/alu_control.v Parsing Verilog input from `Risco-5/src/core/alu_control.v' to AST representation. Generating RTLIL representation for module `\ALU_Control'. Successfully finished Verilog frontend. 5. Executing Verilog-2005 frontend: Risco-5/src/core/control_unit.v Parsing Verilog input from `Risco-5/src/core/control_unit.v' to AST representation. Generating RTLIL representation for module `\Control_Unit'. Risco-5/src/core/control_unit.v:114: Warning: Identifier `\second_block_write_src_b' is implicitly declared. Successfully finished Verilog frontend. 6. Executing Verilog-2005 frontend: Risco-5/src/core/core.v Parsing Verilog input from `Risco-5/src/core/core.v' to AST representation. Generating RTLIL representation for module `\Core'. Risco-5/src/core/core.v:187: Warning: Identifier `\pc_source' is implicitly declared. Successfully finished Verilog frontend. 7. Executing Verilog-2005 frontend: Risco-5/src/core/csr_unit.v Parsing Verilog input from `Risco-5/src/core/csr_unit.v' to AST representation. Successfully finished Verilog frontend. 8. Executing Verilog-2005 frontend: Risco-5/src/core/immediate_generator.v Parsing Verilog input from `Risco-5/src/core/immediate_generator.v' to AST representation. Generating RTLIL representation for module `\Immediate_Generator'. Successfully finished Verilog frontend. 9. Executing Verilog-2005 frontend: Risco-5/src/core/mdu.v Parsing Verilog input from `Risco-5/src/core/mdu.v' to AST representation. Successfully finished Verilog frontend. 10. Executing Verilog-2005 frontend: Risco-5/src/core/mux.v Parsing Verilog input from `Risco-5/src/core/mux.v' to AST representation. Generating RTLIL representation for module `\MUX'. Successfully finished Verilog frontend. 11. Executing Verilog-2005 frontend: Risco-5/src/core/pc.v Parsing Verilog input from `Risco-5/src/core/pc.v' to AST representation. Generating RTLIL representation for module `\PC'. Successfully finished Verilog frontend. 12. Executing Verilog-2005 frontend: Risco-5/src/core/registers.v Parsing Verilog input from `Risco-5/src/core/registers.v' to AST representation. Generating RTLIL representation for module `\Registers'. Successfully finished Verilog frontend. 13. Executing Verilog-2005 frontend: Risco-5/src/peripheral/bus.v Parsing Verilog input from `Risco-5/src/peripheral/bus.v' to AST representation. Generating RTLIL representation for module `\BUS'. Successfully finished Verilog frontend. 14. Executing Verilog-2005 frontend: Risco-5/src/peripheral/fifo.v Parsing Verilog input from `Risco-5/src/peripheral/fifo.v' to AST representation. Generating RTLIL representation for module `\FIFO'. Successfully finished Verilog frontend. 15. Executing Verilog-2005 frontend: Risco-5/src/peripheral/gpio.v Parsing Verilog input from `Risco-5/src/peripheral/gpio.v' to AST representation. Warning: Yosys has only limited support for tri-state logic at the moment. (Risco-5/src/peripheral/gpio.v:13) Generating RTLIL representation for module `\GPIO'. Successfully finished Verilog frontend. 16. Executing Verilog-2005 frontend: Risco-5/src/peripheral/gpios.v Parsing Verilog input from `Risco-5/src/peripheral/gpios.v' to AST representation. Generating RTLIL representation for module `\GPIOS'. Successfully finished Verilog frontend. 17. Executing Verilog-2005 frontend: Risco-5/src/peripheral/leds.v Parsing Verilog input from `Risco-5/src/peripheral/leds.v' to AST representation. Generating RTLIL representation for module `\LEDs'. Successfully finished Verilog frontend. 18. Executing Verilog-2005 frontend: Risco-5/src/peripheral/memory.v Parsing Verilog input from `Risco-5/src/peripheral/memory.v' to AST representation. Generating RTLIL representation for module `\Memory'. Successfully finished Verilog frontend. 19. Executing Verilog-2005 frontend: Risco-5/src/peripheral/pwm.v Parsing Verilog input from `Risco-5/src/peripheral/pwm.v' to AST representation. Generating RTLIL representation for module `\PWM'. Successfully finished Verilog frontend. 20. Executing Verilog-2005 frontend: Risco-5/src/peripheral/soc.v Parsing Verilog input from `Risco-5/src/peripheral/soc.v' to AST representation. Generating RTLIL representation for module `\Risco_5_SOC'. Successfully finished Verilog frontend. 21. Executing Verilog-2005 frontend: Risco-5/src/peripheral/uart.v Parsing Verilog input from `Risco-5/src/peripheral/uart.v' to AST representation. Generating RTLIL representation for module `\UART'. Successfully finished Verilog frontend. 22. Executing Verilog-2005 frontend: Risco-5/src/peripheral/uart_rx.v Parsing Verilog input from `Risco-5/src/peripheral/uart_rx.v' to AST representation. Generating RTLIL representation for module `\uart_tool_rx'. Successfully finished Verilog frontend. 23. Executing Verilog-2005 frontend: Risco-5/src/peripheral/uart_tx.v Parsing Verilog input from `Risco-5/src/peripheral/uart_tx.v' to AST representation. Generating RTLIL representation for module `\uart_tool_tx'. Successfully finished Verilog frontend. 24. Executing SYNTH_ECP5 pass. 24.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v' to AST representation. Generating RTLIL representation for module `\LUT4'. Generating RTLIL representation for module `\$__ABC9_LUT5'. Generating RTLIL representation for module `\$__ABC9_LUT6'. Generating RTLIL representation for module `\$__ABC9_LUT7'. Generating RTLIL representation for module `\L6MUX21'. Generating RTLIL representation for module `\CCU2C'. Generating RTLIL representation for module `\TRELLIS_RAM16X2'. Generating RTLIL representation for module `\PFUMX'. Generating RTLIL representation for module `\TRELLIS_DPR16X4'. Generating RTLIL representation for module `\DPR16X4C'. Generating RTLIL representation for module `\LUT2'. Generating RTLIL representation for module `\TRELLIS_FF'. Generating RTLIL representation for module `\TRELLIS_IO'. Generating RTLIL representation for module `\INV'. Generating RTLIL representation for module `\TRELLIS_COMB'. Generating RTLIL representation for module `\DP16KD'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Successfully finished Verilog frontend. 24.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_bb.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_bb.v' to AST representation. Generating RTLIL representation for module `\MULT18X18D'. Generating RTLIL representation for module `\ALU54B'. Generating RTLIL representation for module `\EHXPLLL'. Generating RTLIL representation for module `\DTR'. Generating RTLIL representation for module `\OSCG'. Generating RTLIL representation for module `\USRMCLK'. Generating RTLIL representation for module `\JTAGG'. Generating RTLIL representation for module `\DELAYF'. Generating RTLIL representation for module `\DELAYG'. Generating RTLIL representation for module `\IDDRX1F'. Generating RTLIL representation for module `\IDDRX2F'. Generating RTLIL representation for module `\IDDR71B'. Generating RTLIL representation for module `\IDDRX2DQA'. Generating RTLIL representation for module `\ODDRX1F'. Generating RTLIL representation for module `\ODDRX2F'. Generating RTLIL representation for module `\ODDR71B'. Generating RTLIL representation for module `\OSHX2A'. Generating RTLIL representation for module `\ODDRX2DQA'. Generating RTLIL representation for module `\ODDRX2DQSB'. Generating RTLIL representation for module `\TSHX2DQA'. Generating RTLIL representation for module `\TSHX2DQSA'. Generating RTLIL representation for module `\DQSBUFM'. Generating RTLIL representation for module `\DDRDLLA'. Generating RTLIL representation for module `\DLLDELD'. Generating RTLIL representation for module `\CLKDIVF'. Generating RTLIL representation for module `\ECLKSYNCB'. Generating RTLIL representation for module `\ECLKBRIDGECS'. Generating RTLIL representation for module `\DCCA'. Generating RTLIL representation for module `\DCSC'. Generating RTLIL representation for module `\DCUA'. Generating RTLIL representation for module `\EXTREFB'. Generating RTLIL representation for module `\PCSCLKDIV'. Generating RTLIL representation for module `\PUR'. Generating RTLIL representation for module `\GSR'. Generating RTLIL representation for module `\SGSR'. Generating RTLIL representation for module `\PDPW16KD'. Successfully finished Verilog frontend. 24.3. Executing HIERARCHY pass (managing design hierarchy). 24.3.1. Finding top of design hierarchy.. root of 0 design levels: uart_tool_tx root of 0 design levels: uart_tool_rx root of 1 design levels: UART root of 2 design levels: Risco_5_SOC root of 0 design levels: PWM root of 0 design levels: Memory root of 0 design levels: LEDs root of 1 design levels: GPIOS root of 0 design levels: GPIO root of 0 design levels: FIFO root of 0 design levels: BUS root of 0 design levels: Registers root of 0 design levels: PC root of 0 design levels: MUX root of 0 design levels: Immediate_Generator root of 1 design levels: Core root of 0 design levels: Control_Unit root of 0 design levels: ALU_Control root of 0 design levels: Alu root of 0 design levels: ResetBootSystem root of 3 design levels: top Automatically selected top as design top module. 24.3.2. Analyzing design hierarchy.. Top module: \top Used module: \Risco_5_SOC Used module: \GPIOS Used module: \GPIO Used module: \PWM Used module: \UART Used module: \uart_tool_tx Used module: \uart_tool_rx Used module: \FIFO Used module: \LEDs Used module: \BUS Used module: \Memory Used module: \Core Used module: \Immediate_Generator Used module: \Alu Used module: \ALU_Control Used module: \Control_Unit Used module: \Registers Used module: \MUX Used module: \PC Used module: \ResetBootSystem Parameter \CLOCK_FREQ = 25000000 Parameter \BIT_RATE = 115200 Parameter \MEMORY_SIZE = 128 Parameter \MEMORY_FILE = 296'00101110001011100010111100101110001011100010111101110011011011110110011001110100011101110110000101110010011001010010111101101101011001010110110101101111011100100111100100101111011001100111000001100111011000010101111101110100011001010111001101110100010111110011001000101110011010000110010101111000 Parameter \GPIO_WIDHT = 6 Parameter \UART_BUFFER_SIZE = 16 24.3.3. Executing AST frontend in derive mode using pre-parsed AST for module `\Risco_5_SOC'. Parameter \CLOCK_FREQ = 25000000 Parameter \BIT_RATE = 115200 Parameter \MEMORY_SIZE = 128 Parameter \MEMORY_FILE = 296'00101110001011100010111100101110001011100010111101110011011011110110011001110100011101110110000101110010011001010010111101101101011001010110110101101111011100100111100100101111011001100111000001100111011000010101111101110100011001010111001101110100010111110011001000101110011010000110010101111000 Parameter \GPIO_WIDHT = 6 Parameter \UART_BUFFER_SIZE = 16 Generating RTLIL representation for module `$paramod$e582745b5be06b945636a80f333e3e68b035ee01\Risco_5_SOC'. Parameter \CYCLES = 20 24.3.4. Executing AST frontend in derive mode using pre-parsed AST for module `\ResetBootSystem'. Parameter \CYCLES = 20 Generating RTLIL representation for module `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100'. Parameter \WIDHT = 5 24.3.5. Executing AST frontend in derive mode using pre-parsed AST for module `\GPIOS'. Parameter \WIDHT = 5 Generating RTLIL representation for module `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000101'. Parameter \CLK_FREQ = 25000000 Parameter \BIT_RATE = 9600 Parameter \BUFFER_SIZE = 8 24.3.6. Executing AST frontend in derive mode using pre-parsed AST for module `\UART'. Parameter \CLK_FREQ = 25000000 Parameter \BIT_RATE = 9600 Parameter \BUFFER_SIZE = 8 Generating RTLIL representation for module `$paramod$65634474087d1ba2b03796f9a45556e4bd507a57\UART'. Parameter \MEMORY_FILE = { } Parameter \MEMORY_SIZE = 4096 24.3.7. Executing AST frontend in derive mode using pre-parsed AST for module `\Memory'. Parameter \MEMORY_FILE = { } Parameter \MEMORY_SIZE = 4096 Generating RTLIL representation for module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'. Parameter \BOOT_ADDRESS = 0 24.3.8. Executing AST frontend in derive mode using pre-parsed AST for module `\Core'. Parameter \BOOT_ADDRESS = 0 Generating RTLIL representation for module `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000'. Risco-5/src/core/core.v:187: Warning: Identifier `\pc_source' is implicitly declared. Reprocessing module GPIOS because instantiated module PWM has become available. Generating RTLIL representation for module `\GPIOS'. Parameter \BIT_RATE = 9600 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 24.3.9. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tool_tx'. Parameter \BIT_RATE = 9600 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 Generating RTLIL representation for module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx'. Parameter \BIT_RATE = 9600 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 24.3.10. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tool_rx'. Parameter \BIT_RATE = 9600 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 Generating RTLIL representation for module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx'. Parameter \DEPTH = 8 Parameter \WIDTH = 8 24.3.11. Executing AST frontend in derive mode using pre-parsed AST for module `\FIFO'. Parameter \DEPTH = 8 Parameter \WIDTH = 8 Generating RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'. Parameter \DEPTH = 8 Parameter \WIDTH = 8 Found cached RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'. 24.3.12. Analyzing design hierarchy.. Top module: \top Used module: $paramod$e582745b5be06b945636a80f333e3e68b035ee01\Risco_5_SOC Used module: \GPIOS Used module: \GPIO Used module: \PWM Used module: \UART Used module: $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx Used module: $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx Used module: $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO Used module: \LEDs Used module: \BUS Used module: \Memory Used module: \Core Used module: \Immediate_Generator Used module: \Alu Used module: \ALU_Control Used module: \Control_Unit Used module: \Registers Used module: \MUX Used module: \PC Used module: $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100 Parameter \WIDHT = 6 24.3.13. Executing AST frontend in derive mode using pre-parsed AST for module `\GPIOS'. Parameter \WIDHT = 6 Generating RTLIL representation for module `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110'. Parameter \CLK_FREQ = 25000000 Parameter \BIT_RATE = 115200 Parameter \BUFFER_SIZE = 16 24.3.14. Executing AST frontend in derive mode using pre-parsed AST for module `\UART'. Parameter \CLK_FREQ = 25000000 Parameter \BIT_RATE = 115200 Parameter \BUFFER_SIZE = 16 Generating RTLIL representation for module `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART'. Parameter \MEMORY_FILE = 296'00101110001011100010111100101110001011100010111101110011011011110110011001110100011101110110000101110010011001010010111101101101011001010110110101101111011100100111100100101111011001100111000001100111011000010101111101110100011001010111001101110100010111110011001000101110011010000110010101111000 Parameter \MEMORY_SIZE = 128 24.3.15. Executing AST frontend in derive mode using pre-parsed AST for module `\Memory'. Parameter \MEMORY_FILE = 296'00101110001011100010111100101110001011100010111101110011011011110110011001110100011101110110000101110010011001010010111101101101011001010110110101101111011100100111100100101111011001100111000001100111011000010101111101110100011001010111001101110100010111110011001000101110011010000110010101111000 Parameter \MEMORY_SIZE = 128 Generating RTLIL representation for module `$paramod$c31b266b644e4b515b582da1252fb11d77b9f11b\Memory'. Parameter \BOOT_ADDRESS = 0 Found cached RTLIL representation for module `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000'. 24.3.16. Analyzing design hierarchy.. Top module: \top Used module: $paramod$e582745b5be06b945636a80f333e3e68b035ee01\Risco_5_SOC Used module: $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110 Used module: \GPIO Used module: \PWM Used module: $paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART Used module: \uart_tool_tx Used module: \uart_tool_rx Used module: \FIFO Used module: \LEDs Used module: \BUS Used module: $paramod$c31b266b644e4b515b582da1252fb11d77b9f11b\Memory Used module: $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000 Used module: \Immediate_Generator Used module: \Alu Used module: \ALU_Control Used module: \Control_Unit Used module: \Registers Used module: \MUX Used module: \PC Used module: $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100 Parameter \BIT_RATE = 115200 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 24.3.17. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tool_tx'. Parameter \BIT_RATE = 115200 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 Generating RTLIL representation for module `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx'. Parameter \BIT_RATE = 115200 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 24.3.18. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tool_rx'. Parameter \BIT_RATE = 115200 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 Generating RTLIL representation for module `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx'. Parameter \DEPTH = 16 Parameter \WIDTH = 8 24.3.19. Executing AST frontend in derive mode using pre-parsed AST for module `\FIFO'. Parameter \DEPTH = 16 Parameter \WIDTH = 8 Generating RTLIL representation for module `$paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO'. Parameter \DEPTH = 16 Parameter \WIDTH = 8 Found cached RTLIL representation for module `$paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO'. 24.3.20. Analyzing design hierarchy.. Top module: \top Used module: $paramod$e582745b5be06b945636a80f333e3e68b035ee01\Risco_5_SOC Used module: $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110 Used module: \GPIO Used module: \PWM Used module: $paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART Used module: $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx Used module: $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx Used module: $paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO Used module: \LEDs Used module: \BUS Used module: $paramod$c31b266b644e4b515b582da1252fb11d77b9f11b\Memory Used module: $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000 Used module: \Immediate_Generator Used module: \Alu Used module: \ALU_Control Used module: \Control_Unit Used module: \Registers Used module: \MUX Used module: \PC Used module: $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100 24.3.21. Analyzing design hierarchy.. Top module: \top Used module: $paramod$e582745b5be06b945636a80f333e3e68b035ee01\Risco_5_SOC Used module: $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110 Used module: \GPIO Used module: \PWM Used module: $paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART Used module: $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx Used module: $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx Used module: $paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO Used module: \LEDs Used module: \BUS Used module: $paramod$c31b266b644e4b515b582da1252fb11d77b9f11b\Memory Used module: $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000 Used module: \Immediate_Generator Used module: \Alu Used module: \ALU_Control Used module: \Control_Unit Used module: \Registers Used module: \MUX Used module: \PC Used module: $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100 Removing unused module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx'. Removing unused module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx'. Removing unused module `\GPIOS'. Removing unused module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'. Removing unused module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'. Removing unused module `$paramod$65634474087d1ba2b03796f9a45556e4bd507a57\UART'. Removing unused module `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000101'. Removing unused module `\uart_tool_tx'. Removing unused module `\uart_tool_rx'. Removing unused module `\UART'. Removing unused module `\Risco_5_SOC'. Removing unused module `\Memory'. Removing unused module `\FIFO'. Removing unused module `\Core'. Removing unused module `\ResetBootSystem'. Removed 15 unused modules. 24.4. Executing PROC pass (convert processes to netlists). 24.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$600'. Found and cleaned up 1 empty switch in `$paramod$c31b266b644e4b515b582da1252fb11d77b9f11b\Memory.$proc$Risco-5/src/peripheral/memory.v:0$1299'. Cleaned up 2 empty switches. 24.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$707 in module TRELLIS_FF. Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$659 in module DPR16X4C. Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$601 in module TRELLIS_DPR16X4. Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:192$1392 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx. Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:181$1390 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx. Marked 2 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:166$1382 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx. Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:155$1379 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx. Marked 2 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:143$1373 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx. Marked 3 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:128$1368 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx. Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:111$1363 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx. Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:92$1354 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx. Marked 4 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:170$1341 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx. Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:159$1339 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx. Marked 2 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:144$1331 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx. Marked 4 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:127$1317 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx. Marked 3 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:112$1311 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx. Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:95$1306 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx. Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/memory.v:59$1297 in module $paramod$c31b266b644e4b515b582da1252fb11d77b9f11b\Memory. Marked 3 switch rules as full_case in process $proc$Risco-5/src/peripheral/memory.v:47$1260 in module $paramod$c31b266b644e4b515b582da1252fb11d77b9f11b\Memory. Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart.v:161$1243 in module $paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART. Marked 7 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart.v:67$1235 in module $paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART. Marked 3 switch rules as full_case in process $proc$Risco-5/src/peripheral/pwm.v:15$364 in module PWM. Marked 3 switch rules as full_case in process $proc$Risco-5/src/peripheral/gpios.v:63$1169 in module $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110. Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/leds.v:27$315 in module LEDs. Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/core.v:305$866 in module $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000. Marked 2 switch rules as full_case in process $proc$Risco-5/src/peripheral/fifo.v:31$1397 in module $paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO. Marked 2 switch rules as full_case in process $proc$Risco-5/src/core/registers.v:33$72 in module Registers. Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/pc.v:15$62 in module PC. Removed 1 dead cases from process $proc$Risco-5/src/core/mux.v:14$61 in module MUX. Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/mux.v:14$61 in module MUX. Marked 2 switch rules as full_case in process $proc$Risco-5/src/core/immediate_generator.v:18$60 in module Immediate_Generator. Marked 5 switch rules as full_case in process $proc$Risco-5/debug/reset.v:24$710 in module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100. Marked 6 switch rules as full_case in process $proc$Risco-5/src/core/control_unit.v:157$39 in module Control_Unit. Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/control_unit.v:149$38 in module Control_Unit. Removed 1 dead cases from process $proc$Risco-5/src/core/alu_control.v:9$31 in module ALU_Control. Marked 4 switch rules as full_case in process $proc$Risco-5/src/core/alu_control.v:9$31 in module ALU_Control. Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/alu.v:26$11 in module Alu. Removed a total of 2 dead cases. 24.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 10 redundant assignments. Promoted 139 assignments to connections. 24.4.4. Executing PROC_INIT pass (extract init attributes). Found init rule in `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$708'. Set init value: \Q = 1'0 Found init rule in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:127$1394'. Set init value: \i = 0 Found init rule in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:111$1347'. Set init value: \i = 0 Found init rule in `$paramod$c31b266b644e4b515b582da1252fb11d77b9f11b\Memory.$proc$Risco-5/src/peripheral/memory.v:0$1299'. Set init value: \memory_response = 1'0 Found init rule in `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.$proc$Risco-5/src/peripheral/uart.v:0$1253'. Set init value: \state = 4'0000 Set init value: \counter = 3'000 Set init value: \read_data = 0 Set init value: \response = 1'0 Set init value: \uart_tx_en = 1'0 Set init value: \tx_fifo_read = 1'0 Set init value: \tx_fifo_write = 1'0 Set init value: \rx_fifo_read = 1'0 Set init value: \rx_fifo_write = 1'0 Set init value: \uart_tx_data = 8'00000000 Set init value: \tx_fifo_write_data = 8'00000000 Set init value: \rx_fifo_write_data = 8'00000000 Found init rule in `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:0$1234'. Set init value: \is_pwm = 2'00 Found init rule in `\LEDs.$proc$Risco-5/src/peripheral/leds.v:0$318'. Set init value: \data = 0 Found init rule in `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:0$869'. Set init value: \instruction_register = 0 Set init value: \memory_register = 0 Set init value: \alu_out_register = 0 Set init value: \register_data_1 = 0 Set init value: \register_data_2 = 0 Set init value: \pc_old = 0 Found init rule in `$paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO.$proc$Risco-5/src/peripheral/fifo.v:0$1424'. Set init value: \counter = 6'000000 Set init value: \read_ptr = 6'000000 Set init value: \write_ptr = 6'000000 Found init rule in `\PC.$proc$Risco-5/src/core/pc.v:0$65'. Set init value: \Output = 0 Found init rule in `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:0$716'. Set init value: \reset_o = 1'0 Set init value: \state = 2'01 Set init value: \counter = 6'000000 Found init rule in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:0$42'. Set init value: \state = 6'000000 Set init value: \is_immediate = 1'0 Set init value: \pc_write = 1'0 Set init value: \ir_write = 1'0 Set init value: \pc_source = 1'0 Set init value: \reg_write = 1'0 Set init value: \memory_read = 1'0 Set init value: \memory_write = 1'0 Set init value: \pc_write_cond = 1'0 Set init value: \csr_write_enable = 1'0 Set init value: \alu_input_selector = 1'0 Set init value: \save_address = 1'0 Set init value: \save_value = 1'0 Set init value: \save_value_2 = 1'0 Set init value: \save_write_value = 1'0 Set init value: \control_memory_op = 1'0 Set init value: \write_data_in = 1'0 Set init value: \mdu_start = 1'0 Set init value: \lorD = 2'00 Set init value: \aluop = 2'00 Set init value: \alu_src_a = 3'000 Set init value: \alu_src_b = 3'000 Set init value: \memory_to_reg = 3'000 Set init value: \control_unit_memory_op = 3'010 Set init value: \control_unit_aluop = 4'0000 Set init value: \nextstate = 6'000000 24.4.5. Executing PROC_ARST pass (detect async resets in processes). 24.4.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~95 debug messages> 24.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$708'. Creating decoders for process `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$707'. 1/1: $0\Q[0:0] Creating decoders for process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$682'. Creating decoders for process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$659'. 1/3: $1$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$658_EN[3:0]$665 2/3: $1$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$658_DATA[3:0]$664 3/3: $1$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$658_ADDR[3:0]$663 Creating decoders for process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$625'. Creating decoders for process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$601'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$599_EN[3:0]$607 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$599_DATA[3:0]$606 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$599_ADDR[3:0]$605 Creating decoders for process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$600'. Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:127$1394'. Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:192$1392'. 1/2: $0\rxd_reg_0[0:0] 2/2: $0\rxd_reg[0:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:181$1390'. 1/1: $0\fsm_state[2:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:166$1382'. 1/1: $0\cycle_counter[8:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:155$1379'. 1/1: $0\bit_sample[0:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:143$1373'. 1/1: $0\bit_counter[3:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:128$1368'. 1/11: $3\i[31:0] 2/11: $0\recieved_data[7:0] [1] 3/11: $0\recieved_data[7:0] [0] 4/11: $0\recieved_data[7:0] [2] 5/11: $0\recieved_data[7:0] [3] 6/11: $0\recieved_data[7:0] [4] 7/11: $0\recieved_data[7:0] [5] 8/11: $0\recieved_data[7:0] [6] 9/11: $0\recieved_data[7:0] [7] 10/11: $1\i[31:0] 11/11: $2\i[31:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:111$1363'. 1/1: $1\n_fsm_state[2:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:92$1354'. 1/1: $0\uart_rx_data[7:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:111$1347'. Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:170$1341'. 1/1: $0\txd_reg[0:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:159$1339'. 1/1: $0\fsm_state[2:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:144$1331'. 1/1: $0\cycle_counter[8:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:127$1317'. 1/1: $0\bit_counter[3:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:112$1311'. 1/11: $3\i[31:0] 2/11: $0\data_to_send[7:0] [1] 3/11: $0\data_to_send[7:0] [0] 4/11: $0\data_to_send[7:0] [2] 5/11: $0\data_to_send[7:0] [3] 6/11: $0\data_to_send[7:0] [4] 7/11: $0\data_to_send[7:0] [5] 8/11: $0\data_to_send[7:0] [6] 9/11: $0\data_to_send[7:0] [7] 10/11: $1\i[31:0] 11/11: $2\i[31:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:95$1306'. 1/1: $1\n_fsm_state[2:0] Creating decoders for process `$paramod$c31b266b644e4b515b582da1252fb11d77b9f11b\Memory.$proc$Risco-5/src/peripheral/memory.v:0$1299'. Creating decoders for process `$paramod$c31b266b644e4b515b582da1252fb11d77b9f11b\Memory.$proc$Risco-5/src/peripheral/memory.v:59$1297'. 1/1: $1\read_data[31:0] Creating decoders for process `$paramod$c31b266b644e4b515b582da1252fb11d77b9f11b\Memory.$proc$Risco-5/src/peripheral/memory.v:47$1260'. 1/24: $3$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1255_EN[31:0]$1291 2/24: $3$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1255_DATA[31:0]$1292 3/24: $3$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1255_ADDR[31:0]$1293 4/24: $3$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1256_ADDR[31:0]$1296 5/24: $3$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1256_DATA[31:0]$1295 6/24: $3$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1256_EN[31:0]$1294 7/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1254_EN[31:0]$1284 8/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1254_DATA[31:0]$1285 9/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1254_ADDR[31:0]$1286 10/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1256_ADDR[31:0]$1289 11/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1256_DATA[31:0]$1288 12/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1256_EN[31:0]$1287 13/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1255_ADDR[31:0]$1283 14/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1255_DATA[31:0]$1282 15/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1255_EN[31:0]$1281 16/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1256_ADDR[31:0]$1279 17/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1256_DATA[31:0]$1278 18/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1256_EN[31:0]$1277 19/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1254_ADDR[31:0]$1276 20/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1254_DATA[31:0]$1275 21/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1254_EN[31:0]$1274 22/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1255_ADDR[31:0]$1273 23/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1255_DATA[31:0]$1272 24/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1255_EN[31:0]$1271 Creating decoders for process `$paramod$c31b266b644e4b515b582da1252fb11d77b9f11b\Memory.$proc$Risco-5/src/peripheral/memory.v:39$1258'. 1/1: $0\memory_response[0:0] Creating decoders for process `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.$proc$Risco-5/src/peripheral/uart.v:0$1253'. Creating decoders for process `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.$proc$Risco-5/src/peripheral/uart.v:161$1243'. 1/5: $0\rx_fifo_write[0:0] 2/5: $0\tx_fifo_read[0:0] 3/5: $0\uart_tx_en[0:0] 4/5: $0\rx_fifo_write_data[7:0] 5/5: $0\uart_tx_data[7:0] Creating decoders for process `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.$proc$Risco-5/src/peripheral/uart.v:67$1235'. 1/8: $0\tx_fifo_write[0:0] 2/8: $0\rx_fifo_read[0:0] 3/8: $0\response[0:0] 4/8: $0\write_data_buffer[31:0] 5/8: $0\tx_fifo_write_data[7:0] 6/8: $0\read_data[31:0] 7/8: $0\counter[2:0] 8/8: $0\state[3:0] Creating decoders for process `\PWM.$proc$Risco-5/src/peripheral/pwm.v:15$364'. 1/2: $0\pwm_out[0:0] 2/2: $0\counter[31:0] Creating decoders for process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:0$1234'. Creating decoders for process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:63$1169'. 1/21: $3$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:73$1164_EN[15:0]$1193 2/21: $3$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:73$1164_DATA[15:0]$1192 3/21: $3$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:73$1164_ADDR[0:0]$1191 4/21: $3$memwr$\period$Risco-5/src/peripheral/gpios.v:72$1163_EN[15:0]$1190 5/21: $3$memwr$\period$Risco-5/src/peripheral/gpios.v:72$1163_DATA[15:0]$1189 6/21: $3$memwr$\period$Risco-5/src/peripheral/gpios.v:72$1163_ADDR[0:0]$1188 7/21: $2$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:73$1164_EN[15:0]$1187 8/21: $2$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:73$1164_DATA[15:0]$1186 9/21: $2$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:73$1164_ADDR[0:0]$1185 10/21: $2$memwr$\period$Risco-5/src/peripheral/gpios.v:72$1163_EN[15:0]$1184 11/21: $2$memwr$\period$Risco-5/src/peripheral/gpios.v:72$1163_DATA[15:0]$1183 12/21: $2$memwr$\period$Risco-5/src/peripheral/gpios.v:72$1163_ADDR[0:0]$1182 13/21: $1$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:73$1164_EN[15:0]$1181 14/21: $1$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:73$1164_DATA[15:0]$1180 15/21: $1$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:73$1164_ADDR[0:0]$1179 16/21: $1$memwr$\period$Risco-5/src/peripheral/gpios.v:72$1163_EN[15:0]$1178 17/21: $1$memwr$\period$Risco-5/src/peripheral/gpios.v:72$1163_DATA[15:0]$1177 18/21: $1$memwr$\period$Risco-5/src/peripheral/gpios.v:72$1163_ADDR[0:0]$1176 19/21: $0\is_pwm[1:0] 20/21: $0\gpio_value[5:0] 21/21: $0\gpio_direction[5:0] Creating decoders for process `\LEDs.$proc$Risco-5/src/peripheral/leds.v:0$318'. Creating decoders for process `\LEDs.$proc$Risco-5/src/peripheral/leds.v:27$315'. 1/1: $0\data[31:0] Creating decoders for process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:0$869'. Creating decoders for process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:305$866'. 1/6: $0\alu_out_register[31:0] 2/6: $0\register_data_2[31:0] 3/6: $0\register_data_1[31:0] 4/6: $0\memory_register[31:0] 5/6: $0\pc_old[31:0] 6/6: $0\instruction_register[31:0] Creating decoders for process `$paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO.$proc$Risco-5/src/peripheral/fifo.v:0$1424'. Creating decoders for process `$paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO.$proc$Risco-5/src/peripheral/fifo.v:31$1397'. 1/9: $2$memwr$\memory$Risco-5/src/peripheral/fifo.v:39$1395_EN[7:0]$1409 2/9: $2$memwr$\memory$Risco-5/src/peripheral/fifo.v:39$1395_DATA[7:0]$1408 3/9: $2$memwr$\memory$Risco-5/src/peripheral/fifo.v:39$1395_ADDR[5:0]$1407 4/9: $1$memwr$\memory$Risco-5/src/peripheral/fifo.v:39$1395_EN[7:0]$1404 5/9: $1$memwr$\memory$Risco-5/src/peripheral/fifo.v:39$1395_DATA[7:0]$1403 6/9: $1$memwr$\memory$Risco-5/src/peripheral/fifo.v:39$1395_ADDR[5:0]$1402 7/9: $0\write_ptr[5:0] 8/9: $0\read_ptr[5:0] 9/9: $0\counter[5:0] Creating decoders for process `\Registers.$proc$Risco-5/src/core/registers.v:0$90'. Creating decoders for process `\Registers.$proc$Risco-5/src/core/registers.v:33$72'. 1/9: $2$memwr$\registers$Risco-5/src/core/registers.v:37$68_EN[31:0]$87 2/9: $2$memwr$\registers$Risco-5/src/core/registers.v:37$68_DATA[31:0]$86 3/9: $2$memwr$\registers$Risco-5/src/core/registers.v:37$68_ADDR[4:0]$85 4/9: $2$memwr$\registers$Risco-5/src/core/registers.v:39$69_EN[31:0]$88 5/9: $1$memwr$\registers$Risco-5/src/core/registers.v:35$67_EN[31:0]$79 6/9: $1$memwr$\registers$Risco-5/src/core/registers.v:39$69_EN[31:0]$83 7/9: $1$memwr$\registers$Risco-5/src/core/registers.v:37$68_EN[31:0]$82 8/9: $1$memwr$\registers$Risco-5/src/core/registers.v:37$68_DATA[31:0]$81 9/9: $1$memwr$\registers$Risco-5/src/core/registers.v:37$68_ADDR[4:0]$80 Creating decoders for process `\PC.$proc$Risco-5/src/core/pc.v:0$65'. Creating decoders for process `\PC.$proc$Risco-5/src/core/pc.v:15$62'. 1/1: $0\Output[31:0] Creating decoders for process `\MUX.$proc$Risco-5/src/core/mux.v:14$61'. 1/1: $1\S[31:0] Creating decoders for process `\Immediate_Generator.$proc$Risco-5/src/core/immediate_generator.v:18$60'. 1/2: $2\immediate[31:0] 2/2: $1\immediate[31:0] Creating decoders for process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:0$716'. Creating decoders for process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$710'. 1/3: $0\counter[5:0] 2/3: $0\state[1:0] 3/3: $0\reset_o[0:0] Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:0$42'. Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:357$41'. 1/15: $0\save_address[0:0] 2/15: $0\csr_write_enable[0:0] 3/15: $0\is_immediate[0:0] 4/15: $0\reg_write[0:0] 5/15: $0\alu_src_a[2:0] 6/15: $0\alu_src_b[2:0] 7/15: $0\aluop[1:0] 8/15: $0\pc_source[0:0] 9/15: $0\memory_to_reg[2:0] 10/15: $0\memory_write[0:0] 11/15: $0\memory_read[0:0] 12/15: $0\lorD[1:0] 13/15: $0\ir_write[0:0] 14/15: $0\pc_write[0:0] 15/15: $0\pc_write_cond[0:0] Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:157$39'. 1/6: $6\nextstate[5:0] 2/6: $5\nextstate[5:0] 3/6: $4\nextstate[5:0] 4/6: $3\nextstate[5:0] 5/6: $2\nextstate[5:0] 6/6: $1\nextstate[5:0] Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:149$38'. 1/1: $0\state[5:0] Creating decoders for process `\ALU_Control.$proc$Risco-5/src/core/alu_control.v:9$31'. 1/1: $0\aluop_out[3:0] Creating decoders for process `\Alu.$proc$Risco-5/src/core/alu.v:26$11'. 1/1: $0\ALU_out_S[31:0] 24.4.8. Executing PROC_DLATCH pass (convert process syncs to latches). No latch inferred for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\n_fsm_state' from process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:111$1363'. No latch inferred for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.\n_fsm_state' from process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:95$1306'. No latch inferred for signal `$paramod$c31b266b644e4b515b582da1252fb11d77b9f11b\Memory.\read_data' from process `$paramod$c31b266b644e4b515b582da1252fb11d77b9f11b\Memory.$proc$Risco-5/src/peripheral/memory.v:59$1297'. No latch inferred for signal `\Registers.$memwr$\registers$Risco-5/src/core/registers.v:22$66_EN' from process `\Registers.$proc$Risco-5/src/core/registers.v:0$90'. No latch inferred for signal `\MUX.\S' from process `\MUX.$proc$Risco-5/src/core/mux.v:14$61'. No latch inferred for signal `\Immediate_Generator.\immediate' from process `\Immediate_Generator.$proc$Risco-5/src/core/immediate_generator.v:18$60'. No latch inferred for signal `\Control_Unit.\is_immediate' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:357$41'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\is_immediate` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:357$41`. No latch inferred for signal `\Control_Unit.\pc_write' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:357$41'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\pc_write` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:357$41`. No latch inferred for signal `\Control_Unit.\ir_write' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:357$41'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\ir_write` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:357$41`. No latch inferred for signal `\Control_Unit.\pc_source' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:357$41'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\pc_source` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:357$41`. No latch inferred for signal `\Control_Unit.\reg_write' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:357$41'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\reg_write` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:357$41`. No latch inferred for signal `\Control_Unit.\memory_read' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:357$41'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_read` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:357$41`. No latch inferred for signal `\Control_Unit.\memory_write' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:357$41'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_write` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:357$41`. No latch inferred for signal `\Control_Unit.\pc_write_cond' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:357$41'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\pc_write_cond` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:357$41`. No latch inferred for signal `\Control_Unit.\csr_write_enable' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:357$41'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\csr_write_enable` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:357$41`. No latch inferred for signal `\Control_Unit.\alu_input_selector' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:357$41'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_input_selector` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:357$41`. No latch inferred for signal `\Control_Unit.\save_address' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:357$41'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\save_address` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:357$41`. No latch inferred for signal `\Control_Unit.\save_value' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:357$41'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\save_value` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:357$41`. No latch inferred for signal `\Control_Unit.\save_value_2' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:357$41'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\save_value_2` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:357$41`. No latch inferred for signal `\Control_Unit.\save_write_value' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:357$41'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\save_write_value` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:357$41`. No latch inferred for signal `\Control_Unit.\control_memory_op' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:357$41'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\control_memory_op` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:357$41`. No latch inferred for signal `\Control_Unit.\write_data_in' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:357$41'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\write_data_in` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:357$41`. No latch inferred for signal `\Control_Unit.\mdu_start' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:357$41'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\mdu_start` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:357$41`. No latch inferred for signal `\Control_Unit.\lorD' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:357$41'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\lorD [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:357$41`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\lorD [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:357$41`. No latch inferred for signal `\Control_Unit.\aluop' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:357$41'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\aluop [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:357$41`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\aluop [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:357$41`. No latch inferred for signal `\Control_Unit.\alu_src_a' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:357$41'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_a [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:357$41`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_a [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:357$41`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_a [2]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:357$41`. No latch inferred for signal `\Control_Unit.\alu_src_b' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:357$41'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_b [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:357$41`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_b [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:357$41`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_b [2]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:357$41`. No latch inferred for signal `\Control_Unit.\memory_to_reg' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:357$41'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_to_reg [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:357$41`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_to_reg [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:357$41`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_to_reg [2]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:357$41`. No latch inferred for signal `\Control_Unit.\control_unit_memory_op' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:357$41'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\control_unit_memory_op [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:357$41`. Removing init bit 1'1 for non-memory siginal `\Control_Unit.\control_unit_memory_op [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:357$41`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\control_unit_memory_op [2]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:357$41`. No latch inferred for signal `\Control_Unit.\control_unit_aluop' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:357$41'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\control_unit_aluop [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:357$41`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\control_unit_aluop [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:357$41`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\control_unit_aluop [2]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:357$41`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\control_unit_aluop [3]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:357$41`. No latch inferred for signal `\Control_Unit.\nextstate' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:157$39'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:157$39`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:157$39`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [2]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:157$39`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [3]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:157$39`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [4]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:157$39`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [5]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:157$39`. No latch inferred for signal `\ALU_Control.\aluop_out' from process `\ALU_Control.$proc$Risco-5/src/core/alu_control.v:9$31'. No latch inferred for signal `\Alu.\ALU_out_S' from process `\Alu.$proc$Risco-5/src/core/alu.v:26$11'. 24.4.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `\TRELLIS_FF.\Q' using process `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$707'. created $dff cell `$procdff$2688' with positive edge clock. Creating register for signal `\DPR16X4C.\i' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$682'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$643_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$682'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$644_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$682'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$645_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$682'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$646_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$682'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$647_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$682'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$648_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$682'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$649_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$682'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$650_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$682'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$651_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$682'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$652_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$682'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$653_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$682'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$654_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$682'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$655_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$682'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$656_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$682'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$657_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$682'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$658_ADDR' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$659'. created $dff cell `$procdff$2689' with positive edge clock. Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$658_DATA' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$659'. created $dff cell `$procdff$2690' with positive edge clock. Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$658_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$659'. created $dff cell `$procdff$2691' with positive edge clock. Creating register for signal `\TRELLIS_DPR16X4.\i' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$625'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$583_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$625'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$584_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$625'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$585_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$625'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$586_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$625'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$587_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$625'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$588_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$625'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$589_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$625'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$590_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$625'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$591_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$625'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$592_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$625'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$593_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$625'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$594_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$625'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$595_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$625'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$596_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$625'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$597_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$625'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$598_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$625'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$599_ADDR' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$601'. created $dff cell `$procdff$2692' with positive edge clock. Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$599_DATA' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$601'. created $dff cell `$procdff$2693' with positive edge clock. Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$599_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$601'. created $dff cell `$procdff$2694' with positive edge clock. Creating register for signal `\TRELLIS_DPR16X4.\muxwre' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$600'. created direct connection (no actual register cell created). Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\rxd_reg' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:192$1392'. created $dff cell `$procdff$2695' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\rxd_reg_0' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:192$1392'. created $dff cell `$procdff$2696' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\fsm_state' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:181$1390'. created $dff cell `$procdff$2697' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\cycle_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:166$1382'. created $dff cell `$procdff$2698' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\bit_sample' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:155$1379'. created $dff cell `$procdff$2699' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\bit_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:143$1373'. created $dff cell `$procdff$2700' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\recieved_data' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:128$1368'. created $dff cell `$procdff$2701' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\i' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:128$1368'. created $dff cell `$procdff$2702' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\uart_rx_data' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:92$1354'. created $dff cell `$procdff$2703' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.\txd_reg' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:170$1341'. created $dff cell `$procdff$2704' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.\fsm_state' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:159$1339'. created $dff cell `$procdff$2705' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.\cycle_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:144$1331'. created $dff cell `$procdff$2706' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.\bit_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:127$1317'. created $dff cell `$procdff$2707' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.\i' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:112$1311'. created $dff cell `$procdff$2708' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.\data_to_send' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:112$1311'. created $dff cell `$procdff$2709' with positive edge clock. Creating register for signal `$paramod$c31b266b644e4b515b582da1252fb11d77b9f11b\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1255_EN' using process `$paramod$c31b266b644e4b515b582da1252fb11d77b9f11b\Memory.$proc$Risco-5/src/peripheral/memory.v:47$1260'. created $dff cell `$procdff$2710' with positive edge clock. Creating register for signal `$paramod$c31b266b644e4b515b582da1252fb11d77b9f11b\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1255_DATA' using process `$paramod$c31b266b644e4b515b582da1252fb11d77b9f11b\Memory.$proc$Risco-5/src/peripheral/memory.v:47$1260'. created $dff cell `$procdff$2711' with positive edge clock. Creating register for signal `$paramod$c31b266b644e4b515b582da1252fb11d77b9f11b\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1255_ADDR' using process `$paramod$c31b266b644e4b515b582da1252fb11d77b9f11b\Memory.$proc$Risco-5/src/peripheral/memory.v:47$1260'. created $dff cell `$procdff$2712' with positive edge clock. Creating register for signal `$paramod$c31b266b644e4b515b582da1252fb11d77b9f11b\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1254_EN' using process `$paramod$c31b266b644e4b515b582da1252fb11d77b9f11b\Memory.$proc$Risco-5/src/peripheral/memory.v:47$1260'. created $dff cell `$procdff$2713' with positive edge clock. Creating register for signal `$paramod$c31b266b644e4b515b582da1252fb11d77b9f11b\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1254_DATA' using process `$paramod$c31b266b644e4b515b582da1252fb11d77b9f11b\Memory.$proc$Risco-5/src/peripheral/memory.v:47$1260'. created $dff cell `$procdff$2714' with positive edge clock. Creating register for signal `$paramod$c31b266b644e4b515b582da1252fb11d77b9f11b\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1254_ADDR' using process `$paramod$c31b266b644e4b515b582da1252fb11d77b9f11b\Memory.$proc$Risco-5/src/peripheral/memory.v:47$1260'. created $dff cell `$procdff$2715' with positive edge clock. Creating register for signal `$paramod$c31b266b644e4b515b582da1252fb11d77b9f11b\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1256_EN' using process `$paramod$c31b266b644e4b515b582da1252fb11d77b9f11b\Memory.$proc$Risco-5/src/peripheral/memory.v:47$1260'. created $dff cell `$procdff$2716' with positive edge clock. Creating register for signal `$paramod$c31b266b644e4b515b582da1252fb11d77b9f11b\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1256_DATA' using process `$paramod$c31b266b644e4b515b582da1252fb11d77b9f11b\Memory.$proc$Risco-5/src/peripheral/memory.v:47$1260'. created $dff cell `$procdff$2717' with positive edge clock. Creating register for signal `$paramod$c31b266b644e4b515b582da1252fb11d77b9f11b\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1256_ADDR' using process `$paramod$c31b266b644e4b515b582da1252fb11d77b9f11b\Memory.$proc$Risco-5/src/peripheral/memory.v:47$1260'. created $dff cell `$procdff$2718' with positive edge clock. Creating register for signal `$paramod$c31b266b644e4b515b582da1252fb11d77b9f11b\Memory.\memory_response' using process `$paramod$c31b266b644e4b515b582da1252fb11d77b9f11b\Memory.$proc$Risco-5/src/peripheral/memory.v:39$1258'. created $dff cell `$procdff$2719' with positive edge clock. Creating register for signal `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.\uart_tx_en' using process `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.$proc$Risco-5/src/peripheral/uart.v:161$1243'. created $dff cell `$procdff$2720' with positive edge clock. Creating register for signal `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.\tx_fifo_read' using process `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.$proc$Risco-5/src/peripheral/uart.v:161$1243'. created $dff cell `$procdff$2721' with positive edge clock. Creating register for signal `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.\rx_fifo_write' using process `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.$proc$Risco-5/src/peripheral/uart.v:161$1243'. created $dff cell `$procdff$2722' with positive edge clock. Creating register for signal `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.\uart_tx_data' using process `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.$proc$Risco-5/src/peripheral/uart.v:161$1243'. created $dff cell `$procdff$2723' with positive edge clock. Creating register for signal `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.\rx_fifo_write_data' using process `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.$proc$Risco-5/src/peripheral/uart.v:161$1243'. created $dff cell `$procdff$2724' with positive edge clock. Creating register for signal `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.\state' using process `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.$proc$Risco-5/src/peripheral/uart.v:67$1235'. created $dff cell `$procdff$2725' with positive edge clock. Creating register for signal `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.\counter' using process `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.$proc$Risco-5/src/peripheral/uart.v:67$1235'. created $dff cell `$procdff$2726' with positive edge clock. Creating register for signal `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.\read_data' using process `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.$proc$Risco-5/src/peripheral/uart.v:67$1235'. created $dff cell `$procdff$2727' with positive edge clock. Creating register for signal `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.\response' using process `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.$proc$Risco-5/src/peripheral/uart.v:67$1235'. created $dff cell `$procdff$2728' with positive edge clock. Creating register for signal `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.\tx_fifo_write' using process `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.$proc$Risco-5/src/peripheral/uart.v:67$1235'. created $dff cell `$procdff$2729' with positive edge clock. Creating register for signal `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.\rx_fifo_read' using process `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.$proc$Risco-5/src/peripheral/uart.v:67$1235'. created $dff cell `$procdff$2730' with positive edge clock. Creating register for signal `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.\tx_fifo_write_data' using process `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.$proc$Risco-5/src/peripheral/uart.v:67$1235'. created $dff cell `$procdff$2731' with positive edge clock. Creating register for signal `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.\write_data_buffer' using process `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.$proc$Risco-5/src/peripheral/uart.v:67$1235'. created $dff cell `$procdff$2732' with positive edge clock. Creating register for signal `\PWM.\counter' using process `\PWM.$proc$Risco-5/src/peripheral/pwm.v:15$364'. created $dff cell `$procdff$2733' with positive edge clock. Creating register for signal `\PWM.\pwm_out' using process `\PWM.$proc$Risco-5/src/peripheral/pwm.v:15$364'. created $dff cell `$procdff$2734' with positive edge clock. Creating register for signal `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.\gpio_direction' using process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:63$1169'. created $dff cell `$procdff$2735' with positive edge clock. Creating register for signal `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.\gpio_value' using process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:63$1169'. created $dff cell `$procdff$2736' with positive edge clock. Creating register for signal `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.\is_pwm' using process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:63$1169'. created $dff cell `$procdff$2737' with positive edge clock. Creating register for signal `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$memwr$\period$Risco-5/src/peripheral/gpios.v:72$1163_ADDR' using process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:63$1169'. created $dff cell `$procdff$2738' with positive edge clock. Creating register for signal `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$memwr$\period$Risco-5/src/peripheral/gpios.v:72$1163_DATA' using process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:63$1169'. created $dff cell `$procdff$2739' with positive edge clock. Creating register for signal `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$memwr$\period$Risco-5/src/peripheral/gpios.v:72$1163_EN' using process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:63$1169'. created $dff cell `$procdff$2740' with positive edge clock. Creating register for signal `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:73$1164_ADDR' using process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:63$1169'. created $dff cell `$procdff$2741' with positive edge clock. Creating register for signal `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:73$1164_DATA' using process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:63$1169'. created $dff cell `$procdff$2742' with positive edge clock. Creating register for signal `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:73$1164_EN' using process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:63$1169'. created $dff cell `$procdff$2743' with positive edge clock. Creating register for signal `\LEDs.\data' using process `\LEDs.$proc$Risco-5/src/peripheral/leds.v:27$315'. created $dff cell `$procdff$2744' with positive edge clock. Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\instruction_register' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:305$866'. created $dff cell `$procdff$2745' with positive edge clock. Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\memory_register' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:305$866'. created $dff cell `$procdff$2746' with positive edge clock. Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\alu_out_register' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:305$866'. created $dff cell `$procdff$2747' with positive edge clock. Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\register_data_1' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:305$866'. created $dff cell `$procdff$2748' with positive edge clock. Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\register_data_2' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:305$866'. created $dff cell `$procdff$2749' with positive edge clock. Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\pc_old' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:305$866'. created $dff cell `$procdff$2750' with positive edge clock. Creating register for signal `$paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO.\counter' using process `$paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO.$proc$Risco-5/src/peripheral/fifo.v:31$1397'. created $dff cell `$procdff$2751' with positive edge clock. Creating register for signal `$paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO.\read_ptr' using process `$paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO.$proc$Risco-5/src/peripheral/fifo.v:31$1397'. created $dff cell `$procdff$2752' with positive edge clock. Creating register for signal `$paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO.\write_ptr' using process `$paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO.$proc$Risco-5/src/peripheral/fifo.v:31$1397'. created $dff cell `$procdff$2753' with positive edge clock. Creating register for signal `$paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO.$memwr$\memory$Risco-5/src/peripheral/fifo.v:39$1395_ADDR' using process `$paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO.$proc$Risco-5/src/peripheral/fifo.v:31$1397'. created $dff cell `$procdff$2754' with positive edge clock. Creating register for signal `$paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO.$memwr$\memory$Risco-5/src/peripheral/fifo.v:39$1395_DATA' using process `$paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO.$proc$Risco-5/src/peripheral/fifo.v:31$1397'. created $dff cell `$procdff$2755' with positive edge clock. Creating register for signal `$paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO.$memwr$\memory$Risco-5/src/peripheral/fifo.v:39$1395_EN' using process `$paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO.$proc$Risco-5/src/peripheral/fifo.v:31$1397'. created $dff cell `$procdff$2756' with positive edge clock. Creating register for signal `\Registers.$memwr$\registers$Risco-5/src/core/registers.v:35$67_EN' using process `\Registers.$proc$Risco-5/src/core/registers.v:33$72'. created $dff cell `$procdff$2757' with positive edge clock. Creating register for signal `\Registers.$memwr$\registers$Risco-5/src/core/registers.v:37$68_ADDR' using process `\Registers.$proc$Risco-5/src/core/registers.v:33$72'. created $dff cell `$procdff$2758' with positive edge clock. Creating register for signal `\Registers.$memwr$\registers$Risco-5/src/core/registers.v:37$68_DATA' using process `\Registers.$proc$Risco-5/src/core/registers.v:33$72'. created $dff cell `$procdff$2759' with positive edge clock. Creating register for signal `\Registers.$memwr$\registers$Risco-5/src/core/registers.v:37$68_EN' using process `\Registers.$proc$Risco-5/src/core/registers.v:33$72'. created $dff cell `$procdff$2760' with positive edge clock. Creating register for signal `\Registers.$memwr$\registers$Risco-5/src/core/registers.v:39$69_EN' using process `\Registers.$proc$Risco-5/src/core/registers.v:33$72'. created $dff cell `$procdff$2761' with positive edge clock. Creating register for signal `\PC.\Output' using process `\PC.$proc$Risco-5/src/core/pc.v:15$62'. created $dff cell `$procdff$2762' with positive edge clock. Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\reset_o' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$710'. created $dff cell `$procdff$2763' with positive edge clock. Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\state' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$710'. created $dff cell `$procdff$2764' with positive edge clock. Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\counter' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$710'. created $dff cell `$procdff$2765' with positive edge clock. Creating register for signal `\Control_Unit.\state' using process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:149$38'. created $dff cell `$procdff$2766' with positive edge clock. 24.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 24.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$708'. Found and cleaned up 2 empty switches in `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$707'. Removing empty process `TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$707'. Removing empty process `DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$682'. Found and cleaned up 1 empty switch in `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$659'. Removing empty process `TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$625'. Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$601'. Removing empty process `TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$600'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:127$1394'. Found and cleaned up 2 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:192$1392'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:192$1392'. Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:181$1390'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:181$1390'. Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:166$1382'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:166$1382'. Found and cleaned up 2 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:155$1379'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:155$1379'. Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:143$1373'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:143$1373'. Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:128$1368'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:128$1368'. Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:111$1363'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:111$1363'. Found and cleaned up 2 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:92$1354'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:92$1354'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:111$1347'. Found and cleaned up 5 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:170$1341'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:170$1341'. Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:159$1339'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:159$1339'. Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:144$1331'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:144$1331'. Found and cleaned up 5 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:127$1317'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:127$1317'. Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:112$1311'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:112$1311'. Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:95$1306'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:95$1306'. Removing empty process `$paramod$c31b266b644e4b515b582da1252fb11d77b9f11b\Memory.$proc$Risco-5/src/peripheral/memory.v:0$1299'. Found and cleaned up 1 empty switch in `$paramod$c31b266b644e4b515b582da1252fb11d77b9f11b\Memory.$proc$Risco-5/src/peripheral/memory.v:59$1297'. Removing empty process `$paramod$c31b266b644e4b515b582da1252fb11d77b9f11b\Memory.$proc$Risco-5/src/peripheral/memory.v:59$1297'. Found and cleaned up 3 empty switches in `$paramod$c31b266b644e4b515b582da1252fb11d77b9f11b\Memory.$proc$Risco-5/src/peripheral/memory.v:47$1260'. Removing empty process `$paramod$c31b266b644e4b515b582da1252fb11d77b9f11b\Memory.$proc$Risco-5/src/peripheral/memory.v:47$1260'. Found and cleaned up 1 empty switch in `$paramod$c31b266b644e4b515b582da1252fb11d77b9f11b\Memory.$proc$Risco-5/src/peripheral/memory.v:39$1258'. Removing empty process `$paramod$c31b266b644e4b515b582da1252fb11d77b9f11b\Memory.$proc$Risco-5/src/peripheral/memory.v:39$1258'. Removing empty process `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.$proc$Risco-5/src/peripheral/uart.v:0$1253'. Found and cleaned up 3 empty switches in `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.$proc$Risco-5/src/peripheral/uart.v:161$1243'. Removing empty process `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.$proc$Risco-5/src/peripheral/uart.v:161$1243'. Found and cleaned up 9 empty switches in `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.$proc$Risco-5/src/peripheral/uart.v:67$1235'. Removing empty process `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.$proc$Risco-5/src/peripheral/uart.v:67$1235'. Found and cleaned up 3 empty switches in `\PWM.$proc$Risco-5/src/peripheral/pwm.v:15$364'. Removing empty process `PWM.$proc$Risco-5/src/peripheral/pwm.v:15$364'. Removing empty process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:0$1234'. Found and cleaned up 3 empty switches in `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:63$1169'. Removing empty process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:63$1169'. Removing empty process `LEDs.$proc$Risco-5/src/peripheral/leds.v:0$318'. Found and cleaned up 2 empty switches in `\LEDs.$proc$Risco-5/src/peripheral/leds.v:27$315'. Removing empty process `LEDs.$proc$Risco-5/src/peripheral/leds.v:27$315'. Removing empty process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:0$869'. Found and cleaned up 2 empty switches in `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:305$866'. Removing empty process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:305$866'. Removing empty process `$paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO.$proc$Risco-5/src/peripheral/fifo.v:0$1424'. Found and cleaned up 3 empty switches in `$paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO.$proc$Risco-5/src/peripheral/fifo.v:31$1397'. Removing empty process `$paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO.$proc$Risco-5/src/peripheral/fifo.v:31$1397'. Removing empty process `Registers.$proc$Risco-5/src/core/registers.v:0$90'. Found and cleaned up 2 empty switches in `\Registers.$proc$Risco-5/src/core/registers.v:33$72'. Removing empty process `Registers.$proc$Risco-5/src/core/registers.v:33$72'. Removing empty process `PC.$proc$Risco-5/src/core/pc.v:0$65'. Found and cleaned up 2 empty switches in `\PC.$proc$Risco-5/src/core/pc.v:15$62'. Removing empty process `PC.$proc$Risco-5/src/core/pc.v:15$62'. Found and cleaned up 1 empty switch in `\MUX.$proc$Risco-5/src/core/mux.v:14$61'. Removing empty process `MUX.$proc$Risco-5/src/core/mux.v:14$61'. Found and cleaned up 2 empty switches in `\Immediate_Generator.$proc$Risco-5/src/core/immediate_generator.v:18$60'. Removing empty process `Immediate_Generator.$proc$Risco-5/src/core/immediate_generator.v:18$60'. Removing empty process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:0$716'. Found and cleaned up 5 empty switches in `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$710'. Removing empty process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$710'. Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:0$42'. Found and cleaned up 1 empty switch in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:357$41'. Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:357$41'. Found and cleaned up 6 empty switches in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:157$39'. Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:157$39'. Found and cleaned up 1 empty switch in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:149$38'. Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:149$38'. Found and cleaned up 5 empty switches in `\ALU_Control.$proc$Risco-5/src/core/alu_control.v:9$31'. Removing empty process `ALU_Control.$proc$Risco-5/src/core/alu_control.v:9$31'. Found and cleaned up 1 empty switch in `\Alu.$proc$Risco-5/src/core/alu.v:26$11'. Removing empty process `Alu.$proc$Risco-5/src/core/alu.v:26$11'. Cleaned up 95 empty switches. 24.4.12. Executing OPT_EXPR pass (perform const folding). Optimizing module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx. <suppressed ~21 debug messages> Optimizing module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx. <suppressed ~19 debug messages> Optimizing module $paramod$c31b266b644e4b515b582da1252fb11d77b9f11b\Memory. <suppressed ~4 debug messages> Optimizing module $paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART. <suppressed ~17 debug messages> Optimizing module PWM. Optimizing module $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110. <suppressed ~2 debug messages> Optimizing module LEDs. <suppressed ~2 debug messages> Optimizing module $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000. <suppressed ~4 debug messages> Optimizing module GPIO. <suppressed ~1 debug messages> Optimizing module $paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO. <suppressed ~4 debug messages> Optimizing module BUS. <suppressed ~4 debug messages> Optimizing module Registers. <suppressed ~2 debug messages> Optimizing module PC. <suppressed ~2 debug messages> Optimizing module MUX. <suppressed ~1 debug messages> Optimizing module Immediate_Generator. Optimizing module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100. <suppressed ~7 debug messages> Optimizing module Control_Unit. <suppressed ~4 debug messages> Optimizing module ALU_Control. <suppressed ~4 debug messages> Optimizing module Alu. <suppressed ~1 debug messages> Optimizing module $paramod$e582745b5be06b945636a80f333e3e68b035ee01\Risco_5_SOC. Optimizing module top. 24.5. Executing FLATTEN pass (flatten design). Deleting now unused module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx. Deleting now unused module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx. Deleting now unused module $paramod$c31b266b644e4b515b582da1252fb11d77b9f11b\Memory. Deleting now unused module $paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART. Deleting now unused module PWM. Deleting now unused module $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110. Deleting now unused module LEDs. Deleting now unused module $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000. Deleting now unused module GPIO. Deleting now unused module $paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO. Deleting now unused module BUS. Deleting now unused module Registers. Deleting now unused module PC. Deleting now unused module MUX. Deleting now unused module Immediate_Generator. Deleting now unused module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100. Deleting now unused module Control_Unit. Deleting now unused module ALU_Control. Deleting now unused module Alu. Deleting now unused module $paramod$e582745b5be06b945636a80f333e3e68b035ee01\Risco_5_SOC. <suppressed ~31 debug messages> 24.6. Executing TRIBUF pass. 24.7. Executing DEMINOUT pass (demote inout ports to input or output). 24.8. Executing OPT_EXPR pass (perform const folding). [Pipeline] sh Optimizing module top. <suppressed ~48 debug messages> 24.9. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 78 unused cells and 791 unused wires. <suppressed ~101 debug messages> 24.10. Executing CHECK pass (checking for obvious problems). Checking module top... Warning: Wire top.\SOC.Core.MemoryDataMUX.C [31] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.C [30] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.C [29] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.C [28] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.C [27] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.C [26] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.C [25] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.C [24] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.C [23] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.C [22] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.C [21] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.C [20] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.C [19] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.C [18] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.C [17] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.C [16] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.C [15] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.C [14] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.C [13] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.C [12] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.C [11] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.C [10] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.C [9] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.C [8] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.C [7] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.C [6] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.C [5] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.C [4] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.C [3] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.C [2] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.C [1] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.C [0] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [31] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [30] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [29] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [28] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [27] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [26] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [25] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [24] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [23] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [22] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [21] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [20] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [19] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [18] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [17] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [16] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [15] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [14] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [13] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [12] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [11] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [10] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [9] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [8] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [7] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [6] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [5] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [4] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [3] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [2] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [1] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [0] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [31] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [30] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [29] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [28] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [27] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [26] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [25] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [24] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [23] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [22] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [21] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [20] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [19] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [18] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [17] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [16] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [15] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [14] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [13] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [12] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [11] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [10] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [9] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [8] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [7] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [6] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [5] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [4] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [3] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [2] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [1] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [0] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.E [31] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.E [30] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.E [29] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.E [28] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.E [27] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.E [26] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.E [25] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.E [24] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.E [23] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.E [22] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.E [21] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.E [20] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.E [19] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.E [18] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.E [17] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.E [16] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.E [15] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.E [14] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.E [13] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.E [12] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.E [11] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.E [10] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.E [9] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.E [8] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.E [7] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.E [6] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.E [5] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.E [4] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.E [3] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.E [2] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.E [1] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.E [0] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.F [31] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.F [30] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.F [29] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.F [28] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.F [27] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.F [26] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.F [25] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.F [24] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.F [23] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.F [22] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.F [21] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.F [20] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.F [19] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.F [18] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.F [17] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.F [16] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.F [15] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.F [14] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.F [13] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.F [12] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.F [11] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.F [10] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.F [9] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.F [8] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.F [7] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.F [6] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.F [5] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.F [4] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.F [3] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.F [2] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.F [1] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.F [0] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.G [31] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.G [30] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.G [29] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.G [28] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.G [27] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.G [26] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.G [25] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.G [24] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.G [23] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.G [22] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.G [21] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.G [20] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.G [19] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.G [18] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.G [17] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.G [16] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.G [15] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.G [14] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.G [13] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.G [12] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.G [11] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.G [10] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.G [9] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.G [8] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.G [7] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.G [6] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.G [5] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.G [4] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.G [3] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.G [2] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.G [1] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.G [0] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.H [31] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.H [30] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.H [29] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.H [28] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.H [27] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.H [26] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.H [25] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.H [24] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.H [23] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.H [22] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.H [21] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.H [20] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.H [19] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.H [18] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.H [17] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.H [16] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.H [15] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.H [14] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.H [13] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.H [12] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.H [11] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.H [10] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.H [9] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.H [8] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.H [7] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.H [6] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.H [5] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.H [4] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.H [3] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.H [2] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.H [1] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.H [0] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.D [31] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.D [30] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.D [29] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.D [28] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.D [27] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.D [26] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.D [25] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.D [24] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.D [23] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.D [22] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.D [21] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.D [20] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.D [19] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.D [18] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.D [17] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.D [16] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.D [15] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.D [14] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.D [13] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.D [12] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.D [11] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.D [10] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.D [9] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.D [8] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.D [7] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.D [6] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.D [5] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.D [4] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.D [3] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.D [2] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.D [1] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.D [0] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.E [31] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.E [30] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.E [29] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.E [28] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.E [27] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.E [26] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.E [25] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.E [24] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.E [23] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.E [22] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.E [21] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.E [20] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.E [19] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.E [18] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.E [17] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.E [16] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.E [15] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.E [14] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.E [13] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.E [12] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.E [11] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.E [10] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.E [9] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.E [8] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.E [7] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.E [6] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.E [5] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.E [4] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.E [3] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.E [2] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.E [1] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.E [0] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.F [31] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.F [30] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.F [29] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.F [28] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.F [27] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.F [26] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.F [25] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.F [24] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.F [23] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.F [22] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.F [21] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.F [20] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.F [19] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.F [18] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.F [17] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.F [16] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.F [15] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.F [14] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.F [13] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.F [12] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.F [11] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.F [10] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.F [9] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.F [8] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.F [7] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.F [6] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.F [5] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.F [4] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.F [3] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.F [2] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.F [1] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.F [0] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.G [31] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.G [30] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.G [29] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.G [28] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.G [27] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.G [26] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.G [25] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.G [24] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.G [23] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.G [22] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.G [21] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.G [20] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.G [19] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.G [18] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.G [17] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.G [16] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.G [15] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.G [14] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.G [13] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.G [12] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.G [11] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.G [10] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.G [9] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.G [8] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.G [7] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.G [6] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.G [5] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.G [4] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.G [3] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.G [2] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.G [1] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.G [0] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.H [31] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.H [30] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.H [29] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.H [28] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.H [27] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.H [26] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.H [25] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.H [24] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.H [23] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.H [22] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.H [21] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.H [20] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.H [19] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.H [18] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.H [17] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.H [16] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.H [15] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.H [14] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.H [13] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.H [12] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.H [11] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.H [10] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.H [9] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.H [8] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.H [7] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.H [6] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.H [5] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.H [4] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.H [3] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.H [2] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.H [1] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.H [0] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputAMUX.G [31] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputAMUX.G [30] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputAMUX.G [29] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputAMUX.G [28] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputAMUX.G [27] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputAMUX.G [26] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputAMUX.G [25] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputAMUX.G [24] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputAMUX.G [23] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputAMUX.G [22] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputAMUX.G [21] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputAMUX.G [20] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputAMUX.G [19] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputAMUX.G [18] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputAMUX.G [17] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputAMUX.G [16] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputAMUX.G [15] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputAMUX.G [14] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputAMUX.G [13] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputAMUX.G [12] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputAMUX.G [11] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputAMUX.G [10] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputAMUX.G [9] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputAMUX.G [8] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputAMUX.G [7] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputAMUX.G [6] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputAMUX.G [5] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputAMUX.G [4] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputAMUX.G [3] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputAMUX.G [2] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputAMUX.G [1] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputAMUX.G [0] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputAMUX.H [31] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputAMUX.H [30] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputAMUX.H [29] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputAMUX.H [28] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputAMUX.H [27] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputAMUX.H [26] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputAMUX.H [25] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputAMUX.H [24] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputAMUX.H [23] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputAMUX.H [22] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputAMUX.H [21] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputAMUX.H [20] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputAMUX.H [19] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputAMUX.H [18] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputAMUX.H [17] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputAMUX.H [16] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputAMUX.H [15] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputAMUX.H [14] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputAMUX.H [13] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputAMUX.H [12] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputAMUX.H [11] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputAMUX.H [10] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputAMUX.H [9] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputAMUX.H [8] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputAMUX.H [7] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputAMUX.H [6] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputAMUX.H [5] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputAMUX.H [4] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputAMUX.H [3] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputAMUX.H [2] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputAMUX.H [1] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputAMUX.H [0] is used but has no driver. Found and reported 448 problems. 24.11. Executing OPT pass (performing simple optimizations). 24.11.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~11 debug messages> 24.11.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~423 debug messages> Removed a total of 141 cells. 24.11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2538. dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2556. dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2575. dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2604. dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2626. dead port 2/2 on $mux $flatten\SOC.\Core.\Immediate_Generator.$procmux$2330. dead port 1/9 on $pmux $flatten\SOC.\Core.\MemoryAddressMUX.$procmux$2312. dead port 2/9 on $pmux $flatten\SOC.\Core.\MemoryAddressMUX.$procmux$2312. dead port 3/9 on $pmux $flatten\SOC.\Core.\MemoryAddressMUX.$procmux$2312. dead port 4/9 on $pmux $flatten\SOC.\Core.\MemoryAddressMUX.$procmux$2312. dead port 1/9 on $pmux $flatten\SOC.\Core.\PCSourceMUX.$procmux$2312. dead port 2/9 on $pmux $flatten\SOC.\Core.\PCSourceMUX.$procmux$2312. dead port 3/9 on $pmux $flatten\SOC.\Core.\PCSourceMUX.$procmux$2312. dead port 4/9 on $pmux $flatten\SOC.\Core.\PCSourceMUX.$procmux$2312. dead port 5/9 on $pmux $flatten\SOC.\Core.\PCSourceMUX.$procmux$2312. dead port 6/9 on $pmux $flatten\SOC.\Core.\PCSourceMUX.$procmux$2312. dead port 1/2 on $mux $flatten\SOC.\Core.\RegisterBank.$procmux$2272. dead port 1/2 on $mux $flatten\SOC.\Core.\RegisterBank.$procmux$2278. dead port 1/2 on $mux $flatten\SOC.\Core.\RegisterBank.$procmux$2284. dead port 1/2 on $mux $flatten\SOC.\Core.\RegisterBank.$procmux$2290. dead port 2/2 on $mux $flatten\SOC.\GPIOS.$procmux$2049. dead port 1/2 on $mux $flatten\SOC.\GPIOS.$procmux$2052. dead port 2/2 on $mux $flatten\SOC.\GPIOS.$procmux$2058. dead port 1/2 on $mux $flatten\SOC.\GPIOS.$procmux$2061. dead port 2/2 on $mux $flatten\SOC.\GPIOS.$procmux$2067. dead port 1/2 on $mux $flatten\SOC.\GPIOS.$procmux$2070. dead port 2/2 on $mux $flatten\SOC.\GPIOS.$procmux$2077. dead port 1/2 on $mux $flatten\SOC.\GPIOS.$procmux$2080. dead port 2/2 on $mux $flatten\SOC.\GPIOS.$procmux$2087. dead port 1/2 on $mux $flatten\SOC.\GPIOS.$procmux$2090. dead port 2/2 on $mux $flatten\SOC.\GPIOS.$procmux$2097. dead port 1/2 on $mux $flatten\SOC.\GPIOS.$procmux$2100. dead port 1/2 on $mux $flatten\SOC.\GPIOS.$procmux$2106. dead port 1/2 on $mux $flatten\SOC.\GPIOS.$procmux$2112. dead port 1/2 on $mux $flatten\SOC.\GPIOS.$procmux$2118. dead port 1/2 on $mux $flatten\SOC.\GPIOS.$procmux$2124. dead port 1/2 on $mux $flatten\SOC.\GPIOS.$procmux$2130. dead port 1/2 on $mux $flatten\SOC.\GPIOS.$procmux$2136. dead port 1/2 on $mux $flatten\SOC.\Memory.$procmux$1727. dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1729. dead port 1/2 on $mux $flatten\SOC.\Memory.$procmux$1736. dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1738. dead port 1/2 on $mux $flatten\SOC.\Memory.$procmux$1745. dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1747. dead port 1/2 on $mux $flatten\SOC.\Memory.$procmux$1754. dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1756. dead port 1/2 on $mux $flatten\SOC.\Memory.$procmux$1763. dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1765. dead port 1/2 on $mux $flatten\SOC.\Memory.$procmux$1772. dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1774. dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1780. dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1786. dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1792. dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1798. dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1804. dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1810. dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1816. dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1822. dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1828. dead port 1/2 on $mux $flatten\SOC.\Uart.\RX_FIFO.$procmux$2223. dead port 1/2 on $mux $flatten\SOC.\Uart.\RX_FIFO.$procmux$2229. dead port 1/2 on $mux $flatten\SOC.\Uart.\RX_FIFO.$procmux$2235. dead port 1/2 on $mux $flatten\SOC.\Uart.\TX_FIFO.$procmux$2223. dead port 1/2 on $mux $flatten\SOC.\Uart.\TX_FIFO.$procmux$2229. dead port 1/2 on $mux $flatten\SOC.\Uart.\TX_FIFO.$procmux$2235. Removed 65 multiplexer ports. <suppressed ~127 debug messages> 24.11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2593: { $auto$opt_reduce.cc:134:opt_pmux$2820 $flatten\SOC.\Core.\Control_Unit.$procmux$2601_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2600_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2599_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2598_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2597_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2596_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2595_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2594_CMP } New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2401: $auto$opt_reduce.cc:134:opt_pmux$2822 New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2630: { $flatten\SOC.\Core.\Control_Unit.$procmux$2478_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2430_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2419_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2418_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2476_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2462_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2413_CMP $auto$opt_reduce.cc:134:opt_pmux$2824 } New ctrl vector for $pmux cell $flatten\SOC.\Core.\Immediate_Generator.$procmux$2333: { $flatten\SOC.\Core.\Control_Unit.$procmux$2598_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2599_CMP $auto$opt_reduce.cc:134:opt_pmux$2828 $flatten\SOC.\Core.\Control_Unit.$procmux$2600_CMP $auto$opt_reduce.cc:134:opt_pmux$2826 $flatten\SOC.\Core.\Control_Unit.$procmux$2594_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2602_CMP } Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\RegisterBank.$procmux$2269: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\SOC.\Core.\RegisterBank.$procmux$2269_Y New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Core.\RegisterBank.$procmux$2269_Y [0] New connections: $flatten\SOC.\Core.\RegisterBank.$procmux$2269_Y [31:1] = { $flatten\SOC.\Core.\RegisterBank.$procmux$2269_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2269_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2269_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2269_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2269_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2269_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2269_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2269_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2269_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2269_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2269_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2269_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2269_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2269_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2269_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2269_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2269_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2269_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2269_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2269_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2269_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2269_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2269_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2269_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2269_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2269_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2269_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2269_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2269_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2269_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2269_Y [0] } New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2404: $auto$opt_reduce.cc:134:opt_pmux$2830 Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\RegisterBank.$procmux$2287: Old ports: A=32'11111111111111111111111111111111, B=0, Y=$flatten\SOC.\Core.\RegisterBank.$procmux$2287_Y New ports: A=1'1, B=1'0, Y=$flatten\SOC.\Core.\RegisterBank.$procmux$2287_Y [0] New connections: $flatten\SOC.\Core.\RegisterBank.$procmux$2287_Y [31:1] = { $flatten\SOC.\Core.\RegisterBank.$procmux$2287_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2287_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2287_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2287_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2287_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2287_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2287_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2287_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2287_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2287_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2287_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2287_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2287_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2287_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2287_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2287_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2287_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2287_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2287_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2287_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2287_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2287_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2287_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2287_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2287_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2287_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2287_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2287_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2287_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2287_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2287_Y [0] } Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\RegisterBank.$procmux$2293: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:35$67_EN[31:0]$73 New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:35$67_EN[31:0]$73 [0] New connections: $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:35$67_EN[31:0]$73 [31:1] = { $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:35$67_EN[31:0]$73 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:35$67_EN[31:0]$73 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:35$67_EN[31:0]$73 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:35$67_EN[31:0]$73 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:35$67_EN[31:0]$73 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:35$67_EN[31:0]$73 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:35$67_EN[31:0]$73 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:35$67_EN[31:0]$73 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:35$67_EN[31:0]$73 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:35$67_EN[31:0]$73 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:35$67_EN[31:0]$73 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:35$67_EN[31:0]$73 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:35$67_EN[31:0]$73 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:35$67_EN[31:0]$73 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:35$67_EN[31:0]$73 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:35$67_EN[31:0]$73 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:35$67_EN[31:0]$73 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:35$67_EN[31:0]$73 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:35$67_EN[31:0]$73 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:35$67_EN[31:0]$73 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:35$67_EN[31:0]$73 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:35$67_EN[31:0]$73 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:35$67_EN[31:0]$73 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:35$67_EN[31:0]$73 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:35$67_EN[31:0]$73 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:35$67_EN[31:0]$73 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:35$67_EN[31:0]$73 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:35$67_EN[31:0]$73 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:35$67_EN[31:0]$73 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:35$67_EN[31:0]$73 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:35$67_EN[31:0]$73 [0] } Consolidated identical input bits for $mux cell $flatten\SOC.\GPIOS.$procmux$2047: Old ports: A=16'0000000000000000, B=16'1111111111111111, Y=$flatten\SOC.\GPIOS.$procmux$2047_Y New ports: A=1'0, B=1'1, Y=$flatten\SOC.\GPIOS.$procmux$2047_Y [0] New connections: $flatten\SOC.\GPIOS.$procmux$2047_Y [15:1] = { $flatten\SOC.\GPIOS.$procmux$2047_Y [0] $flatten\SOC.\GPIOS.$procmux$2047_Y [0] $flatten\SOC.\GPIOS.$procmux$2047_Y [0] $flatten\SOC.\GPIOS.$procmux$2047_Y [0] $flatten\SOC.\GPIOS.$procmux$2047_Y [0] $flatten\SOC.\GPIOS.$procmux$2047_Y [0] $flatten\SOC.\GPIOS.$procmux$2047_Y [0] $flatten\SOC.\GPIOS.$procmux$2047_Y [0] $flatten\SOC.\GPIOS.$procmux$2047_Y [0] $flatten\SOC.\GPIOS.$procmux$2047_Y [0] $flatten\SOC.\GPIOS.$procmux$2047_Y [0] $flatten\SOC.\GPIOS.$procmux$2047_Y [0] $flatten\SOC.\GPIOS.$procmux$2047_Y [0] $flatten\SOC.\GPIOS.$procmux$2047_Y [0] $flatten\SOC.\GPIOS.$procmux$2047_Y [0] } New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2409: { $auto$opt_reduce.cc:134:opt_pmux$2834 $auto$opt_reduce.cc:134:opt_pmux$2832 $flatten\SOC.\Core.\Control_Unit.$procmux$2410_CMP } Consolidated identical input bits for $mux cell $flatten\SOC.\GPIOS.$procmux$2075: Old ports: A=16'0000000000000000, B=16'1111111111111111, Y=$flatten\SOC.\GPIOS.$procmux$2075_Y New ports: A=1'0, B=1'1, Y=$flatten\SOC.\GPIOS.$procmux$2075_Y [0] New connections: $flatten\SOC.\GPIOS.$procmux$2075_Y [15:1] = { $flatten\SOC.\GPIOS.$procmux$2075_Y [0] $flatten\SOC.\GPIOS.$procmux$2075_Y [0] $flatten\SOC.\GPIOS.$procmux$2075_Y [0] $flatten\SOC.\GPIOS.$procmux$2075_Y [0] $flatten\SOC.\GPIOS.$procmux$2075_Y [0] $flatten\SOC.\GPIOS.$procmux$2075_Y [0] $flatten\SOC.\GPIOS.$procmux$2075_Y [0] $flatten\SOC.\GPIOS.$procmux$2075_Y [0] $flatten\SOC.\GPIOS.$procmux$2075_Y [0] $flatten\SOC.\GPIOS.$procmux$2075_Y [0] $flatten\SOC.\GPIOS.$procmux$2075_Y [0] $flatten\SOC.\GPIOS.$procmux$2075_Y [0] $flatten\SOC.\GPIOS.$procmux$2075_Y [0] $flatten\SOC.\GPIOS.$procmux$2075_Y [0] $flatten\SOC.\GPIOS.$procmux$2075_Y [0] } New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2421: { $auto$opt_reduce.cc:134:opt_pmux$2838 $auto$opt_reduce.cc:134:opt_pmux$2836 } Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1724: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\SOC.\Memory.$procmux$1724_Y New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Memory.$procmux$1724_Y [0] New connections: $flatten\SOC.\Memory.$procmux$1724_Y [31:1] = { $flatten\SOC.\Memory.$procmux$1724_Y [0] $flatten\SOC.\Memory.$procmux$1724_Y [0] $flatten\SOC.\Memory.$procmux$1724_Y [0] $flatten\SOC.\Memory.$procmux$1724_Y [0] $flatten\SOC.\Memory.$procmux$1724_Y [0] $flatten\SOC.\Memory.$procmux$1724_Y [0] $flatten\SOC.\Memory.$procmux$1724_Y [0] $flatten\SOC.\Memory.$procmux$1724_Y [0] $flatten\SOC.\Memory.$procmux$1724_Y [0] $flatten\SOC.\Memory.$procmux$1724_Y [0] $flatten\SOC.\Memory.$procmux$1724_Y [0] $flatten\SOC.\Memory.$procmux$1724_Y [0] $flatten\SOC.\Memory.$procmux$1724_Y [0] $flatten\SOC.\Memory.$procmux$1724_Y [0] $flatten\SOC.\Memory.$procmux$1724_Y [0] $flatten\SOC.\Memory.$procmux$1724_Y [0] $flatten\SOC.\Memory.$procmux$1724_Y [0] $flatten\SOC.\Memory.$procmux$1724_Y [0] $flatten\SOC.\Memory.$procmux$1724_Y [0] $flatten\SOC.\Memory.$procmux$1724_Y [0] $flatten\SOC.\Memory.$procmux$1724_Y [0] $flatten\SOC.\Memory.$procmux$1724_Y [0] $flatten\SOC.\Memory.$procmux$1724_Y [0] $flatten\SOC.\Memory.$procmux$1724_Y [0] $flatten\SOC.\Memory.$procmux$1724_Y [0] $flatten\SOC.\Memory.$procmux$1724_Y [0] $flatten\SOC.\Memory.$procmux$1724_Y [0] $flatten\SOC.\Memory.$procmux$1724_Y [0] $flatten\SOC.\Memory.$procmux$1724_Y [0] $flatten\SOC.\Memory.$procmux$1724_Y [0] $flatten\SOC.\Memory.$procmux$1724_Y [0] } New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2436: { $auto$opt_reduce.cc:134:opt_pmux$2840 $flatten\SOC.\Core.\Control_Unit.$procmux$2414_CMP } New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2443: $auto$opt_reduce.cc:134:opt_pmux$2842 Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1769: Old ports: A=32'11111111111111111111111111111111, B=0, Y=$flatten\SOC.\Memory.$procmux$1769_Y New ports: A=1'1, B=1'0, Y=$flatten\SOC.\Memory.$procmux$1769_Y [0] New connections: $flatten\SOC.\Memory.$procmux$1769_Y [31:1] = { $flatten\SOC.\Memory.$procmux$1769_Y [0] $flatten\SOC.\Memory.$procmux$1769_Y [0] $flatten\SOC.\Memory.$procmux$1769_Y [0] $flatten\SOC.\Memory.$procmux$1769_Y [0] $flatten\SOC.\Memory.$procmux$1769_Y [0] $flatten\SOC.\Memory.$procmux$1769_Y [0] $flatten\SOC.\Memory.$procmux$1769_Y [0] $flatten\SOC.\Memory.$procmux$1769_Y [0] $flatten\SOC.\Memory.$procmux$1769_Y [0] $flatten\SOC.\Memory.$procmux$1769_Y [0] $flatten\SOC.\Memory.$procmux$1769_Y [0] $flatten\SOC.\Memory.$procmux$1769_Y [0] $flatten\SOC.\Memory.$procmux$1769_Y [0] $flatten\SOC.\Memory.$procmux$1769_Y [0] $flatten\SOC.\Memory.$procmux$1769_Y [0] $flatten\SOC.\Memory.$procmux$1769_Y [0] $flatten\SOC.\Memory.$procmux$1769_Y [0] $flatten\SOC.\Memory.$procmux$1769_Y [0] $flatten\SOC.\Memory.$procmux$1769_Y [0] $flatten\SOC.\Memory.$procmux$1769_Y [0] $flatten\SOC.\Memory.$procmux$1769_Y [0] $flatten\SOC.\Memory.$procmux$1769_Y [0] $flatten\SOC.\Memory.$procmux$1769_Y [0] $flatten\SOC.\Memory.$procmux$1769_Y [0] $flatten\SOC.\Memory.$procmux$1769_Y [0] $flatten\SOC.\Memory.$procmux$1769_Y [0] $flatten\SOC.\Memory.$procmux$1769_Y [0] $flatten\SOC.\Memory.$procmux$1769_Y [0] $flatten\SOC.\Memory.$procmux$1769_Y [0] $flatten\SOC.\Memory.$procmux$1769_Y [0] $flatten\SOC.\Memory.$procmux$1769_Y [0] } Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1778: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\SOC.\Memory.$procmux$1778_Y New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Memory.$procmux$1778_Y [0] New connections: $flatten\SOC.\Memory.$procmux$1778_Y [31:1] = { $flatten\SOC.\Memory.$procmux$1778_Y [0] $flatten\SOC.\Memory.$procmux$1778_Y [0] $flatten\SOC.\Memory.$procmux$1778_Y [0] $flatten\SOC.\Memory.$procmux$1778_Y [0] $flatten\SOC.\Memory.$procmux$1778_Y [0] $flatten\SOC.\Memory.$procmux$1778_Y [0] $flatten\SOC.\Memory.$procmux$1778_Y [0] $flatten\SOC.\Memory.$procmux$1778_Y [0] $flatten\SOC.\Memory.$procmux$1778_Y [0] $flatten\SOC.\Memory.$procmux$1778_Y [0] $flatten\SOC.\Memory.$procmux$1778_Y [0] $flatten\SOC.\Memory.$procmux$1778_Y [0] $flatten\SOC.\Memory.$procmux$1778_Y [0] $flatten\SOC.\Memory.$procmux$1778_Y [0] $flatten\SOC.\Memory.$procmux$1778_Y [0] $flatten\SOC.\Memory.$procmux$1778_Y [0] $flatten\SOC.\Memory.$procmux$1778_Y [0] $flatten\SOC.\Memory.$procmux$1778_Y [0] $flatten\SOC.\Memory.$procmux$1778_Y [0] $flatten\SOC.\Memory.$procmux$1778_Y [0] $flatten\SOC.\Memory.$procmux$1778_Y [0] $flatten\SOC.\Memory.$procmux$1778_Y [0] $flatten\SOC.\Memory.$procmux$1778_Y [0] $flatten\SOC.\Memory.$procmux$1778_Y [0] $flatten\SOC.\Memory.$procmux$1778_Y [0] $flatten\SOC.\Memory.$procmux$1778_Y [0] $flatten\SOC.\Memory.$procmux$1778_Y [0] $flatten\SOC.\Memory.$procmux$1778_Y [0] $flatten\SOC.\Memory.$procmux$1778_Y [0] $flatten\SOC.\Memory.$procmux$1778_Y [0] $flatten\SOC.\Memory.$procmux$1778_Y [0] } New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2475: $auto$opt_reduce.cc:134:opt_pmux$2844 New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2490: $auto$opt_reduce.cc:134:opt_pmux$2846 New ctrl vector for $pmux cell $flatten\SOC.\Uart.$procmux$2005: { $flatten\SOC.\Uart.$procmux$1999_CMP $flatten\SOC.\Uart.$procmux$1916_CMP $flatten\SOC.\Uart.$procmux$1941_CMP $flatten\SOC.\Uart.$procmux$1897_CMP $auto$opt_reduce.cc:134:opt_pmux$2848 $flatten\SOC.\Uart.$procmux$1923_CMP } Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\RX_FIFO.$procmux$2220: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\SOC.\Uart.\RX_FIFO.$procmux$2220_Y New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Uart.\RX_FIFO.$procmux$2220_Y [0] New connections: $flatten\SOC.\Uart.\RX_FIFO.$procmux$2220_Y [7:1] = { $flatten\SOC.\Uart.\RX_FIFO.$procmux$2220_Y [0] $flatten\SOC.\Uart.\RX_FIFO.$procmux$2220_Y [0] $flatten\SOC.\Uart.\RX_FIFO.$procmux$2220_Y [0] $flatten\SOC.\Uart.\RX_FIFO.$procmux$2220_Y [0] $flatten\SOC.\Uart.\RX_FIFO.$procmux$2220_Y [0] $flatten\SOC.\Uart.\RX_FIFO.$procmux$2220_Y [0] $flatten\SOC.\Uart.\RX_FIFO.$procmux$2220_Y [0] } Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\TX_FIFO.$procmux$2220: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\SOC.\Uart.\TX_FIFO.$procmux$2220_Y New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Uart.\TX_FIFO.$procmux$2220_Y [0] New connections: $flatten\SOC.\Uart.\TX_FIFO.$procmux$2220_Y [7:1] = { $flatten\SOC.\Uart.\TX_FIFO.$procmux$2220_Y [0] $flatten\SOC.\Uart.\TX_FIFO.$procmux$2220_Y [0] $flatten\SOC.\Uart.\TX_FIFO.$procmux$2220_Y [0] $flatten\SOC.\Uart.\TX_FIFO.$procmux$2220_Y [0] $flatten\SOC.\Uart.\TX_FIFO.$procmux$2220_Y [0] $flatten\SOC.\Uart.\TX_FIFO.$procmux$2220_Y [0] $flatten\SOC.\Uart.\TX_FIFO.$procmux$2220_Y [0] } New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2513: $auto$opt_reduce.cc:134:opt_pmux$2850 Optimizing cells in module \top. Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\RegisterBank.$procmux$2296: Old ports: A=$flatten\SOC.\Core.\RegisterBank.$2$memwr$\registers$Risco-5/src/core/registers.v:39$69_EN[31:0]$88, B=0, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:39$69_EN[31:0]$77 New ports: A=$flatten\SOC.\Core.\RegisterBank.$procmux$2287_Y [0], B=1'0, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:39$69_EN[31:0]$77 [0] New connections: $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:39$69_EN[31:0]$77 [31:1] = { $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:39$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:39$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:39$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:39$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:39$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:39$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:39$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:39$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:39$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:39$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:39$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:39$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:39$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:39$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:39$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:39$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:39$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:39$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:39$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:39$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:39$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:39$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:39$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:39$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:39$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:39$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:39$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:39$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:39$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:39$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:39$69_EN[31:0]$77 [0] } Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\RegisterBank.$procmux$2299: Old ports: A=$flatten\SOC.\Core.\RegisterBank.$2$memwr$\registers$Risco-5/src/core/registers.v:37$68_EN[31:0]$87, B=0, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:37$68_EN[31:0]$76 New ports: A=$flatten\SOC.\Core.\RegisterBank.$procmux$2269_Y [0], B=1'0, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:37$68_EN[31:0]$76 [0] New connections: $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:37$68_EN[31:0]$76 [31:1] = { $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:37$68_EN[31:0]$76 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:37$68_EN[31:0]$76 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:37$68_EN[31:0]$76 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:37$68_EN[31:0]$76 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:37$68_EN[31:0]$76 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:37$68_EN[31:0]$76 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:37$68_EN[31:0]$76 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:37$68_EN[31:0]$76 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:37$68_EN[31:0]$76 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:37$68_EN[31:0]$76 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:37$68_EN[31:0]$76 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:37$68_EN[31:0]$76 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:37$68_EN[31:0]$76 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:37$68_EN[31:0]$76 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:37$68_EN[31:0]$76 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:37$68_EN[31:0]$76 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:37$68_EN[31:0]$76 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:37$68_EN[31:0]$76 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:37$68_EN[31:0]$76 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:37$68_EN[31:0]$76 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:37$68_EN[31:0]$76 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:37$68_EN[31:0]$76 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:37$68_EN[31:0]$76 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:37$68_EN[31:0]$76 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:37$68_EN[31:0]$76 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:37$68_EN[31:0]$76 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:37$68_EN[31:0]$76 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:37$68_EN[31:0]$76 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:37$68_EN[31:0]$76 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:37$68_EN[31:0]$76 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:37$68_EN[31:0]$76 [0] } Consolidated identical input bits for $mux cell $flatten\SOC.\GPIOS.$procmux$2103: Old ports: A=16'0000000000000000, B=$flatten\SOC.\GPIOS.$3$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:73$1164_EN[15:0]$1193, Y=$flatten\SOC.\GPIOS.$procmux$2103_Y New ports: A=1'0, B=$flatten\SOC.\GPIOS.$procmux$2047_Y [0], Y=$flatten\SOC.\GPIOS.$procmux$2103_Y [0] New connections: $flatten\SOC.\GPIOS.$procmux$2103_Y [15:1] = { $flatten\SOC.\GPIOS.$procmux$2103_Y [0] $flatten\SOC.\GPIOS.$procmux$2103_Y [0] $flatten\SOC.\GPIOS.$procmux$2103_Y [0] $flatten\SOC.\GPIOS.$procmux$2103_Y [0] $flatten\SOC.\GPIOS.$procmux$2103_Y [0] $flatten\SOC.\GPIOS.$procmux$2103_Y [0] $flatten\SOC.\GPIOS.$procmux$2103_Y [0] $flatten\SOC.\GPIOS.$procmux$2103_Y [0] $flatten\SOC.\GPIOS.$procmux$2103_Y [0] $flatten\SOC.\GPIOS.$procmux$2103_Y [0] $flatten\SOC.\GPIOS.$procmux$2103_Y [0] $flatten\SOC.\GPIOS.$procmux$2103_Y [0] $flatten\SOC.\GPIOS.$procmux$2103_Y [0] $flatten\SOC.\GPIOS.$procmux$2103_Y [0] $flatten\SOC.\GPIOS.$procmux$2103_Y [0] } Consolidated identical input bits for $mux cell $flatten\SOC.\GPIOS.$procmux$2121: Old ports: A=16'0000000000000000, B=$flatten\SOC.\GPIOS.$3$memwr$\period$Risco-5/src/peripheral/gpios.v:72$1163_EN[15:0]$1190, Y=$flatten\SOC.\GPIOS.$procmux$2121_Y New ports: A=1'0, B=$flatten\SOC.\GPIOS.$procmux$2075_Y [0], Y=$flatten\SOC.\GPIOS.$procmux$2121_Y [0] New connections: $flatten\SOC.\GPIOS.$procmux$2121_Y [15:1] = { $flatten\SOC.\GPIOS.$procmux$2121_Y [0] $flatten\SOC.\GPIOS.$procmux$2121_Y [0] $flatten\SOC.\GPIOS.$procmux$2121_Y [0] $flatten\SOC.\GPIOS.$procmux$2121_Y [0] $flatten\SOC.\GPIOS.$procmux$2121_Y [0] $flatten\SOC.\GPIOS.$procmux$2121_Y [0] $flatten\SOC.\GPIOS.$procmux$2121_Y [0] $flatten\SOC.\GPIOS.$procmux$2121_Y [0] $flatten\SOC.\GPIOS.$procmux$2121_Y [0] $flatten\SOC.\GPIOS.$procmux$2121_Y [0] $flatten\SOC.\GPIOS.$procmux$2121_Y [0] $flatten\SOC.\GPIOS.$procmux$2121_Y [0] $flatten\SOC.\GPIOS.$procmux$2121_Y [0] $flatten\SOC.\GPIOS.$procmux$2121_Y [0] $flatten\SOC.\GPIOS.$procmux$2121_Y [0] } Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1808: Old ports: A=$flatten\SOC.\Memory.$3$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1256_EN[31:0]$1294, B=0, Y=$flatten\SOC.\Memory.$procmux$1808_Y New ports: A=$flatten\SOC.\Memory.$procmux$1769_Y [0], B=1'0, Y=$flatten\SOC.\Memory.$procmux$1808_Y [0] New connections: $flatten\SOC.\Memory.$procmux$1808_Y [31:1] = { $flatten\SOC.\Memory.$procmux$1808_Y [0] $flatten\SOC.\Memory.$procmux$1808_Y [0] $flatten\SOC.\Memory.$procmux$1808_Y [0] $flatten\SOC.\Memory.$procmux$1808_Y [0] $flatten\SOC.\Memory.$procmux$1808_Y [0] $flatten\SOC.\Memory.$procmux$1808_Y [0] $flatten\SOC.\Memory.$procmux$1808_Y [0] $flatten\SOC.\Memory.$procmux$1808_Y [0] $flatten\SOC.\Memory.$procmux$1808_Y [0] $flatten\SOC.\Memory.$procmux$1808_Y [0] $flatten\SOC.\Memory.$procmux$1808_Y [0] $flatten\SOC.\Memory.$procmux$1808_Y [0] $flatten\SOC.\Memory.$procmux$1808_Y [0] $flatten\SOC.\Memory.$procmux$1808_Y [0] $flatten\SOC.\Memory.$procmux$1808_Y [0] $flatten\SOC.\Memory.$procmux$1808_Y [0] $flatten\SOC.\Memory.$procmux$1808_Y [0] $flatten\SOC.\Memory.$procmux$1808_Y [0] $flatten\SOC.\Memory.$procmux$1808_Y [0] $flatten\SOC.\Memory.$procmux$1808_Y [0] $flatten\SOC.\Memory.$procmux$1808_Y [0] $flatten\SOC.\Memory.$procmux$1808_Y [0] $flatten\SOC.\Memory.$procmux$1808_Y [0] $flatten\SOC.\Memory.$procmux$1808_Y [0] $flatten\SOC.\Memory.$procmux$1808_Y [0] $flatten\SOC.\Memory.$procmux$1808_Y [0] $flatten\SOC.\Memory.$procmux$1808_Y [0] $flatten\SOC.\Memory.$procmux$1808_Y [0] $flatten\SOC.\Memory.$procmux$1808_Y [0] $flatten\SOC.\Memory.$procmux$1808_Y [0] $flatten\SOC.\Memory.$procmux$1808_Y [0] } Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1826: Old ports: A=$flatten\SOC.\Memory.$3$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1255_EN[31:0]$1291, B=0, Y=$flatten\SOC.\Memory.$procmux$1826_Y New ports: A=$flatten\SOC.\Memory.$procmux$1724_Y [0], B=1'0, Y=$flatten\SOC.\Memory.$procmux$1826_Y [0] New connections: $flatten\SOC.\Memory.$procmux$1826_Y [31:1] = { $flatten\SOC.\Memory.$procmux$1826_Y [0] $flatten\SOC.\Memory.$procmux$1826_Y [0] $flatten\SOC.\Memory.$procmux$1826_Y [0] $flatten\SOC.\Memory.$procmux$1826_Y [0] $flatten\SOC.\Memory.$procmux$1826_Y [0] $flatten\SOC.\Memory.$procmux$1826_Y [0] $flatten\SOC.\Memory.$procmux$1826_Y [0] $flatten\SOC.\Memory.$procmux$1826_Y [0] $flatten\SOC.\Memory.$procmux$1826_Y [0] $flatten\SOC.\Memory.$procmux$1826_Y [0] $flatten\SOC.\Memory.$procmux$1826_Y [0] $flatten\SOC.\Memory.$procmux$1826_Y [0] $flatten\SOC.\Memory.$procmux$1826_Y [0] $flatten\SOC.\Memory.$procmux$1826_Y [0] $flatten\SOC.\Memory.$procmux$1826_Y [0] $flatten\SOC.\Memory.$procmux$1826_Y [0] $flatten\SOC.\Memory.$procmux$1826_Y [0] $flatten\SOC.\Memory.$procmux$1826_Y [0] $flatten\SOC.\Memory.$procmux$1826_Y [0] $flatten\SOC.\Memory.$procmux$1826_Y [0] $flatten\SOC.\Memory.$procmux$1826_Y [0] $flatten\SOC.\Memory.$procmux$1826_Y [0] $flatten\SOC.\Memory.$procmux$1826_Y [0] $flatten\SOC.\Memory.$procmux$1826_Y [0] $flatten\SOC.\Memory.$procmux$1826_Y [0] $flatten\SOC.\Memory.$procmux$1826_Y [0] $flatten\SOC.\Memory.$procmux$1826_Y [0] $flatten\SOC.\Memory.$procmux$1826_Y [0] $flatten\SOC.\Memory.$procmux$1826_Y [0] $flatten\SOC.\Memory.$procmux$1826_Y [0] $flatten\SOC.\Memory.$procmux$1826_Y [0] } Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1846: Old ports: A=0, B=$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1254_EN[31:0]$1284, Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1254_EN[31:0]$1264 New ports: A=1'0, B=$flatten\SOC.\Memory.$procmux$1778_Y [0], Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1254_EN[31:0]$1264 [0] New connections: $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1254_EN[31:0]$1264 [31:1] = { $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1254_EN[31:0]$1264 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1254_EN[31:0]$1264 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1254_EN[31:0]$1264 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1254_EN[31:0]$1264 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1254_EN[31:0]$1264 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1254_EN[31:0]$1264 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1254_EN[31:0]$1264 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1254_EN[31:0]$1264 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1254_EN[31:0]$1264 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1254_EN[31:0]$1264 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1254_EN[31:0]$1264 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1254_EN[31:0]$1264 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1254_EN[31:0]$1264 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1254_EN[31:0]$1264 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1254_EN[31:0]$1264 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1254_EN[31:0]$1264 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1254_EN[31:0]$1264 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1254_EN[31:0]$1264 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1254_EN[31:0]$1264 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1254_EN[31:0]$1264 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1254_EN[31:0]$1264 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1254_EN[31:0]$1264 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1254_EN[31:0]$1264 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1254_EN[31:0]$1264 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1254_EN[31:0]$1264 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1254_EN[31:0]$1264 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1254_EN[31:0]$1264 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1254_EN[31:0]$1264 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1254_EN[31:0]$1264 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1254_EN[31:0]$1264 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1254_EN[31:0]$1264 [0] } Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\RX_FIFO.$procmux$2238: Old ports: A=$flatten\SOC.\Uart.\RX_FIFO.$2$memwr$\memory$Risco-5/src/peripheral/fifo.v:39$1395_EN[7:0]$1409, B=8'00000000, Y=$flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:39$1395_EN[7:0]$1400 New ports: A=$flatten\SOC.\Uart.\RX_FIFO.$procmux$2220_Y [0], B=1'0, Y=$flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:39$1395_EN[7:0]$1400 [0] New connections: $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:39$1395_EN[7:0]$1400 [7:1] = { $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:39$1395_EN[7:0]$1400 [0] $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:39$1395_EN[7:0]$1400 [0] $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:39$1395_EN[7:0]$1400 [0] $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:39$1395_EN[7:0]$1400 [0] $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:39$1395_EN[7:0]$1400 [0] $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:39$1395_EN[7:0]$1400 [0] $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:39$1395_EN[7:0]$1400 [0] } Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\TX_FIFO.$procmux$2238: Old ports: A=$flatten\SOC.\Uart.\TX_FIFO.$2$memwr$\memory$Risco-5/src/peripheral/fifo.v:39$1395_EN[7:0]$1409, B=8'00000000, Y=$flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:39$1395_EN[7:0]$1400 New ports: A=$flatten\SOC.\Uart.\TX_FIFO.$procmux$2220_Y [0], B=1'0, Y=$flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:39$1395_EN[7:0]$1400 [0] New connections: $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:39$1395_EN[7:0]$1400 [7:1] = { $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:39$1395_EN[7:0]$1400 [0] $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:39$1395_EN[7:0]$1400 [0] $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:39$1395_EN[7:0]$1400 [0] $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:39$1395_EN[7:0]$1400 [0] $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:39$1395_EN[7:0]$1400 [0] $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:39$1395_EN[7:0]$1400 [0] $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:39$1395_EN[7:0]$1400 [0] } Optimizing cells in module \top. Consolidated identical input bits for $mux cell $flatten\SOC.\GPIOS.$procmux$2139: Old ports: A=$flatten\SOC.\GPIOS.$2$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:73$1164_EN[15:0]$1187, B=16'0000000000000000, Y=$flatten\SOC.\GPIOS.$0$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:73$1164_EN[15:0]$1175 New ports: A=$flatten\SOC.\GPIOS.$procmux$2103_Y [0], B=1'0, Y=$flatten\SOC.\GPIOS.$0$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:73$1164_EN[15:0]$1175 [0] New connections: $flatten\SOC.\GPIOS.$0$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:73$1164_EN[15:0]$1175 [15:1] = { $flatten\SOC.\GPIOS.$0$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:73$1164_EN[15:0]$1175 [0] $flatten\SOC.\GPIOS.$0$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:73$1164_EN[15:0]$1175 [0] $flatten\SOC.\GPIOS.$0$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:73$1164_EN[15:0]$1175 [0] $flatten\SOC.\GPIOS.$0$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:73$1164_EN[15:0]$1175 [0] $flatten\SOC.\GPIOS.$0$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:73$1164_EN[15:0]$1175 [0] $flatten\SOC.\GPIOS.$0$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:73$1164_EN[15:0]$1175 [0] $flatten\SOC.\GPIOS.$0$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:73$1164_EN[15:0]$1175 [0] $flatten\SOC.\GPIOS.$0$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:73$1164_EN[15:0]$1175 [0] $flatten\SOC.\GPIOS.$0$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:73$1164_EN[15:0]$1175 [0] $flatten\SOC.\GPIOS.$0$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:73$1164_EN[15:0]$1175 [0] $flatten\SOC.\GPIOS.$0$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:73$1164_EN[15:0]$1175 [0] $flatten\SOC.\GPIOS.$0$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:73$1164_EN[15:0]$1175 [0] $flatten\SOC.\GPIOS.$0$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:73$1164_EN[15:0]$1175 [0] $flatten\SOC.\GPIOS.$0$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:73$1164_EN[15:0]$1175 [0] $flatten\SOC.\GPIOS.$0$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:73$1164_EN[15:0]$1175 [0] } Consolidated identical input bits for $mux cell $flatten\SOC.\GPIOS.$procmux$2148: Old ports: A=$flatten\SOC.\GPIOS.$2$memwr$\period$Risco-5/src/peripheral/gpios.v:72$1163_EN[15:0]$1184, B=16'0000000000000000, Y=$flatten\SOC.\GPIOS.$0$memwr$\period$Risco-5/src/peripheral/gpios.v:72$1163_EN[15:0]$1172 New ports: A=$flatten\SOC.\GPIOS.$procmux$2121_Y [0], B=1'0, Y=$flatten\SOC.\GPIOS.$0$memwr$\period$Risco-5/src/peripheral/gpios.v:72$1163_EN[15:0]$1172 [0] New connections: $flatten\SOC.\GPIOS.$0$memwr$\period$Risco-5/src/peripheral/gpios.v:72$1163_EN[15:0]$1172 [15:1] = { $flatten\SOC.\GPIOS.$0$memwr$\period$Risco-5/src/peripheral/gpios.v:72$1163_EN[15:0]$1172 [0] $flatten\SOC.\GPIOS.$0$memwr$\period$Risco-5/src/peripheral/gpios.v:72$1163_EN[15:0]$1172 [0] $flatten\SOC.\GPIOS.$0$memwr$\period$Risco-5/src/peripheral/gpios.v:72$1163_EN[15:0]$1172 [0] $flatten\SOC.\GPIOS.$0$memwr$\period$Risco-5/src/peripheral/gpios.v:72$1163_EN[15:0]$1172 [0] $flatten\SOC.\GPIOS.$0$memwr$\period$Risco-5/src/peripheral/gpios.v:72$1163_EN[15:0]$1172 [0] $flatten\SOC.\GPIOS.$0$memwr$\period$Risco-5/src/peripheral/gpios.v:72$1163_EN[15:0]$1172 [0] $flatten\SOC.\GPIOS.$0$memwr$\period$Risco-5/src/peripheral/gpios.v:72$1163_EN[15:0]$1172 [0] $flatten\SOC.\GPIOS.$0$memwr$\period$Risco-5/src/peripheral/gpios.v:72$1163_EN[15:0]$1172 [0] $flatten\SOC.\GPIOS.$0$memwr$\period$Risco-5/src/peripheral/gpios.v:72$1163_EN[15:0]$1172 [0] $flatten\SOC.\GPIOS.$0$memwr$\period$Risco-5/src/peripheral/gpios.v:72$1163_EN[15:0]$1172 [0] $flatten\SOC.\GPIOS.$0$memwr$\period$Risco-5/src/peripheral/gpios.v:72$1163_EN[15:0]$1172 [0] $flatten\SOC.\GPIOS.$0$memwr$\period$Risco-5/src/peripheral/gpios.v:72$1163_EN[15:0]$1172 [0] $flatten\SOC.\GPIOS.$0$memwr$\period$Risco-5/src/peripheral/gpios.v:72$1163_EN[15:0]$1172 [0] $flatten\SOC.\GPIOS.$0$memwr$\period$Risco-5/src/peripheral/gpios.v:72$1163_EN[15:0]$1172 [0] $flatten\SOC.\GPIOS.$0$memwr$\period$Risco-5/src/peripheral/gpios.v:72$1163_EN[15:0]$1172 [0] } Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1837: Old ports: A=0, B=$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1256_EN[31:0]$1287, Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1256_EN[31:0]$1267 New ports: A=1'0, B=$flatten\SOC.\Memory.$procmux$1808_Y [0], Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1256_EN[31:0]$1267 [0] New connections: $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1256_EN[31:0]$1267 [31:1] = { $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1256_EN[31:0]$1267 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1256_EN[31:0]$1267 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1256_EN[31:0]$1267 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1256_EN[31:0]$1267 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1256_EN[31:0]$1267 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1256_EN[31:0]$1267 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1256_EN[31:0]$1267 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1256_EN[31:0]$1267 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1256_EN[31:0]$1267 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1256_EN[31:0]$1267 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1256_EN[31:0]$1267 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1256_EN[31:0]$1267 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1256_EN[31:0]$1267 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1256_EN[31:0]$1267 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1256_EN[31:0]$1267 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1256_EN[31:0]$1267 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1256_EN[31:0]$1267 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1256_EN[31:0]$1267 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1256_EN[31:0]$1267 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1256_EN[31:0]$1267 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1256_EN[31:0]$1267 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1256_EN[31:0]$1267 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1256_EN[31:0]$1267 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1256_EN[31:0]$1267 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1256_EN[31:0]$1267 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1256_EN[31:0]$1267 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1256_EN[31:0]$1267 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1256_EN[31:0]$1267 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1256_EN[31:0]$1267 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1256_EN[31:0]$1267 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1256_EN[31:0]$1267 [0] } Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1855: Old ports: A=0, B=$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1255_EN[31:0]$1281, Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1255_EN[31:0]$1261 New ports: A=1'0, B=$flatten\SOC.\Memory.$procmux$1826_Y [0], Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1255_EN[31:0]$1261 [0] New connections: $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1255_EN[31:0]$1261 [31:1] = { $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1255_EN[31:0]$1261 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1255_EN[31:0]$1261 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1255_EN[31:0]$1261 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1255_EN[31:0]$1261 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1255_EN[31:0]$1261 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1255_EN[31:0]$1261 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1255_EN[31:0]$1261 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1255_EN[31:0]$1261 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1255_EN[31:0]$1261 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1255_EN[31:0]$1261 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1255_EN[31:0]$1261 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1255_EN[31:0]$1261 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1255_EN[31:0]$1261 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1255_EN[31:0]$1261 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1255_EN[31:0]$1261 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1255_EN[31:0]$1261 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1255_EN[31:0]$1261 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1255_EN[31:0]$1261 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1255_EN[31:0]$1261 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1255_EN[31:0]$1261 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1255_EN[31:0]$1261 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1255_EN[31:0]$1261 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1255_EN[31:0]$1261 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1255_EN[31:0]$1261 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1255_EN[31:0]$1261 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1255_EN[31:0]$1261 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1255_EN[31:0]$1261 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1255_EN[31:0]$1261 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1255_EN[31:0]$1261 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1255_EN[31:0]$1261 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1255_EN[31:0]$1261 [0] } Optimizing cells in module \top. Performed a total of 36 changes. 24.11.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~21 debug messages> Removed a total of 7 cells. 24.11.6. Executing OPT_DFF pass (perform DFF optimizations). 24.11.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 219 unused wires. <suppressed ~5 debug messages> 24.11.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 24.11.9. Rerunning OPT passes. (Maybe there is more to do..) 24.11.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~126 debug messages> 24.11.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. New ctrl vector for $pmux cell $flatten\SOC.\Core.\Alu.$procmux$2673: { $flatten\SOC.\Core.\Alu.$procmux$2687_CMP $flatten\SOC.\Core.\Alu.$procmux$2686_CMP $flatten\SOC.\Core.\Alu.$procmux$2685_CMP $flatten\SOC.\Core.\Alu.$procmux$2684_CMP $auto$opt_reduce.cc:134:opt_pmux$2854 $flatten\SOC.\Core.\Alu.$procmux$2681_CMP $flatten\SOC.\Core.\Alu.$procmux$2680_CMP $flatten\SOC.\Core.\Alu.$procmux$2679_CMP $flatten\SOC.\Core.\Alu.$procmux$2678_CMP $flatten\SOC.\Core.\Alu.$procmux$2677_CMP $flatten\SOC.\Core.\Alu.$procmux$2676_CMP $auto$opt_reduce.cc:134:opt_pmux$2852 } New ctrl vector for $pmux cell $flatten\SOC.\Uart.$procmux$2005: { $flatten\SOC.\Uart.$procmux$1999_CMP $flatten\SOC.\Uart.$procmux$1941_CMP $auto$opt_reduce.cc:134:opt_pmux$2856 $auto$opt_reduce.cc:134:opt_pmux$2848 $flatten\SOC.\Uart.$procmux$1923_CMP } Optimizing cells in module \top. Performed a total of 2 changes. 24.11.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 24.11.13. Executing OPT_DFF pass (perform DFF optimizations). 24.11.14. Executing OPT_CLEAN pass (remove unused cells and wires). + mkdir -p Risco-5/impl/pnr Finding unused cells or wires in module \top.. 24.11.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 24.11.16. Rerunning OPT passes. (Maybe there is more to do..) 24.11.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~126 debug messages> 24.11.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 24.11.19. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 24.11.20. Executing OPT_DFF pass (perform DFF optimizations). 24.11.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 24.11.22. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 24.11.23. Finished OPT passes. (There is nothing left to do.) 24.12. Executing FSM pass (extract and optimize FSM). 24.12.1. Executing FSM_DETECT pass (finding FSMs in design). Not marking top.ResetBootSystem.state as FSM state register: Register has an initialization value. Circuit seems to be self-resetting. Not marking top.SOC.Core.Control_Unit.state as FSM state register: Register has an initialization value. Found FSM state register top.SOC.Uart.i_uart_rx.fsm_state. Not marking top.SOC.Uart.i_uart_tx.fsm_state as FSM state register: Users of register don't seem to benefit from recoding. Not marking top.SOC.Uart.state as FSM state register: Register has an initialization value. 24.12.2. Executing FSM_EXTRACT pass (extracting FSM from design). Extracting FSM `\SOC.Uart.i_uart_rx.fsm_state' from module `\top'. found $dff cell for state register: $flatten\SOC.\Uart.\i_uart_rx.$procdff$2697 root of input selection tree: $flatten\SOC.\Uart.\i_uart_rx.$0\fsm_state[2:0] found reset state: 3'000 (guessed from mux tree) found ctrl input: \ResetBootSystem.reset_o found ctrl input: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:105$1358_Y found ctrl input: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:133$1371_Y found ctrl input: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:171$1384_Y found ctrl input: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:131$1370_Y found state code: 3'000 found ctrl input: \SOC.Uart.i_uart_rx.next_bit found state code: 3'011 found ctrl input: \SOC.Uart.i_uart_rx.payload_done found state code: 3'010 found state code: 3'001 found ctrl input: \SOC.Uart.i_uart_rx.rxd_reg found ctrl output: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:171$1384_Y found ctrl output: $flatten\SOC.\Uart.\i_uart_rx.$ne$Risco-5/src/peripheral/uart_rx.v:146$1375_Y found ctrl output: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:133$1371_Y found ctrl output: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:131$1370_Y found ctrl output: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:105$1358_Y ctrl inputs: { \SOC.Uart.i_uart_rx.rxd_reg \SOC.Uart.i_uart_rx.next_bit \SOC.Uart.i_uart_rx.payload_done \ResetBootSystem.reset_o } ctrl outputs: { $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:105$1358_Y $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:131$1370_Y $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:133$1371_Y $flatten\SOC.\Uart.\i_uart_rx.$ne$Risco-5/src/peripheral/uart_rx.v:146$1375_Y $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:171$1384_Y $flatten\SOC.\Uart.\i_uart_rx.$0\fsm_state[2:0] } transition: 3'000 4'0--0 -> 3'001 8'01010001 transition: 3'000 4'1--0 -> 3'000 8'01010000 transition: 3'000 4'---1 -> 3'000 8'01010000 transition: 3'010 4'--00 -> 3'010 8'00100010 transition: 3'010 4'--10 -> 3'011 8'00100011 transition: 3'010 4'---1 -> 3'000 8'00100000 transition: 3'001 4'-0-0 -> 3'001 8'00011001 transition: 3'001 4'-1-0 -> 3'010 8'00011010 transition: 3'001 4'---1 -> 3'000 8'00011000 transition: 3'011 4'-0-0 -> 3'011 8'10010011 transition: 3'011 4'-1-0 -> 3'000 8'10010000 transition: 3'011 4'---1 -> 3'000 8'10010000 24.12.3. Executing FSM_OPT pass (simple optimizations of FSMs). Optimizing FSM `$fsm$\SOC.Uart.i_uart_rx.fsm_state$2857' from module `\top'. 24.12.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 7 unused cells and 7 unused wires. <suppressed ~8 debug messages> 24.12.5. Executing FSM_OPT pass (simple optimizations of FSMs). Optimizing FSM `$fsm$\SOC.Uart.i_uart_rx.fsm_state$2857' from module `\top'. Removing unused output signal $flatten\SOC.\Uart.\i_uart_rx.$0\fsm_state[2:0] [0]. Removing unused output signal $flatten\SOC.\Uart.\i_uart_rx.$0\fsm_state[2:0] [1]. Removing unused output signal $flatten\SOC.\Uart.\i_uart_rx.$0\fsm_state[2:0] [2]. 24.12.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). Recoding FSM `$fsm$\SOC.Uart.i_uart_rx.fsm_state$2857' from module `\top' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 000 -> ---1 010 -> --1- 001 -> -1-- 011 -> 1--- 24.12.7. Executing FSM_INFO pass (dumping all available information on FSM cells). FSM `$fsm$\SOC.Uart.i_uart_rx.fsm_state$2857' from module `top': ------------------------------------- Information on FSM $fsm$\SOC.Uart.i_uart_rx.fsm_state$2857 (\SOC.Uart.i_uart_rx.fsm_state): Number of input signals: 4 Number of output signals: 5 Number of state bits: 4 Input signals: 0: \ResetBootSystem.reset_o 1: \SOC.Uart.i_uart_rx.payload_done 2: \SOC.Uart.i_uart_rx.next_bit 3: \SOC.Uart.i_uart_rx.rxd_reg Output signals: 0: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:171$1384_Y 1: $flatten\SOC.\Uart.\i_uart_rx.$ne$Risco-5/src/peripheral/uart_rx.v:146$1375_Y 2: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:133$1371_Y 3: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:131$1370_Y 4: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:105$1358_Y State encoding: 0: 4'---1 <RESET STATE> 1: 4'--1- 2: 4'-1-- 3: 4'1--- Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 4'1--0 -> 0 5'01010 1: 0 4'---1 -> 0 5'01010 2: 0 4'0--0 -> 2 5'01010 3: 1 4'---1 -> 0 5'00100 4: 1 4'--00 -> 1 5'00100 5: 1 4'--10 -> 3 5'00100 6: 2 4'---1 -> 0 5'00011 7: 2 4'-1-0 -> 1 5'00011 8: 2 4'-0-0 -> 2 5'00011 9: 3 4'-1-0 -> 0 5'10010 10: 3 4'---1 -> 0 5'10010 11: 3 4'-0-0 -> 3 5'10010 ------------------------------------- 24.12.8. Executing FSM_MAP pass (mapping FSMs to basic logic). Mapping FSM `$fsm$\SOC.Uart.i_uart_rx.fsm_state$2857' from module `\top'. 24.13. Executing OPT pass (performing simple optimizations). 24.13.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~5 debug messages> 24.13.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~6 debug messages> Removed a total of 2 cells. 24.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~125 debug messages> 24.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 24.13.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 24.13.6. Executing OPT_DFF pass (perform DFF optimizations). Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$2709 ($dff) from module top (D = { $flatten\SOC.\Uart.\i_uart_tx.$procmux$1695_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1689_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1680_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1671_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1662_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1653_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1635_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1644_Y }, Q = \SOC.Uart.i_uart_tx.data_to_send, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$2907 ($sdff) from module top (D = \SOC.Uart.uart_tx_data [7], Q = \SOC.Uart.i_uart_tx.data_to_send [7]). Adding EN signal on $auto$ff.cc:266:slice$2907 ($sdff) from module top (D = { $flatten\SOC.\Uart.\i_uart_tx.$procmux$1689_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1680_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1671_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1662_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1653_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1635_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1644_Y }, Q = \SOC.Uart.i_uart_tx.data_to_send [6:0]). Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$2707 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$1611_Y, Q = \SOC.Uart.i_uart_tx.bit_counter, rval = 4'0000). Adding EN signal on $auto$ff.cc:266:slice$2912 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$1611_Y, Q = \SOC.Uart.i_uart_tx.bit_counter). Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$2706 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$1600_Y, Q = \SOC.Uart.i_uart_tx.cycle_counter, rval = 9'000000000). Adding EN signal on $auto$ff.cc:266:slice$2918 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:152$1338_Y, Q = \SOC.Uart.i_uart_tx.cycle_counter). Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$2705 ($dff) from module top (D = \SOC.Uart.i_uart_tx.n_fsm_state, Q = \SOC.Uart.i_uart_tx.fsm_state, rval = 3'000). Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$2704 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$1589_Y, Q = \SOC.Uart.i_uart_tx.txd_reg, rval = 1'1). Adding EN signal on $auto$ff.cc:266:slice$2923 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$1589_Y, Q = \SOC.Uart.i_uart_tx.txd_reg). Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$2703 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$procmux$1578_Y, Q = \SOC.Uart.i_uart_rx.uart_rx_data, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$2929 ($sdff) from module top (D = \SOC.Uart.i_uart_rx.recieved_data, Q = \SOC.Uart.i_uart_rx.uart_rx_data). Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$2701 ($dff) from module top (D = { $flatten\SOC.\Uart.\i_uart_rx.$procmux$1555_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1546_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1537_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1528_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1519_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1510_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1492_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1501_Y }, Q = \SOC.Uart.i_uart_rx.recieved_data, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$2931 ($sdff) from module top (D = { \SOC.Uart.i_uart_rx.bit_sample \SOC.Uart.i_uart_rx.recieved_data [7:1] }, Q = \SOC.Uart.i_uart_rx.recieved_data). Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$2700 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$procmux$1474_Y, Q = \SOC.Uart.i_uart_rx.bit_counter, rval = 4'0000). Adding EN signal on $auto$ff.cc:266:slice$2935 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:149$1378_Y, Q = \SOC.Uart.i_uart_rx.bit_counter). Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$2699 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$procmux$1469_Y, Q = \SOC.Uart.i_uart_rx.bit_sample, rval = 1'0). Adding EN signal on $auto$ff.cc:266:slice$2939 ($sdff) from module top (D = \SOC.Uart.i_uart_rx.rxd_reg, Q = \SOC.Uart.i_uart_rx.bit_sample). Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$2698 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$procmux$1461_Y, Q = \SOC.Uart.i_uart_rx.cycle_counter, rval = 9'000000000). Adding EN signal on $auto$ff.cc:266:slice$2941 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:174$1389_Y, Q = \SOC.Uart.i_uart_rx.cycle_counter). Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$2696 ($dff) from module top (D = \rx, Q = \SOC.Uart.i_uart_rx.rxd_reg_0, rval = 1'1). Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$2695 ($dff) from module top (D = \SOC.Uart.i_uart_rx.rxd_reg_0, Q = \SOC.Uart.i_uart_rx.rxd_reg, rval = 1'1). Adding SRST signal on $flatten\SOC.\Uart.\TX_FIFO.$procdff$2753 ($dff) from module top (D = $flatten\SOC.\Uart.\TX_FIFO.$procmux$2247_Y, Q = \SOC.Uart.TX_FIFO.write_ptr, rval = 6'000000). Adding EN signal on $auto$ff.cc:266:slice$2947 ($sdff) from module top (D = $flatten\SOC.\Uart.\TX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:40$1413_Y, Q = \SOC.Uart.TX_FIFO.write_ptr). Adding SRST signal on $flatten\SOC.\Uart.\TX_FIFO.$procdff$2752 ($dff) from module top (D = $flatten\SOC.\Uart.\TX_FIFO.$procmux$2255_Y, Q = \SOC.Uart.TX_FIFO.read_ptr, rval = 6'000000). Adding EN signal on $auto$ff.cc:266:slice$2949 ($sdff) from module top (D = $flatten\SOC.\Uart.\TX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:43$1419_Y [5:0], Q = \SOC.Uart.TX_FIFO.read_ptr). Adding SRST signal on $flatten\SOC.\Uart.\TX_FIFO.$procdff$2751 ($dff) from module top (D = $flatten\SOC.\Uart.\TX_FIFO.$procmux$2263_Y, Q = \SOC.Uart.TX_FIFO.counter, rval = 6'000000). Adding EN signal on $auto$ff.cc:266:slice$2955 ($sdff) from module top (D = $flatten\SOC.\Uart.\TX_FIFO.$procmux$2263_Y, Q = \SOC.Uart.TX_FIFO.counter). Adding SRST signal on $flatten\SOC.\Uart.\RX_FIFO.$procdff$2753 ($dff) from module top (D = $flatten\SOC.\Uart.\RX_FIFO.$procmux$2247_Y, Q = \SOC.Uart.RX_FIFO.write_ptr, rval = 6'000000). Adding EN signal on $auto$ff.cc:266:slice$2959 ($sdff) from module top (D = $flatten\SOC.\Uart.\RX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:40$1413_Y, Q = \SOC.Uart.RX_FIFO.write_ptr). Adding SRST signal on $flatten\SOC.\Uart.\RX_FIFO.$procdff$2752 ($dff) from module top (D = $flatten\SOC.\Uart.\RX_FIFO.$procmux$2255_Y, Q = \SOC.Uart.RX_FIFO.read_ptr, rval = 6'000000). Adding EN signal on $auto$ff.cc:266:slice$2961 ($sdff) from module top (D = $flatten\SOC.\Uart.\RX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:43$1419_Y [5:0], Q = \SOC.Uart.RX_FIFO.read_ptr). Adding SRST signal on $flatten\SOC.\Uart.\RX_FIFO.$procdff$2751 ($dff) from module top (D = $flatten\SOC.\Uart.\RX_FIFO.$procmux$2263_Y, Q = \SOC.Uart.RX_FIFO.counter, rval = 6'000000). Adding EN signal on $auto$ff.cc:266:slice$2967 ($sdff) from module top (D = $flatten\SOC.\Uart.\RX_FIFO.$procmux$2263_Y, Q = \SOC.Uart.RX_FIFO.counter). Adding SRST signal on $flatten\SOC.\Uart.$procdff$2732 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1939_Y, Q = \SOC.Uart.write_data_buffer, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$2971 ($sdff) from module top (D = $flatten\SOC.\Uart.$procmux$1939_Y, Q = \SOC.Uart.write_data_buffer). Adding SRST signal on $flatten\SOC.\Uart.$procdff$2731 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1957_Y, Q = \SOC.Uart.tx_fifo_write_data, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$2981 ($sdff) from module top (D = \SOC.Uart.write_data_buffer [7:0], Q = \SOC.Uart.tx_fifo_write_data). Adding SRST signal on $flatten\SOC.\Uart.$procdff$2730 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1911_Y, Q = \SOC.Uart.rx_fifo_read, rval = 1'0). Adding SRST signal on $flatten\SOC.\Uart.$procdff$2729 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1892_Y, Q = \SOC.Uart.tx_fifo_write, rval = 1'0). Adding SRST signal on $flatten\SOC.\Uart.$procdff$2728 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1922_Y, Q = \SOC.Uart.response, rval = 1'0). Adding SRST signal on $flatten\SOC.\Uart.$procdff$2727 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1965_Y, Q = \SOC.Uart.read_data, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$3002 ($sdff) from module top (D = $flatten\SOC.\Uart.$procmux$1965_Y, Q = \SOC.Uart.read_data). Adding EN signal on $flatten\SOC.\Uart.$procdff$2726 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1991_Y, Q = \SOC.Uart.counter). Adding SRST signal on $flatten\SOC.\Uart.$procdff$2725 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$2005_Y, Q = \SOC.Uart.state, rval = 4'0000). Adding EN signal on $auto$ff.cc:266:slice$3027 ($sdff) from module top (D = $flatten\SOC.\Uart.$procmux$2005_Y, Q = \SOC.Uart.state). Adding SRST signal on $flatten\SOC.\Uart.$procdff$2724 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1874_Y, Q = \SOC.Uart.rx_fifo_write_data, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$3031 ($sdff) from module top (D = \SOC.Uart.i_uart_rx.uart_rx_data, Q = \SOC.Uart.rx_fifo_write_data). Adding SRST signal on $flatten\SOC.\Uart.$procdff$2723 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1879_Y, Q = \SOC.Uart.uart_tx_data, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$3033 ($sdff) from module top (D = \SOC.Uart.tx_fifo_read_data, Q = \SOC.Uart.uart_tx_data). Adding SRST signal on $flatten\SOC.\Uart.$procdff$2722 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1859_Y, Q = \SOC.Uart.rx_fifo_write, rval = 1'0). Adding SRST signal on $flatten\SOC.\Uart.$procdff$2720 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1864_Y, Q = \SOC.Uart.uart_tx_en, rval = 1'0). Adding SRST signal on $flatten\SOC.\Leds.$procdff$2744 ($dff) from module top (D = $flatten\SOC.\Leds.$procmux$2192_Y, Q = \SOC.Leds.data, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$3037 ($sdff) from module top (D = \SOC.Core.register_data_2, Q = \SOC.Leds.data). Adding SRST signal on $flatten\SOC.\GPIOS.\Pwm1.$procdff$2733 ($dff) from module top (D = $flatten\SOC.\GPIOS.\Pwm1.$add$Risco-5/src/peripheral/pwm.v:21$366_Y, Q = \SOC.GPIOS.Pwm1.counter, rval = 0). Adding SRST signal on $flatten\SOC.\GPIOS.\Pwm0.$procdff$2733 ($dff) from module top (D = $flatten\SOC.\GPIOS.\Pwm0.$add$Risco-5/src/peripheral/pwm.v:21$366_Y, Q = \SOC.GPIOS.Pwm0.counter, rval = 0). Adding EN signal on $flatten\SOC.\GPIOS.$procdff$2737 ($dff) from module top (D = \SOC.Core.register_data_2 [1:0], Q = \SOC.GPIOS.is_pwm). Adding SRST signal on $flatten\SOC.\GPIOS.$procdff$2736 ($dff) from module top (D = $flatten\SOC.\GPIOS.$procmux$2174_Y, Q = \SOC.GPIOS.gpio_value, rval = 6'000000). Adding EN signal on $auto$ff.cc:266:slice$3054 ($sdff) from module top (D = \SOC.Core.register_data_2 [5:0], Q = \SOC.GPIOS.gpio_value). Adding SRST signal on $flatten\SOC.\GPIOS.$procdff$2735 ($dff) from module top (D = $flatten\SOC.\GPIOS.$procmux$2187_Y, Q = \SOC.GPIOS.gpio_direction, rval = 6'000000). Adding EN signal on $auto$ff.cc:266:slice$3058 ($sdff) from module top (D = \SOC.Core.register_data_2 [5:0], Q = \SOC.GPIOS.gpio_direction). Adding SRST signal on $flatten\SOC.\Core.\Pc.$procdff$2762 ($dff) from module top (D = $flatten\SOC.\Core.\Pc.$procmux$2307_Y, Q = \SOC.Core.Pc.Output, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$3062 ($sdff) from module top (D = \SOC.Core.Pc.Input, Q = \SOC.Core.Pc.Output). Adding SRST signal on $flatten\SOC.\Core.\Control_Unit.$procdff$2766 ($dff) from module top (D = \SOC.Core.Control_Unit.nextstate, Q = \SOC.Core.Control_Unit.state, rval = 6'000000). Adding SRST signal on $flatten\SOC.\Core.$procdff$2750 ($dff) from module top (D = $flatten\SOC.\Core.$procmux$2209_Y, Q = \SOC.Core.pc_old, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$3065 ($sdff) from module top (D = \SOC.Core.Pc.Output, Q = \SOC.Core.pc_old). Adding SRST signal on $flatten\SOC.\Core.$procdff$2749 ($dff) from module top (D = \SOC.Core.register_data_2_out, Q = \SOC.Core.register_data_2, rval = 0). Adding SRST signal on $flatten\SOC.\Core.$procdff$2748 ($dff) from module top (D = \SOC.Core.register_data_1_out, Q = \SOC.Core.register_data_1, rval = 0). Adding SRST signal on $flatten\SOC.\Core.$procdff$2747 ($dff) from module top (D = \SOC.Core.Alu.ALU_out_S, Q = \SOC.Core.alu_out_register, rval = 0). Adding SRST signal on $flatten\SOC.\Core.$procdff$2746 ($dff) from module top (D = \SOC.Core.read_data, Q = \SOC.Core.memory_register, rval = 0). Adding SRST signal on $flatten\SOC.\Core.$procdff$2745 ($dff) from module top (D = $flatten\SOC.\Core.$procmux$2214_Y, Q = \SOC.Core.instruction_register, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$3071 ($sdff) from module top (D = \SOC.Core.read_data, Q = \SOC.Core.instruction_register). Adding EN signal on $flatten\ResetBootSystem.$procdff$2765 ($dff) from module top (D = $flatten\ResetBootSystem.$0\counter[5:0], Q = \ResetBootSystem.counter). Adding EN signal on $flatten\ResetBootSystem.$procdff$2764 ($dff) from module top (D = $flatten\ResetBootSystem.$0\state[1:0], Q = \ResetBootSystem.state). Adding EN signal on $flatten\ResetBootSystem.$procdff$2763 ($dff) from module top (D = $flatten\ResetBootSystem.$0\reset_o[0:0], Q = \ResetBootSystem.reset_o). 24.13.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 113 unused cells and 109 unused wires. <suppressed ~114 debug messages> 24.13.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~10 debug messages> 24.13.9. Rerunning OPT passes. (Maybe there is more to do..) 24.13.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~93 debug messages> 24.13.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. New input vector for $reduce_or cell $auto$opt_dff.cc:254:combine_resets$2937: { \SOC.Uart.i_uart_rx.fsm_state [3:2] \SOC.Uart.i_uart_rx.fsm_state [0] \ResetBootSystem.reset_o } Optimizing cells in module \top. Performed a total of 1 changes. 24.13.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~21 debug messages> Removed a total of 7 cells. 24.13.13. Executing OPT_DFF pass (perform DFF optimizations). 24.13.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 1 unused cells and 8 unused wires. <suppressed ~2 debug messages> 24.13.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 24.13.16. Rerunning OPT passes. (Maybe there is more to do..) 24.13.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). [Pipeline] sh Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~93 debug messages> 24.13.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 24.13.19. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 24.13.20. Executing OPT_DFF pass (perform DFF optimizations). 24.13.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 24.13.22. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 24.13.23. Finished OPT passes. (There is nothing left to do.) 24.14. Executing WREDUCE pass (reducing word size of cells). Removed top 27 address bits (of 32) from memory init port top.$flatten\SOC.\Core.\RegisterBank.$auto$proc_memwr.cc:45:proc_memwr$2773 (SOC.Core.RegisterBank.registers). Removed top 27 address bits (of 32) from memory init port top.$flatten\SOC.\Core.\RegisterBank.$auto$proc_memwr.cc:45:proc_memwr$2775 (SOC.Core.RegisterBank.registers). Removed top 27 address bits (of 32) from memory init port top.$flatten\SOC.\Core.\RegisterBank.$meminit$\registers$Risco-5/src/core/registers.v:22$89 (SOC.Core.RegisterBank.registers). Removed top 31 address bits (of 32) from memory read port top.$flatten\SOC.\GPIOS.$memrd$\duty_cycle$Risco-5/src/peripheral/gpios.v:50$1230 (SOC.GPIOS.duty_cycle). Removed top 31 address bits (of 32) from memory read port top.$flatten\SOC.\GPIOS.$memrd$\duty_cycle$Risco-5/src/peripheral/gpios.v:58$1232 (SOC.GPIOS.duty_cycle). Removed top 31 address bits (of 32) from memory read port top.$flatten\SOC.\GPIOS.$memrd$\period$Risco-5/src/peripheral/gpios.v:51$1231 (SOC.GPIOS.period). Removed top 31 address bits (of 32) from memory read port top.$flatten\SOC.\GPIOS.$memrd$\period$Risco-5/src/peripheral/gpios.v:59$1233 (SOC.GPIOS.period). Removed top 27 address bits (of 32) from memory init port top.$flatten\SOC.\Memory.$auto$proc_memwr.cc:45:proc_memwr$2767 (SOC.Memory.memory). Removed top 27 address bits (of 32) from memory init port top.$flatten\SOC.\Memory.$auto$proc_memwr.cc:45:proc_memwr$2768 (SOC.Memory.memory). Removed top 27 address bits (of 32) from memory init port top.$flatten\SOC.\Memory.$auto$proc_memwr.cc:45:proc_memwr$2769 (SOC.Memory.memory). Removed top 27 address bits (of 32) from memory init port top.$flatten\SOC.\Memory.$meminit$\memory$Risco-5/src/peripheral/memory.v:0$1298 (SOC.Memory.memory). Removed top 27 address bits (of 32) from memory read port top.$flatten\SOC.\Memory.$memrd$\memory$Risco-5/src/peripheral/memory.v:24$1257 (SOC.Memory.memory). Removed top 2 address bits (of 6) from memory init port top.$flatten\SOC.\Uart.\RX_FIFO.$auto$proc_memwr.cc:45:proc_memwr$2772 (SOC.Uart.RX_FIFO.memory). Removed top 2 address bits (of 6) from memory read port top.$flatten\SOC.\Uart.\RX_FIFO.$memrd$\memory$Risco-5/src/peripheral/fifo.v:23$1396 (SOC.Uart.RX_FIFO.memory). Removed top 2 address bits (of 6) from memory init port top.$flatten\SOC.\Uart.\TX_FIFO.$auto$proc_memwr.cc:45:proc_memwr$2772 (SOC.Uart.TX_FIFO.memory). Removed top 2 address bits (of 6) from memory read port top.$flatten\SOC.\Uart.\TX_FIFO.$memrd$\memory$Risco-5/src/peripheral/fifo.v:23$1396 (SOC.Uart.TX_FIFO.memory). Removed top 1 bits (of 2) from port B of cell top.$flatten\ResetBootSystem.$procmux$2355_CMP0 ($eq). Removed top 1 bits (of 6) from port B of cell top.$flatten\ResetBootSystem.$eq$Risco-5/debug/reset.v:38$714 ($eq). Removed top 31 bits (of 32) from port B of cell top.$flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$713 ($add). Removed top 26 bits (of 32) from port Y of cell top.$flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$713 ($add). Removed top 27 bits (of 32) from port B of cell top.$flatten\ResetBootSystem.$lt$Risco-5/debug/reset.v:36$712 ($lt). Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$3079 ($ne). Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$3084 ($ne). Removed top 26 bits (of 32) from mux cell top.$flatten\SOC.\GPIOS.$ternary$Risco-5/src/peripheral/gpios.v:37$1168 ($mux). Removed top 3 bits (of 8) from port B of cell top.$flatten\SOC.\GPIOS.$procmux$2048_CMP0 ($eq). Removed top 4 bits (of 8) from port B of cell top.$flatten\SOC.\GPIOS.$procmux$2076_CMP0 ($eq). Removed top 4 bits (of 8) from port B of cell top.$flatten\SOC.\GPIOS.$procmux$2161_CMP0 ($eq). Removed top 5 bits (of 8) from port B of cell top.$flatten\SOC.\GPIOS.$procmux$2173_CMP0 ($eq). Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.$ne$Risco-5/src/peripheral/uart.v:100$1237 ($ne). Removed top 2 bits (of 4) from port B of cell top.$flatten\SOC.\Uart.$procmux$1897_CMP0 ($eq). Removed top 3 bits (of 4) from port B of cell top.$flatten\SOC.\Uart.$procmux$1916_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\SOC.\Uart.$procmux$1923_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\SOC.\Uart.$procmux$1941_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\SOC.\Uart.$procmux$1968_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\SOC.\Uart.$procmux$1969_CMP0 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.$procmux$2024_CMP0 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.$procmux$2025_CMP0 ($eq). Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.$procmux$2026_CMP0 ($eq). Removed top 2 bits (of 6) from mux cell top.$flatten\SOC.\Uart.\TX_FIFO.$procmux$2244 ($mux). Removed top 2 bits (of 6) from mux cell top.$flatten\SOC.\Uart.\TX_FIFO.$procmux$2232 ($mux). Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Uart.\TX_FIFO.$eq$Risco-5/src/peripheral/fifo.v:48$1420 ($eq). Removed top 26 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\TX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:43$1419 ($mux). Removed top 26 bits (of 32) from port Y of cell top.$flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:43$1418 ($add). Removed top 2 bits (of 6) from port B of cell top.$flatten\SOC.\Uart.\TX_FIFO.$eq$Risco-5/src/peripheral/fifo.v:43$1417 ($eq). Removed top 2 bits (of 6) from port B of cell top.$flatten\SOC.\Uart.\TX_FIFO.$eq$Risco-5/src/peripheral/fifo.v:40$1411 ($eq). Removed top 2 bits (of 6) from mux cell top.$flatten\SOC.\Uart.\RX_FIFO.$procmux$2244 ($mux). Removed top 2 bits (of 6) from mux cell top.$flatten\SOC.\Uart.\RX_FIFO.$procmux$2232 ($mux). Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Uart.\RX_FIFO.$eq$Risco-5/src/peripheral/fifo.v:48$1420 ($eq). Removed top 26 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\RX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:43$1419 ($mux). Removed top 26 bits (of 32) from port Y of cell top.$flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:43$1418 ($add). Removed top 2 bits (of 6) from port B of cell top.$flatten\SOC.\Uart.\RX_FIFO.$eq$Risco-5/src/peripheral/fifo.v:43$1417 ($eq). Removed top 2 bits (of 6) from port B of cell top.$flatten\SOC.\Uart.\RX_FIFO.$eq$Risco-5/src/peripheral/fifo.v:40$1411 ($eq). Removed top 30 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:116$1367 ($mux). Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:115$1366 ($mux). Removed top 30 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:114$1365 ($mux). Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:113$1364 ($mux). Removed top 2 bits (of 9) from port B of cell top.$flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:106$1359 ($eq). Removed top 1 bits (of 9) from port B of cell top.$flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:104$1357 ($eq). Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:149$1333 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:134$1325 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:132$1323 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$ne$Risco-5/src/peripheral/uart_tx.v:130$1320 ($ne). Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$ne$Risco-5/src/peripheral/uart_tx.v:130$1319 ($ne). Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:117$1315 ($eq). Removed top 30 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:100$1310 ($mux). Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:99$1309 ($mux). Removed top 30 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:98$1308 ($mux). Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:97$1307 ($mux). Removed top 3 bits (of 4) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:91$1303 ($eq). Removed top 1 bits (of 9) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:89$1301 ($eq). Removed top 1 bits (of 2) from port B of cell top.$flatten\SOC.\Bus.$eq$Risco-5/src/peripheral/bus.v:53$96 ($eq). Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Memory.$procmux$1720_CMP0 ($eq). Removed top 27 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1831 ($mux). Removed top 27 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1840 ($mux). Removed top 27 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1849 ($mux). Removed top 1 bits (of 2) from port B of cell top.$flatten\SOC.\Core.\MemoryAddressMUX.$procmux$2319_CMP0 ($eq). Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\MemoryDataMUX.$procmux$2319_CMP0 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\MemoryDataMUX.$procmux$2318_CMP0 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\MemoryDataMUX.$procmux$2317_CMP0 ($eq). Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\AluInputAMUX.$procmux$2319_CMP0 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\AluInputAMUX.$procmux$2318_CMP0 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\AluInputAMUX.$procmux$2317_CMP0 ($eq). Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\AluInputBMUX.$procmux$2319_CMP0 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\AluInputBMUX.$procmux$2318_CMP0 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\AluInputBMUX.$procmux$2317_CMP0 ($eq). Removed top 1 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2602_CMP0 ($eq). Removed top 1 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2601_CMP0 ($eq). Removed top 2 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2600_CMP0 ($eq). Removed top 2 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2597_CMP0 ($eq). Removed top 1 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2596_CMP0 ($eq). Removed top 2 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2593 ($pmux). Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2573 ($mux). Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2554 ($mux). Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2536 ($mux). Removed top 4 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2476_CMP0 ($eq). Removed top 3 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2462_CMP0 ($eq). Removed top 1 bits (of 3) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2447 ($pmux). Removed top 1 bits (of 3) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2421 ($pmux). Removed top 5 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2419_CMP0 ($eq). Removed top 4 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2418_CMP0 ($eq). Removed top 3 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2417_CMP0 ($eq). Removed top 2 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2415_CMP0 ($eq). Removed top 2 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2414_CMP0 ($eq). Removed top 2 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2413_CMP0 ($eq). Removed top 2 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2411_CMP0 ($eq). Removed top 1 bits (of 3) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2409 ($pmux). Removed top 2 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2410_CMP0 ($eq). Removed top 3 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2407_CMP0 ($eq). Removed top 3 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2406_CMP0 ($eq). Removed top 2 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2405_CMP0 ($eq). Removed top 2 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2403_CMP0 ($eq). Removed top 2 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2402_CMP0 ($eq). Removed top 5 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$eq$Risco-5/src/core/control_unit.v:210$40 ($eq). Removed top 1 bits (of 4) from mux cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$2659 ($mux). Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$2657_CMP0 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$2656_CMP0 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$2655_CMP0 ($eq). Removed top 1 bits (of 2) from port B of cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$2671_CMP0 ($eq). Removed top 3 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Alu.$procmux$2686_CMP0 ($eq). Removed top 2 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Alu.$procmux$2685_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Alu.$procmux$2684_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Alu.$procmux$2683_CMP0 ($eq). Removed top 2 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Alu.$procmux$2676_CMP0 ($eq). Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Core.\Alu.$ternary$Risco-5/src/core/alu.v:53$28 ($mux). Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Core.\Alu.$ternary$Risco-5/src/core/alu.v:37$17 ($mux). Removed top 27 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1790 ($mux). Removed top 27 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1796 ($mux). Removed top 27 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1814 ($mux). Removed top 27 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1742 ($mux). Removed top 27 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1751 ($mux). Removed top 26 bits (of 32) from wire top.$flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$713_Y. Removed top 1 bits (of 4) from wire top.$flatten\SOC.\Core.\ALU_Control.$procmux$2659_Y. Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Core.\Alu.$eq$Risco-5/src/core/alu.v:45$23_Y. Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Core.\Alu.$ternary$Risco-5/src/core/alu.v:37$17_Y. Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Core.\Alu.$ternary$Risco-5/src/core/alu.v:53$28_Y. Removed top 2 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$3\nextstate[5:0]. Removed top 3 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$4\nextstate[5:0]. Removed top 3 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$5\nextstate[5:0]. Removed top 3 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$6\nextstate[5:0]. Removed top 27 bits (of 32) from wire top.$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1254_ADDR[31:0]$1266. Removed top 27 bits (of 32) from wire top.$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1255_ADDR[31:0]$1263. Removed top 27 bits (of 32) from wire top.$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1256_ADDR[31:0]$1269. Removed top 1 bits (of 32) from wire top.$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1256_DATA[31:0]$1268. Removed top 27 bits (of 32) from wire top.$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1254_ADDR[31:0]$1286. Removed top 3 bits (of 32) from wire top.$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1254_DATA[31:0]$1285. Removed top 27 bits (of 32) from wire top.$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1255_ADDR[31:0]$1283. Removed top 27 bits (of 32) from wire top.$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1256_ADDR[31:0]$1289. Removed top 27 bits (of 32) from wire top.$flatten\SOC.\Memory.$3$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1255_ADDR[31:0]$1293. Removed top 27 bits (of 32) from wire top.$flatten\SOC.\Memory.$3$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1256_ADDR[31:0]$1296. Removed top 2 bits (of 6) from wire top.$flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:39$1395_ADDR[5:0]$1398. Removed top 2 bits (of 6) from wire top.$flatten\SOC.\Uart.\RX_FIFO.$2$memwr$\memory$Risco-5/src/peripheral/fifo.v:39$1395_ADDR[5:0]$1407. Removed top 26 bits (of 32) from wire top.$flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:43$1418_Y. Removed top 26 bits (of 32) from wire top.$flatten\SOC.\Uart.\RX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:43$1419_Y. Removed top 2 bits (of 6) from wire top.$flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:39$1395_ADDR[5:0]$1398. Removed top 2 bits (of 6) from wire top.$flatten\SOC.\Uart.\TX_FIFO.$2$memwr$\memory$Risco-5/src/peripheral/fifo.v:39$1395_ADDR[5:0]$1407. Removed top 26 bits (of 32) from wire top.$flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:43$1418_Y. Removed top 26 bits (of 32) from wire top.$flatten\SOC.\Uart.\TX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:43$1419_Y. Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:113$1364_Y. Removed top 30 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:114$1365_Y. Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:115$1366_Y. Removed top 30 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:116$1367_Y. Removed top 30 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:100$1310_Y. Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:97$1307_Y. Removed top 30 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:98$1308_Y. 24.15. Executing PEEPOPT pass (run peephole optimizers). 24.16. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 34 unused wires. <suppressed ~1 debug messages> 24.17. Executing SHARE pass (SAT-based resource sharing). Found 5 cells in module top that may be considered for resource sharing. Analyzing resource sharing options for $flatten\SOC.\Uart.\RX_FIFO.$memrd$\memory$Risco-5/src/peripheral/fifo.v:23$1396 ($memrd): Found 1 activation_patterns using ctrl signal { \SOC.Uart.RX_FIFO.empty $flatten\SOC.\Uart.$procmux$1916_CMP $flatten\SOC.\Uart.$ne$Risco-5/src/peripheral/uart.v:100$1237_Y }. No candidates found. Analyzing resource sharing options for $flatten\SOC.\Memory.$memrd$\memory$Risco-5/src/peripheral/memory.v:24$1257 ($memrd): Found 7 activation_patterns using ctrl signal { $flatten\SOC.\Memory.$procmux$1721_CMP $flatten\SOC.\Memory.$procmux$1720_CMP $flatten\SOC.\Memory.$procmux$1719_CMP $flatten\SOC.\Memory.$procmux$1718_CMP \SOC.Memory.option [1:0] \SOC.Memory.memory_write $flatten\SOC.\Bus.$eq$Risco-5/src/peripheral/bus.v:48$92_Y }. No candidates found. Analyzing resource sharing options for $flatten\SOC.\Core.\Alu.$sshr$Risco-5/src/core/alu.v:51$26 ($sshr): Found 1 activation_patterns using ctrl signal $flatten\SOC.\Core.\Alu.$procmux$2676_CMP. No candidates found. Analyzing resource sharing options for $flatten\SOC.\Core.\Alu.$shr$Risco-5/src/core/alu.v:49$25 ($shr): Found 1 activation_patterns using ctrl signal $flatten\SOC.\Core.\Alu.$procmux$2677_CMP. No candidates found. Analyzing resource sharing options for $flatten\SOC.\Core.\Alu.$shl$Risco-5/src/core/alu.v:47$24 ($shl): Found 1 activation_patterns using ctrl signal $flatten\SOC.\Core.\Alu.$procmux$2678_CMP. No candidates found. 24.18. Executing TECHMAP pass (map to technology primitives). 24.18.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/cmp2lut.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/cmp2lut.v' to AST representation. Generating RTLIL representation for module `\_90_lut_cmp_'. Successfully finished Verilog frontend. 24.18.2. Continuing TECHMAP pass. No more expansions possible. <suppressed ~114 debug messages> 24.19. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~12 debug messages> 24.20. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 12 unused wires. <suppressed ~1 debug messages> 24.21. Executing TECHMAP pass (map to technology primitives). 24.21.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v' to AST representation. Generating RTLIL representation for module `\_80_mul'. Generating RTLIL representation for module `\_90_soft_mul'. Successfully finished Verilog frontend. 24.21.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/dsp_map.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/dsp_map.v' to AST representation. Generating RTLIL representation for module `\$__MUL18X18'. Successfully finished Verilog frontend. 24.21.3. Continuing TECHMAP pass. No more expansions possible. <suppressed ~5 debug messages> 24.22. Executing ALUMACC pass (create $alu and $macc cells). Extracting $alu and $macc cells in module top: creating $macc model for $flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$713 ($add). creating $macc model for $flatten\SOC.\Core.\Alu.$add$Risco-5/src/core/alu.v:33$14 ($add). creating $macc model for $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:35$15 ($sub). creating $macc model for $flatten\SOC.\GPIOS.\Pwm0.$add$Risco-5/src/peripheral/pwm.v:21$366 ($add). creating $macc model for $flatten\SOC.\GPIOS.\Pwm1.$add$Risco-5/src/peripheral/pwm.v:21$366 ($add). creating $macc model for $flatten\SOC.\Uart.$add$Risco-5/src/peripheral/uart.v:102$1239 ($add). creating $macc model for $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:38$1410 ($add). creating $macc model for $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:40$1412 ($add). creating $macc model for $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:43$1418 ($add). creating $macc model for $flatten\SOC.\Uart.\RX_FIFO.$sub$Risco-5/src/peripheral/fifo.v:42$1416 ($sub). creating $macc model for $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:38$1410 ($add). creating $macc model for $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:40$1412 ($add). creating $macc model for $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:43$1418 ($add). creating $macc model for $flatten\SOC.\Uart.\TX_FIFO.$sub$Risco-5/src/peripheral/fifo.v:42$1416 ($sub). creating $macc model for $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:149$1378 ($add). creating $macc model for $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:174$1389 ($add). creating $macc model for $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:135$1327 ($add). creating $macc model for $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:152$1338 ($add). creating $alu model for $macc $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:152$1338. creating $alu model for $macc $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:135$1327. creating $alu model for $macc $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:174$1389. creating $alu model for $macc $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:149$1378. creating $alu model for $macc $flatten\SOC.\Uart.\TX_FIFO.$sub$Risco-5/src/peripheral/fifo.v:42$1416. creating $alu model for $macc $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:43$1418. creating $alu model for $macc $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:40$1412. creating $alu model for $macc $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:38$1410. creating $alu model for $macc $flatten\SOC.\Uart.\RX_FIFO.$sub$Risco-5/src/peripheral/fifo.v:42$1416. creating $alu model for $macc $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:43$1418. creating $alu model for $macc $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:40$1412. creating $alu model for $macc $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:38$1410. creating $alu model for $macc $flatten\SOC.\Uart.$add$Risco-5/src/peripheral/uart.v:102$1239. creating $alu model for $macc $flatten\SOC.\GPIOS.\Pwm1.$add$Risco-5/src/peripheral/pwm.v:21$366. creating $alu model for $macc $flatten\SOC.\GPIOS.\Pwm0.$add$Risco-5/src/peripheral/pwm.v:21$366. creating $alu model for $macc $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:35$15. creating $alu model for $macc $flatten\SOC.\Core.\Alu.$add$Risco-5/src/core/alu.v:33$14. creating $alu model for $macc $flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$713. creating $alu model for $flatten\ResetBootSystem.$lt$Risco-5/debug/reset.v:36$712 ($lt): new $alu creating $alu model for $flatten\SOC.\Core.\Alu.$ge$Risco-5/src/core/alu.v:53$27 ($ge): merged with $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:35$15. creating $alu model for $flatten\SOC.\Core.\Alu.$lt$Risco-5/src/core/alu.v:37$16 ($lt): merged with $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:35$15. creating $alu model for $flatten\SOC.\GPIOS.\Pwm0.$lt$Risco-5/src/peripheral/pwm.v:20$365 ($lt): new $alu creating $alu model for $flatten\SOC.\GPIOS.\Pwm0.$lt$Risco-5/src/peripheral/pwm.v:27$367 ($lt): new $alu creating $alu model for $flatten\SOC.\GPIOS.\Pwm1.$lt$Risco-5/src/peripheral/pwm.v:20$365 ($lt): new $alu creating $alu model for $flatten\SOC.\GPIOS.\Pwm1.$lt$Risco-5/src/peripheral/pwm.v:27$367 ($lt): new $alu creating $alu model for $flatten\ResetBootSystem.$eq$Risco-5/debug/reset.v:38$714 ($eq): merged with $flatten\ResetBootSystem.$lt$Risco-5/debug/reset.v:36$712. creating $alu model for $flatten\SOC.\Core.\Alu.$eq$Risco-5/src/core/alu.v:45$23 ($eq): merged with $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:35$15. creating $alu cell for $flatten\SOC.\GPIOS.\Pwm1.$lt$Risco-5/src/peripheral/pwm.v:27$367: $auto$alumacc.cc:485:replace_alu$3136 creating $alu cell for $flatten\SOC.\GPIOS.\Pwm1.$lt$Risco-5/src/peripheral/pwm.v:20$365: $auto$alumacc.cc:485:replace_alu$3147 creating $alu cell for $flatten\SOC.\GPIOS.\Pwm0.$lt$Risco-5/src/peripheral/pwm.v:27$367: $auto$alumacc.cc:485:replace_alu$3158 creating $alu cell for $flatten\SOC.\GPIOS.\Pwm0.$lt$Risco-5/src/peripheral/pwm.v:20$365: $auto$alumacc.cc:485:replace_alu$3169 creating $alu cell for $flatten\ResetBootSystem.$lt$Risco-5/debug/reset.v:36$712, $flatten\ResetBootSystem.$eq$Risco-5/debug/reset.v:38$714: $auto$alumacc.cc:485:replace_alu$3180 creating $alu cell for $flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$713: $auto$alumacc.cc:485:replace_alu$3191 creating $alu cell for $flatten\SOC.\Core.\Alu.$add$Risco-5/src/core/alu.v:33$14: $auto$alumacc.cc:485:replace_alu$3194 creating $alu cell for $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:35$15, $flatten\SOC.\Core.\Alu.$ge$Risco-5/src/core/alu.v:53$27, $flatten\SOC.\Core.\Alu.$lt$Risco-5/src/core/alu.v:37$16, $flatten\SOC.\Core.\Alu.$eq$Risco-5/src/core/alu.v:45$23: $auto$alumacc.cc:485:replace_alu$3197 creating $alu cell for $flatten\SOC.\GPIOS.\Pwm0.$add$Risco-5/src/peripheral/pwm.v:21$366: $auto$alumacc.cc:485:replace_alu$3210 creating $alu cell for $flatten\SOC.\GPIOS.\Pwm1.$add$Risco-5/src/peripheral/pwm.v:21$366: $auto$alumacc.cc:485:replace_alu$3213 creating $alu cell for $flatten\SOC.\Uart.$add$Risco-5/src/peripheral/uart.v:102$1239: $auto$alumacc.cc:485:replace_alu$3216 creating $alu cell for $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:38$1410: $auto$alumacc.cc:485:replace_alu$3219 creating $alu cell for $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:40$1412: $auto$alumacc.cc:485:replace_alu$3222 creating $alu cell for $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:43$1418: $auto$alumacc.cc:485:replace_alu$3225 creating $alu cell for $flatten\SOC.\Uart.\RX_FIFO.$sub$Risco-5/src/peripheral/fifo.v:42$1416: $auto$alumacc.cc:485:replace_alu$3228 creating $alu cell for $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:38$1410: $auto$alumacc.cc:485:replace_alu$3231 creating $alu cell for $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:40$1412: $auto$alumacc.cc:485:replace_alu$3234 creating $alu cell for $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:43$1418: $auto$alumacc.cc:485:replace_alu$3237 creating $alu cell for $flatten\SOC.\Uart.\TX_FIFO.$sub$Risco-5/src/peripheral/fifo.v:42$1416: $auto$alumacc.cc:485:replace_alu$3240 creating $alu cell for $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:149$1378: $auto$alumacc.cc:485:replace_alu$3243 creating $alu cell for $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:174$1389: $auto$alumacc.cc:485:replace_alu$3246 creating $alu cell for $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:135$1327: $auto$alumacc.cc:485:replace_alu$3249 creating $alu cell for $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:152$1338: $auto$alumacc.cc:485:replace_alu$3252 created 23 $alu and 0 $macc cells. 24.23. Executing OPT pass (performing simple optimizations). 24.23.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~7 debug messages> 24.23.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 24.23.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. dead port 1/9 on $pmux $flatten\SOC.\Core.\AluInputAMUX.$procmux$2312. dead port 2/9 on $pmux $flatten\SOC.\Core.\AluInputAMUX.$procmux$2312. dead port 3/9 on $pmux $flatten\SOC.\Core.\AluInputAMUX.$procmux$2312. dead port 4/9 on $pmux $flatten\SOC.\Core.\AluInputAMUX.$procmux$2312. dead port 1/9 on $pmux $flatten\SOC.\Core.\AluInputBMUX.$procmux$2312. dead port 2/9 on $pmux $flatten\SOC.\Core.\AluInputBMUX.$procmux$2312. dead port 3/9 on $pmux $flatten\SOC.\Core.\AluInputBMUX.$procmux$2312. dead port 4/9 on $pmux $flatten\SOC.\Core.\AluInputBMUX.$procmux$2312. dead port 1/9 on $pmux $flatten\SOC.\Core.\MemoryDataMUX.$procmux$2312. dead port 2/9 on $pmux $flatten\SOC.\Core.\MemoryDataMUX.$procmux$2312. dead port 3/9 on $pmux $flatten\SOC.\Core.\MemoryDataMUX.$procmux$2312. dead port 4/9 on $pmux $flatten\SOC.\Core.\MemoryDataMUX.$procmux$2312. Removed 12 multiplexer ports. <suppressed ~93 debug messages> 24.23.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 24.23.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 24.23.6. Executing OPT_DFF pass (perform DFF optimizations). 24.23.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 4 unused cells and 21 unused wires. <suppressed ~11 debug messages> 24.23.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 24.23.9. Rerunning OPT passes. (Maybe there is more to do..) 24.23.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~93 debug messages> 24.23.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 24.23.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 24.23.13. Executing OPT_DFF pass (perform DFF optimizations). + cd Risco-5/fpga/tangnano20k/ + /eda/gowin/IDE/bin/gw_sh run.tcl *** GOWIN Tcl Command Line Console *** current device: GW2AR-18C GW2AR-LV18QN88C8/I7 add new file: "pinout.cst" add new file: "top.sdc" add new file: "main.v" add new file: "../../debug/reset.v" add new file: "../../src/core/alu_control.v" add new file: "../../src/core/alu.v" add new file: "../../src/core/control_unit.v" add new file: "../../src/core/core.v" add new file: "../../src/core/immediate_generator.v" add new file: "../../src/core/mux.v" add new file: "../../src/core/pc.v" add new file: "../../src/core/registers.v" add new file: "../../src/core/csr_unit.v" add new file: "../../src/core/mdu.v" add new file: "../../src/peripheral/bus.v" add new file: "../../src/peripheral/gpio.v" add new file: "../../src/peripheral/gpios.v" add new file: "../../src/peripheral/leds.v" add new file: "../../src/peripheral/memory.v" add new file: "../../src/peripheral/soc.v" add new file: "../../src/peripheral/uart_rx.v" add new file: "../../src/peripheral/uart_tx.v" add new file: "../../src/peripheral/uart.v" add new file: "../../src/peripheral/fifo.v" add new file: "../../src/peripheral/pwm.v" GowinSynthesis start Running parser ... Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/main.v' Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/debug/reset.v' Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v' Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu.v' Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v' Analyzing included file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/config.vh'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v":1) Back to file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v":1) Undeclared symbol 'second_block_write_src_b', assumed default net type 'wire'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v":114) Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v' Analyzing included file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/config.vh'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":1) Back to file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":1) Undeclared symbol 'pc_source', assumed default net type 'wire'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":187) Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/immediate_generator.v' Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/mux.v' Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/pc.v' Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/registers.v' Analyzing included file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/config.vh'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/registers.v":1) Back to file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/registers.v'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/registers.v":1) Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/csr_unit.v' Analyzing included file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/config.vh'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/csr_unit.v":1) Back to file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/csr_unit.v'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/csr_unit.v":1) Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/mdu.v' Analyzing included file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/config.vh'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/mdu.v":4) Back to file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/mdu.v'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/mdu.v":4) Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/bus.v' Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpio.v' Analyzing included file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/config.vh'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpio.v":1) Back to file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpio.v'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpio.v":1) Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v' Analyzing included file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/config.vh'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":1) Back to file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":1) Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/leds.v' Analyzing included file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/config.vh'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/leds.v":1) Back to file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/leds.v'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/leds.v":1) Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v' WARN (EX3012) : Empty statement in sequential block("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v":54) Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v' Analyzing included file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/config.vh'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":1) Back to file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":1) Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_rx.v' Analyzing included file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/config.vh'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_rx.v":1) Back to file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_rx.v'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_rx.v":1) Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_tx.v' Analyzing included file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/config.vh'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_tx.v":1) Back to file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_tx.v'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_tx.v":1) Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart.v' Analyzing included file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/config.vh'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart.v":1) Back to file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart.v'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart.v":1) Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/fifo.v' Analyzing included file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/config.vh'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/fifo.v":1) Back to file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/fifo.v'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/fifo.v":1) Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/pwm.v' Analyzing included file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/config.vh'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/pwm.v":1) Back to file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/pwm.v'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/pwm.v":1) WARN (EX3073) : Port 'resetn_o' remains unconnected for this instance("/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/main.v":18) Compiling module 'top'("/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/main.v":1) Compiling module 'ResetBootSystem'("/var/lib/jenkins/workspace/Risco_5/Risco-5/debug/reset.v":1) WARN (EX3791) : Expression size 7 truncated to fit in target size 6("/var/lib/jenkins/workspace/Risco_5/Risco-5/debug/reset.v":37) Compiling module 'Risco_5_SOC(CLOCK_FREQ=27000000,BIT_RATE=115200,MEMORY_SIZE=2048,MEMORY_FILE="../../software/memory/teste_uart_fpga.hex",UART_BUFFER_SIZE=16)'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":3) WARN (EX3073) : Port 'C' remains unconnected for this instance("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX3073) : Port 'C' remains unconnected for this instance("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":138) WARN (EX3073) : Port 'G' remains unconnected for this instance("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":154) WARN (EX3073) : Port 'D' remains unconnected for this instance("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) Compiling module 'Core(BOOT_ADDRESS=32'b00000000000000000000000000000000)'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":2) Compiling module 'PC'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/pc.v":1) Compiling module 'MUX'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/mux.v":1) Compiling module 'Registers'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/registers.v":2) Compiling module 'Control_Unit'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v":2) WARN (EX3791) : Expression size 3 truncated to fit in target size 1("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v":114) Compiling module 'ALU_Control'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v":1) Compiling module 'Alu'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu.v":1) Compiling module 'Immediate_Generator'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/immediate_generator.v":1) WARN (EX1998) : Net 'mdu_done' does not have a driver("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":55) WARN (EX2565) : Input 'C[31]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'C[30]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'C[29]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'C[28]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'C[27]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'C[26]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'C[25]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'C[24]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'C[23]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'C[22]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'C[21]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'C[20]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'C[19]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'C[18]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'C[17]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'C[16]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'C[15]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'C[14]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'C[13]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'C[12]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'C[11]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'C[10]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'C[9]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'C[8]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'C[7]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'C[6]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'C[5]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'C[4]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'C[3]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'C[2]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'C[1]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'C[0]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'D[31]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'D[30]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'D[29]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'D[28]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'D[27]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'D[26]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'D[25]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'D[24]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'D[23]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'D[22]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'D[21]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'D[20]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'D[19]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'D[18]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'D[17]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'D[16]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'D[15]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'D[14]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'D[13]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'D[12]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'D[11]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'D[10]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'D[9]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'D[8]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'D[7]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'D[6]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'D[5]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'D[4]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'D[3]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'D[2]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'D[1]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'D[0]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'E[31]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'E[30]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'E[29]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'E[28]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'E[27]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'E[26]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'E[25]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'E[24]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'E[23]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'E[22]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'E[21]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'E[20]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'E[19]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'E[18]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'E[17]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'E[16]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'E[15]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'E[14]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'E[13]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'E[12]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'E[11]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'E[10]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'E[9]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'E[8]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'E[7]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'E[6]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'E[5]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'E[4]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'E[3]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'E[2]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'E[1]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'E[0]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'F[31]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'F[30]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'F[29]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'F[28]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'F[27]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'F[26]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'F[25]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'F[24]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'F[23]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'F[22]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'F[21]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'F[20]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'F[19]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'F[18]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'F[17]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'F[16]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'F[15]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'F[14]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'F[13]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'F[12]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'F[11]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'F[10]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'F[9]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'F[8]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'F[7]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'F[6]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'F[5]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'F[4]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'F[3]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'F[2]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'F[1]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'F[0]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'G[31]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'G[30]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'G[29]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'G[28]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'G[27]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'G[26]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'G[25]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'G[24]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'G[23]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'G[22]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'G[21]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'G[20]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'G[19]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'G[18]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'G[17]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'G[16]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'G[15]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'G[14]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'G[13]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'G[12]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'G[11]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'G[10]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'G[9]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'G[8]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'G[7]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'G[6]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'G[5]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'G[4]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'G[3]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'G[2]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'G[1]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'G[0]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'H[31]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'H[30]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'H[29]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'H[28]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'H[27]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'H[26]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'H[25]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'H[24]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'H[23]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'H[22]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'H[21]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'H[20]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'H[19]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'H[18]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'H[17]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'H[16]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'H[15]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'H[14]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'H[13]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'H[12]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'H[11]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'H[10]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'H[9]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'H[8]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'H[7]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'H[6]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'H[5]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'H[4]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'H[3]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'H[2]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'H[1]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'H[0]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":117) WARN (EX2565) : Input 'C[31]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":138) WARN (EX2565) : Input 'C[30]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":138) WARN (EX2565) : Input 'C[29]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":138) WARN (EX2565) : Input 'C[28]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":138) WARN (EX2565) : Input 'C[27]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":138) WARN (EX2565) : Input 'C[26]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":138) WARN (EX2565) : Input 'C[25]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":138) WARN (EX2565) : Input 'C[24]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":138) WARN (EX2565) : Input 'C[23]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":138) WARN (EX2565) : Input 'C[22]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":138) WARN (EX2565) : Input 'C[21]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":138) WARN (EX2565) : Input 'C[20]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":138) WARN (EX2565) : Input 'C[19]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":138) WARN (EX2565) : Input 'C[18]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":138) WARN (EX2565) : Input 'C[17]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":138) WARN (EX2565) : Input 'C[16]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":138) WARN (EX2565) : Input 'C[15]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":138) WARN (EX2565) : Input 'C[14]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":138) WARN (EX2565) : Input 'C[13]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":138) WARN (EX2565) : Input 'C[12]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":138) WARN (EX2565) : Input 'C[11]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":138) WARN (EX2565) : Input 'C[10]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":138) WARN (EX2565) : Input 'C[9]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":138) WARN (EX2565) : Input 'C[8]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":138) WARN (EX2565) : Input 'C[7]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":138) WARN (EX2565) : Input 'C[6]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":138) WARN (EX2565) : Input 'C[5]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":138) WARN (EX2565) : Input 'C[4]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":138) WARN (EX2565) : Input 'C[3]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":138) WARN (EX2565) : Input 'C[2]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":138) WARN (EX2565) : Input 'C[1]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":138) WARN (EX2565) : Input 'C[0]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":138) WARN (EX2565) : Input 'G[31]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":154) WARN (EX2565) : Input 'G[30]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":154) WARN (EX2565) : Input 'G[29]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":154) WARN (EX2565) : Input 'G[28]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":154) WARN (EX2565) : Input 'G[27]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":154) WARN (EX2565) : Input 'G[26]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":154) WARN (EX2565) : Input 'G[25]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":154) WARN (EX2565) : Input 'G[24]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":154) WARN (EX2565) : Input 'G[23]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":154) WARN (EX2565) : Input 'G[22]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":154) WARN (EX2565) : Input 'G[21]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":154) WARN (EX2565) : Input 'G[20]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":154) WARN (EX2565) : Input 'G[19]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":154) WARN (EX2565) : Input 'G[18]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":154) WARN (EX2565) : Input 'G[17]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":154) WARN (EX2565) : Input 'G[16]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":154) WARN (EX2565) : Input 'G[15]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":154) WARN (EX2565) : Input 'G[14]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":154) WARN (EX2565) : Input 'G[13]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":154) WARN (EX2565) : Input 'G[12]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":154) WARN (EX2565) : Input 'G[11]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":154) WARN (EX2565) : Input 'G[10]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":154) WARN (EX2565) : Input 'G[9]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":154) WARN (EX2565) : Input 'G[8]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":154) WARN (EX2565) : Input 'G[7]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":154) WARN (EX2565) : Input 'G[6]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":154) WARN (EX2565) : Input 'G[5]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":154) WARN (EX2565) : Input 'G[4]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":154) WARN (EX2565) : Input 'G[3]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":154) WARN (EX2565) : Input 'G[2]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":154) WARN (EX2565) : Input 'G[1]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":154) WARN (EX2565) : Input 'G[0]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":154) WARN (EX2565) : Input 'H[31]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":154) WARN (EX2565) : Input 'H[30]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":154) WARN (EX2565) : Input 'H[29]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":154) WARN (EX2565) : Input 'H[28]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":154) WARN (EX2565) : Input 'H[27]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":154) WARN (EX2565) : Input 'H[26]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":154) WARN (EX2565) : Input 'H[25]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":154) WARN (EX2565) : Input 'H[24]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":154) WARN (EX2565) : Input 'H[23]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":154) WARN (EX2565) : Input 'H[22]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":154) WARN (EX2565) : Input 'H[21]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":154) WARN (EX2565) : Input 'H[20]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":154) WARN (EX2565) : Input 'H[19]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":154) WARN (EX2565) : Input 'H[18]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":154) WARN (EX2565) : Input 'H[17]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":154) WARN (EX2565) : Input 'H[16]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":154) WARN (EX2565) : Input 'H[15]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":154) WARN (EX2565) : Input 'H[14]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":154) WARN (EX2565) : Input 'H[13]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":154) WARN (EX2565) : Input 'H[12]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":154) WARN (EX2565) : Input 'H[11]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":154) WARN (EX2565) : Input 'H[10]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":154) WARN (EX2565) : Input 'H[9]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":154) WARN (EX2565) : Input 'H[8]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":154) WARN (EX2565) : Input 'H[7]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":154) WARN (EX2565) : Input 'H[6]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":154) WARN (EX2565) : Input 'H[5]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":154) WARN (EX2565) : Input 'H[4]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":154) WARN (EX2565) : Input 'H[3]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":154) WARN (EX2565) : Input 'H[2]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":154) WARN (EX2565) : Input 'H[1]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":154) WARN (EX2565) : Input 'H[0]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":154) WARN (EX2565) : Input 'D[31]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'D[30]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'D[29]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'D[28]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'D[27]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'D[26]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'D[25]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'D[24]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'D[23]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'D[22]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'D[21]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'D[20]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'D[19]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'D[18]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'D[17]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'D[16]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'D[15]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'D[14]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'D[13]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'D[12]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'D[11]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'D[10]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'D[9]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'D[8]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'D[7]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'D[6]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'D[5]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'D[4]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'D[3]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'D[2]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'D[1]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'D[0]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'E[31]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'E[30]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'E[29]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'E[28]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'E[27]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'E[26]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'E[25]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'E[24]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'E[23]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'E[22]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'E[21]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'E[20]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'E[19]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'E[18]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'E[17]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'E[16]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'E[15]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'E[14]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'E[13]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'E[12]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'E[11]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'E[10]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'E[9]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'E[8]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'E[7]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'E[6]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'E[5]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'E[4]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'E[3]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'E[2]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'E[1]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'E[0]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'F[31]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'F[30]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'F[29]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'F[28]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'F[27]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'F[26]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'F[25]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'F[24]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'F[23]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'F[22]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'F[21]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'F[20]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'F[19]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'F[18]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'F[17]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'F[16]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'F[15]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'F[14]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'F[13]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'F[12]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'F[11]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'F[10]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'F[9]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'F[8]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'F[7]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'F[6]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'F[5]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'F[4]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'F[3]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'F[2]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'F[1]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'F[0]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'G[31]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'G[30]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'G[29]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'G[28]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'G[27]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'G[26]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'G[25]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'G[24]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'G[23]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'G[22]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'G[21]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'G[20]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'G[19]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'G[18]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'G[17]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'G[16]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'G[15]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'G[14]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'G[13]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'G[12]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'G[11]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'G[10]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'G[9]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'G[8]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'G[7]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'G[6]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'G[5]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'G[4]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'G[3]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'G[2]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'G[1]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'G[0]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'H[31]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'H[30]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'H[29]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'H[28]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'H[27]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'H[26]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'H[25]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'H[24]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'H[23]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'H[22]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'H[21]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'H[20]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'H[19]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'H[18]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'H[17]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'H[16]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'H[15]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'H[14]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'H[13]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'H[12]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'H[11]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'H[10]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'H[9]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'H[8]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'H[7]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'H[6]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'H[5]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'H[4]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'H[3]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'H[2]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'H[1]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'H[0]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":171) WARN (EX2565) : Input 'last_bits_saved_address[1]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":253) WARN (EX2565) : Input 'last_bits_saved_address[0]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":253) Compiling module 'Memory(MEMORY_FILE="../../software/memory/teste_uart_fpga.hex",MEMORY_SIZE=2048)'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v":1) Extracting RAM for identifier 'memory'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v":16) Compiling module 'BUS'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/bus.v":1) Compiling module 'LEDs'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/leds.v":5) Compiling module 'UART(CLK_FREQ=27000000,BIT_RATE=115200,BUFFER_SIZE=16)'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart.v":4) Compiling module 'FIFO(DEPTH=16)'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/fifo.v":4) Extracting RAM for identifier 'memory'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/fifo.v":19) WARN (EX3791) : Expression size 7 truncated to fit in target size 6("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/fifo.v":43) Compiling module 'uart_tool_rx(BIT_RATE=115200,CLK_HZ=27000000)'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_rx.v":13) Compiling module 'uart_tool_tx(BIT_RATE=115200,CLK_HZ=27000000)'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_tx.v":13) Compiling module 'GPIOS(WIDHT=5)'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":4) Compiling module 'GPIO'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpio.v":5) Compiling module 'PWM'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/pwm.v":5) 24.23.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 24.23.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 24.23.16. Finished OPT passes. (There is nothing left to do.) 24.24. Executing MEMORY pass. 24.24.1. Executing OPT_MEM pass (optimize memories). Performed a total of 0 transformations. 24.24.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). Performed a total of 0 transformations. 24.24.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). Analyzing top.SOC.Core.RegisterBank.registers write port 0. Analyzing top.SOC.Core.RegisterBank.registers write port 1. Analyzing top.SOC.Core.RegisterBank.registers write port 2. Analyzing top.SOC.GPIOS.duty_cycle write port 0. Analyzing top.SOC.GPIOS.period write port 0. Analyzing top.SOC.Memory.memory write port 0. Analyzing top.SOC.Memory.memory write port 1. Analyzing top.SOC.Memory.memory write port 2. Analyzing top.SOC.Uart.RX_FIFO.memory write port 0. Analyzing top.SOC.Uart.TX_FIFO.memory write port 0. 24.24.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). 24.24.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). Checking read port `\SOC.Core.RegisterBank.registers'[0] in module `\top': merging output FF to cell. Write port 0: don't care on collision. Write port 1: non-transparent. Write port 2: non-transparent. Checking read port `\SOC.Core.RegisterBank.registers'[1] in module `\top': merging output FF to cell. Write port 0: don't care on collision. Write port 1: non-transparent. Write port 2: non-transparent. Checking read port `\SOC.GPIOS.duty_cycle'[0] in module `\top': no output FF found. Checking read port `\SOC.GPIOS.duty_cycle'[1] in module `\top': no output FF found. Checking read port `\SOC.GPIOS.period'[0] in module `\top': no output FF found. Checking read port `\SOC.GPIOS.period'[1] in module `\top': no output FF found. Checking read port `\SOC.Memory.memory'[0] in module `\top': no output FF found. Checking read port `\SOC.Uart.RX_FIFO.memory'[0] in module `\top': no output FF found. Checking read port `\SOC.Uart.TX_FIFO.memory'[0] in module `\top': merging output FF to cell. Write port 0: non-transparent. Checking read port address `\SOC.GPIOS.duty_cycle'[0] in module `\top': no address FF found. Checking read port address `\SOC.GPIOS.duty_cycle'[1] in module `\top': no address FF found. Checking read port address `\SOC.GPIOS.period'[0] in module `\top': no address FF found. Checking read port address `\SOC.GPIOS.period'[1] in module `\top': no address FF found. Checking read port address `\SOC.Memory.memory'[0] in module `\top': no address FF found. Checking read port address `\SOC.Uart.RX_FIFO.memory'[0] in module `\top': address FF has fully-defined init value, not supported. 24.24.6. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 3 unused cells and 78 unused wires. <suppressed ~10 debug messages> 24.24.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). Consolidating read ports of memory top.SOC.Core.RegisterBank.registers by address: Consolidating write ports of memory top.SOC.Core.RegisterBank.registers by address: Merging ports 0, 2 (address 5'00000). Consolidating write ports of memory top.SOC.Core.RegisterBank.registers by address: Consolidating read ports of memory top.SOC.GPIOS.duty_cycle by address: Merging ports 0, 1 (address 1'1). Consolidating read ports of memory top.SOC.GPIOS.period by address: Merging ports 0, 1 (address 1'1). Consolidating write ports of memory top.SOC.Memory.memory by address: Merging ports 0, 1 (address \SOC.GPIOS.address [6:2]). Merging ports 0, 2 (address \SOC.GPIOS.address [6:2]). Consolidating write ports of memory top.SOC.Core.RegisterBank.registers using sat-based resource sharing: Checking group clocked with posedge \clk, width 32: ports 0, 1. Common input cone for all EN signals: 11 cells. Size of unconstrained SAT problem: 89 variables, 233 clauses Merging port 1 into port 0. 24.24.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). Performed a total of 0 transformations. 24.24.9. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 8 unused cells and 10 unused wires. <suppressed ~9 debug messages> 24.24.10. Executing MEMORY_COLLECT pass (generating $mem cells). 24.25. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 24.26. Executing MEMORY_LIBMAP pass (mapping memories to cells). mapping memory top.SOC.Core.RegisterBank.registers via $__TRELLIS_DPR16X4_ Extracted data FF from read port 0 of top.SOC.Core.RegisterBank.registers: $\SOC.Core.RegisterBank.registers$rdreg[0] Extracted data FF from read port 1 of top.SOC.Core.RegisterBank.registers: $\SOC.Core.RegisterBank.registers$rdreg[1] using FF mapping for memory top.SOC.GPIOS.duty_cycle using FF mapping for memory top.SOC.GPIOS.period mapping memory top.SOC.Memory.memory via $__TRELLIS_DPR16X4_ mapping memory top.SOC.Uart.RX_FIFO.memory via $__TRELLIS_DPR16X4_ mapping memory top.SOC.Uart.TX_FIFO.memory via $__TRELLIS_DPR16X4_ Extracted data FF from read port 0 of top.SOC.Uart.TX_FIFO.memory: $\SOC.Uart.TX_FIFO.memory$rdreg[0] <suppressed ~2274 debug messages> 24.27. Executing TECHMAP pass (map to technology primitives). 24.27.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/lutrams_map.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/lutrams_map.v' to AST representation. Generating RTLIL representation for module `\$__TRELLIS_DPR16X4_'. Successfully finished Verilog frontend. 24.27.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/brams_map.v WARN (EX2565) : Input 'halt' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":45) WARN (EX2565) : Input 'interruption_request_external' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":45) WARN (EX2565) : Input 'interruption_request_timer' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":45) WARN (EX2565) : Input 'interruption_request_software' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":45) WARN (EX2565) : Input 'interruption_request_fast[15]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":45) WARN (EX2565) : Input 'interruption_request_fast[14]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":45) WARN (EX2565) : Input 'interruption_request_fast[13]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":45) WARN (EX2565) : Input 'interruption_request_fast[12]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":45) WARN (EX2565) : Input 'interruption_request_fast[11]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":45) WARN (EX2565) : Input 'interruption_request_fast[10]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":45) WARN (EX2565) : Input 'interruption_request_fast[9]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":45) WARN (EX2565) : Input 'interruption_request_fast[8]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":45) WARN (EX2565) : Input 'interruption_request_fast[7]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":45) WARN (EX2565) : Input 'interruption_request_fast[6]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":45) WARN (EX2565) : Input 'interruption_request_fast[5]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":45) WARN (EX2565) : Input 'interruption_request_fast[4]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":45) WARN (EX2565) : Input 'interruption_request_fast[3]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":45) WARN (EX2565) : Input 'interruption_request_fast[2]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":45) WARN (EX2565) : Input 'interruption_request_fast[1]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":45) WARN (EX2565) : Input 'interruption_request_fast[0]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":45) NOTE (EX0101) : Current top module is "top" [5%] Running netlist conversion ... WARN (CV0016) : Input reset is unused("/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/main.v":3) Running device independent optimization ... Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/brams_map.v' to AST representation. Generating RTLIL representation for module `\$__ECP5_DP16KD_'. Generating RTLIL representation for module `\$__ECP5_PDPW16KD_'. Successfully finished Verilog frontend. 24.27.3. Continuing TECHMAP pass. Using template $paramod$04778961cc1285a5efea28f98f28381eb2862208\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$15a30c0adea1773747fb1e5409402feaeb43e8db\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$29182684153f2fb5ebfb27a421b2c2469028f00f\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$514fc941ac1ae997c717a8e6a1180ed8e0cf8fa9\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$ad8eda0ac04584c80041382f18acc83bd7cf2460\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$f458c10c6c2555868d055fd78c4dddde09fb9ee6\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$794d4b3a9b67efbbe66bd5480f9e760642c9fd0f\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$401c6701ad06c89ced83dc458f3b90b7cc08ca12\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$e6e931acfb19b62a7006279f4af5899ed81aa39b\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$d7e07a2ca5f4ebc06480108dd0fbd70d117841a2\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$a5683bd256b1c48ab6324bd8811d61a4f852df7f\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$2222d9b7c61243c9bb79b209f46f9e0fe8e064a1\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$52ac46df0c79e47d52bcbca72d67a7d0abe0fc40\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$dd6769d6be4b97c08c655314d974b149d05ec29a\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$a286033e7753bc4ebe3b505fa5642ab810e63837\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$2981816adfcb6e17bcbba8ea14bfc7c9a6fe3086\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$4cba2198ec7ad230820532105d9be1af3b14d6ee\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$885f339e618a6d3e49342a71b24df65f08b7749f\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. No more expansions possible. <suppressed ~291 debug messages> 24.28. Executing OPT pass (performing simple optimizations). 24.28.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~199 debug messages> 24.28.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~6 debug messages> Removed a total of 2 cells. 24.28.3. Executing OPT_DFF pass (perform DFF optimizations). Adding SRST signal on $auto$ff.cc:266:slice$3073 ($dffe) from module top (D = $flatten\ResetBootSystem.$procmux$2352_Y, Q = \ResetBootSystem.counter, rval = 6'000000). 24.28.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 6 unused cells and 460 unused wires. <suppressed ~7 debug messages> 24.28.5. Rerunning OPT passes. (Removed registers in this run.) 24.28.6. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~3 debug messages> 24.28.7. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 24.28.8. Executing OPT_DFF pass (perform DFF optimizations). Adding SRST signal on $auto$ff.cc:266:slice$3613 ($sdffce) from module top (D = $auto$wreduce.cc:461:run$3096 [5:0], Q = \ResetBootSystem.counter, rval = 6'000000). 24.28.9. Executing OPT_CLEAN pass (remove unused cells and wires). [10%] Optimizing Phase 0 completed [15%] Optimizing Phase 1 completed Finding unused cells or wires in module \top.. Removed 5 unused cells and 5 unused wires. <suppressed ~6 debug messages> 24.28.10. Rerunning OPT passes. (Removed registers in this run.) 24.28.11. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 24.28.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 24.28.13. Executing OPT_DFF pass (perform DFF optimizations). 24.28.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 24.28.15. Finished fast OPT passes. 24.29. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). Mapping memory \SOC.GPIOS.duty_cycle in module \top: created 2 $dff cells and 0 static cells of width 16. read interface: 0 $dff and 0 $mux cells. write interface: 2 write mux blocks. Mapping memory \SOC.GPIOS.period in module \top: created 2 $dff cells and 0 static cells of width 16. read interface: 0 $dff and 0 $mux cells. write interface: 2 write mux blocks. 24.30. Executing OPT pass (performing simple optimizations). 24.30.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~2 debug messages> 24.30.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 24.30.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Replacing known input bits on port B of cell $auto$memory_share.cc:453:consolidate_wr_using_sat$3363: $auto$rtlil.cc:2489:ReduceOr$3357 -> 1'1 Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~66 debug messages> 24.30.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Consolidated identical input bits for $mux cell $auto$memory_share.cc:273:consolidate_wr_by_addr$3348: Old ports: A={ \SOC.Memory.buffer [31:16] \SOC.Core.register_data_2 [15:0] }, B=\SOC.Core.register_data_2, Y=$auto$rtlil.cc:2603:Mux$3349 New ports: A=\SOC.Memory.buffer [31:16], B=\SOC.Core.register_data_2 [31:16], Y=$auto$rtlil.cc:2603:Mux$3349 [31:16] New connections: $auto$rtlil.cc:2603:Mux$3349 [15:0] = \SOC.Core.register_data_2 [15:0] New ctrl vector for $pmux cell $flatten\ResetBootSystem.$procmux$2361: { $flatten\ResetBootSystem.$procmux$2356_CMP $flatten\ResetBootSystem.$procmux$2355_CMP } Consolidated identical input bits for $mux cell $flatten\ResetBootSystem.$procmux$2364: Old ports: A=2'00, B=2'10, Y=$flatten\ResetBootSystem.$procmux$2364_Y New ports: A=1'0, B=1'1, Y=$flatten\ResetBootSystem.$procmux$2364_Y [1] New connections: $flatten\ResetBootSystem.$procmux$2364_Y [0] = 1'0 Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\ALU_Control.$procmux$2651: Old ports: A=4'1001, B=4'0011, Y=$flatten\SOC.\Core.\ALU_Control.$procmux$2651_Y New ports: A=2'10, B=2'01, Y={ $flatten\SOC.\Core.\ALU_Control.$procmux$2651_Y [3] $flatten\SOC.\Core.\ALU_Control.$procmux$2651_Y [1] } New connections: { $flatten\SOC.\Core.\ALU_Control.$procmux$2651_Y [2] $flatten\SOC.\Core.\ALU_Control.$procmux$2651_Y [0] } = 2'01 Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\ALU_Control.$procmux$2659: Old ports: A=3'010, B=3'110, Y=$auto$wreduce.cc:461:run$3097 [2:0] New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:461:run$3097 [2] New connections: $auto$wreduce.cc:461:run$3097 [1:0] = 2'10 Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2490: Old ports: A=2'00, B=2'10, Y=\SOC.Core.lorD New ports: A=1'0, B=1'1, Y=\SOC.Core.lorD [1] New connections: \SOC.Core.lorD [0] = 1'0 Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2536: Old ports: A=3'101, B=3'000, Y=$auto$wreduce.cc:461:run$3104 [2:0] New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$3104 [0] New connections: $auto$wreduce.cc:461:run$3104 [2:1] = { $auto$wreduce.cc:461:run$3104 [0] 1'0 } Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2554: Old ports: A=3'011, B=3'100, Y=$auto$wreduce.cc:461:run$3103 [2:0] New ports: A=2'01, B=2'10, Y={ $auto$wreduce.cc:461:run$3103 [2] $auto$wreduce.cc:461:run$3103 [0] } New connections: $auto$wreduce.cc:461:run$3103 [1] = $auto$wreduce.cc:461:run$3103 [0] Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2573: Old ports: A=3'101, B=3'011, Y=$auto$wreduce.cc:461:run$3102 [2:0] New ports: A=2'10, B=2'01, Y=$auto$wreduce.cc:461:run$3102 [2:1] New connections: $auto$wreduce.cc:461:run$3102 [0] = 1'1 Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2624: Old ports: A=6'000000, B=6'101110, Y=$flatten\SOC.\Core.\Control_Unit.$2\nextstate[5:0] New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Core.\Control_Unit.$2\nextstate[5:0] [1] New connections: { $flatten\SOC.\Core.\Control_Unit.$2\nextstate[5:0] [5:2] $flatten\SOC.\Core.\Control_Unit.$2\nextstate[5:0] [0] } = { $flatten\SOC.\Core.\Control_Unit.$2\nextstate[5:0] [1] 1'0 $flatten\SOC.\Core.\Control_Unit.$2\nextstate[5:0] [1] $flatten\SOC.\Core.\Control_Unit.$2\nextstate[5:0] [1] 1'0 } Consolidated identical input bits for $pmux cell $flatten\SOC.\Core.\Immediate_Generator.$procmux$2326: Old ports: A={ \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31:20] }, B={ \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24:20] 20'00000000000000000000 \SOC.Core.instruction_register [31:20] 27'000000000000000000000000000 \SOC.Core.instruction_register [24:20] }, Y=$flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] New ports: A={ \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31:25] }, B={ \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] 1'0 \SOC.Core.instruction_register [31:25] 8'00000000 }, Y=$flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12:5] New connections: { $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [31:13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [4:0] } = { $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] \SOC.Core.instruction_register [24:20] } Consolidated identical input bits for $pmux cell $flatten\SOC.\Memory.$procmux$1717: Old ports: A=\SOC.Memory.buffer, B={ \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7:0] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15:0] 24'000000000000000000000000 \SOC.Memory.buffer [7:0] 16'0000000000000000 \SOC.Memory.buffer [15:0] }, Y=\SOC.Bus.slave_0_read_data New ports: A=\SOC.Memory.buffer [31:8], B={ \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15:8] 40'0000000000000000000000000000000000000000 \SOC.Memory.buffer [15:8] }, Y=\SOC.Bus.slave_0_read_data [31:8] New connections: \SOC.Bus.slave_0_read_data [7:0] = \SOC.Memory.buffer [7:0] New ctrl vector for $pmux cell $flatten\SOC.\Uart.$procmux$1991: $auto$opt_reduce.cc:134:opt_pmux$3648 New ctrl vector for $pmux cell $flatten\SOC.\Uart.$procmux$2005: { $flatten\SOC.\Uart.$procmux$1999_CMP $flatten\SOC.\Uart.$procmux$1941_CMP $auto$opt_reduce.cc:134:opt_pmux$3650 $flatten\SOC.\Uart.$procmux$1922_Y } Consolidated identical input bits for $pmux cell $flatten\SOC.\Uart.$procmux$2022: Old ports: A=4'0001, B=16'0110011110001001, Y=$flatten\SOC.\Uart.$procmux$2022_Y New ports: A=3'001, B=12'010011100101, Y={ $flatten\SOC.\Uart.$procmux$2022_Y [3] $flatten\SOC.\Uart.$procmux$2022_Y [1:0] } New connections: $flatten\SOC.\Uart.$procmux$2022_Y [2] = $flatten\SOC.\Uart.$procmux$2022_Y [1] Consolidated identical input bits for $pmux cell $flatten\SOC.\Uart.\i_uart_rx.$procmux$1573: Old ports: A=3'000, B={ 2'00 $auto$wreduce.cc:461:run$3123 [0] 1'0 $auto$wreduce.cc:461:run$3124 [1:0] 2'01 \SOC.Uart.i_uart_rx.payload_done 1'0 $auto$wreduce.cc:461:run$3126 [1:0] }, Y=\SOC.Uart.i_uart_rx.n_fsm_state New ports: A=2'00, B={ 1'0 $auto$wreduce.cc:461:run$3123 [0] $auto$wreduce.cc:461:run$3124 [1:0] 1'1 \SOC.Uart.i_uart_rx.payload_done $auto$wreduce.cc:461:run$3126 [1:0] }, Y=\SOC.Uart.i_uart_rx.n_fsm_state [1:0] New connections: \SOC.Uart.i_uart_rx.n_fsm_state [2] = 1'0 Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:116$1367: Old ports: A=2'11, B=2'00, Y=$auto$wreduce.cc:461:run$3126 [1:0] New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$3126 [0] New connections: $auto$wreduce.cc:461:run$3126 [1] = $auto$wreduce.cc:461:run$3126 [0] Consolidated identical input bits for $pmux cell $flatten\SOC.\Uart.\i_uart_tx.$procmux$1710: Old ports: A=3'000, B={ 2'00 \SOC.Uart.uart_tx_en 1'0 $auto$wreduce.cc:461:run$3129 [1:0] 2'01 \SOC.Uart.i_uart_tx.payload_done 1'0 $auto$wreduce.cc:461:run$3127 [1:0] }, Y=\SOC.Uart.i_uart_tx.n_fsm_state New ports: A=2'00, B={ 1'0 \SOC.Uart.uart_tx_en $auto$wreduce.cc:461:run$3129 [1:0] 1'1 \SOC.Uart.i_uart_tx.payload_done $auto$wreduce.cc:461:run$3127 [1:0] }, Y=\SOC.Uart.i_uart_tx.n_fsm_state [1:0] New connections: \SOC.Uart.i_uart_tx.n_fsm_state [2] = 1'0 Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:100$1310: Old ports: A=2'11, B=2'00, Y=$auto$wreduce.cc:461:run$3127 [1:0] New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$3127 [0] New connections: $auto$wreduce.cc:461:run$3127 [1] = $auto$wreduce.cc:461:run$3127 [0] New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_pmux$3649: { $flatten\SOC.\Uart.$procmux$1969_CMP $flatten\SOC.\Uart.$procmux$1968_CMP $flatten\SOC.\Uart.$procmux$1967_CMP $flatten\SOC.\Uart.$procmux$1966_CMP $flatten\SOC.\Uart.$procmux$1916_CMP $flatten\SOC.\Uart.$procmux$1897_CMP } Optimizing cells in module \top. Consolidated identical input bits for $mux cell $auto$memory_share.cc:273:consolidate_wr_by_addr$3352: Old ports: A=$auto$rtlil.cc:2603:Mux$3349, B={ \SOC.Memory.buffer [31:8] \SOC.Core.register_data_2 [7:0] }, Y=$auto$rtlil.cc:2603:Mux$3353 New ports: A={ $auto$rtlil.cc:2603:Mux$3349 [31:16] \SOC.Core.register_data_2 [15:8] }, B=\SOC.Memory.buffer [31:8], Y=$auto$rtlil.cc:2603:Mux$3353 [31:8] New connections: $auto$rtlil.cc:2603:Mux$3353 [7:0] = \SOC.Core.register_data_2 [7:0] Consolidated identical input bits for $mux cell $flatten\ResetBootSystem.$procmux$2370: Old ports: A=2'00, B=$flatten\ResetBootSystem.$procmux$2364_Y, Y=$flatten\ResetBootSystem.$procmux$2370_Y New ports: A=1'0, B=$flatten\ResetBootSystem.$procmux$2364_Y [1], Y=$flatten\ResetBootSystem.$procmux$2370_Y [1] New connections: $flatten\ResetBootSystem.$procmux$2370_Y [0] = 1'0 Consolidated identical input bits for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2630: Old ports: A=6'000000, B={ $flatten\SOC.\Core.\Control_Unit.$2\nextstate[5:0] 8'00000100 $auto$wreduce.cc:461:run$3101 [3:0] 3'000 $auto$wreduce.cc:461:run$3102 [2:0] 3'000 $auto$wreduce.cc:461:run$3103 [2:0] 3'000 $auto$wreduce.cc:461:run$3104 [2:0] 12'001011000111 }, Y=\SOC.Core.Control_Unit.nextstate New ports: A=5'00000, B={ $flatten\SOC.\Core.\Control_Unit.$2\nextstate[5:0] [1] $flatten\SOC.\Core.\Control_Unit.$2\nextstate[5:0] [1] $flatten\SOC.\Core.\Control_Unit.$2\nextstate[5:0] [1] $flatten\SOC.\Core.\Control_Unit.$2\nextstate[5:0] [1] 7'0000010 $auto$wreduce.cc:461:run$3101 [3:0] 2'00 $auto$wreduce.cc:461:run$3102 [2:1] 3'100 $auto$wreduce.cc:461:run$3103 [2] $auto$wreduce.cc:461:run$3103 [0] $auto$wreduce.cc:461:run$3103 [0] 2'00 $auto$wreduce.cc:461:run$3104 [0] 1'0 $auto$wreduce.cc:461:run$3104 [0] 10'0101100111 }, Y={ \SOC.Core.Control_Unit.nextstate [5] \SOC.Core.Control_Unit.nextstate [3:0] } New connections: \SOC.Core.Control_Unit.nextstate [4] = 1'0 Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.$procmux$2027: Old ports: A=4'0000, B=$flatten\SOC.\Uart.$procmux$2022_Y, Y=$flatten\SOC.\Uart.$procmux$2027_Y New ports: A=3'000, B={ $flatten\SOC.\Uart.$procmux$2022_Y [3] $flatten\SOC.\Uart.$procmux$2022_Y [1:0] }, Y={ $flatten\SOC.\Uart.$procmux$2027_Y [3] $flatten\SOC.\Uart.$procmux$2027_Y [1:0] } New connections: $flatten\SOC.\Uart.$procmux$2027_Y [2] = $flatten\SOC.\Uart.$procmux$2027_Y [1] Optimizing cells in module \top. Performed a total of 27 changes. 24.30.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~3 debug messages> Removed a total of 1 cells. 24.30.6. Executing OPT_DFF pass (perform DFF optimizations). Adding SRST signal on $auto$ff.cc:266:slice$3012 ($dffe) from module top (D = $flatten\SOC.\Uart.$add$Risco-5/src/peripheral/uart.v:102$1239_Y, Q = \SOC.Uart.counter, rval = 3'000). 24.30.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 2 unused cells and 8 unused wires. <suppressed ~3 debug messages> 24.30.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~5 debug messages> 24.30.9. Rerunning OPT passes. (Maybe there is more to do..) 24.30.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~67 debug messages> 24.30.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 24.30.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 24.30.13. Executing OPT_DFF pass (perform DFF optimizations). Adding EN signal on $memory\SOC.GPIOS.period[1]$3637 ($dff) from module top (D = \SOC.Core.register_data_2 [15:0], Q = \SOC.GPIOS.period[1]). Adding EN signal on $memory\SOC.GPIOS.period[0]$3635 ($dff) from module top (D = \SOC.Core.register_data_2 [15:0], Q = \SOC.GPIOS.period[0]). Adding EN signal on $memory\SOC.GPIOS.duty_cycle[1]$3621 ($dff) from module top (D = \SOC.Core.register_data_2 [15:0], Q = \SOC.GPIOS.duty_cycle[1]). Adding EN signal on $memory\SOC.GPIOS.duty_cycle[0]$3619 ($dff) from module top (D = \SOC.Core.register_data_2 [15:0], Q = \SOC.GPIOS.duty_cycle[0]). Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$2922 ($sdff) from module top. Setting constant 0-bit at position 4 on $auto$ff.cc:266:slice$3064 ($sdff) from module top. 24.30.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 5 unused cells and 6 unused wires. <suppressed ~6 debug messages> 24.30.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~3 debug messages> 24.30.16. Rerunning OPT passes. (Maybe there is more to do..) 24.30.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~63 debug messages> 24.30.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 24.30.19. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 24.30.20. Executing OPT_DFF pass (perform DFF optimizations). [25%] Optimizing Phase 2 completed Running inference ... [30%] Inferring Phase 0 completed [40%] Inferring Phase 1 completed [50%] Inferring Phase 2 completed [55%] Inferring Phase 3 completed Running technical mapping ... 24.30.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 24.30.22. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 24.30.23. Finished OPT passes. (There is nothing left to do.) 24.31. Executing TECHMAP pass (map to technology primitives). 24.31.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/techmap.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu_brent_kung'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `\$__div_mod_u'. Generating RTLIL representation for module `\$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `\$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_pmux'. Generating RTLIL representation for module `\_90_demux'. Generating RTLIL representation for module `\_90_lut'. Successfully finished Verilog frontend. 24.31.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v' to AST representation. Generating RTLIL representation for module `\_80_ecp5_alu'. Successfully finished Verilog frontend. 24.31.3. Continuing TECHMAP pass. Using extmapper simplemap for cells of type $not. Using extmapper simplemap for cells of type $reduce_or. Using extmapper simplemap for cells of type $sdffce. Using extmapper simplemap for cells of type $sdff. Using extmapper simplemap for cells of type $dffe. Using extmapper simplemap for cells of type $mux. Using template $paramod$521ce43182eecb9f60c72393a788160d2c356bf5\_90_pmux for cells of type $pmux. Using extmapper simplemap for cells of type $eq. Using extmapper simplemap for cells of type $logic_not. Using extmapper simplemap for cells of type $reduce_bool. Using template $paramod$32efbfac1c4dc57230cf86180788fdfd12e3b511\_80_ecp5_alu for cells of type $alu. Using template $paramod$54d740639e1393b22262823179ff783ea9f17a35\_90_pmux for cells of type $pmux. Using template $paramod$645fe0cc96ae5edb83bff90cc2c78f4a20ca3e3c\_90_pmux for cells of type $pmux. Using template $paramod$49f1dc3dcd6d2c748486fe94c6744a34a19bbafe\_90_pmux for cells of type $pmux. Using template $paramod$8fabc56b80a569262acfc42757a02ca0b8e91278\_90_pmux for cells of type $pmux. Using template $paramod$fbc7873bff55778c0b3173955b7e4bce1d9d6834\_80_ecp5_alu for cells of type $alu. Using extmapper simplemap for cells of type $reduce_and. Using extmapper simplemap for cells of type $ne. Using extmapper simplemap for cells of type $or. Using template $paramod$824a2ca00d29d886599434cf8ea60471635f2955\_90_demux for cells of type $demux. Using extmapper simplemap for cells of type $dff. Using template $paramod$2bd81f420048247ff6903399c560fe0f8bd48ccc\_80_ecp5_alu for cells of type $alu. Using extmapper simplemap for cells of type $and. Using extmapper simplemap for cells of type $sdffe. Using template $paramod$e04283ca12514baf3d204c6994bec8f178dd89f8\_80_ecp5_alu for cells of type $alu. Using template $paramod$6a42b6fefed750f8a1c58eab59479d960557103c\_80_ecp5_alu for cells of type $alu. Using template $paramod$3ef7d3dd227da7627a99c5e5a6a4deb817573e39\_90_alu for cells of type $alu. Using extmapper simplemap for cells of type $tribuf. Using extmapper simplemap for cells of type $logic_and. Using template $paramod$b098bc6f249c0ac91c4d6e19d54b23c285914115\_90_pmux for cells of type $pmux. Using template $paramod$20d3ee62d72123142eb855d7ddafd835e31ba009\_90_pmux for cells of type $pmux. Using template $paramod$d31bf4d7d72e59528d18fbd4f322e9d608532043\_90_pmux for cells of type $pmux. Using template $paramod$a04dd9d4d8b430140c4ff94b50470fb380fda2a0\_80_ecp5_alu for cells of type $alu. Using template $paramod$32a7b7b86c07519b7537abc18e96f0331f97914d\_90_alu for cells of type $alu. Using template $paramod$068ad458e7761d78e5eed8238508872e7b0aef95\_90_pmux for cells of type $pmux. Using extmapper simplemap for cells of type $logic_or. Using template $paramod$53700bbee849b2010ad0b60a61ccd204a10e24ca\_80_ecp5_alu for cells of type $alu. Using template $paramod$19e9557905baa9d3741d0daa66e2ef076e9bab7d\_90_pmux for cells of type $pmux. Using template $paramod$4d45682f6d5f8751d24fc75184ef72226da353f7\_90_pmux for cells of type $pmux. Using template $paramod$f587f97d3019cb6509bb9d96ec321cde2ec5fd64\_90_pmux for cells of type $pmux. Using template $paramod$97565c3687be688407d1272a293bd9d0ae6852dc\_90_pmux for cells of type $pmux. Using template $paramod$95ab7b964273918a033d1324366ecc612d202989\_90_pmux for cells of type $pmux. Using template $paramod$33afdd83bf3811dac2de7a968d39eea5718691bc\_90_pmux for cells of type $pmux. Using template $paramod$bf2533632d512eac76dd186c0da49367e29b8e98\_90_pmux for cells of type $pmux. Using template $paramod$constmap:4621fcf06a436d1e2a4080e2ed9866a7d07a6e07$paramod$5180471e6f22625c8e3c4261cd538e11648586b5\_90_shift_ops_shr_shl_sshl_sshr for cells of type $sshr. Using template $paramod$constmap:4621fcf06a436d1e2a4080e2ed9866a7d07a6e07$paramod$feecc7a0dbd012970970f2858f15e786e251f677\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shr. Using template $paramod$constmap:4621fcf06a436d1e2a4080e2ed9866a7d07a6e07$paramod$335cfd09f1afa8139c4aafcbbe5f361887b79c5e\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl. Using template $paramod$ed6389a5938b09f91843a91d67becca5abedb1bd\_90_pmux for cells of type $pmux. Using extmapper simplemap for cells of type $xor. Using extmapper simplemap for cells of type $pos. Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000100 for cells of type $lcu. Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000011 for cells of type $lcu. No more expansions possible. <suppressed ~3663 debug messages> 24.32. Executing OPT pass (performing simple optimizations). 24.32.1. Executing OPT_EXPR pass (perform const folding). [60%] Tech-Mapping Phase 0 completed [65%] Tech-Mapping Phase 1 completed [75%] Tech-Mapping Phase 2 completed Optimizing module top. <suppressed ~2760 debug messages> 24.32.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~2937 debug messages> Removed a total of 979 cells. 24.32.3. Executing OPT_DFF pass (perform DFF optimizations). 24.32.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 352 unused cells and 2939 unused wires. <suppressed ~353 debug messages> 24.32.5. Finished fast OPT passes. 24.33. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 24.34. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). 24.35. Executing TECHMAP pass (map to technology primitives). 24.35.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v' to AST representation. Generating RTLIL representation for module `\$_DFF_N_'. Generating RTLIL representation for module `\$_DFF_P_'. Generating RTLIL representation for module `\$_DFFE_NN_'. Generating RTLIL representation for module `\$_DFFE_PN_'. Generating RTLIL representation for module `\$_DFFE_NP_'. Generating RTLIL representation for module `\$_DFFE_PP_'. Generating RTLIL representation for module `\$_DFF_NP0_'. Generating RTLIL representation for module `\$_DFF_NP1_'. Generating RTLIL representation for module `\$_DFF_PP0_'. Generating RTLIL representation for module `\$_DFF_PP1_'. Generating RTLIL representation for module `\$_SDFF_NP0_'. Generating RTLIL representation for module `\$_SDFF_NP1_'. Generating RTLIL representation for module `\$_SDFF_PP0_'. Generating RTLIL representation for module `\$_SDFF_PP1_'. Generating RTLIL representation for module `\$_DFFE_NP0P_'. Generating RTLIL representation for module `\$_DFFE_NP1P_'. Generating RTLIL representation for module `\$_DFFE_PP0P_'. Generating RTLIL representation for module `\$_DFFE_PP1P_'. Generating RTLIL representation for module `\$_DFFE_NP0N_'. Generating RTLIL representation for module `\$_DFFE_NP1N_'. Generating RTLIL representation for module `\$_DFFE_PP0N_'. Generating RTLIL representation for module `\$_DFFE_PP1N_'. Generating RTLIL representation for module `\$_SDFFE_NP0P_'. Generating RTLIL representation for module `\$_SDFFE_NP1P_'. Generating RTLIL representation for module `\$_SDFFE_PP0P_'. Generating RTLIL representation for module `\$_SDFFE_PP1P_'. Generating RTLIL representation for module `\$_SDFFE_NP0N_'. Generating RTLIL representation for module `\$_SDFFE_NP1N_'. Generating RTLIL representation for module `\$_SDFFE_PP0N_'. Generating RTLIL representation for module `\$_SDFFE_PP1N_'. Generating RTLIL representation for module `\$_ALDFF_NP_'. Generating RTLIL representation for module `\$_ALDFF_PP_'. Generating RTLIL representation for module `\$_ALDFFE_NPN_'. Generating RTLIL representation for module `\$_ALDFFE_NPP_'. Generating RTLIL representation for module `\$_ALDFFE_PPN_'. Generating RTLIL representation for module `\$_ALDFFE_PPP_'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Successfully finished Verilog frontend. 24.35.2. Continuing TECHMAP pass. Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'0 for cells of type $_DFFE_PP_. Using template \$_SDFFE_PP0P_ for cells of type $_SDFFE_PP0P_. Using template \$_SDFF_PP1_ for cells of type $_SDFF_PP1_. Using template \$_SDFFE_PP0N_ for cells of type $_SDFFE_PP0N_. Using template \$_SDFF_PP0_ for cells of type $_SDFF_PP0_. Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFFE_PP_. Using template $paramod\$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_. Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'1 for cells of type $_DFFE_PP_. Using template \$_SDFFE_PP1P_ for cells of type $_SDFFE_PP1P_. Using template $paramod\$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'0 for cells of type $_DFF_P_. No more expansions possible. <suppressed ~737 debug messages> 24.36. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 24.37. Executing SIMPLEMAP pass (map simple cells to gate primitives). 24.38. Executing LATTICE_GSR pass (implement FF init values). Handling GSR in top. 24.39. Executing ATTRMVCP pass (move or copy attributes). 24.40. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 3377 unused wires. <suppressed ~1 debug messages> 24.41. Executing TECHMAP pass (map to technology primitives). 24.41.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/latches_map.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/latches_map.v' to AST representation. Generating RTLIL representation for module `\$_DLATCH_N_'. Generating RTLIL representation for module `\$_DLATCH_P_'. Successfully finished Verilog frontend. 24.41.2. Continuing TECHMAP pass. No more expansions possible. <suppressed ~4 debug messages> 24.42. Executing ABC9 pass. 24.42.1. Executing ABC9_OPS pass (helper functions for ABC9). 24.42.2. Executing ABC9_OPS pass (helper functions for ABC9). 24.42.3. Executing PROC pass (convert processes to netlists). 24.42.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$15719'. Cleaned up 1 empty switch. 24.42.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$15720 in module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 24.42.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 24.42.3.4. Executing PROC_INIT pass (extract init attributes). 24.42.3.5. Executing PROC_ARST pass (detect async resets in processes). 24.42.3.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 24.42.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$15744'. Creating decoders for process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$15720'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$15718_EN[3:0]$15726 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$15718_DATA[3:0]$15725 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$15718_ADDR[3:0]$15724 Creating decoders for process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$15719'. 24.42.3.8. Executing PROC_DLATCH pass (convert process syncs to latches). 24.42.3.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$15702_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$15744'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$15703_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$15744'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$15707_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$15744'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$15708_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$15744'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$15712_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$15744'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$15704_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$15744'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$15713_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$15744'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.\i' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$15744'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$15717_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$15744'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$15709_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$15744'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$15714_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$15744'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$15710_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$15744'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$15705_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$15744'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$15715_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$15744'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$15716_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$15744'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$15711_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$15744'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$15706_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$15744'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$15718_ADDR' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$15720'. created $dff cell `$procdff$15770' with positive edge clock. Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$15718_DATA' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$15720'. created $dff cell `$procdff$15771' with positive edge clock. Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$15718_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$15720'. created $dff cell `$procdff$15772' with positive edge clock. Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.\muxwre' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$15719'. created direct connection (no actual register cell created). 24.42.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 24.42.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$15744'. Found and cleaned up 1 empty switch in `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$15720'. Removing empty process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$15719'. Cleaned up 1 empty switch. 24.42.3.12. Executing OPT_EXPR pass (perform const folding). 24.42.4. Executing PROC pass (convert processes to netlists). 24.42.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$15790'. Cleaned up 1 empty switch. 24.42.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$15791 in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 24.42.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 24.42.4.4. Executing PROC_INIT pass (extract init attributes). 24.42.4.5. Executing PROC_ARST pass (detect async resets in processes). 24.42.4.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 24.42.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$15815'. Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$15791'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$15789_EN[3:0]$15797 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$15789_DATA[3:0]$15796 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$15789_ADDR[3:0]$15795 Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$15790'. 24.42.4.8. Executing PROC_DLATCH pass (convert process syncs to latches). 24.42.4.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.\i' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$15815'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$15773_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$15815'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$15776_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$15815'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$15777_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$15815'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$15778_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$15815'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$15782_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$15815'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$15783_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$15815'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$15784_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$15815'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$15788_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$15815'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$15774_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$15815'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$15779_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$15815'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$15786_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$15815'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$15780_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$15815'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$15785_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$15815'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$15787_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$15815'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$15781_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$15815'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$15775_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$15815'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$15789_ADDR' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$15791'. created $dff cell `$procdff$15841' with positive edge clock. Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$15789_DATA' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$15791'. created $dff cell `$procdff$15842' with positive edge clock. Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$15789_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$15791'. created $dff cell `$procdff$15843' with positive edge clock. Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.\muxwre' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$15790'. created direct connection (no actual register cell created). 24.42.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 24.42.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$15815'. Found and cleaned up 1 empty switch in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$15791'. Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$15790'. Cleaned up 1 empty switch. 24.42.4.12. Executing OPT_EXPR pass (perform const folding). 24.42.5. Executing PROC pass (convert processes to netlists). 24.42.5.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$240b3d214c7091ed87f7feed01a813ca9ca1b727\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$15861'. Cleaned up 1 empty switch. 24.42.5.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$15862 in module $paramod$240b3d214c7091ed87f7feed01a813ca9ca1b727\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 24.42.5.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 24.42.5.4. Executing PROC_INIT pass (extract init attributes). 24.42.5.5. Executing PROC_ARST pass (detect async resets in processes). 24.42.5.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 24.42.5.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$240b3d214c7091ed87f7feed01a813ca9ca1b727\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$15886'. Creating decoders for process `$paramod$240b3d214c7091ed87f7feed01a813ca9ca1b727\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$15862'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$15860_EN[3:0]$15866 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$15860_DATA[3:0]$15868 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$15860_ADDR[3:0]$15867 Creating decoders for process `$paramod$240b3d214c7091ed87f7feed01a813ca9ca1b727\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$15861'. 24.42.5.8. Executing PROC_DLATCH pass (convert process syncs to latches). 24.42.5.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$240b3d214c7091ed87f7feed01a813ca9ca1b727\TRELLIS_DPR16X4.\i' using process `$paramod$240b3d214c7091ed87f7feed01a813ca9ca1b727\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$15886'. created direct connection (no actual register cell created). Creating register for signal `$paramod$240b3d214c7091ed87f7feed01a813ca9ca1b727\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$15844_EN' using process `$paramod$240b3d214c7091ed87f7feed01a813ca9ca1b727\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$15886'. created direct connection (no actual register cell created). Creating register for signal `$paramod$240b3d214c7091ed87f7feed01a813ca9ca1b727\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$15845_EN' using process `$paramod$240b3d214c7091ed87f7feed01a813ca9ca1b727\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$15886'. created direct connection (no actual register cell created). Creating register for signal `$paramod$240b3d214c7091ed87f7feed01a813ca9ca1b727\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$15846_EN' using process `$paramod$240b3d214c7091ed87f7feed01a813ca9ca1b727\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$15886'. created direct connection (no actual register cell created). Creating register for signal `$paramod$240b3d214c7091ed87f7feed01a813ca9ca1b727\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$15847_EN' using process `$paramod$240b3d214c7091ed87f7feed01a813ca9ca1b727\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$15886'. created direct connection (no actual register cell created). Creating register for signal `$paramod$240b3d214c7091ed87f7feed01a813ca9ca1b727\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$15851_EN' using process `$paramod$240b3d214c7091ed87f7feed01a813ca9ca1b727\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$15886'. created direct connection (no actual register cell created). Creating register for signal `$paramod$240b3d214c7091ed87f7feed01a813ca9ca1b727\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$15852_EN' using process `$paramod$240b3d214c7091ed87f7feed01a813ca9ca1b727\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$15886'. created direct connection (no actual register cell created). Creating register for signal `$paramod$240b3d214c7091ed87f7feed01a813ca9ca1b727\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$15856_EN' using process `$paramod$240b3d214c7091ed87f7feed01a813ca9ca1b727\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$15886'. created direct connection (no actual register cell created). Creating register for signal `$paramod$240b3d214c7091ed87f7feed01a813ca9ca1b727\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$15848_EN' using process `$paramod$240b3d214c7091ed87f7feed01a813ca9ca1b727\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$15886'. created direct connection (no actual register cell created). Creating register for signal `$paramod$240b3d214c7091ed87f7feed01a813ca9ca1b727\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$15857_EN' using process `$paramod$240b3d214c7091ed87f7feed01a813ca9ca1b727\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$15886'. created direct connection (no actual register cell created). Creating register for signal `$paramod$240b3d214c7091ed87f7feed01a813ca9ca1b727\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$15858_EN' using process `$paramod$240b3d214c7091ed87f7feed01a813ca9ca1b727\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$15886'. created direct connection (no actual register cell created). Creating register for signal `$paramod$240b3d214c7091ed87f7feed01a813ca9ca1b727\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$15854_EN' using process `$paramod$240b3d214c7091ed87f7feed01a813ca9ca1b727\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$15886'. created direct connection (no actual register cell created). Creating register for signal `$paramod$240b3d214c7091ed87f7feed01a813ca9ca1b727\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$15859_EN' using process `$paramod$240b3d214c7091ed87f7feed01a813ca9ca1b727\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$15886'. created direct connection (no actual register cell created). Creating register for signal `$paramod$240b3d214c7091ed87f7feed01a813ca9ca1b727\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$15849_EN' using process `$paramod$240b3d214c7091ed87f7feed01a813ca9ca1b727\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$15886'. created direct connection (no actual register cell created). Creating register for signal `$paramod$240b3d214c7091ed87f7feed01a813ca9ca1b727\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$15853_EN' using process `$paramod$240b3d214c7091ed87f7feed01a813ca9ca1b727\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$15886'. created direct connection (no actual register cell created). Creating register for signal `$paramod$240b3d214c7091ed87f7feed01a813ca9ca1b727\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$15855_EN' using process `$paramod$240b3d214c7091ed87f7feed01a813ca9ca1b727\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$15886'. created direct connection (no actual register cell created). Creating register for signal `$paramod$240b3d214c7091ed87f7feed01a813ca9ca1b727\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$15850_EN' using process `$paramod$240b3d214c7091ed87f7feed01a813ca9ca1b727\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$15886'. created direct connection (no actual register cell created). Creating register for signal `$paramod$240b3d214c7091ed87f7feed01a813ca9ca1b727\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$15860_EN' using process `$paramod$240b3d214c7091ed87f7feed01a813ca9ca1b727\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$15862'. created $dff cell `$procdff$15912' with positive edge clock. Creating register for signal `$paramod$240b3d214c7091ed87f7feed01a813ca9ca1b727\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$15860_ADDR' using process `$paramod$240b3d214c7091ed87f7feed01a813ca9ca1b727\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$15862'. created $dff cell `$procdff$15913' with positive edge clock. Creating register for signal `$paramod$240b3d214c7091ed87f7feed01a813ca9ca1b727\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$15860_DATA' using process `$paramod$240b3d214c7091ed87f7feed01a813ca9ca1b727\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$15862'. created $dff cell `$procdff$15914' with positive edge clock. Creating register for signal `$paramod$240b3d214c7091ed87f7feed01a813ca9ca1b727\TRELLIS_DPR16X4.\muxwre' using process `$paramod$240b3d214c7091ed87f7feed01a813ca9ca1b727\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$15861'. created direct connection (no actual register cell created). 24.42.5.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 24.42.5.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$240b3d214c7091ed87f7feed01a813ca9ca1b727\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$15886'. Found and cleaned up 1 empty switch in `$paramod$240b3d214c7091ed87f7feed01a813ca9ca1b727\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$15862'. Removing empty process `$paramod$240b3d214c7091ed87f7feed01a813ca9ca1b727\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$15861'. Cleaned up 1 empty switch. 24.42.5.12. Executing OPT_EXPR pass (perform const folding). 24.42.6. Executing PROC pass (convert processes to netlists). 24.42.6.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$54859518bee4eabb76b31063a8cd09e44ba7903d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$15932'. Cleaned up 1 empty switch. 24.42.6.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$15933 in module $paramod$54859518bee4eabb76b31063a8cd09e44ba7903d\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 24.42.6.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 24.42.6.4. Executing PROC_INIT pass (extract init attributes). 24.42.6.5. Executing PROC_ARST pass (detect async resets in processes). 24.42.6.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 24.42.6.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$54859518bee4eabb76b31063a8cd09e44ba7903d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$15957'. Creating decoders for process `$paramod$54859518bee4eabb76b31063a8cd09e44ba7903d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$15933'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$15931_EN[3:0]$15939 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$15931_DATA[3:0]$15938 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$15931_ADDR[3:0]$15937 Creating decoders for process `$paramod$54859518bee4eabb76b31063a8cd09e44ba7903d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$15932'. 24.42.6.8. Executing PROC_DLATCH pass (convert process syncs to latches). 24.42.6.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$54859518bee4eabb76b31063a8cd09e44ba7903d\TRELLIS_DPR16X4.\i' using process `$paramod$54859518bee4eabb76b31063a8cd09e44ba7903d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$15957'. created direct connection (no actual register cell created). Creating register for signal `$paramod$54859518bee4eabb76b31063a8cd09e44ba7903d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$15915_EN' using process `$paramod$54859518bee4eabb76b31063a8cd09e44ba7903d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$15957'. created direct connection (no actual register cell created). Creating register for signal `$paramod$54859518bee4eabb76b31063a8cd09e44ba7903d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$15916_EN' using process `$paramod$54859518bee4eabb76b31063a8cd09e44ba7903d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$15957'. created direct connection (no actual register cell created). Creating register for signal `$paramod$54859518bee4eabb76b31063a8cd09e44ba7903d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$15917_EN' using process `$paramod$54859518bee4eabb76b31063a8cd09e44ba7903d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$15957'. created direct connection (no actual register cell created). Creating register for signal `$paramod$54859518bee4eabb76b31063a8cd09e44ba7903d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$15920_EN' using process `$paramod$54859518bee4eabb76b31063a8cd09e44ba7903d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$15957'. created direct connection (no actual register cell created). Creating register for signal `$paramod$54859518bee4eabb76b31063a8cd09e44ba7903d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$15924_EN' using process `$paramod$54859518bee4eabb76b31063a8cd09e44ba7903d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$15957'. created direct connection (no actual register cell created). Creating register for signal `$paramod$54859518bee4eabb76b31063a8cd09e44ba7903d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$15925_EN' using process `$paramod$54859518bee4eabb76b31063a8cd09e44ba7903d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$15957'. created direct connection (no actual register cell created). Creating register for signal `$paramod$54859518bee4eabb76b31063a8cd09e44ba7903d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$15918_EN' using process `$paramod$54859518bee4eabb76b31063a8cd09e44ba7903d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$15957'. created direct connection (no actual register cell created). Creating register for signal `$paramod$54859518bee4eabb76b31063a8cd09e44ba7903d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$15926_EN' using process `$paramod$54859518bee4eabb76b31063a8cd09e44ba7903d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$15957'. created direct connection (no actual register cell created). Creating register for signal `$paramod$54859518bee4eabb76b31063a8cd09e44ba7903d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$15930_EN' using process `$paramod$54859518bee4eabb76b31063a8cd09e44ba7903d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$15957'. created direct connection (no actual register cell created). Creating register for signal `$paramod$54859518bee4eabb76b31063a8cd09e44ba7903d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$15921_EN' using process `$paramod$54859518bee4eabb76b31063a8cd09e44ba7903d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$15957'. created direct connection (no actual register cell created). Creating register for signal `$paramod$54859518bee4eabb76b31063a8cd09e44ba7903d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$15928_EN' using process `$paramod$54859518bee4eabb76b31063a8cd09e44ba7903d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$15957'. created direct connection (no actual register cell created). Creating register for signal `$paramod$54859518bee4eabb76b31063a8cd09e44ba7903d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$15929_EN' using process `$paramod$54859518bee4eabb76b31063a8cd09e44ba7903d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$15957'. created direct connection (no actual register cell created). Creating register for signal `$paramod$54859518bee4eabb76b31063a8cd09e44ba7903d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$15923_EN' using process `$paramod$54859518bee4eabb76b31063a8cd09e44ba7903d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$15957'. created direct connection (no actual register cell created). Creating register for signal `$paramod$54859518bee4eabb76b31063a8cd09e44ba7903d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$15919_EN' using process `$paramod$54859518bee4eabb76b31063a8cd09e44ba7903d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$15957'. created direct connection (no actual register cell created). Creating register for signal `$paramod$54859518bee4eabb76b31063a8cd09e44ba7903d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$15922_EN' using process `$paramod$54859518bee4eabb76b31063a8cd09e44ba7903d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$15957'. created direct connection (no actual register cell created). Creating register for signal `$paramod$54859518bee4eabb76b31063a8cd09e44ba7903d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$15927_EN' using process `$paramod$54859518bee4eabb76b31063a8cd09e44ba7903d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$15957'. created direct connection (no actual register cell created). Creating register for signal `$paramod$54859518bee4eabb76b31063a8cd09e44ba7903d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$15931_ADDR' using process `$paramod$54859518bee4eabb76b31063a8cd09e44ba7903d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$15933'. created $dff cell `$procdff$15983' with positive edge clock. Creating register for signal `$paramod$54859518bee4eabb76b31063a8cd09e44ba7903d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$15931_DATA' using process `$paramod$54859518bee4eabb76b31063a8cd09e44ba7903d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$15933'. created $dff cell `$procdff$15984' with positive edge clock. Creating register for signal `$paramod$54859518bee4eabb76b31063a8cd09e44ba7903d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$15931_EN' using process `$paramod$54859518bee4eabb76b31063a8cd09e44ba7903d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$15933'. created $dff cell `$procdff$15985' with positive edge clock. Creating register for signal `$paramod$54859518bee4eabb76b31063a8cd09e44ba7903d\TRELLIS_DPR16X4.\muxwre' using process `$paramod$54859518bee4eabb76b31063a8cd09e44ba7903d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$15932'. created direct connection (no actual register cell created). 24.42.6.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 24.42.6.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$54859518bee4eabb76b31063a8cd09e44ba7903d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$15957'. Found and cleaned up 1 empty switch in `$paramod$54859518bee4eabb76b31063a8cd09e44ba7903d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$15933'. Removing empty process `$paramod$54859518bee4eabb76b31063a8cd09e44ba7903d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$15932'. Cleaned up 1 empty switch. 24.42.6.12. Executing OPT_EXPR pass (perform const folding). 24.42.7. Executing PROC pass (convert processes to netlists). 24.42.7.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$c58b622e748098fb95d7cce3391b5b90d49d749c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$16003'. Cleaned up 1 empty switch. 24.42.7.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$16004 in module $paramod$c58b622e748098fb95d7cce3391b5b90d49d749c\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 24.42.7.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 24.42.7.4. Executing PROC_INIT pass (extract init attributes). 24.42.7.5. Executing PROC_ARST pass (detect async resets in processes). 24.42.7.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 24.42.7.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$c58b622e748098fb95d7cce3391b5b90d49d749c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16028'. Creating decoders for process `$paramod$c58b622e748098fb95d7cce3391b5b90d49d749c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$16004'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$16002_EN[3:0]$16010 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$16002_DATA[3:0]$16009 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$16002_ADDR[3:0]$16008 Creating decoders for process `$paramod$c58b622e748098fb95d7cce3391b5b90d49d749c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$16003'. 24.42.7.8. Executing PROC_DLATCH pass (convert process syncs to latches). 24.42.7.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$c58b622e748098fb95d7cce3391b5b90d49d749c\TRELLIS_DPR16X4.\i' using process `$paramod$c58b622e748098fb95d7cce3391b5b90d49d749c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16028'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c58b622e748098fb95d7cce3391b5b90d49d749c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$15996_EN' using process `$paramod$c58b622e748098fb95d7cce3391b5b90d49d749c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16028'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c58b622e748098fb95d7cce3391b5b90d49d749c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$15991_EN' using process `$paramod$c58b622e748098fb95d7cce3391b5b90d49d749c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16028'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c58b622e748098fb95d7cce3391b5b90d49d749c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$15995_EN' using process `$paramod$c58b622e748098fb95d7cce3391b5b90d49d749c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16028'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c58b622e748098fb95d7cce3391b5b90d49d749c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$15986_EN' using process `$paramod$c58b622e748098fb95d7cce3391b5b90d49d749c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16028'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c58b622e748098fb95d7cce3391b5b90d49d749c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$15987_EN' using process `$paramod$c58b622e748098fb95d7cce3391b5b90d49d749c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16028'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c58b622e748098fb95d7cce3391b5b90d49d749c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$15988_EN' using process `$paramod$c58b622e748098fb95d7cce3391b5b90d49d749c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16028'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c58b622e748098fb95d7cce3391b5b90d49d749c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$15992_EN' using process `$paramod$c58b622e748098fb95d7cce3391b5b90d49d749c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16028'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c58b622e748098fb95d7cce3391b5b90d49d749c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$15993_EN' using process `$paramod$c58b622e748098fb95d7cce3391b5b90d49d749c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16028'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c58b622e748098fb95d7cce3391b5b90d49d749c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$15997_EN' using process `$paramod$c58b622e748098fb95d7cce3391b5b90d49d749c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16028'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c58b622e748098fb95d7cce3391b5b90d49d749c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$15998_EN' using process `$paramod$c58b622e748098fb95d7cce3391b5b90d49d749c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16028'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c58b622e748098fb95d7cce3391b5b90d49d749c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$15989_EN' using process `$paramod$c58b622e748098fb95d7cce3391b5b90d49d749c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16028'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c58b622e748098fb95d7cce3391b5b90d49d749c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$15999_EN' using process `$paramod$c58b622e748098fb95d7cce3391b5b90d49d749c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16028'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c58b622e748098fb95d7cce3391b5b90d49d749c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$15994_EN' using process `$paramod$c58b622e748098fb95d7cce3391b5b90d49d749c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16028'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c58b622e748098fb95d7cce3391b5b90d49d749c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$15990_EN' using process `$paramod$c58b622e748098fb95d7cce3391b5b90d49d749c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16028'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c58b622e748098fb95d7cce3391b5b90d49d749c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16000_EN' using process `$paramod$c58b622e748098fb95d7cce3391b5b90d49d749c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16028'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c58b622e748098fb95d7cce3391b5b90d49d749c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16001_EN' using process `$paramod$c58b622e748098fb95d7cce3391b5b90d49d749c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16028'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c58b622e748098fb95d7cce3391b5b90d49d749c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$16002_ADDR' using process `$paramod$c58b622e748098fb95d7cce3391b5b90d49d749c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$16004'. created $dff cell `$procdff$16054' with positive edge clock. Creating register for signal `$paramod$c58b622e748098fb95d7cce3391b5b90d49d749c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$16002_DATA' using process `$paramod$c58b622e748098fb95d7cce3391b5b90d49d749c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$16004'. created $dff cell `$procdff$16055' with positive edge clock. Creating register for signal `$paramod$c58b622e748098fb95d7cce3391b5b90d49d749c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$16002_EN' using process `$paramod$c58b622e748098fb95d7cce3391b5b90d49d749c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$16004'. created $dff cell `$procdff$16056' with positive edge clock. Creating register for signal `$paramod$c58b622e748098fb95d7cce3391b5b90d49d749c\TRELLIS_DPR16X4.\muxwre' using process `$paramod$c58b622e748098fb95d7cce3391b5b90d49d749c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$16003'. created direct connection (no actual register cell created). 24.42.7.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 24.42.7.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$c58b622e748098fb95d7cce3391b5b90d49d749c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16028'. Found and cleaned up 1 empty switch in `$paramod$c58b622e748098fb95d7cce3391b5b90d49d749c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$16004'. Removing empty process `$paramod$c58b622e748098fb95d7cce3391b5b90d49d749c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$16003'. Cleaned up 1 empty switch. 24.42.7.12. Executing OPT_EXPR pass (perform const folding). 24.42.8. Executing PROC pass (convert processes to netlists). 24.42.8.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$4a126fa1688fbcbb97471f2a58f335ad46a1b683\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$16074'. Cleaned up 1 empty switch. 24.42.8.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$16075 in module $paramod$4a126fa1688fbcbb97471f2a58f335ad46a1b683\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 24.42.8.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 24.42.8.4. Executing PROC_INIT pass (extract init attributes). 24.42.8.5. Executing PROC_ARST pass (detect async resets in processes). 24.42.8.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 24.42.8.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$4a126fa1688fbcbb97471f2a58f335ad46a1b683\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16099'. Creating decoders for process `$paramod$4a126fa1688fbcbb97471f2a58f335ad46a1b683\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$16075'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$16073_EN[3:0]$16079 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$16073_DATA[3:0]$16080 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$16073_ADDR[3:0]$16081 Creating decoders for process `$paramod$4a126fa1688fbcbb97471f2a58f335ad46a1b683\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$16074'. 24.42.8.8. Executing PROC_DLATCH pass (convert process syncs to latches). 24.42.8.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$4a126fa1688fbcbb97471f2a58f335ad46a1b683\TRELLIS_DPR16X4.\i' using process `$paramod$4a126fa1688fbcbb97471f2a58f335ad46a1b683\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16099'. created direct connection (no actual register cell created). Creating register for signal `$paramod$4a126fa1688fbcbb97471f2a58f335ad46a1b683\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16072_EN' using process `$paramod$4a126fa1688fbcbb97471f2a58f335ad46a1b683\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16099'. created direct connection (no actual register cell created). Creating register for signal `$paramod$4a126fa1688fbcbb97471f2a58f335ad46a1b683\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16066_EN' using process `$paramod$4a126fa1688fbcbb97471f2a58f335ad46a1b683\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16099'. created direct connection (no actual register cell created). Creating register for signal `$paramod$4a126fa1688fbcbb97471f2a58f335ad46a1b683\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16060_EN' using process `$paramod$4a126fa1688fbcbb97471f2a58f335ad46a1b683\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16099'. created direct connection (no actual register cell created). Creating register for signal `$paramod$4a126fa1688fbcbb97471f2a58f335ad46a1b683\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16070_EN' using process `$paramod$4a126fa1688fbcbb97471f2a58f335ad46a1b683\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16099'. created direct connection (no actual register cell created). Creating register for signal `$paramod$4a126fa1688fbcbb97471f2a58f335ad46a1b683\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16065_EN' using process `$paramod$4a126fa1688fbcbb97471f2a58f335ad46a1b683\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16099'. created direct connection (no actual register cell created). Creating register for signal `$paramod$4a126fa1688fbcbb97471f2a58f335ad46a1b683\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16064_EN' using process `$paramod$4a126fa1688fbcbb97471f2a58f335ad46a1b683\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16099'. created direct connection (no actual register cell created). Creating register for signal `$paramod$4a126fa1688fbcbb97471f2a58f335ad46a1b683\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16059_EN' using process `$paramod$4a126fa1688fbcbb97471f2a58f335ad46a1b683\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16099'. created direct connection (no actual register cell created). Creating register for signal `$paramod$4a126fa1688fbcbb97471f2a58f335ad46a1b683\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16069_EN' using process `$paramod$4a126fa1688fbcbb97471f2a58f335ad46a1b683\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16099'. created direct connection (no actual register cell created). Creating register for signal `$paramod$4a126fa1688fbcbb97471f2a58f335ad46a1b683\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16058_EN' using process `$paramod$4a126fa1688fbcbb97471f2a58f335ad46a1b683\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16099'. created direct connection (no actual register cell created). Creating register for signal `$paramod$4a126fa1688fbcbb97471f2a58f335ad46a1b683\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16068_EN' using process `$paramod$4a126fa1688fbcbb97471f2a58f335ad46a1b683\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16099'. created direct connection (no actual register cell created). Creating register for signal `$paramod$4a126fa1688fbcbb97471f2a58f335ad46a1b683\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16067_EN' using process `$paramod$4a126fa1688fbcbb97471f2a58f335ad46a1b683\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16099'. created direct connection (no actual register cell created). Creating register for signal `$paramod$4a126fa1688fbcbb97471f2a58f335ad46a1b683\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16063_EN' using process `$paramod$4a126fa1688fbcbb97471f2a58f335ad46a1b683\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16099'. created direct connection (no actual register cell created). Creating register for signal `$paramod$4a126fa1688fbcbb97471f2a58f335ad46a1b683\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16061_EN' using process `$paramod$4a126fa1688fbcbb97471f2a58f335ad46a1b683\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16099'. created direct connection (no actual register cell created). Creating register for signal `$paramod$4a126fa1688fbcbb97471f2a58f335ad46a1b683\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16062_EN' using process `$paramod$4a126fa1688fbcbb97471f2a58f335ad46a1b683\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16099'. created direct connection (no actual register cell created). Creating register for signal `$paramod$4a126fa1688fbcbb97471f2a58f335ad46a1b683\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16057_EN' using process `$paramod$4a126fa1688fbcbb97471f2a58f335ad46a1b683\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16099'. created direct connection (no actual register cell created). Creating register for signal `$paramod$4a126fa1688fbcbb97471f2a58f335ad46a1b683\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16071_EN' using process `$paramod$4a126fa1688fbcbb97471f2a58f335ad46a1b683\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16099'. created direct connection (no actual register cell created). Creating register for signal `$paramod$4a126fa1688fbcbb97471f2a58f335ad46a1b683\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$16073_EN' using process `$paramod$4a126fa1688fbcbb97471f2a58f335ad46a1b683\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$16075'. created $dff cell `$procdff$16125' with positive edge clock. Creating register for signal `$paramod$4a126fa1688fbcbb97471f2a58f335ad46a1b683\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$16073_DATA' using process `$paramod$4a126fa1688fbcbb97471f2a58f335ad46a1b683\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$16075'. created $dff cell `$procdff$16126' with positive edge clock. Creating register for signal `$paramod$4a126fa1688fbcbb97471f2a58f335ad46a1b683\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$16073_ADDR' using process `$paramod$4a126fa1688fbcbb97471f2a58f335ad46a1b683\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$16075'. created $dff cell `$procdff$16127' with positive edge clock. Creating register for signal `$paramod$4a126fa1688fbcbb97471f2a58f335ad46a1b683\TRELLIS_DPR16X4.\muxwre' using process `$paramod$4a126fa1688fbcbb97471f2a58f335ad46a1b683\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$16074'. created direct connection (no actual register cell created). 24.42.8.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 24.42.8.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$4a126fa1688fbcbb97471f2a58f335ad46a1b683\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16099'. Found and cleaned up 1 empty switch in `$paramod$4a126fa1688fbcbb97471f2a58f335ad46a1b683\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$16075'. Removing empty process `$paramod$4a126fa1688fbcbb97471f2a58f335ad46a1b683\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$16074'. Cleaned up 1 empty switch. 24.42.8.12. Executing OPT_EXPR pass (perform const folding). 24.42.9. Executing PROC pass (convert processes to netlists). 24.42.9.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$3fea245e43c817e3ab409ba408c64d50b3c3410d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$16145'. Cleaned up 1 empty switch. 24.42.9.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$16146 in module $paramod$3fea245e43c817e3ab409ba408c64d50b3c3410d\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 24.42.9.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 24.42.9.4. Executing PROC_INIT pass (extract init attributes). 24.42.9.5. Executing PROC_ARST pass (detect async resets in processes). 24.42.9.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 24.42.9.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$3fea245e43c817e3ab409ba408c64d50b3c3410d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16170'. Creating decoders for process `$paramod$3fea245e43c817e3ab409ba408c64d50b3c3410d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$16146'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$16144_EN[3:0]$16150 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$16144_DATA[3:0]$16151 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$16144_ADDR[3:0]$16152 Creating decoders for process `$paramod$3fea245e43c817e3ab409ba408c64d50b3c3410d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$16145'. 24.42.9.8. Executing PROC_DLATCH pass (convert process syncs to latches). 24.42.9.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$3fea245e43c817e3ab409ba408c64d50b3c3410d\TRELLIS_DPR16X4.\i' using process `$paramod$3fea245e43c817e3ab409ba408c64d50b3c3410d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16170'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3fea245e43c817e3ab409ba408c64d50b3c3410d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16142_EN' using process `$paramod$3fea245e43c817e3ab409ba408c64d50b3c3410d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16170'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3fea245e43c817e3ab409ba408c64d50b3c3410d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16136_EN' using process `$paramod$3fea245e43c817e3ab409ba408c64d50b3c3410d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16170'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3fea245e43c817e3ab409ba408c64d50b3c3410d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16130_EN' using process `$paramod$3fea245e43c817e3ab409ba408c64d50b3c3410d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16170'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3fea245e43c817e3ab409ba408c64d50b3c3410d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16128_EN' using process `$paramod$3fea245e43c817e3ab409ba408c64d50b3c3410d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16170'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3fea245e43c817e3ab409ba408c64d50b3c3410d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16134_EN' using process `$paramod$3fea245e43c817e3ab409ba408c64d50b3c3410d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16170'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3fea245e43c817e3ab409ba408c64d50b3c3410d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16140_EN' using process `$paramod$3fea245e43c817e3ab409ba408c64d50b3c3410d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16170'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3fea245e43c817e3ab409ba408c64d50b3c3410d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16141_EN' using process `$paramod$3fea245e43c817e3ab409ba408c64d50b3c3410d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16170'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3fea245e43c817e3ab409ba408c64d50b3c3410d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16137_EN' using process `$paramod$3fea245e43c817e3ab409ba408c64d50b3c3410d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16170'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3fea245e43c817e3ab409ba408c64d50b3c3410d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16138_EN' using process `$paramod$3fea245e43c817e3ab409ba408c64d50b3c3410d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16170'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3fea245e43c817e3ab409ba408c64d50b3c3410d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16139_EN' using process `$paramod$3fea245e43c817e3ab409ba408c64d50b3c3410d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16170'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3fea245e43c817e3ab409ba408c64d50b3c3410d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16135_EN' using process `$paramod$3fea245e43c817e3ab409ba408c64d50b3c3410d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16170'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3fea245e43c817e3ab409ba408c64d50b3c3410d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16143_EN' using process `$paramod$3fea245e43c817e3ab409ba408c64d50b3c3410d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16170'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3fea245e43c817e3ab409ba408c64d50b3c3410d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16129_EN' using process `$paramod$3fea245e43c817e3ab409ba408c64d50b3c3410d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16170'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3fea245e43c817e3ab409ba408c64d50b3c3410d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16131_EN' using process `$paramod$3fea245e43c817e3ab409ba408c64d50b3c3410d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16170'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3fea245e43c817e3ab409ba408c64d50b3c3410d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16132_EN' using process `$paramod$3fea245e43c817e3ab409ba408c64d50b3c3410d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16170'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3fea245e43c817e3ab409ba408c64d50b3c3410d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16133_EN' using process `$paramod$3fea245e43c817e3ab409ba408c64d50b3c3410d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16170'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3fea245e43c817e3ab409ba408c64d50b3c3410d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$16144_EN' using process `$paramod$3fea245e43c817e3ab409ba408c64d50b3c3410d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$16146'. created $dff cell `$procdff$16196' with positive edge clock. Creating register for signal `$paramod$3fea245e43c817e3ab409ba408c64d50b3c3410d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$16144_DATA' using process `$paramod$3fea245e43c817e3ab409ba408c64d50b3c3410d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$16146'. created $dff cell `$procdff$16197' with positive edge clock. Creating register for signal `$paramod$3fea245e43c817e3ab409ba408c64d50b3c3410d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$16144_ADDR' using process `$paramod$3fea245e43c817e3ab409ba408c64d50b3c3410d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$16146'. created $dff cell `$procdff$16198' with positive edge clock. Creating register for signal `$paramod$3fea245e43c817e3ab409ba408c64d50b3c3410d\TRELLIS_DPR16X4.\muxwre' using process `$paramod$3fea245e43c817e3ab409ba408c64d50b3c3410d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$16145'. created direct connection (no actual register cell created). 24.42.9.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 24.42.9.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$3fea245e43c817e3ab409ba408c64d50b3c3410d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16170'. Found and cleaned up 1 empty switch in `$paramod$3fea245e43c817e3ab409ba408c64d50b3c3410d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$16146'. Removing empty process `$paramod$3fea245e43c817e3ab409ba408c64d50b3c3410d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$16145'. Cleaned up 1 empty switch. 24.42.9.12. Executing OPT_EXPR pass (perform const folding). 24.42.10. Executing PROC pass (convert processes to netlists). 24.42.10.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$828eab860e7ad1344f71b7dcac93a993e09abfc2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$16216'. Cleaned up 1 empty switch. 24.42.10.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$16217 in module $paramod$828eab860e7ad1344f71b7dcac93a993e09abfc2\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 24.42.10.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 24.42.10.4. Executing PROC_INIT pass (extract init attributes). 24.42.10.5. Executing PROC_ARST pass (detect async resets in processes). 24.42.10.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 24.42.10.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$828eab860e7ad1344f71b7dcac93a993e09abfc2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16241'. Creating decoders for process `$paramod$828eab860e7ad1344f71b7dcac93a993e09abfc2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$16217'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$16215_EN[3:0]$16223 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$16215_DATA[3:0]$16221 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$16215_ADDR[3:0]$16222 Creating decoders for process `$paramod$828eab860e7ad1344f71b7dcac93a993e09abfc2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$16216'. 24.42.10.8. Executing PROC_DLATCH pass (convert process syncs to latches). 24.42.10.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$828eab860e7ad1344f71b7dcac93a993e09abfc2\TRELLIS_DPR16X4.\i' using process `$paramod$828eab860e7ad1344f71b7dcac93a993e09abfc2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16241'. created direct connection (no actual register cell created). Creating register for signal `$paramod$828eab860e7ad1344f71b7dcac93a993e09abfc2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16214_EN' using process `$paramod$828eab860e7ad1344f71b7dcac93a993e09abfc2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16241'. created direct connection (no actual register cell created). Creating register for signal `$paramod$828eab860e7ad1344f71b7dcac93a993e09abfc2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16209_EN' using process `$paramod$828eab860e7ad1344f71b7dcac93a993e09abfc2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16241'. created direct connection (no actual register cell created). Creating register for signal `$paramod$828eab860e7ad1344f71b7dcac93a993e09abfc2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16204_EN' using process `$paramod$828eab860e7ad1344f71b7dcac93a993e09abfc2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16241'. created direct connection (no actual register cell created). Creating register for signal `$paramod$828eab860e7ad1344f71b7dcac93a993e09abfc2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16199_EN' using process `$paramod$828eab860e7ad1344f71b7dcac93a993e09abfc2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16241'. created direct connection (no actual register cell created). Creating register for signal `$paramod$828eab860e7ad1344f71b7dcac93a993e09abfc2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16213_EN' using process `$paramod$828eab860e7ad1344f71b7dcac93a993e09abfc2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16241'. created direct connection (no actual register cell created). Creating register for signal `$paramod$828eab860e7ad1344f71b7dcac93a993e09abfc2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16205_EN' using process `$paramod$828eab860e7ad1344f71b7dcac93a993e09abfc2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16241'. created direct connection (no actual register cell created). Creating register for signal `$paramod$828eab860e7ad1344f71b7dcac93a993e09abfc2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16200_EN' using process `$paramod$828eab860e7ad1344f71b7dcac93a993e09abfc2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16241'. created direct connection (no actual register cell created). Creating register for signal `$paramod$828eab860e7ad1344f71b7dcac93a993e09abfc2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16201_EN' using process `$paramod$828eab860e7ad1344f71b7dcac93a993e09abfc2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16241'. created direct connection (no actual register cell created). Creating register for signal `$paramod$828eab860e7ad1344f71b7dcac93a993e09abfc2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16212_EN' using process `$paramod$828eab860e7ad1344f71b7dcac93a993e09abfc2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16241'. created direct connection (no actual register cell created). Creating register for signal `$paramod$828eab860e7ad1344f71b7dcac93a993e09abfc2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16208_EN' using process `$paramod$828eab860e7ad1344f71b7dcac93a993e09abfc2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16241'. created direct connection (no actual register cell created). Creating register for signal `$paramod$828eab860e7ad1344f71b7dcac93a993e09abfc2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16203_EN' using process `$paramod$828eab860e7ad1344f71b7dcac93a993e09abfc2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16241'. created direct connection (no actual register cell created). Creating register for signal `$paramod$828eab860e7ad1344f71b7dcac93a993e09abfc2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16207_EN' using process `$paramod$828eab860e7ad1344f71b7dcac93a993e09abfc2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16241'. created direct connection (no actual register cell created). Creating register for signal `$paramod$828eab860e7ad1344f71b7dcac93a993e09abfc2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16206_EN' using process `$paramod$828eab860e7ad1344f71b7dcac93a993e09abfc2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16241'. created direct connection (no actual register cell created). Creating register for signal `$paramod$828eab860e7ad1344f71b7dcac93a993e09abfc2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16211_EN' using process `$paramod$828eab860e7ad1344f71b7dcac93a993e09abfc2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16241'. created direct connection (no actual register cell created). Creating register for signal `$paramod$828eab860e7ad1344f71b7dcac93a993e09abfc2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16210_EN' using process `$paramod$828eab860e7ad1344f71b7dcac93a993e09abfc2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16241'. created direct connection (no actual register cell created). Creating register for signal `$paramod$828eab860e7ad1344f71b7dcac93a993e09abfc2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16202_EN' using process `$paramod$828eab860e7ad1344f71b7dcac93a993e09abfc2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16241'. created direct connection (no actual register cell created). Creating register for signal `$paramod$828eab860e7ad1344f71b7dcac93a993e09abfc2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$16215_DATA' using process `$paramod$828eab860e7ad1344f71b7dcac93a993e09abfc2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$16217'. created $dff cell `$procdff$16267' with positive edge clock. Creating register for signal `$paramod$828eab860e7ad1344f71b7dcac93a993e09abfc2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$16215_ADDR' using process `$paramod$828eab860e7ad1344f71b7dcac93a993e09abfc2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$16217'. created $dff cell `$procdff$16268' with positive edge clock. Creating register for signal `$paramod$828eab860e7ad1344f71b7dcac93a993e09abfc2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$16215_EN' using process `$paramod$828eab860e7ad1344f71b7dcac93a993e09abfc2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$16217'. created $dff cell `$procdff$16269' with positive edge clock. Creating register for signal `$paramod$828eab860e7ad1344f71b7dcac93a993e09abfc2\TRELLIS_DPR16X4.\muxwre' using process `$paramod$828eab860e7ad1344f71b7dcac93a993e09abfc2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$16216'. created direct connection (no actual register cell created). 24.42.10.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 24.42.10.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$828eab860e7ad1344f71b7dcac93a993e09abfc2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16241'. Found and cleaned up 1 empty switch in `$paramod$828eab860e7ad1344f71b7dcac93a993e09abfc2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$16217'. Removing empty process `$paramod$828eab860e7ad1344f71b7dcac93a993e09abfc2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$16216'. Cleaned up 1 empty switch. 24.42.10.12. Executing OPT_EXPR pass (perform const folding). 24.42.11. Executing PROC pass (convert processes to netlists). 24.42.11.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$b4055cc4c76830d75a5da93152e34111ac58d5fb\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$16287'. Cleaned up 1 empty switch. 24.42.11.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$16288 in module $paramod$b4055cc4c76830d75a5da93152e34111ac58d5fb\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 24.42.11.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 24.42.11.4. Executing PROC_INIT pass (extract init attributes). 24.42.11.5. Executing PROC_ARST pass (detect async resets in processes). 24.42.11.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 24.42.11.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$b4055cc4c76830d75a5da93152e34111ac58d5fb\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16312'. Creating decoders for process `$paramod$b4055cc4c76830d75a5da93152e34111ac58d5fb\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$16288'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$16286_EN[3:0]$16294 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$16286_DATA[3:0]$16292 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$16286_ADDR[3:0]$16293 Creating decoders for process `$paramod$b4055cc4c76830d75a5da93152e34111ac58d5fb\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$16287'. 24.42.11.8. Executing PROC_DLATCH pass (convert process syncs to latches). 24.42.11.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$b4055cc4c76830d75a5da93152e34111ac58d5fb\TRELLIS_DPR16X4.\i' using process `$paramod$b4055cc4c76830d75a5da93152e34111ac58d5fb\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16312'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b4055cc4c76830d75a5da93152e34111ac58d5fb\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16282_EN' using process `$paramod$b4055cc4c76830d75a5da93152e34111ac58d5fb\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16312'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b4055cc4c76830d75a5da93152e34111ac58d5fb\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16277_EN' using process `$paramod$b4055cc4c76830d75a5da93152e34111ac58d5fb\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16312'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b4055cc4c76830d75a5da93152e34111ac58d5fb\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16272_EN' using process `$paramod$b4055cc4c76830d75a5da93152e34111ac58d5fb\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16312'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b4055cc4c76830d75a5da93152e34111ac58d5fb\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16270_EN' using process `$paramod$b4055cc4c76830d75a5da93152e34111ac58d5fb\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16312'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b4055cc4c76830d75a5da93152e34111ac58d5fb\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16275_EN' using process `$paramod$b4055cc4c76830d75a5da93152e34111ac58d5fb\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16312'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b4055cc4c76830d75a5da93152e34111ac58d5fb\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16283_EN' using process `$paramod$b4055cc4c76830d75a5da93152e34111ac58d5fb\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16312'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b4055cc4c76830d75a5da93152e34111ac58d5fb\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16279_EN' using process `$paramod$b4055cc4c76830d75a5da93152e34111ac58d5fb\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16312'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b4055cc4c76830d75a5da93152e34111ac58d5fb\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16278_EN' using process `$paramod$b4055cc4c76830d75a5da93152e34111ac58d5fb\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16312'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b4055cc4c76830d75a5da93152e34111ac58d5fb\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16274_EN' using process `$paramod$b4055cc4c76830d75a5da93152e34111ac58d5fb\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16312'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b4055cc4c76830d75a5da93152e34111ac58d5fb\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16273_EN' using process `$paramod$b4055cc4c76830d75a5da93152e34111ac58d5fb\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16312'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b4055cc4c76830d75a5da93152e34111ac58d5fb\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16281_EN' using process `$paramod$b4055cc4c76830d75a5da93152e34111ac58d5fb\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16312'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b4055cc4c76830d75a5da93152e34111ac58d5fb\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16285_EN' using process `$paramod$b4055cc4c76830d75a5da93152e34111ac58d5fb\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16312'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b4055cc4c76830d75a5da93152e34111ac58d5fb\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16276_EN' using process `$paramod$b4055cc4c76830d75a5da93152e34111ac58d5fb\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16312'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b4055cc4c76830d75a5da93152e34111ac58d5fb\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16280_EN' using process `$paramod$b4055cc4c76830d75a5da93152e34111ac58d5fb\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16312'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b4055cc4c76830d75a5da93152e34111ac58d5fb\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16284_EN' using process `$paramod$b4055cc4c76830d75a5da93152e34111ac58d5fb\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16312'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b4055cc4c76830d75a5da93152e34111ac58d5fb\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16271_EN' using process `$paramod$b4055cc4c76830d75a5da93152e34111ac58d5fb\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16312'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b4055cc4c76830d75a5da93152e34111ac58d5fb\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$16286_DATA' using process `$paramod$b4055cc4c76830d75a5da93152e34111ac58d5fb\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$16288'. created $dff cell `$procdff$16338' with positive edge clock. Creating register for signal `$paramod$b4055cc4c76830d75a5da93152e34111ac58d5fb\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$16286_ADDR' using process `$paramod$b4055cc4c76830d75a5da93152e34111ac58d5fb\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$16288'. created $dff cell `$procdff$16339' with positive edge clock. Creating register for signal `$paramod$b4055cc4c76830d75a5da93152e34111ac58d5fb\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$16286_EN' using process `$paramod$b4055cc4c76830d75a5da93152e34111ac58d5fb\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$16288'. created $dff cell `$procdff$16340' with positive edge clock. Creating register for signal `$paramod$b4055cc4c76830d75a5da93152e34111ac58d5fb\TRELLIS_DPR16X4.\muxwre' using process `$paramod$b4055cc4c76830d75a5da93152e34111ac58d5fb\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$16287'. created direct connection (no actual register cell created). 24.42.11.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 24.42.11.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$b4055cc4c76830d75a5da93152e34111ac58d5fb\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16312'. Found and cleaned up 1 empty switch in `$paramod$b4055cc4c76830d75a5da93152e34111ac58d5fb\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$16288'. Removing empty process `$paramod$b4055cc4c76830d75a5da93152e34111ac58d5fb\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$16287'. Cleaned up 1 empty switch. 24.42.11.12. Executing OPT_EXPR pass (perform const folding). 24.42.12. Executing PROC pass (convert processes to netlists). 24.42.12.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$28331dd642fda78247f997daeb218f7111f59a79\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$16358'. Cleaned up 1 empty switch. 24.42.12.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$16359 in module $paramod$28331dd642fda78247f997daeb218f7111f59a79\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 24.42.12.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 24.42.12.4. Executing PROC_INIT pass (extract init attributes). 24.42.12.5. Executing PROC_ARST pass (detect async resets in processes). 24.42.12.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 24.42.12.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$28331dd642fda78247f997daeb218f7111f59a79\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16383'. Creating decoders for process `$paramod$28331dd642fda78247f997daeb218f7111f59a79\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$16359'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$16357_EN[3:0]$16363 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$16357_DATA[3:0]$16364 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$16357_ADDR[3:0]$16365 Creating decoders for process `$paramod$28331dd642fda78247f997daeb218f7111f59a79\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$16358'. 24.42.12.8. Executing PROC_DLATCH pass (convert process syncs to latches). 24.42.12.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$28331dd642fda78247f997daeb218f7111f59a79\TRELLIS_DPR16X4.\i' using process `$paramod$28331dd642fda78247f997daeb218f7111f59a79\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16383'. created direct connection (no actual register cell created). Creating register for signal `$paramod$28331dd642fda78247f997daeb218f7111f59a79\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16355_EN' using process `$paramod$28331dd642fda78247f997daeb218f7111f59a79\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16383'. created direct connection (no actual register cell created). Creating register for signal `$paramod$28331dd642fda78247f997daeb218f7111f59a79\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16350_EN' using process `$paramod$28331dd642fda78247f997daeb218f7111f59a79\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16383'. created direct connection (no actual register cell created). Creating register for signal `$paramod$28331dd642fda78247f997daeb218f7111f59a79\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16345_EN' using process `$paramod$28331dd642fda78247f997daeb218f7111f59a79\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16383'. created direct connection (no actual register cell created). Creating register for signal `$paramod$28331dd642fda78247f997daeb218f7111f59a79\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16343_EN' using process `$paramod$28331dd642fda78247f997daeb218f7111f59a79\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16383'. created direct connection (no actual register cell created). Creating register for signal `$paramod$28331dd642fda78247f997daeb218f7111f59a79\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16351_EN' using process `$paramod$28331dd642fda78247f997daeb218f7111f59a79\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16383'. created direct connection (no actual register cell created). Creating register for signal `$paramod$28331dd642fda78247f997daeb218f7111f59a79\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16354_EN' using process `$paramod$28331dd642fda78247f997daeb218f7111f59a79\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16383'. created direct connection (no actual register cell created). Creating register for signal `$paramod$28331dd642fda78247f997daeb218f7111f59a79\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16353_EN' using process `$paramod$28331dd642fda78247f997daeb218f7111f59a79\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16383'. created direct connection (no actual register cell created). Creating register for signal `$paramod$28331dd642fda78247f997daeb218f7111f59a79\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16349_EN' using process `$paramod$28331dd642fda78247f997daeb218f7111f59a79\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16383'. created direct connection (no actual register cell created). Creating register for signal `$paramod$28331dd642fda78247f997daeb218f7111f59a79\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16352_EN' using process `$paramod$28331dd642fda78247f997daeb218f7111f59a79\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16383'. created direct connection (no actual register cell created). Creating register for signal `$paramod$28331dd642fda78247f997daeb218f7111f59a79\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16347_EN' using process `$paramod$28331dd642fda78247f997daeb218f7111f59a79\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16383'. created direct connection (no actual register cell created). Creating register for signal `$paramod$28331dd642fda78247f997daeb218f7111f59a79\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16356_EN' using process `$paramod$28331dd642fda78247f997daeb218f7111f59a79\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16383'. created direct connection (no actual register cell created). Creating register for signal `$paramod$28331dd642fda78247f997daeb218f7111f59a79\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16348_EN' using process `$paramod$28331dd642fda78247f997daeb218f7111f59a79\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16383'. created direct connection (no actual register cell created). Creating register for signal `$paramod$28331dd642fda78247f997daeb218f7111f59a79\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16344_EN' using process `$paramod$28331dd642fda78247f997daeb218f7111f59a79\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16383'. created direct connection (no actual register cell created). Creating register for signal `$paramod$28331dd642fda78247f997daeb218f7111f59a79\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16342_EN' using process `$paramod$28331dd642fda78247f997daeb218f7111f59a79\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16383'. created direct connection (no actual register cell created). Creating register for signal `$paramod$28331dd642fda78247f997daeb218f7111f59a79\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16341_EN' using process `$paramod$28331dd642fda78247f997daeb218f7111f59a79\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16383'. created direct connection (no actual register cell created). Creating register for signal `$paramod$28331dd642fda78247f997daeb218f7111f59a79\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16346_EN' using process `$paramod$28331dd642fda78247f997daeb218f7111f59a79\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16383'. created direct connection (no actual register cell created). Creating register for signal `$paramod$28331dd642fda78247f997daeb218f7111f59a79\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$16357_EN' using process `$paramod$28331dd642fda78247f997daeb218f7111f59a79\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$16359'. created $dff cell `$procdff$16409' with positive edge clock. Creating register for signal `$paramod$28331dd642fda78247f997daeb218f7111f59a79\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$16357_DATA' using process `$paramod$28331dd642fda78247f997daeb218f7111f59a79\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$16359'. created $dff cell `$procdff$16410' with positive edge clock. Creating register for signal `$paramod$28331dd642fda78247f997daeb218f7111f59a79\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$16357_ADDR' using process `$paramod$28331dd642fda78247f997daeb218f7111f59a79\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$16359'. created $dff cell `$procdff$16411' with positive edge clock. Creating register for signal `$paramod$28331dd642fda78247f997daeb218f7111f59a79\TRELLIS_DPR16X4.\muxwre' using process `$paramod$28331dd642fda78247f997daeb218f7111f59a79\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$16358'. created direct connection (no actual register cell created). 24.42.12.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 24.42.12.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$28331dd642fda78247f997daeb218f7111f59a79\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16383'. Found and cleaned up 1 empty switch in `$paramod$28331dd642fda78247f997daeb218f7111f59a79\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$16359'. Removing empty process `$paramod$28331dd642fda78247f997daeb218f7111f59a79\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$16358'. Cleaned up 1 empty switch. 24.42.12.12. Executing OPT_EXPR pass (perform const folding). 24.42.13. Executing PROC pass (convert processes to netlists). 24.42.13.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$242712b50c0a2a6b7d501d3b8f15d1e042886c7d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$16429'. Cleaned up 1 empty switch. 24.42.13.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$16430 in module $paramod$242712b50c0a2a6b7d501d3b8f15d1e042886c7d\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 24.42.13.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 24.42.13.4. Executing PROC_INIT pass (extract init attributes). 24.42.13.5. Executing PROC_ARST pass (detect async resets in processes). 24.42.13.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 24.42.13.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$242712b50c0a2a6b7d501d3b8f15d1e042886c7d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16454'. Creating decoders for process `$paramod$242712b50c0a2a6b7d501d3b8f15d1e042886c7d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$16430'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$16428_EN[3:0]$16434 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$16428_DATA[3:0]$16435 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$16428_ADDR[3:0]$16436 Creating decoders for process `$paramod$242712b50c0a2a6b7d501d3b8f15d1e042886c7d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$16429'. 24.42.13.8. Executing PROC_DLATCH pass (convert process syncs to latches). 24.42.13.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$242712b50c0a2a6b7d501d3b8f15d1e042886c7d\TRELLIS_DPR16X4.\i' using process `$paramod$242712b50c0a2a6b7d501d3b8f15d1e042886c7d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16454'. created direct connection (no actual register cell created). Creating register for signal `$paramod$242712b50c0a2a6b7d501d3b8f15d1e042886c7d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16427_EN' using process `$paramod$242712b50c0a2a6b7d501d3b8f15d1e042886c7d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16454'. created direct connection (no actual register cell created). Creating register for signal `$paramod$242712b50c0a2a6b7d501d3b8f15d1e042886c7d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16421_EN' using process `$paramod$242712b50c0a2a6b7d501d3b8f15d1e042886c7d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16454'. created direct connection (no actual register cell created). Creating register for signal `$paramod$242712b50c0a2a6b7d501d3b8f15d1e042886c7d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16415_EN' using process `$paramod$242712b50c0a2a6b7d501d3b8f15d1e042886c7d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16454'. created direct connection (no actual register cell created). Creating register for signal `$paramod$242712b50c0a2a6b7d501d3b8f15d1e042886c7d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16426_EN' using process `$paramod$242712b50c0a2a6b7d501d3b8f15d1e042886c7d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16454'. created direct connection (no actual register cell created). Creating register for signal `$paramod$242712b50c0a2a6b7d501d3b8f15d1e042886c7d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16425_EN' using process `$paramod$242712b50c0a2a6b7d501d3b8f15d1e042886c7d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16454'. created direct connection (no actual register cell created). Creating register for signal `$paramod$242712b50c0a2a6b7d501d3b8f15d1e042886c7d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16420_EN' using process `$paramod$242712b50c0a2a6b7d501d3b8f15d1e042886c7d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16454'. created direct connection (no actual register cell created). Creating register for signal `$paramod$242712b50c0a2a6b7d501d3b8f15d1e042886c7d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16419_EN' using process `$paramod$242712b50c0a2a6b7d501d3b8f15d1e042886c7d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16454'. created direct connection (no actual register cell created). Creating register for signal `$paramod$242712b50c0a2a6b7d501d3b8f15d1e042886c7d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16414_EN' using process `$paramod$242712b50c0a2a6b7d501d3b8f15d1e042886c7d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16454'. created direct connection (no actual register cell created). Creating register for signal `$paramod$242712b50c0a2a6b7d501d3b8f15d1e042886c7d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16424_EN' using process `$paramod$242712b50c0a2a6b7d501d3b8f15d1e042886c7d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16454'. created direct connection (no actual register cell created). Creating register for signal `$paramod$242712b50c0a2a6b7d501d3b8f15d1e042886c7d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16413_EN' using process `$paramod$242712b50c0a2a6b7d501d3b8f15d1e042886c7d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16454'. created direct connection (no actual register cell created). Creating register for signal `$paramod$242712b50c0a2a6b7d501d3b8f15d1e042886c7d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16423_EN' using process `$paramod$242712b50c0a2a6b7d501d3b8f15d1e042886c7d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16454'. created direct connection (no actual register cell created). Creating register for signal `$paramod$242712b50c0a2a6b7d501d3b8f15d1e042886c7d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16422_EN' using process `$paramod$242712b50c0a2a6b7d501d3b8f15d1e042886c7d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16454'. created direct connection (no actual register cell created). Creating register for signal `$paramod$242712b50c0a2a6b7d501d3b8f15d1e042886c7d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16418_EN' using process `$paramod$242712b50c0a2a6b7d501d3b8f15d1e042886c7d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16454'. created direct connection (no actual register cell created). Creating register for signal `$paramod$242712b50c0a2a6b7d501d3b8f15d1e042886c7d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16417_EN' using process `$paramod$242712b50c0a2a6b7d501d3b8f15d1e042886c7d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16454'. created direct connection (no actual register cell created). Creating register for signal `$paramod$242712b50c0a2a6b7d501d3b8f15d1e042886c7d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16416_EN' using process `$paramod$242712b50c0a2a6b7d501d3b8f15d1e042886c7d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16454'. created direct connection (no actual register cell created). Creating register for signal `$paramod$242712b50c0a2a6b7d501d3b8f15d1e042886c7d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16412_EN' using process `$paramod$242712b50c0a2a6b7d501d3b8f15d1e042886c7d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16454'. created direct connection (no actual register cell created). Creating register for signal `$paramod$242712b50c0a2a6b7d501d3b8f15d1e042886c7d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$16428_EN' using process `$paramod$242712b50c0a2a6b7d501d3b8f15d1e042886c7d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$16430'. created $dff cell `$procdff$16480' with positive edge clock. Creating register for signal `$paramod$242712b50c0a2a6b7d501d3b8f15d1e042886c7d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$16428_DATA' using process `$paramod$242712b50c0a2a6b7d501d3b8f15d1e042886c7d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$16430'. created $dff cell `$procdff$16481' with positive edge clock. Creating register for signal `$paramod$242712b50c0a2a6b7d501d3b8f15d1e042886c7d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$16428_ADDR' using process `$paramod$242712b50c0a2a6b7d501d3b8f15d1e042886c7d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$16430'. created $dff cell `$procdff$16482' with positive edge clock. Creating register for signal `$paramod$242712b50c0a2a6b7d501d3b8f15d1e042886c7d\TRELLIS_DPR16X4.\muxwre' using process `$paramod$242712b50c0a2a6b7d501d3b8f15d1e042886c7d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$16429'. created direct connection (no actual register cell created). 24.42.13.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 24.42.13.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$242712b50c0a2a6b7d501d3b8f15d1e042886c7d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16454'. Found and cleaned up 1 empty switch in `$paramod$242712b50c0a2a6b7d501d3b8f15d1e042886c7d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$16430'. Removing empty process `$paramod$242712b50c0a2a6b7d501d3b8f15d1e042886c7d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$16429'. Cleaned up 1 empty switch. 24.42.13.12. Executing OPT_EXPR pass (perform const folding). 24.42.14. Executing PROC pass (convert processes to netlists). 24.42.14.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$896c13102149326c20257183c5d146c2879d74e6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$16500'. Cleaned up 1 empty switch. 24.42.14.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$16501 in module $paramod$896c13102149326c20257183c5d146c2879d74e6\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 24.42.14.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 24.42.14.4. Executing PROC_INIT pass (extract init attributes). 24.42.14.5. Executing PROC_ARST pass (detect async resets in processes). 24.42.14.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 24.42.14.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$896c13102149326c20257183c5d146c2879d74e6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16525'. Creating decoders for process `$paramod$896c13102149326c20257183c5d146c2879d74e6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$16501'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$16499_EN[3:0]$16505 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$16499_DATA[3:0]$16506 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$16499_ADDR[3:0]$16507 Creating decoders for process `$paramod$896c13102149326c20257183c5d146c2879d74e6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$16500'. 24.42.14.8. Executing PROC_DLATCH pass (convert process syncs to latches). 24.42.14.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$896c13102149326c20257183c5d146c2879d74e6\TRELLIS_DPR16X4.\i' using process `$paramod$896c13102149326c20257183c5d146c2879d74e6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16525'. created direct connection (no actual register cell created). Creating register for signal `$paramod$896c13102149326c20257183c5d146c2879d74e6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16497_EN' using process `$paramod$896c13102149326c20257183c5d146c2879d74e6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16525'. created direct connection (no actual register cell created). Creating register for signal `$paramod$896c13102149326c20257183c5d146c2879d74e6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16491_EN' using process `$paramod$896c13102149326c20257183c5d146c2879d74e6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16525'. created direct connection (no actual register cell created). Creating register for signal `$paramod$896c13102149326c20257183c5d146c2879d74e6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16485_EN' using process `$paramod$896c13102149326c20257183c5d146c2879d74e6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16525'. created direct connection (no actual register cell created). Creating register for signal `$paramod$896c13102149326c20257183c5d146c2879d74e6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16483_EN' using process `$paramod$896c13102149326c20257183c5d146c2879d74e6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16525'. created direct connection (no actual register cell created). Creating register for signal `$paramod$896c13102149326c20257183c5d146c2879d74e6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16496_EN' using process `$paramod$896c13102149326c20257183c5d146c2879d74e6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16525'. created direct connection (no actual register cell created). Creating register for signal `$paramod$896c13102149326c20257183c5d146c2879d74e6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16495_EN' using process `$paramod$896c13102149326c20257183c5d146c2879d74e6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16525'. created direct connection (no actual register cell created). Creating register for signal `$paramod$896c13102149326c20257183c5d146c2879d74e6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16490_EN' using process `$paramod$896c13102149326c20257183c5d146c2879d74e6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16525'. created direct connection (no actual register cell created). Creating register for signal `$paramod$896c13102149326c20257183c5d146c2879d74e6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16489_EN' using process `$paramod$896c13102149326c20257183c5d146c2879d74e6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16525'. created direct connection (no actual register cell created). Creating register for signal `$paramod$896c13102149326c20257183c5d146c2879d74e6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16484_EN' using process `$paramod$896c13102149326c20257183c5d146c2879d74e6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16525'. created direct connection (no actual register cell created). Creating register for signal `$paramod$896c13102149326c20257183c5d146c2879d74e6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16498_EN' using process `$paramod$896c13102149326c20257183c5d146c2879d74e6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16525'. created direct connection (no actual register cell created). Creating register for signal `$paramod$896c13102149326c20257183c5d146c2879d74e6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16494_EN' using process `$paramod$896c13102149326c20257183c5d146c2879d74e6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16525'. created direct connection (no actual register cell created). Creating register for signal `$paramod$896c13102149326c20257183c5d146c2879d74e6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16493_EN' using process `$paramod$896c13102149326c20257183c5d146c2879d74e6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16525'. created direct connection (no actual register cell created). Creating register for signal `$paramod$896c13102149326c20257183c5d146c2879d74e6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16492_EN' using process `$paramod$896c13102149326c20257183c5d146c2879d74e6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16525'. created direct connection (no actual register cell created). Creating register for signal `$paramod$896c13102149326c20257183c5d146c2879d74e6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16488_EN' using process `$paramod$896c13102149326c20257183c5d146c2879d74e6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16525'. created direct connection (no actual register cell created). Creating register for signal `$paramod$896c13102149326c20257183c5d146c2879d74e6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16487_EN' using process `$paramod$896c13102149326c20257183c5d146c2879d74e6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16525'. created direct connection (no actual register cell created). Creating register for signal `$paramod$896c13102149326c20257183c5d146c2879d74e6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16486_EN' using process `$paramod$896c13102149326c20257183c5d146c2879d74e6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16525'. created direct connection (no actual register cell created). Creating register for signal `$paramod$896c13102149326c20257183c5d146c2879d74e6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$16499_EN' using process `$paramod$896c13102149326c20257183c5d146c2879d74e6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$16501'. created $dff cell `$procdff$16551' with positive edge clock. Creating register for signal `$paramod$896c13102149326c20257183c5d146c2879d74e6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$16499_DATA' using process `$paramod$896c13102149326c20257183c5d146c2879d74e6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$16501'. created $dff cell `$procdff$16552' with positive edge clock. Creating register for signal `$paramod$896c13102149326c20257183c5d146c2879d74e6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$16499_ADDR' using process `$paramod$896c13102149326c20257183c5d146c2879d74e6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$16501'. created $dff cell `$procdff$16553' with positive edge clock. Creating register for signal `$paramod$896c13102149326c20257183c5d146c2879d74e6\TRELLIS_DPR16X4.\muxwre' using process `$paramod$896c13102149326c20257183c5d146c2879d74e6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$16500'. created direct connection (no actual register cell created). 24.42.14.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 24.42.14.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$896c13102149326c20257183c5d146c2879d74e6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16525'. Found and cleaned up 1 empty switch in `$paramod$896c13102149326c20257183c5d146c2879d74e6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$16501'. Removing empty process `$paramod$896c13102149326c20257183c5d146c2879d74e6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$16500'. Cleaned up 1 empty switch. 24.42.14.12. Executing OPT_EXPR pass (perform const folding). 24.42.15. Executing PROC pass (convert processes to netlists). 24.42.15.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$53a840446cdc2b5aa298a080f49764e881c60b99\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$16571'. Cleaned up 1 empty switch. 24.42.15.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$16572 in module $paramod$53a840446cdc2b5aa298a080f49764e881c60b99\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 24.42.15.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 24.42.15.4. Executing PROC_INIT pass (extract init attributes). 24.42.15.5. Executing PROC_ARST pass (detect async resets in processes). 24.42.15.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 24.42.15.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$53a840446cdc2b5aa298a080f49764e881c60b99\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16596'. Creating decoders for process `$paramod$53a840446cdc2b5aa298a080f49764e881c60b99\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$16572'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$16570_EN[3:0]$16576 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$16570_DATA[3:0]$16577 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$16570_ADDR[3:0]$16578 Creating decoders for process `$paramod$53a840446cdc2b5aa298a080f49764e881c60b99\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$16571'. 24.42.15.8. Executing PROC_DLATCH pass (convert process syncs to latches). 24.42.15.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$53a840446cdc2b5aa298a080f49764e881c60b99\TRELLIS_DPR16X4.\i' using process `$paramod$53a840446cdc2b5aa298a080f49764e881c60b99\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16596'. created direct connection (no actual register cell created). Creating register for signal `$paramod$53a840446cdc2b5aa298a080f49764e881c60b99\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16567_EN' using process `$paramod$53a840446cdc2b5aa298a080f49764e881c60b99\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16596'. created direct connection (no actual register cell created). Creating register for signal `$paramod$53a840446cdc2b5aa298a080f49764e881c60b99\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16561_EN' using process `$paramod$53a840446cdc2b5aa298a080f49764e881c60b99\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16596'. created direct connection (no actual register cell created). Creating register for signal `$paramod$53a840446cdc2b5aa298a080f49764e881c60b99\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16555_EN' using process `$paramod$53a840446cdc2b5aa298a080f49764e881c60b99\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16596'. created direct connection (no actual register cell created). Creating register for signal `$paramod$53a840446cdc2b5aa298a080f49764e881c60b99\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16566_EN' using process `$paramod$53a840446cdc2b5aa298a080f49764e881c60b99\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16596'. created direct connection (no actual register cell created). Creating register for signal `$paramod$53a840446cdc2b5aa298a080f49764e881c60b99\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16565_EN' using process `$paramod$53a840446cdc2b5aa298a080f49764e881c60b99\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16596'. created direct connection (no actual register cell created). Creating register for signal `$paramod$53a840446cdc2b5aa298a080f49764e881c60b99\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16560_EN' using process `$paramod$53a840446cdc2b5aa298a080f49764e881c60b99\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16596'. created direct connection (no actual register cell created). Creating register for signal `$paramod$53a840446cdc2b5aa298a080f49764e881c60b99\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16559_EN' using process `$paramod$53a840446cdc2b5aa298a080f49764e881c60b99\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16596'. created direct connection (no actual register cell created). Creating register for signal `$paramod$53a840446cdc2b5aa298a080f49764e881c60b99\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16569_EN' using process `$paramod$53a840446cdc2b5aa298a080f49764e881c60b99\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16596'. created direct connection (no actual register cell created). Creating register for signal `$paramod$53a840446cdc2b5aa298a080f49764e881c60b99\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16568_EN' using process `$paramod$53a840446cdc2b5aa298a080f49764e881c60b99\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16596'. created direct connection (no actual register cell created). Creating register for signal `$paramod$53a840446cdc2b5aa298a080f49764e881c60b99\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16564_EN' using process `$paramod$53a840446cdc2b5aa298a080f49764e881c60b99\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16596'. created direct connection (no actual register cell created). Creating register for signal `$paramod$53a840446cdc2b5aa298a080f49764e881c60b99\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16563_EN' using process `$paramod$53a840446cdc2b5aa298a080f49764e881c60b99\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16596'. created direct connection (no actual register cell created). Creating register for signal `$paramod$53a840446cdc2b5aa298a080f49764e881c60b99\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16562_EN' using process `$paramod$53a840446cdc2b5aa298a080f49764e881c60b99\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16596'. created direct connection (no actual register cell created). Creating register for signal `$paramod$53a840446cdc2b5aa298a080f49764e881c60b99\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16558_EN' using process `$paramod$53a840446cdc2b5aa298a080f49764e881c60b99\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16596'. created direct connection (no actual register cell created). Creating register for signal `$paramod$53a840446cdc2b5aa298a080f49764e881c60b99\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16557_EN' using process `$paramod$53a840446cdc2b5aa298a080f49764e881c60b99\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16596'. created direct connection (no actual register cell created). Creating register for signal `$paramod$53a840446cdc2b5aa298a080f49764e881c60b99\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16556_EN' using process `$paramod$53a840446cdc2b5aa298a080f49764e881c60b99\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16596'. created direct connection (no actual register cell created). Creating register for signal `$paramod$53a840446cdc2b5aa298a080f49764e881c60b99\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16554_EN' using process `$paramod$53a840446cdc2b5aa298a080f49764e881c60b99\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16596'. created direct connection (no actual register cell created). Creating register for signal `$paramod$53a840446cdc2b5aa298a080f49764e881c60b99\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$16570_EN' using process `$paramod$53a840446cdc2b5aa298a080f49764e881c60b99\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$16572'. created $dff cell `$procdff$16622' with positive edge clock. Creating register for signal `$paramod$53a840446cdc2b5aa298a080f49764e881c60b99\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$16570_DATA' using process `$paramod$53a840446cdc2b5aa298a080f49764e881c60b99\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$16572'. created $dff cell `$procdff$16623' with positive edge clock. Creating register for signal `$paramod$53a840446cdc2b5aa298a080f49764e881c60b99\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$16570_ADDR' using process `$paramod$53a840446cdc2b5aa298a080f49764e881c60b99\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$16572'. created $dff cell `$procdff$16624' with positive edge clock. Creating register for signal `$paramod$53a840446cdc2b5aa298a080f49764e881c60b99\TRELLIS_DPR16X4.\muxwre' using process `$paramod$53a840446cdc2b5aa298a080f49764e881c60b99\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$16571'. created direct connection (no actual register cell created). 24.42.15.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 24.42.15.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$53a840446cdc2b5aa298a080f49764e881c60b99\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16596'. Found and cleaned up 1 empty switch in `$paramod$53a840446cdc2b5aa298a080f49764e881c60b99\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$16572'. Removing empty process `$paramod$53a840446cdc2b5aa298a080f49764e881c60b99\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$16571'. Cleaned up 1 empty switch. 24.42.15.12. Executing OPT_EXPR pass (perform const folding). 24.42.16. Executing PROC pass (convert processes to netlists). 24.42.16.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$0ec150df0608fe9d13bbd7ba55d0b68aebde8574\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$16642'. Cleaned up 1 empty switch. 24.42.16.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$16643 in module $paramod$0ec150df0608fe9d13bbd7ba55d0b68aebde8574\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 24.42.16.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 24.42.16.4. Executing PROC_INIT pass (extract init attributes). 24.42.16.5. Executing PROC_ARST pass (detect async resets in processes). 24.42.16.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 24.42.16.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$0ec150df0608fe9d13bbd7ba55d0b68aebde8574\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16667'. Creating decoders for process `$paramod$0ec150df0608fe9d13bbd7ba55d0b68aebde8574\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$16643'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$16641_EN[3:0]$16649 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$16641_DATA[3:0]$16647 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$16641_ADDR[3:0]$16648 Creating decoders for process `$paramod$0ec150df0608fe9d13bbd7ba55d0b68aebde8574\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$16642'. 24.42.16.8. Executing PROC_DLATCH pass (convert process syncs to latches). 24.42.16.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$0ec150df0608fe9d13bbd7ba55d0b68aebde8574\TRELLIS_DPR16X4.\i' using process `$paramod$0ec150df0608fe9d13bbd7ba55d0b68aebde8574\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16667'. created direct connection (no actual register cell created). Creating register for signal `$paramod$0ec150df0608fe9d13bbd7ba55d0b68aebde8574\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16637_EN' using process `$paramod$0ec150df0608fe9d13bbd7ba55d0b68aebde8574\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16667'. created direct connection (no actual register cell created). Creating register for signal `$paramod$0ec150df0608fe9d13bbd7ba55d0b68aebde8574\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16631_EN' using process `$paramod$0ec150df0608fe9d13bbd7ba55d0b68aebde8574\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16667'. created direct connection (no actual register cell created). Creating register for signal `$paramod$0ec150df0608fe9d13bbd7ba55d0b68aebde8574\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16636_EN' using process `$paramod$0ec150df0608fe9d13bbd7ba55d0b68aebde8574\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16667'. created direct connection (no actual register cell created). Creating register for signal `$paramod$0ec150df0608fe9d13bbd7ba55d0b68aebde8574\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16640_EN' using process `$paramod$0ec150df0608fe9d13bbd7ba55d0b68aebde8574\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16667'. created direct connection (no actual register cell created). Creating register for signal `$paramod$0ec150df0608fe9d13bbd7ba55d0b68aebde8574\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16635_EN' using process `$paramod$0ec150df0608fe9d13bbd7ba55d0b68aebde8574\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16667'. created direct connection (no actual register cell created). Creating register for signal `$paramod$0ec150df0608fe9d13bbd7ba55d0b68aebde8574\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16629_EN' using process `$paramod$0ec150df0608fe9d13bbd7ba55d0b68aebde8574\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16667'. created direct connection (no actual register cell created). Creating register for signal `$paramod$0ec150df0608fe9d13bbd7ba55d0b68aebde8574\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16639_EN' using process `$paramod$0ec150df0608fe9d13bbd7ba55d0b68aebde8574\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16667'. created direct connection (no actual register cell created). Creating register for signal `$paramod$0ec150df0608fe9d13bbd7ba55d0b68aebde8574\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16638_EN' using process `$paramod$0ec150df0608fe9d13bbd7ba55d0b68aebde8574\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16667'. created direct connection (no actual register cell created). Creating register for signal `$paramod$0ec150df0608fe9d13bbd7ba55d0b68aebde8574\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16630_EN' using process `$paramod$0ec150df0608fe9d13bbd7ba55d0b68aebde8574\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16667'. created direct connection (no actual register cell created). Creating register for signal `$paramod$0ec150df0608fe9d13bbd7ba55d0b68aebde8574\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16634_EN' using process `$paramod$0ec150df0608fe9d13bbd7ba55d0b68aebde8574\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16667'. created direct connection (no actual register cell created). Creating register for signal `$paramod$0ec150df0608fe9d13bbd7ba55d0b68aebde8574\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16633_EN' using process `$paramod$0ec150df0608fe9d13bbd7ba55d0b68aebde8574\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16667'. created direct connection (no actual register cell created). Creating register for signal `$paramod$0ec150df0608fe9d13bbd7ba55d0b68aebde8574\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16632_EN' using process `$paramod$0ec150df0608fe9d13bbd7ba55d0b68aebde8574\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16667'. created direct connection (no actual register cell created). Creating register for signal `$paramod$0ec150df0608fe9d13bbd7ba55d0b68aebde8574\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16628_EN' using process `$paramod$0ec150df0608fe9d13bbd7ba55d0b68aebde8574\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16667'. created direct connection (no actual register cell created). Creating register for signal `$paramod$0ec150df0608fe9d13bbd7ba55d0b68aebde8574\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16626_EN' using process `$paramod$0ec150df0608fe9d13bbd7ba55d0b68aebde8574\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16667'. created direct connection (no actual register cell created). Creating register for signal `$paramod$0ec150df0608fe9d13bbd7ba55d0b68aebde8574\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16625_EN' using process `$paramod$0ec150df0608fe9d13bbd7ba55d0b68aebde8574\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16667'. created direct connection (no actual register cell created). Creating register for signal `$paramod$0ec150df0608fe9d13bbd7ba55d0b68aebde8574\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16627_EN' using process `$paramod$0ec150df0608fe9d13bbd7ba55d0b68aebde8574\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16667'. created direct connection (no actual register cell created). Creating register for signal `$paramod$0ec150df0608fe9d13bbd7ba55d0b68aebde8574\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$16641_DATA' using process `$paramod$0ec150df0608fe9d13bbd7ba55d0b68aebde8574\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$16643'. created $dff cell `$procdff$16693' with positive edge clock. Creating register for signal `$paramod$0ec150df0608fe9d13bbd7ba55d0b68aebde8574\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$16641_ADDR' using process `$paramod$0ec150df0608fe9d13bbd7ba55d0b68aebde8574\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$16643'. created $dff cell `$procdff$16694' with positive edge clock. Creating register for signal `$paramod$0ec150df0608fe9d13bbd7ba55d0b68aebde8574\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$16641_EN' using process `$paramod$0ec150df0608fe9d13bbd7ba55d0b68aebde8574\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$16643'. created $dff cell `$procdff$16695' with positive edge clock. Creating register for signal `$paramod$0ec150df0608fe9d13bbd7ba55d0b68aebde8574\TRELLIS_DPR16X4.\muxwre' using process `$paramod$0ec150df0608fe9d13bbd7ba55d0b68aebde8574\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$16642'. created direct connection (no actual register cell created). 24.42.16.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 24.42.16.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$0ec150df0608fe9d13bbd7ba55d0b68aebde8574\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16667'. Found and cleaned up 1 empty switch in `$paramod$0ec150df0608fe9d13bbd7ba55d0b68aebde8574\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$16643'. Removing empty process `$paramod$0ec150df0608fe9d13bbd7ba55d0b68aebde8574\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$16642'. Cleaned up 1 empty switch. 24.42.16.12. Executing OPT_EXPR pass (perform const folding). 24.42.17. Executing PROC pass (convert processes to netlists). 24.42.17.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$3cdce45cfe40dd4cba4b9a5e0edd92348d96d81f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$16713'. Cleaned up 1 empty switch. 24.42.17.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$16714 in module $paramod$3cdce45cfe40dd4cba4b9a5e0edd92348d96d81f\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 24.42.17.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 24.42.17.4. Executing PROC_INIT pass (extract init attributes). 24.42.17.5. Executing PROC_ARST pass (detect async resets in processes). 24.42.17.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 24.42.17.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$3cdce45cfe40dd4cba4b9a5e0edd92348d96d81f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16738'. Creating decoders for process `$paramod$3cdce45cfe40dd4cba4b9a5e0edd92348d96d81f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$16714'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$16712_EN[3:0]$16718 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$16712_DATA[3:0]$16720 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$16712_ADDR[3:0]$16719 Creating decoders for process `$paramod$3cdce45cfe40dd4cba4b9a5e0edd92348d96d81f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$16713'. 24.42.17.8. Executing PROC_DLATCH pass (convert process syncs to latches). 24.42.17.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$3cdce45cfe40dd4cba4b9a5e0edd92348d96d81f\TRELLIS_DPR16X4.\i' using process `$paramod$3cdce45cfe40dd4cba4b9a5e0edd92348d96d81f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16738'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3cdce45cfe40dd4cba4b9a5e0edd92348d96d81f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16704_EN' using process `$paramod$3cdce45cfe40dd4cba4b9a5e0edd92348d96d81f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16738'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3cdce45cfe40dd4cba4b9a5e0edd92348d96d81f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16710_EN' using process `$paramod$3cdce45cfe40dd4cba4b9a5e0edd92348d96d81f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16738'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3cdce45cfe40dd4cba4b9a5e0edd92348d96d81f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16705_EN' using process `$paramod$3cdce45cfe40dd4cba4b9a5e0edd92348d96d81f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16738'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3cdce45cfe40dd4cba4b9a5e0edd92348d96d81f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16700_EN' using process `$paramod$3cdce45cfe40dd4cba4b9a5e0edd92348d96d81f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16738'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3cdce45cfe40dd4cba4b9a5e0edd92348d96d81f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16709_EN' using process `$paramod$3cdce45cfe40dd4cba4b9a5e0edd92348d96d81f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16738'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3cdce45cfe40dd4cba4b9a5e0edd92348d96d81f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16699_EN' using process `$paramod$3cdce45cfe40dd4cba4b9a5e0edd92348d96d81f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16738'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3cdce45cfe40dd4cba4b9a5e0edd92348d96d81f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16703_EN' using process `$paramod$3cdce45cfe40dd4cba4b9a5e0edd92348d96d81f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16738'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3cdce45cfe40dd4cba4b9a5e0edd92348d96d81f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16711_EN' using process `$paramod$3cdce45cfe40dd4cba4b9a5e0edd92348d96d81f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16738'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3cdce45cfe40dd4cba4b9a5e0edd92348d96d81f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16698_EN' using process `$paramod$3cdce45cfe40dd4cba4b9a5e0edd92348d96d81f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16738'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3cdce45cfe40dd4cba4b9a5e0edd92348d96d81f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16706_EN' using process `$paramod$3cdce45cfe40dd4cba4b9a5e0edd92348d96d81f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16738'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3cdce45cfe40dd4cba4b9a5e0edd92348d96d81f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16702_EN' using process `$paramod$3cdce45cfe40dd4cba4b9a5e0edd92348d96d81f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16738'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3cdce45cfe40dd4cba4b9a5e0edd92348d96d81f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16701_EN' using process `$paramod$3cdce45cfe40dd4cba4b9a5e0edd92348d96d81f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16738'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3cdce45cfe40dd4cba4b9a5e0edd92348d96d81f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16697_EN' using process `$paramod$3cdce45cfe40dd4cba4b9a5e0edd92348d96d81f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16738'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3cdce45cfe40dd4cba4b9a5e0edd92348d96d81f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16696_EN' using process `$paramod$3cdce45cfe40dd4cba4b9a5e0edd92348d96d81f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16738'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3cdce45cfe40dd4cba4b9a5e0edd92348d96d81f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16707_EN' using process `$paramod$3cdce45cfe40dd4cba4b9a5e0edd92348d96d81f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16738'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3cdce45cfe40dd4cba4b9a5e0edd92348d96d81f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16708_EN' using process `$paramod$3cdce45cfe40dd4cba4b9a5e0edd92348d96d81f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16738'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3cdce45cfe40dd4cba4b9a5e0edd92348d96d81f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$16712_EN' using process `$paramod$3cdce45cfe40dd4cba4b9a5e0edd92348d96d81f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$16714'. created $dff cell `$procdff$16764' with positive edge clock. Creating register for signal `$paramod$3cdce45cfe40dd4cba4b9a5e0edd92348d96d81f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$16712_ADDR' using process `$paramod$3cdce45cfe40dd4cba4b9a5e0edd92348d96d81f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$16714'. created $dff cell `$procdff$16765' with positive edge clock. Creating register for signal `$paramod$3cdce45cfe40dd4cba4b9a5e0edd92348d96d81f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$16712_DATA' using process `$paramod$3cdce45cfe40dd4cba4b9a5e0edd92348d96d81f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$16714'. created $dff cell `$procdff$16766' with positive edge clock. Creating register for signal `$paramod$3cdce45cfe40dd4cba4b9a5e0edd92348d96d81f\TRELLIS_DPR16X4.\muxwre' using process `$paramod$3cdce45cfe40dd4cba4b9a5e0edd92348d96d81f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$16713'. created direct connection (no actual register cell created). 24.42.17.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 24.42.17.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$3cdce45cfe40dd4cba4b9a5e0edd92348d96d81f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16738'. Found and cleaned up 1 empty switch in `$paramod$3cdce45cfe40dd4cba4b9a5e0edd92348d96d81f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$16714'. Removing empty process `$paramod$3cdce45cfe40dd4cba4b9a5e0edd92348d96d81f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$16713'. Cleaned up 1 empty switch. 24.42.17.12. Executing OPT_EXPR pass (perform const folding). 24.42.18. Executing PROC pass (convert processes to netlists). 24.42.18.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$50a3456423815ea2ad88f4cd62b0b75c0753cc69\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$16784'. Cleaned up 1 empty switch. 24.42.18.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$16785 in module $paramod$50a3456423815ea2ad88f4cd62b0b75c0753cc69\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 24.42.18.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 24.42.18.4. Executing PROC_INIT pass (extract init attributes). 24.42.18.5. Executing PROC_ARST pass (detect async resets in processes). 24.42.18.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 24.42.18.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$50a3456423815ea2ad88f4cd62b0b75c0753cc69\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16809'. Creating decoders for process `$paramod$50a3456423815ea2ad88f4cd62b0b75c0753cc69\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$16785'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$16783_EN[3:0]$16789 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$16783_DATA[3:0]$16790 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$16783_ADDR[3:0]$16791 Creating decoders for process `$paramod$50a3456423815ea2ad88f4cd62b0b75c0753cc69\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$16784'. 24.42.18.8. Executing PROC_DLATCH pass (convert process syncs to latches). 24.42.18.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$50a3456423815ea2ad88f4cd62b0b75c0753cc69\TRELLIS_DPR16X4.\i' using process `$paramod$50a3456423815ea2ad88f4cd62b0b75c0753cc69\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16809'. created direct connection (no actual register cell created). Creating register for signal `$paramod$50a3456423815ea2ad88f4cd62b0b75c0753cc69\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16780_EN' using process `$paramod$50a3456423815ea2ad88f4cd62b0b75c0753cc69\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16809'. created direct connection (no actual register cell created). Creating register for signal `$paramod$50a3456423815ea2ad88f4cd62b0b75c0753cc69\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16774_EN' using process `$paramod$50a3456423815ea2ad88f4cd62b0b75c0753cc69\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16809'. created direct connection (no actual register cell created). Creating register for signal `$paramod$50a3456423815ea2ad88f4cd62b0b75c0753cc69\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16768_EN' using process `$paramod$50a3456423815ea2ad88f4cd62b0b75c0753cc69\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16809'. created direct connection (no actual register cell created). Creating register for signal `$paramod$50a3456423815ea2ad88f4cd62b0b75c0753cc69\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16779_EN' using process `$paramod$50a3456423815ea2ad88f4cd62b0b75c0753cc69\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16809'. created direct connection (no actual register cell created). Creating register for signal `$paramod$50a3456423815ea2ad88f4cd62b0b75c0753cc69\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16778_EN' using process `$paramod$50a3456423815ea2ad88f4cd62b0b75c0753cc69\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16809'. created direct connection (no actual register cell created). Creating register for signal `$paramod$50a3456423815ea2ad88f4cd62b0b75c0753cc69\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16773_EN' using process `$paramod$50a3456423815ea2ad88f4cd62b0b75c0753cc69\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16809'. created direct connection (no actual register cell created). Creating register for signal `$paramod$50a3456423815ea2ad88f4cd62b0b75c0753cc69\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16772_EN' using process `$paramod$50a3456423815ea2ad88f4cd62b0b75c0753cc69\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16809'. created direct connection (no actual register cell created). Creating register for signal `$paramod$50a3456423815ea2ad88f4cd62b0b75c0753cc69\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16782_EN' using process `$paramod$50a3456423815ea2ad88f4cd62b0b75c0753cc69\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16809'. created direct connection (no actual register cell created). Creating register for signal `$paramod$50a3456423815ea2ad88f4cd62b0b75c0753cc69\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16781_EN' using process `$paramod$50a3456423815ea2ad88f4cd62b0b75c0753cc69\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16809'. created direct connection (no actual register cell created). Creating register for signal `$paramod$50a3456423815ea2ad88f4cd62b0b75c0753cc69\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16770_EN' using process `$paramod$50a3456423815ea2ad88f4cd62b0b75c0753cc69\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16809'. created direct connection (no actual register cell created). Creating register for signal `$paramod$50a3456423815ea2ad88f4cd62b0b75c0753cc69\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16771_EN' using process `$paramod$50a3456423815ea2ad88f4cd62b0b75c0753cc69\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16809'. created direct connection (no actual register cell created). Creating register for signal `$paramod$50a3456423815ea2ad88f4cd62b0b75c0753cc69\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16769_EN' using process `$paramod$50a3456423815ea2ad88f4cd62b0b75c0753cc69\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16809'. created direct connection (no actual register cell created). Creating register for signal `$paramod$50a3456423815ea2ad88f4cd62b0b75c0753cc69\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16775_EN' using process `$paramod$50a3456423815ea2ad88f4cd62b0b75c0753cc69\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16809'. created direct connection (no actual register cell created). Creating register for signal `$paramod$50a3456423815ea2ad88f4cd62b0b75c0753cc69\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16776_EN' using process `$paramod$50a3456423815ea2ad88f4cd62b0b75c0753cc69\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16809'. created direct connection (no actual register cell created). Creating register for signal `$paramod$50a3456423815ea2ad88f4cd62b0b75c0753cc69\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16767_EN' using process `$paramod$50a3456423815ea2ad88f4cd62b0b75c0753cc69\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16809'. created direct connection (no actual register cell created). Creating register for signal `$paramod$50a3456423815ea2ad88f4cd62b0b75c0753cc69\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16777_EN' using process `$paramod$50a3456423815ea2ad88f4cd62b0b75c0753cc69\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16809'. created direct connection (no actual register cell created). Creating register for signal `$paramod$50a3456423815ea2ad88f4cd62b0b75c0753cc69\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$16783_EN' using process `$paramod$50a3456423815ea2ad88f4cd62b0b75c0753cc69\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$16785'. created $dff cell `$procdff$16835' with positive edge clock. Creating register for signal `$paramod$50a3456423815ea2ad88f4cd62b0b75c0753cc69\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$16783_DATA' using process `$paramod$50a3456423815ea2ad88f4cd62b0b75c0753cc69\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$16785'. created $dff cell `$procdff$16836' with positive edge clock. Creating register for signal `$paramod$50a3456423815ea2ad88f4cd62b0b75c0753cc69\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$16783_ADDR' using process `$paramod$50a3456423815ea2ad88f4cd62b0b75c0753cc69\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$16785'. created $dff cell `$procdff$16837' with positive edge clock. Creating register for signal `$paramod$50a3456423815ea2ad88f4cd62b0b75c0753cc69\TRELLIS_DPR16X4.\muxwre' using process `$paramod$50a3456423815ea2ad88f4cd62b0b75c0753cc69\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$16784'. created direct connection (no actual register cell created). 24.42.18.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 24.42.18.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$50a3456423815ea2ad88f4cd62b0b75c0753cc69\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16809'. Found and cleaned up 1 empty switch in `$paramod$50a3456423815ea2ad88f4cd62b0b75c0753cc69\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$16785'. Removing empty process `$paramod$50a3456423815ea2ad88f4cd62b0b75c0753cc69\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$16784'. Cleaned up 1 empty switch. 24.42.18.12. Executing OPT_EXPR pass (perform const folding). 24.42.19. Executing PROC pass (convert processes to netlists). 24.42.19.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$55d7bec832f9f63c717e9458c8d5bd2bb91537b6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$16855'. Cleaned up 1 empty switch. 24.42.19.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$16856 in module $paramod$55d7bec832f9f63c717e9458c8d5bd2bb91537b6\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 24.42.19.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 24.42.19.4. Executing PROC_INIT pass (extract init attributes). 24.42.19.5. Executing PROC_ARST pass (detect async resets in processes). 24.42.19.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 24.42.19.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$55d7bec832f9f63c717e9458c8d5bd2bb91537b6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16880'. Creating decoders for process `$paramod$55d7bec832f9f63c717e9458c8d5bd2bb91537b6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$16856'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$16854_EN[3:0]$16862 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$16854_DATA[3:0]$16860 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$16854_ADDR[3:0]$16861 Creating decoders for process `$paramod$55d7bec832f9f63c717e9458c8d5bd2bb91537b6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$16855'. 24.42.19.8. Executing PROC_DLATCH pass (convert process syncs to latches). 24.42.19.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$55d7bec832f9f63c717e9458c8d5bd2bb91537b6\TRELLIS_DPR16X4.\i' using process `$paramod$55d7bec832f9f63c717e9458c8d5bd2bb91537b6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16880'. created direct connection (no actual register cell created). Creating register for signal `$paramod$55d7bec832f9f63c717e9458c8d5bd2bb91537b6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16849_EN' using process `$paramod$55d7bec832f9f63c717e9458c8d5bd2bb91537b6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16880'. created direct connection (no actual register cell created). Creating register for signal `$paramod$55d7bec832f9f63c717e9458c8d5bd2bb91537b6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16853_EN' using process `$paramod$55d7bec832f9f63c717e9458c8d5bd2bb91537b6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16880'. created direct connection (no actual register cell created). Creating register for signal `$paramod$55d7bec832f9f63c717e9458c8d5bd2bb91537b6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16850_EN' using process `$paramod$55d7bec832f9f63c717e9458c8d5bd2bb91537b6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16880'. created direct connection (no actual register cell created). Creating register for signal `$paramod$55d7bec832f9f63c717e9458c8d5bd2bb91537b6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16844_EN' using process `$paramod$55d7bec832f9f63c717e9458c8d5bd2bb91537b6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16880'. created direct connection (no actual register cell created). Creating register for signal `$paramod$55d7bec832f9f63c717e9458c8d5bd2bb91537b6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16852_EN' using process `$paramod$55d7bec832f9f63c717e9458c8d5bd2bb91537b6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16880'. created direct connection (no actual register cell created). Creating register for signal `$paramod$55d7bec832f9f63c717e9458c8d5bd2bb91537b6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16851_EN' using process `$paramod$55d7bec832f9f63c717e9458c8d5bd2bb91537b6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16880'. created direct connection (no actual register cell created). Creating register for signal `$paramod$55d7bec832f9f63c717e9458c8d5bd2bb91537b6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16847_EN' using process `$paramod$55d7bec832f9f63c717e9458c8d5bd2bb91537b6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16880'. created direct connection (no actual register cell created). Creating register for signal `$paramod$55d7bec832f9f63c717e9458c8d5bd2bb91537b6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16846_EN' using process `$paramod$55d7bec832f9f63c717e9458c8d5bd2bb91537b6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16880'. created direct connection (no actual register cell created). Creating register for signal `$paramod$55d7bec832f9f63c717e9458c8d5bd2bb91537b6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16845_EN' using process `$paramod$55d7bec832f9f63c717e9458c8d5bd2bb91537b6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16880'. created direct connection (no actual register cell created). Creating register for signal `$paramod$55d7bec832f9f63c717e9458c8d5bd2bb91537b6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16841_EN' using process `$paramod$55d7bec832f9f63c717e9458c8d5bd2bb91537b6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16880'. created direct connection (no actual register cell created). Creating register for signal `$paramod$55d7bec832f9f63c717e9458c8d5bd2bb91537b6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16840_EN' using process `$paramod$55d7bec832f9f63c717e9458c8d5bd2bb91537b6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16880'. created direct connection (no actual register cell created). Creating register for signal `$paramod$55d7bec832f9f63c717e9458c8d5bd2bb91537b6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16839_EN' using process `$paramod$55d7bec832f9f63c717e9458c8d5bd2bb91537b6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16880'. created direct connection (no actual register cell created). Creating register for signal `$paramod$55d7bec832f9f63c717e9458c8d5bd2bb91537b6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16838_EN' using process `$paramod$55d7bec832f9f63c717e9458c8d5bd2bb91537b6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16880'. created direct connection (no actual register cell created). Creating register for signal `$paramod$55d7bec832f9f63c717e9458c8d5bd2bb91537b6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16842_EN' using process `$paramod$55d7bec832f9f63c717e9458c8d5bd2bb91537b6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16880'. created direct connection (no actual register cell created). Creating register for signal `$paramod$55d7bec832f9f63c717e9458c8d5bd2bb91537b6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16843_EN' using process `$paramod$55d7bec832f9f63c717e9458c8d5bd2bb91537b6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16880'. created direct connection (no actual register cell created). Creating register for signal `$paramod$55d7bec832f9f63c717e9458c8d5bd2bb91537b6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16848_EN' using process `$paramod$55d7bec832f9f63c717e9458c8d5bd2bb91537b6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16880'. created direct connection (no actual register cell created). Creating register for signal `$paramod$55d7bec832f9f63c717e9458c8d5bd2bb91537b6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$16854_DATA' using process `$paramod$55d7bec832f9f63c717e9458c8d5bd2bb91537b6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$16856'. created $dff cell `$procdff$16906' with positive edge clock. Creating register for signal `$paramod$55d7bec832f9f63c717e9458c8d5bd2bb91537b6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$16854_ADDR' using process `$paramod$55d7bec832f9f63c717e9458c8d5bd2bb91537b6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$16856'. created $dff cell `$procdff$16907' with positive edge clock. Creating register for signal `$paramod$55d7bec832f9f63c717e9458c8d5bd2bb91537b6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$16854_EN' using process `$paramod$55d7bec832f9f63c717e9458c8d5bd2bb91537b6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$16856'. created $dff cell `$procdff$16908' with positive edge clock. Creating register for signal `$paramod$55d7bec832f9f63c717e9458c8d5bd2bb91537b6\TRELLIS_DPR16X4.\muxwre' using process `$paramod$55d7bec832f9f63c717e9458c8d5bd2bb91537b6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$16855'. created direct connection (no actual register cell created). 24.42.19.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 24.42.19.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$55d7bec832f9f63c717e9458c8d5bd2bb91537b6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16880'. Found and cleaned up 1 empty switch in `$paramod$55d7bec832f9f63c717e9458c8d5bd2bb91537b6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$16856'. Removing empty process `$paramod$55d7bec832f9f63c717e9458c8d5bd2bb91537b6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$16855'. Cleaned up 1 empty switch. 24.42.19.12. Executing OPT_EXPR pass (perform const folding). 24.42.20. Executing PROC pass (convert processes to netlists). 24.42.20.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$6f6b0ecb6502c3a0ff5a34ccfc87ee0dc217c0aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$16926'. Cleaned up 1 empty switch. 24.42.20.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$16927 in module $paramod$6f6b0ecb6502c3a0ff5a34ccfc87ee0dc217c0aa\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 24.42.20.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 24.42.20.4. Executing PROC_INIT pass (extract init attributes). 24.42.20.5. Executing PROC_ARST pass (detect async resets in processes). 24.42.20.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 24.42.20.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$6f6b0ecb6502c3a0ff5a34ccfc87ee0dc217c0aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16951'. Creating decoders for process `$paramod$6f6b0ecb6502c3a0ff5a34ccfc87ee0dc217c0aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$16927'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$16925_EN[3:0]$16931 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$16925_DATA[3:0]$16932 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$16925_ADDR[3:0]$16933 Creating decoders for process `$paramod$6f6b0ecb6502c3a0ff5a34ccfc87ee0dc217c0aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$16926'. 24.42.20.8. Executing PROC_DLATCH pass (convert process syncs to latches). 24.42.20.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$6f6b0ecb6502c3a0ff5a34ccfc87ee0dc217c0aa\TRELLIS_DPR16X4.\i' using process `$paramod$6f6b0ecb6502c3a0ff5a34ccfc87ee0dc217c0aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16951'. created direct connection (no actual register cell created). Creating register for signal `$paramod$6f6b0ecb6502c3a0ff5a34ccfc87ee0dc217c0aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16919_EN' using process `$paramod$6f6b0ecb6502c3a0ff5a34ccfc87ee0dc217c0aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16951'. created direct connection (no actual register cell created). Creating register for signal `$paramod$6f6b0ecb6502c3a0ff5a34ccfc87ee0dc217c0aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16924_EN' using process `$paramod$6f6b0ecb6502c3a0ff5a34ccfc87ee0dc217c0aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16951'. created direct connection (no actual register cell created). Creating register for signal `$paramod$6f6b0ecb6502c3a0ff5a34ccfc87ee0dc217c0aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16923_EN' using process `$paramod$6f6b0ecb6502c3a0ff5a34ccfc87ee0dc217c0aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16951'. created direct connection (no actual register cell created). Creating register for signal `$paramod$6f6b0ecb6502c3a0ff5a34ccfc87ee0dc217c0aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16912_EN' using process `$paramod$6f6b0ecb6502c3a0ff5a34ccfc87ee0dc217c0aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16951'. created direct connection (no actual register cell created). Creating register for signal `$paramod$6f6b0ecb6502c3a0ff5a34ccfc87ee0dc217c0aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16918_EN' using process `$paramod$6f6b0ecb6502c3a0ff5a34ccfc87ee0dc217c0aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16951'. created direct connection (no actual register cell created). Creating register for signal `$paramod$6f6b0ecb6502c3a0ff5a34ccfc87ee0dc217c0aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16922_EN' using process `$paramod$6f6b0ecb6502c3a0ff5a34ccfc87ee0dc217c0aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16951'. created direct connection (no actual register cell created). Creating register for signal `$paramod$6f6b0ecb6502c3a0ff5a34ccfc87ee0dc217c0aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16921_EN' using process `$paramod$6f6b0ecb6502c3a0ff5a34ccfc87ee0dc217c0aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16951'. created direct connection (no actual register cell created). Creating register for signal `$paramod$6f6b0ecb6502c3a0ff5a34ccfc87ee0dc217c0aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16913_EN' using process `$paramod$6f6b0ecb6502c3a0ff5a34ccfc87ee0dc217c0aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16951'. created direct connection (no actual register cell created). Creating register for signal `$paramod$6f6b0ecb6502c3a0ff5a34ccfc87ee0dc217c0aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16917_EN' using process `$paramod$6f6b0ecb6502c3a0ff5a34ccfc87ee0dc217c0aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16951'. created direct connection (no actual register cell created). Creating register for signal `$paramod$6f6b0ecb6502c3a0ff5a34ccfc87ee0dc217c0aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16916_EN' using process `$paramod$6f6b0ecb6502c3a0ff5a34ccfc87ee0dc217c0aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16951'. created direct connection (no actual register cell created). Creating register for signal `$paramod$6f6b0ecb6502c3a0ff5a34ccfc87ee0dc217c0aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16915_EN' using process `$paramod$6f6b0ecb6502c3a0ff5a34ccfc87ee0dc217c0aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16951'. created direct connection (no actual register cell created). Creating register for signal `$paramod$6f6b0ecb6502c3a0ff5a34ccfc87ee0dc217c0aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16911_EN' using process `$paramod$6f6b0ecb6502c3a0ff5a34ccfc87ee0dc217c0aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16951'. created direct connection (no actual register cell created). Creating register for signal `$paramod$6f6b0ecb6502c3a0ff5a34ccfc87ee0dc217c0aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16910_EN' using process `$paramod$6f6b0ecb6502c3a0ff5a34ccfc87ee0dc217c0aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16951'. created direct connection (no actual register cell created). Creating register for signal `$paramod$6f6b0ecb6502c3a0ff5a34ccfc87ee0dc217c0aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16909_EN' using process `$paramod$6f6b0ecb6502c3a0ff5a34ccfc87ee0dc217c0aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16951'. created direct connection (no actual register cell created). Creating register for signal `$paramod$6f6b0ecb6502c3a0ff5a34ccfc87ee0dc217c0aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16920_EN' using process `$paramod$6f6b0ecb6502c3a0ff5a34ccfc87ee0dc217c0aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16951'. created direct connection (no actual register cell created). Creating register for signal `$paramod$6f6b0ecb6502c3a0ff5a34ccfc87ee0dc217c0aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$16914_EN' using process `$paramod$6f6b0ecb6502c3a0ff5a34ccfc87ee0dc217c0aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16951'. created direct connection (no actual register cell created). Creating register for signal `$paramod$6f6b0ecb6502c3a0ff5a34ccfc87ee0dc217c0aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$16925_EN' using process `$paramod$6f6b0ecb6502c3a0ff5a34ccfc87ee0dc217c0aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$16927'. created $dff cell `$procdff$16977' with positive edge clock. Creating register for signal `$paramod$6f6b0ecb6502c3a0ff5a34ccfc87ee0dc217c0aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$16925_DATA' using process `$paramod$6f6b0ecb6502c3a0ff5a34ccfc87ee0dc217c0aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$16927'. created $dff cell `$procdff$16978' with positive edge clock. Creating register for signal `$paramod$6f6b0ecb6502c3a0ff5a34ccfc87ee0dc217c0aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$16925_ADDR' using process `$paramod$6f6b0ecb6502c3a0ff5a34ccfc87ee0dc217c0aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$16927'. created $dff cell `$procdff$16979' with positive edge clock. Creating register for signal `$paramod$6f6b0ecb6502c3a0ff5a34ccfc87ee0dc217c0aa\TRELLIS_DPR16X4.\muxwre' using process `$paramod$6f6b0ecb6502c3a0ff5a34ccfc87ee0dc217c0aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$16926'. created direct connection (no actual register cell created). 24.42.20.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 24.42.20.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$6f6b0ecb6502c3a0ff5a34ccfc87ee0dc217c0aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$16951'. Found and cleaned up 1 empty switch in `$paramod$6f6b0ecb6502c3a0ff5a34ccfc87ee0dc217c0aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$16927'. Removing empty process `$paramod$6f6b0ecb6502c3a0ff5a34ccfc87ee0dc217c0aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$16926'. Cleaned up 1 empty switch. 24.42.20.12. Executing OPT_EXPR pass (perform const folding). 24.42.21. Executing SCC pass (detecting logic loops). Found an SCC: $auto$opt_expr.cc:613:replace_const_cells$14657 $auto$ff.cc:266:slice$5778 $auto$opt_expr.cc:613:replace_const_cells$14763 $auto$ff.cc:266:slice$5781 $auto$simplemap.cc:126:simplemap_reduce$5903 $auto$simplemap.cc:126:simplemap_reduce$5888 $auto$ff.cc:266:slice$5780 $auto$simplemap.cc:75:simplemap_bitop$9504 $auto$simplemap.cc:196:simplemap_lognot$5907 $auto$simplemap.cc:126:simplemap_reduce$5905 $auto$simplemap.cc:126:simplemap_reduce$5902 $auto$opt_expr.cc:613:replace_const_cells$14821 $auto$simplemap.cc:267:simplemap_mux$9509 $auto$simplemap.cc:126:simplemap_reduce$9422 $auto$simplemap.cc:126:simplemap_reduce$9419 $auto$simplemap.cc:126:simplemap_reduce$9496 $auto$simplemap.cc:75:simplemap_bitop$9506 $auto$simplemap.cc:267:simplemap_mux$5874 $auto$simplemap.cc:225:simplemap_logbin$5877 $auto$simplemap.cc:196:simplemap_lognot$5892 $auto$simplemap.cc:126:simplemap_reduce$5890 $auto$simplemap.cc:126:simplemap_reduce$5887 $auto$ff.cc:266:slice$5779 $auto$simplemap.cc:126:simplemap_reduce$4484 $auto$simplemap.cc:126:simplemap_reduce$4482 $auto$simplemap.cc:225:simplemap_logbin$5833 $auto$simplemap.cc:196:simplemap_lognot$5843 $auto$simplemap.cc:126:simplemap_reduce$5841 $auto$opt_expr.cc:613:replace_const_cells$14823 $auto$simplemap.cc:267:simplemap_mux$9508 $auto$simplemap.cc:126:simplemap_reduce$9499 Found an SCC: $auto$simplemap.cc:38:simplemap_not$11014 $auto$ff.cc:266:slice$4899 $auto$simplemap.cc:38:simplemap_not$11013 $auto$ff.cc:266:slice$4898 $auto$simplemap.cc:126:simplemap_reduce$4556 $auto$simplemap.cc:38:simplemap_not$11012 $auto$ff.cc:266:slice$4897 $auto$simplemap.cc:38:simplemap_not$11011 $auto$ff.cc:266:slice$4896 $auto$simplemap.cc:126:simplemap_reduce$4555 $auto$simplemap.cc:38:simplemap_not$11010 $auto$ff.cc:266:slice$4895 $auto$simplemap.cc:38:simplemap_not$11008 $auto$ff.cc:266:slice$4893 $auto$simplemap.cc:38:simplemap_not$11007 $auto$ff.cc:266:slice$4892 $auto$simplemap.cc:126:simplemap_reduce$4553 $auto$simplemap.cc:38:simplemap_not$11006 $auto$ff.cc:266:slice$4891 $auto$simplemap.cc:38:simplemap_not$11005 $auto$ff.cc:266:slice$4890 $auto$simplemap.cc:126:simplemap_reduce$4565 $auto$simplemap.cc:126:simplemap_reduce$4552 $auto$simplemap.cc:38:simplemap_not$11004 $auto$ff.cc:266:slice$4889 $auto$simplemap.cc:75:simplemap_bitop$11067 $auto$simplemap.cc:38:simplemap_not$11003 $auto$ff.cc:266:slice$4888 $auto$simplemap.cc:126:simplemap_reduce$4217 $auto$simplemap.cc:75:simplemap_bitop$11066 $auto$simplemap.cc:38:simplemap_not$11002 $auto$ff.cc:266:slice$4887 $auto$simplemap.cc:75:simplemap_bitop$11065 $auto$simplemap.cc:38:simplemap_not$11001 $auto$ff.cc:266:slice$4886 $auto$simplemap.cc:126:simplemap_reduce$4230 $auto$simplemap.cc:126:simplemap_reduce$4216 $auto$simplemap.cc:75:simplemap_bitop$11064 $auto$simplemap.cc:38:simplemap_not$11000 $auto$ff.cc:266:slice$4885 $auto$simplemap.cc:75:simplemap_bitop$11063 $auto$simplemap.cc:38:simplemap_not$10999 $auto$ff.cc:266:slice$4884 $auto$simplemap.cc:126:simplemap_reduce$4215 $auto$simplemap.cc:75:simplemap_bitop$11062 $auto$simplemap.cc:38:simplemap_not$10998 $auto$ff.cc:266:slice$4883 $auto$simplemap.cc:75:simplemap_bitop$11061 $auto$simplemap.cc:38:simplemap_not$10997 $auto$ff.cc:266:slice$4882 $auto$simplemap.cc:126:simplemap_reduce$4237 $auto$simplemap.cc:126:simplemap_reduce$4229 $auto$simplemap.cc:126:simplemap_reduce$4214 $auto$simplemap.cc:75:simplemap_bitop$11060 $auto$simplemap.cc:38:simplemap_not$10996 $auto$ff.cc:266:slice$4881 $auto$simplemap.cc:75:simplemap_bitop$11053 $auto$simplemap.cc:38:simplemap_not$10989 $auto$ff.cc:266:slice$4874 $auto$simplemap.cc:75:simplemap_bitop$11054 $auto$simplemap.cc:38:simplemap_not$10990 $auto$ff.cc:266:slice$4875 $auto$simplemap.cc:126:simplemap_reduce$4211 $auto$simplemap.cc:75:simplemap_bitop$11055 $auto$simplemap.cc:38:simplemap_not$10991 $auto$ff.cc:266:slice$4876 $auto$simplemap.cc:75:simplemap_bitop$11056 $auto$simplemap.cc:38:simplemap_not$10992 $auto$ff.cc:266:slice$4877 $auto$simplemap.cc:126:simplemap_reduce$4212 $auto$simplemap.cc:75:simplemap_bitop$11057 $auto$simplemap.cc:38:simplemap_not$10993 $auto$ff.cc:266:slice$4878 $auto$simplemap.cc:75:simplemap_bitop$11058 $auto$simplemap.cc:38:simplemap_not$10994 $auto$ff.cc:266:slice$4879 $auto$simplemap.cc:126:simplemap_reduce$4227 $auto$simplemap.cc:126:simplemap_reduce$4210 $auto$simplemap.cc:75:simplemap_bitop$11052 $auto$simplemap.cc:38:simplemap_not$10988 $auto$alumacc.cc:485:replace_alu$3169.slice[4].ccu2c_i $auto$alumacc.cc:485:replace_alu$3169.slice[2].ccu2c_i $auto$alumacc.cc:485:replace_alu$3169.slice[0].ccu2c_i $auto$ff.cc:266:slice$4873 $auto$simplemap.cc:38:simplemap_not$14378 $auto$ff.cc:266:slice$4904 $auto$simplemap.cc:126:simplemap_reduce$4559 $auto$simplemap.cc:38:simplemap_not$11018 $auto$ff.cc:266:slice$4903 $auto$simplemap.cc:38:simplemap_not$11017 $auto$ff.cc:266:slice$4902 $auto$simplemap.cc:126:simplemap_reduce$4568 $auto$simplemap.cc:126:simplemap_reduce$4558 $auto$simplemap.cc:38:simplemap_not$11016 $auto$ff.cc:266:slice$4901 $auto$alumacc.cc:485:replace_alu$3169.slice[18].ccu2c_i $auto$alumacc.cc:485:replace_alu$3169.slice[16].ccu2c_i $auto$alumacc.cc:485:replace_alu$3169.slice[14].ccu2c_i $auto$alumacc.cc:485:replace_alu$3169.slice[12].ccu2c_i $auto$alumacc.cc:485:replace_alu$3169.slice[10].ccu2c_i $auto$alumacc.cc:485:replace_alu$3169.slice[8].ccu2c_i $auto$alumacc.cc:485:replace_alu$3169.slice[6].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$4241 $auto$simplemap.cc:126:simplemap_reduce$4236 $auto$simplemap.cc:126:simplemap_reduce$4228 $auto$simplemap.cc:126:simplemap_reduce$4213 $auto$simplemap.cc:75:simplemap_bitop$11059 $auto$simplemap.cc:38:simplemap_not$10995 $auto$ff.cc:266:slice$4880 $auto$alumacc.cc:485:replace_alu$3169.slice[24].ccu2c_i $auto$alumacc.cc:485:replace_alu$3169.slice[22].ccu2c_i $auto$alumacc.cc:485:replace_alu$3169.slice[20].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$4572 $auto$simplemap.cc:126:simplemap_reduce$4566 $auto$simplemap.cc:126:simplemap_reduce$4554 $auto$simplemap.cc:38:simplemap_not$11009 $auto$ff.cc:266:slice$4894 $auto$simplemap.cc:38:simplemap_not$4245 $auto$alumacc.cc:485:replace_alu$3169.slice[30].ccu2c_i $auto$alumacc.cc:485:replace_alu$3169.slice[28].ccu2c_i $auto$alumacc.cc:485:replace_alu$3169.slice[26].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$4244 $auto$simplemap.cc:126:simplemap_reduce$4576 $auto$simplemap.cc:126:simplemap_reduce$4573 $auto$simplemap.cc:126:simplemap_reduce$4567 $auto$simplemap.cc:126:simplemap_reduce$4557 $auto$simplemap.cc:38:simplemap_not$11015 $auto$ff.cc:266:slice$4900 $auto$simplemap.cc:126:simplemap_reduce$4043 $auto$simplemap.cc:75:simplemap_bitop$4246 Found an SCC: $auto$simplemap.cc:75:simplemap_bitop$10621 $auto$opt_expr.cc:613:replace_const_cells$14835 $auto$ff.cc:266:slice$5276 $auto$simplemap.cc:38:simplemap_not$10738 $auto$ff.cc:266:slice$5297 $auto$simplemap.cc:75:simplemap_bitop$10624 $auto$simplemap.cc:38:simplemap_not$10720 $auto$ff.cc:266:slice$5279 $auto$simplemap.cc:75:simplemap_bitop$10625 $auto$simplemap.cc:38:simplemap_not$10721 $auto$ff.cc:266:slice$5280 $auto$alumacc.cc:485:replace_alu$3147.slice[0].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$6636 $auto$simplemap.cc:75:simplemap_bitop$10622 $auto$simplemap.cc:38:simplemap_not$10718 $auto$ff.cc:266:slice$5277 $auto$simplemap.cc:75:simplemap_bitop$10628 $auto$simplemap.cc:38:simplemap_not$10724 $auto$ff.cc:266:slice$5283 $auto$simplemap.cc:126:simplemap_reduce$6639 $auto$simplemap.cc:75:simplemap_bitop$10627 $auto$simplemap.cc:38:simplemap_not$10723 $auto$ff.cc:266:slice$5282 $auto$simplemap.cc:38:simplemap_not$10588 $auto$ff.cc:266:slice$5307 $auto$simplemap.cc:126:simplemap_reduce$6651 $auto$simplemap.cc:38:simplemap_not$10747 $auto$ff.cc:266:slice$5306 $auto$simplemap.cc:38:simplemap_not$10746 $auto$ff.cc:266:slice$5305 $auto$simplemap.cc:126:simplemap_reduce$6660 $auto$simplemap.cc:126:simplemap_reduce$6650 $auto$simplemap.cc:38:simplemap_not$10745 $auto$ff.cc:266:slice$5304 $auto$simplemap.cc:38:simplemap_not$10744 $auto$ff.cc:266:slice$5303 $auto$simplemap.cc:126:simplemap_reduce$6654 $auto$simplemap.cc:126:simplemap_reduce$6638 $auto$simplemap.cc:75:simplemap_bitop$10626 $auto$simplemap.cc:38:simplemap_not$10722 $auto$ff.cc:266:slice$5281 $auto$ff.cc:266:slice$5302 $auto$simplemap.cc:38:simplemap_not$10742 $auto$ff.cc:266:slice$5301 $auto$simplemap.cc:38:simplemap_not$10740 $auto$ff.cc:266:slice$5299 $auto$simplemap.cc:126:simplemap_reduce$6647 $auto$simplemap.cc:38:simplemap_not$10739 $auto$ff.cc:266:slice$5298 $auto$simplemap.cc:75:simplemap_bitop$10636 $auto$simplemap.cc:38:simplemap_not$10732 $auto$ff.cc:266:slice$5291 $auto$simplemap.cc:126:simplemap_reduce$6643 $auto$simplemap.cc:75:simplemap_bitop$10635 $auto$simplemap.cc:38:simplemap_not$10731 $auto$ff.cc:266:slice$5290 $auto$simplemap.cc:75:simplemap_bitop$10634 $auto$simplemap.cc:38:simplemap_not$10730 $auto$ff.cc:266:slice$5289 $auto$alumacc.cc:485:replace_alu$3147.slice[6].ccu2c_i $auto$alumacc.cc:485:replace_alu$3147.slice[4].ccu2c_i $auto$alumacc.cc:485:replace_alu$3147.slice[2].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$6662 $auto$simplemap.cc:126:simplemap_reduce$6653 $auto$simplemap.cc:126:simplemap_reduce$6637 $auto$simplemap.cc:75:simplemap_bitop$10623 $auto$simplemap.cc:38:simplemap_not$10719 $auto$ff.cc:266:slice$5278 $auto$simplemap.cc:126:simplemap_reduce$6656 $auto$simplemap.cc:126:simplemap_reduce$6642 $auto$simplemap.cc:75:simplemap_bitop$10633 $auto$simplemap.cc:38:simplemap_not$10729 $auto$ff.cc:266:slice$5288 $auto$simplemap.cc:75:simplemap_bitop$10632 $auto$simplemap.cc:38:simplemap_not$10728 $auto$ff.cc:266:slice$5287 $auto$simplemap.cc:126:simplemap_reduce$6641 $auto$simplemap.cc:75:simplemap_bitop$10631 $auto$simplemap.cc:38:simplemap_not$10727 $auto$ff.cc:266:slice$5286 $auto$simplemap.cc:75:simplemap_bitop$10630 $auto$simplemap.cc:38:simplemap_not$10726 $auto$ff.cc:266:slice$5285 $auto$simplemap.cc:38:simplemap_not$10733 $auto$ff.cc:266:slice$5292 $auto$alumacc.cc:485:replace_alu$3147.slice[14].ccu2c_i $auto$alumacc.cc:485:replace_alu$3147.slice[12].ccu2c_i $auto$alumacc.cc:485:replace_alu$3147.slice[10].ccu2c_i $auto$alumacc.cc:485:replace_alu$3147.slice[8].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$6667 $auto$simplemap.cc:126:simplemap_reduce$6663 $auto$simplemap.cc:126:simplemap_reduce$6655 $auto$simplemap.cc:126:simplemap_reduce$6640 $auto$simplemap.cc:75:simplemap_bitop$10629 $auto$simplemap.cc:38:simplemap_not$10725 $auto$ff.cc:266:slice$5284 $auto$alumacc.cc:485:replace_alu$3147.slice[16].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$6644 $auto$simplemap.cc:38:simplemap_not$10734 $auto$ff.cc:266:slice$5293 $auto$simplemap.cc:38:simplemap_not$10735 $auto$ff.cc:266:slice$5294 $auto$simplemap.cc:126:simplemap_reduce$6658 $auto$simplemap.cc:126:simplemap_reduce$6646 $auto$simplemap.cc:38:simplemap_not$10737 $auto$ff.cc:266:slice$5296 $auto$simplemap.cc:126:simplemap_reduce$6648 $auto$simplemap.cc:38:simplemap_not$10741 $auto$ff.cc:266:slice$5300 $auto$simplemap.cc:38:simplemap_not$6671 $auto$alumacc.cc:485:replace_alu$3147.slice[30].ccu2c_i $auto$alumacc.cc:485:replace_alu$3147.slice[28].ccu2c_i $auto$alumacc.cc:485:replace_alu$3147.slice[26].ccu2c_i $auto$alumacc.cc:485:replace_alu$3147.slice[24].ccu2c_i $auto$alumacc.cc:485:replace_alu$3147.slice[22].ccu2c_i $auto$alumacc.cc:485:replace_alu$3147.slice[20].ccu2c_i $auto$alumacc.cc:485:replace_alu$3147.slice[18].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$6664 $auto$simplemap.cc:126:simplemap_reduce$6657 $auto$simplemap.cc:126:simplemap_reduce$6645 $auto$simplemap.cc:38:simplemap_not$10736 $auto$ff.cc:266:slice$5295 $auto$simplemap.cc:126:simplemap_reduce$4041 $auto$simplemap.cc:75:simplemap_bitop$6365 $auto$simplemap.cc:126:simplemap_reduce$6670 $auto$simplemap.cc:126:simplemap_reduce$6668 $auto$simplemap.cc:126:simplemap_reduce$6665 $auto$simplemap.cc:126:simplemap_reduce$6659 $auto$simplemap.cc:126:simplemap_reduce$6649 $auto$simplemap.cc:38:simplemap_not$10743 Found an SCC: $auto$ff.cc:266:slice$3754 $auto$dfflegalize.cc:941:flip_pol$14991 $auto$ff.cc:485:convert_ce_over_srst$14989 $auto$opt_expr.cc:613:replace_const_cells$14833 $auto$ff.cc:266:slice$3752 $auto$dfflegalize.cc:941:flip_pol$14983 $auto$ff.cc:485:convert_ce_over_srst$14981 $auto$simplemap.cc:126:simplemap_reduce$4451 $auto$simplemap.cc:126:simplemap_reduce$4442 $auto$simplemap.cc:126:simplemap_reduce$4412 $auto$simplemap.cc:126:simplemap_reduce$4410 $auto$opt_expr.cc:613:replace_const_cells$14879 $auto$simplemap.cc:126:simplemap_reduce$4030 $auto$simplemap.cc:126:simplemap_reduce$4027 $auto$simplemap.cc:126:simplemap_reduce$4419 $auto$simplemap.cc:126:simplemap_reduce$4952 $auto$simplemap.cc:126:simplemap_reduce$4950 $auto$ff.cc:266:slice$3753 $auto$dfflegalize.cc:941:flip_pol$14987 $auto$ff.cc:485:convert_ce_over_srst$14985 $auto$simplemap.cc:126:simplemap_reduce$4032 $auto$simplemap.cc:126:simplemap_reduce$4612 $auto$simplemap.cc:126:simplemap_reduce$4444 Found an SCC: $auto$simplemap.cc:38:simplemap_not$11313 $auto$ff.cc:266:slice$4521 $auto$ff.cc:479:convert_ce_over_srst$15003 $auto$ff.cc:266:slice$4518 $auto$ff.cc:479:convert_ce_over_srst$14997 $auto$simplemap.cc:126:simplemap_reduce$4116 $auto$ff.cc:266:slice$4520 $auto$ff.cc:479:convert_ce_over_srst$15001 $auto$simplemap.cc:38:simplemap_not$11309 $auto$ff.cc:266:slice$4517 $auto$ff.cc:479:convert_ce_over_srst$14995 $auto$simplemap.cc:126:simplemap_reduce$4114 $auto$simplemap.cc:38:simplemap_not$11308 $auto$simplemap.cc:126:simplemap_reduce$4102 $auto$simplemap.cc:38:simplemap_not$4161 $auto$simplemap.cc:75:simplemap_bitop$4162 $auto$simplemap.cc:38:simplemap_not$4121 $auto$alumacc.cc:485:replace_alu$3180.slice[4].ccu2c_i $auto$alumacc.cc:485:replace_alu$3180.slice[2].ccu2c_i $auto$alumacc.cc:485:replace_alu$3180.slice[0].ccu2c_i $auto$ff.cc:266:slice$4516 $auto$ff.cc:479:convert_ce_over_srst$14993 $auto$simplemap.cc:126:simplemap_reduce$4250 $auto$simplemap.cc:126:simplemap_reduce$4248 $auto$simplemap.cc:126:simplemap_reduce$4104 $auto$simplemap.cc:126:simplemap_reduce$4101 $auto$simplemap.cc:126:simplemap_reduce$4120 $auto$simplemap.cc:126:simplemap_reduce$4118 $auto$simplemap.cc:126:simplemap_reduce$4115 $auto$simplemap.cc:38:simplemap_not$11311 $auto$ff.cc:266:slice$4519 $auto$ff.cc:479:convert_ce_over_srst$14999 $auto$simplemap.cc:126:simplemap_reduce$4265 Found an SCC: $auto$opt_expr.cc:613:replace_const_cells$14725 $auto$ff.cc:266:slice$5782 $auto$simplemap.cc:38:simplemap_not$9391 $auto$ff.cc:266:slice$5785 $auto$simplemap.cc:126:simplemap_reduce$5923 $auto$ff.cc:266:slice$5784 $auto$simplemap.cc:126:simplemap_reduce$5927 $auto$simplemap.cc:126:simplemap_reduce$5922 $auto$ff.cc:266:slice$5783 $auto$ff.cc:266:slice$5786 $auto$simplemap.cc:38:simplemap_not$9394 $auto$ff.cc:266:slice$5788 $auto$ff.cc:266:slice$5787 $auto$simplemap.cc:126:simplemap_reduce$5925 $auto$simplemap.cc:38:simplemap_not$9395 $auto$ff.cc:266:slice$5789 $auto$ff.cc:266:slice$5790 $auto$simplemap.cc:126:simplemap_reduce$4478 $auto$simplemap.cc:196:simplemap_lognot$5934 $auto$simplemap.cc:126:simplemap_reduce$5932 $auto$simplemap.cc:126:simplemap_reduce$5930 $auto$simplemap.cc:126:simplemap_reduce$5928 $auto$simplemap.cc:126:simplemap_reduce$5924 $auto$simplemap.cc:38:simplemap_not$9392 Found an SCC: $auto$opt_expr.cc:613:replace_const_cells$14659 $auto$ff.cc:266:slice$5644 $auto$simplemap.cc:126:simplemap_reduce$5761 $auto$simplemap.cc:38:simplemap_not$9585 $auto$ff.cc:266:slice$5640 $auto$opt_expr.cc:613:replace_const_cells$14487 $auto$ff.cc:266:slice$5643 $auto$ff.cc:266:slice$5639 $auto$ff.cc:266:slice$5641 $auto$simplemap.cc:126:simplemap_reduce$5762 $auto$opt_expr.cc:613:replace_const_cells$14663 $auto$simplemap.cc:126:simplemap_reduce$5735 $auto$ff.cc:266:slice$5642 $auto$ff.cc:266:slice$5646 $auto$simplemap.cc:126:simplemap_reduce$5766 $auto$simplemap.cc:126:simplemap_reduce$5763 $auto$opt_expr.cc:613:replace_const_cells$14661 $auto$simplemap.cc:126:simplemap_reduce$5739 $auto$simplemap.cc:126:simplemap_reduce$5736 $auto$ff.cc:266:slice$5645 $auto$simplemap.cc:196:simplemap_lognot$5772 $auto$simplemap.cc:126:simplemap_reduce$5770 $auto$simplemap.cc:126:simplemap_reduce$5768 $auto$simplemap.cc:126:simplemap_reduce$5765 $auto$simplemap.cc:126:simplemap_reduce$5760 $auto$simplemap.cc:38:simplemap_not$9583 $auto$simplemap.cc:126:simplemap_reduce$5733 $auto$ff.cc:266:slice$5638 $auto$simplemap.cc:167:logic_reduce$4489 $auto$simplemap.cc:225:simplemap_logbin$5717 $auto$simplemap.cc:225:simplemap_logbin$5718 $auto$simplemap.cc:196:simplemap_lognot$5745 $auto$simplemap.cc:126:simplemap_reduce$5743 $auto$simplemap.cc:126:simplemap_reduce$5741 $auto$simplemap.cc:126:simplemap_reduce$5738 $auto$simplemap.cc:126:simplemap_reduce$5734 $auto$simplemap.cc:38:simplemap_not$9586 Found 7 SCCs in module top. Found 7 SCCs. 24.42.22. Executing ABC9_OPS pass (helper functions for ABC9). 24.42.23. Executing PROC pass (convert processes to netlists). 24.42.23.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 24.42.23.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 24.42.23.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 0 assignments to connections. 24.42.23.4. Executing PROC_INIT pass (extract init attributes). 24.42.23.5. Executing PROC_ARST pass (detect async resets in processes). 24.42.23.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 24.42.23.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 24.42.23.8. Executing PROC_DLATCH pass (convert process syncs to latches). 24.42.23.9. Executing PROC_DFF pass (convert process syncs to FFs). 24.42.23.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 24.42.23.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 24.42.23.12. Executing OPT_EXPR pass (perform const folding). 24.42.24. Executing TECHMAP pass (map to technology primitives). 24.42.24.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/techmap.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu_brent_kung'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `\$__div_mod_u'. Generating RTLIL representation for module `\$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `\$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_pmux'. Generating RTLIL representation for module `\_90_demux'. Generating RTLIL representation for module `\_90_lut'. Successfully finished Verilog frontend. 24.42.24.2. Continuing TECHMAP pass. No more expansions possible. <suppressed ~196 debug messages> 24.42.25. Executing OPT pass (performing simple optimizations). 24.42.25.1. Executing OPT_EXPR pass (perform const folding). Optimizing module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4. Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. Optimizing module $paramod$240b3d214c7091ed87f7feed01a813ca9ca1b727\TRELLIS_DPR16X4. Optimizing module $paramod$54859518bee4eabb76b31063a8cd09e44ba7903d\TRELLIS_DPR16X4. Optimizing module $paramod$c58b622e748098fb95d7cce3391b5b90d49d749c\TRELLIS_DPR16X4. Optimizing module $paramod$4a126fa1688fbcbb97471f2a58f335ad46a1b683\TRELLIS_DPR16X4. Optimizing module $paramod$3fea245e43c817e3ab409ba408c64d50b3c3410d\TRELLIS_DPR16X4. Optimizing module $paramod$828eab860e7ad1344f71b7dcac93a993e09abfc2\TRELLIS_DPR16X4. Optimizing module $paramod$b4055cc4c76830d75a5da93152e34111ac58d5fb\TRELLIS_DPR16X4. Optimizing module $paramod$28331dd642fda78247f997daeb218f7111f59a79\TRELLIS_DPR16X4. Optimizing module $paramod$242712b50c0a2a6b7d501d3b8f15d1e042886c7d\TRELLIS_DPR16X4. Optimizing module $paramod$896c13102149326c20257183c5d146c2879d74e6\TRELLIS_DPR16X4. Optimizing module $paramod$53a840446cdc2b5aa298a080f49764e881c60b99\TRELLIS_DPR16X4. Optimizing module $paramod$0ec150df0608fe9d13bbd7ba55d0b68aebde8574\TRELLIS_DPR16X4. Optimizing module $paramod$3cdce45cfe40dd4cba4b9a5e0edd92348d96d81f\TRELLIS_DPR16X4. Optimizing module $paramod$50a3456423815ea2ad88f4cd62b0b75c0753cc69\TRELLIS_DPR16X4. Optimizing module $paramod$55d7bec832f9f63c717e9458c8d5bd2bb91537b6\TRELLIS_DPR16X4. Optimizing module $paramod$6f6b0ecb6502c3a0ff5a34ccfc87ee0dc217c0aa\TRELLIS_DPR16X4. 24.42.25.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$240b3d214c7091ed87f7feed01a813ca9ca1b727\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$54859518bee4eabb76b31063a8cd09e44ba7903d\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$c58b622e748098fb95d7cce3391b5b90d49d749c\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$4a126fa1688fbcbb97471f2a58f335ad46a1b683\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$3fea245e43c817e3ab409ba408c64d50b3c3410d\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$828eab860e7ad1344f71b7dcac93a993e09abfc2\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$b4055cc4c76830d75a5da93152e34111ac58d5fb\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$28331dd642fda78247f997daeb218f7111f59a79\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$242712b50c0a2a6b7d501d3b8f15d1e042886c7d\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$896c13102149326c20257183c5d146c2879d74e6\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$53a840446cdc2b5aa298a080f49764e881c60b99\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$0ec150df0608fe9d13bbd7ba55d0b68aebde8574\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$3cdce45cfe40dd4cba4b9a5e0edd92348d96d81f\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$50a3456423815ea2ad88f4cd62b0b75c0753cc69\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$55d7bec832f9f63c717e9458c8d5bd2bb91537b6\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$6f6b0ecb6502c3a0ff5a34ccfc87ee0dc217c0aa\TRELLIS_DPR16X4'. Removed a total of 0 cells. 24.42.25.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$240b3d214c7091ed87f7feed01a813ca9ca1b727\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$54859518bee4eabb76b31063a8cd09e44ba7903d\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$c58b622e748098fb95d7cce3391b5b90d49d749c\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$4a126fa1688fbcbb97471f2a58f335ad46a1b683\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$3fea245e43c817e3ab409ba408c64d50b3c3410d\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$828eab860e7ad1344f71b7dcac93a993e09abfc2\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$b4055cc4c76830d75a5da93152e34111ac58d5fb\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$28331dd642fda78247f997daeb218f7111f59a79\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$242712b50c0a2a6b7d501d3b8f15d1e042886c7d\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$896c13102149326c20257183c5d146c2879d74e6\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$53a840446cdc2b5aa298a080f49764e881c60b99\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$0ec150df0608fe9d13bbd7ba55d0b68aebde8574\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$3cdce45cfe40dd4cba4b9a5e0edd92348d96d81f\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$50a3456423815ea2ad88f4cd62b0b75c0753cc69\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$55d7bec832f9f63c717e9458c8d5bd2bb91537b6\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$6f6b0ecb6502c3a0ff5a34ccfc87ee0dc217c0aa\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 24.42.25.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4. Optimizing cells in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. Optimizing cells in module $paramod$240b3d214c7091ed87f7feed01a813ca9ca1b727\TRELLIS_DPR16X4. Optimizing cells in module $paramod$54859518bee4eabb76b31063a8cd09e44ba7903d\TRELLIS_DPR16X4. Optimizing cells in module $paramod$c58b622e748098fb95d7cce3391b5b90d49d749c\TRELLIS_DPR16X4. Optimizing cells in module $paramod$4a126fa1688fbcbb97471f2a58f335ad46a1b683\TRELLIS_DPR16X4. Optimizing cells in module $paramod$3fea245e43c817e3ab409ba408c64d50b3c3410d\TRELLIS_DPR16X4. Optimizing cells in module $paramod$828eab860e7ad1344f71b7dcac93a993e09abfc2\TRELLIS_DPR16X4. Optimizing cells in module $paramod$b4055cc4c76830d75a5da93152e34111ac58d5fb\TRELLIS_DPR16X4. Optimizing cells in module $paramod$28331dd642fda78247f997daeb218f7111f59a79\TRELLIS_DPR16X4. Optimizing cells in module $paramod$242712b50c0a2a6b7d501d3b8f15d1e042886c7d\TRELLIS_DPR16X4. Optimizing cells in module $paramod$896c13102149326c20257183c5d146c2879d74e6\TRELLIS_DPR16X4. Optimizing cells in module $paramod$53a840446cdc2b5aa298a080f49764e881c60b99\TRELLIS_DPR16X4. Optimizing cells in module $paramod$0ec150df0608fe9d13bbd7ba55d0b68aebde8574\TRELLIS_DPR16X4. Optimizing cells in module $paramod$3cdce45cfe40dd4cba4b9a5e0edd92348d96d81f\TRELLIS_DPR16X4. Optimizing cells in module $paramod$50a3456423815ea2ad88f4cd62b0b75c0753cc69\TRELLIS_DPR16X4. Optimizing cells in module $paramod$55d7bec832f9f63c717e9458c8d5bd2bb91537b6\TRELLIS_DPR16X4. Optimizing cells in module $paramod$6f6b0ecb6502c3a0ff5a34ccfc87ee0dc217c0aa\TRELLIS_DPR16X4. Performed a total of 0 changes. 24.42.25.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$240b3d214c7091ed87f7feed01a813ca9ca1b727\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$54859518bee4eabb76b31063a8cd09e44ba7903d\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$c58b622e748098fb95d7cce3391b5b90d49d749c\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$4a126fa1688fbcbb97471f2a58f335ad46a1b683\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$3fea245e43c817e3ab409ba408c64d50b3c3410d\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$828eab860e7ad1344f71b7dcac93a993e09abfc2\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$b4055cc4c76830d75a5da93152e34111ac58d5fb\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$28331dd642fda78247f997daeb218f7111f59a79\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$242712b50c0a2a6b7d501d3b8f15d1e042886c7d\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$896c13102149326c20257183c5d146c2879d74e6\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$53a840446cdc2b5aa298a080f49764e881c60b99\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$0ec150df0608fe9d13bbd7ba55d0b68aebde8574\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$3cdce45cfe40dd4cba4b9a5e0edd92348d96d81f\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$50a3456423815ea2ad88f4cd62b0b75c0753cc69\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$55d7bec832f9f63c717e9458c8d5bd2bb91537b6\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$6f6b0ecb6502c3a0ff5a34ccfc87ee0dc217c0aa\TRELLIS_DPR16X4'. Removed a total of 0 cells. 24.42.25.6. Executing OPT_DFF pass (perform DFF optimizations). 24.42.25.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$240b3d214c7091ed87f7feed01a813ca9ca1b727\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$54859518bee4eabb76b31063a8cd09e44ba7903d\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$c58b622e748098fb95d7cce3391b5b90d49d749c\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$4a126fa1688fbcbb97471f2a58f335ad46a1b683\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$3fea245e43c817e3ab409ba408c64d50b3c3410d\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$828eab860e7ad1344f71b7dcac93a993e09abfc2\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$b4055cc4c76830d75a5da93152e34111ac58d5fb\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$28331dd642fda78247f997daeb218f7111f59a79\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$242712b50c0a2a6b7d501d3b8f15d1e042886c7d\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$896c13102149326c20257183c5d146c2879d74e6\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$53a840446cdc2b5aa298a080f49764e881c60b99\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$0ec150df0608fe9d13bbd7ba55d0b68aebde8574\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$3cdce45cfe40dd4cba4b9a5e0edd92348d96d81f\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$50a3456423815ea2ad88f4cd62b0b75c0753cc69\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$55d7bec832f9f63c717e9458c8d5bd2bb91537b6\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$6f6b0ecb6502c3a0ff5a34ccfc87ee0dc217c0aa\TRELLIS_DPR16X4.. 24.42.25.8. Executing OPT_EXPR pass (perform const folding). Optimizing module $paramod$0ec150df0608fe9d13bbd7ba55d0b68aebde8574\TRELLIS_DPR16X4. Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. Optimizing module $paramod$240b3d214c7091ed87f7feed01a813ca9ca1b727\TRELLIS_DPR16X4. Optimizing module $paramod$242712b50c0a2a6b7d501d3b8f15d1e042886c7d\TRELLIS_DPR16X4. Optimizing module $paramod$28331dd642fda78247f997daeb218f7111f59a79\TRELLIS_DPR16X4. Optimizing module $paramod$3cdce45cfe40dd4cba4b9a5e0edd92348d96d81f\TRELLIS_DPR16X4. Optimizing module $paramod$3fea245e43c817e3ab409ba408c64d50b3c3410d\TRELLIS_DPR16X4. Optimizing module $paramod$4a126fa1688fbcbb97471f2a58f335ad46a1b683\TRELLIS_DPR16X4. Optimizing module $paramod$50a3456423815ea2ad88f4cd62b0b75c0753cc69\TRELLIS_DPR16X4. Optimizing module $paramod$53a840446cdc2b5aa298a080f49764e881c60b99\TRELLIS_DPR16X4. Optimizing module $paramod$54859518bee4eabb76b31063a8cd09e44ba7903d\TRELLIS_DPR16X4. Optimizing module $paramod$55d7bec832f9f63c717e9458c8d5bd2bb91537b6\TRELLIS_DPR16X4. Optimizing module $paramod$6f6b0ecb6502c3a0ff5a34ccfc87ee0dc217c0aa\TRELLIS_DPR16X4. Optimizing module $paramod$828eab860e7ad1344f71b7dcac93a993e09abfc2\TRELLIS_DPR16X4. Optimizing module $paramod$896c13102149326c20257183c5d146c2879d74e6\TRELLIS_DPR16X4. Optimizing module $paramod$b4055cc4c76830d75a5da93152e34111ac58d5fb\TRELLIS_DPR16X4. Optimizing module $paramod$c58b622e748098fb95d7cce3391b5b90d49d749c\TRELLIS_DPR16X4. Optimizing module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4. 24.42.25.9. Finished OPT passes. (There is nothing left to do.) 24.42.26. Executing TECHMAP pass (map to technology primitives). 24.42.26.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/abc9_map.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/abc9_map.v' to AST representation. Successfully finished Verilog frontend. 24.42.26.2. Continuing TECHMAP pass. Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. Using template $paramod$3cdce45cfe40dd4cba4b9a5e0edd92348d96d81f\TRELLIS_DPR16X4 for cells of type $paramod$3cdce45cfe40dd4cba4b9a5e0edd92348d96d81f\TRELLIS_DPR16X4. Using template $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4 for cells of type $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4. Using template $paramod$c58b622e748098fb95d7cce3391b5b90d49d749c\TRELLIS_DPR16X4 for cells of type $paramod$c58b622e748098fb95d7cce3391b5b90d49d749c\TRELLIS_DPR16X4. Using template $paramod$240b3d214c7091ed87f7feed01a813ca9ca1b727\TRELLIS_DPR16X4 for cells of type $paramod$240b3d214c7091ed87f7feed01a813ca9ca1b727\TRELLIS_DPR16X4. Using template $paramod$50a3456423815ea2ad88f4cd62b0b75c0753cc69\TRELLIS_DPR16X4 for cells of type $paramod$50a3456423815ea2ad88f4cd62b0b75c0753cc69\TRELLIS_DPR16X4. Using template $paramod$55d7bec832f9f63c717e9458c8d5bd2bb91537b6\TRELLIS_DPR16X4 for cells of type $paramod$55d7bec832f9f63c717e9458c8d5bd2bb91537b6\TRELLIS_DPR16X4. Using template $paramod$53a840446cdc2b5aa298a080f49764e881c60b99\TRELLIS_DPR16X4 for cells of type $paramod$53a840446cdc2b5aa298a080f49764e881c60b99\TRELLIS_DPR16X4. Using template $paramod$0ec150df0608fe9d13bbd7ba55d0b68aebde8574\TRELLIS_DPR16X4 for cells of type $paramod$0ec150df0608fe9d13bbd7ba55d0b68aebde8574\TRELLIS_DPR16X4. Using template $paramod$896c13102149326c20257183c5d146c2879d74e6\TRELLIS_DPR16X4 for cells of type $paramod$896c13102149326c20257183c5d146c2879d74e6\TRELLIS_DPR16X4. Using template $paramod$242712b50c0a2a6b7d501d3b8f15d1e042886c7d\TRELLIS_DPR16X4 for cells of type $paramod$242712b50c0a2a6b7d501d3b8f15d1e042886c7d\TRELLIS_DPR16X4. Using template $paramod$3fea245e43c817e3ab409ba408c64d50b3c3410d\TRELLIS_DPR16X4 for cells of type $paramod$3fea245e43c817e3ab409ba408c64d50b3c3410d\TRELLIS_DPR16X4. Using template $paramod$4a126fa1688fbcbb97471f2a58f335ad46a1b683\TRELLIS_DPR16X4 for cells of type $paramod$4a126fa1688fbcbb97471f2a58f335ad46a1b683\TRELLIS_DPR16X4. Using template $paramod$b4055cc4c76830d75a5da93152e34111ac58d5fb\TRELLIS_DPR16X4 for cells of type $paramod$b4055cc4c76830d75a5da93152e34111ac58d5fb\TRELLIS_DPR16X4. Using template $paramod$828eab860e7ad1344f71b7dcac93a993e09abfc2\TRELLIS_DPR16X4 for cells of type $paramod$828eab860e7ad1344f71b7dcac93a993e09abfc2\TRELLIS_DPR16X4. Using template $paramod$54859518bee4eabb76b31063a8cd09e44ba7903d\TRELLIS_DPR16X4 for cells of type $paramod$54859518bee4eabb76b31063a8cd09e44ba7903d\TRELLIS_DPR16X4. Using template $paramod$28331dd642fda78247f997daeb218f7111f59a79\TRELLIS_DPR16X4 for cells of type $paramod$28331dd642fda78247f997daeb218f7111f59a79\TRELLIS_DPR16X4. Using template $paramod$6f6b0ecb6502c3a0ff5a34ccfc87ee0dc217c0aa\TRELLIS_DPR16X4 for cells of type $paramod$6f6b0ecb6502c3a0ff5a34ccfc87ee0dc217c0aa\TRELLIS_DPR16X4. No more expansions possible. <suppressed ~72 debug messages> 24.42.27. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/abc9_model.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/abc9_model.v' to AST representation. Generating RTLIL representation for module `$__ABC9_DELAY'. Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'. Generating RTLIL representation for module `$__DFF_N__$abc9_flop'. Generating RTLIL representation for module `$__DFF_P__$abc9_flop'. Successfully finished Verilog frontend. 24.42.28. Executing ABC9_OPS pass (helper functions for ABC9). <suppressed ~2 debug messages> 24.42.29. Executing ABC9_OPS pass (helper functions for ABC9). 24.42.30. Executing ABC9_OPS pass (helper functions for ABC9). <suppressed ~2 debug messages> 24.42.31. Executing TECHMAP pass (map to technology primitives). 24.42.31.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/techmap.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu_brent_kung'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `\$__div_mod_u'. Generating RTLIL representation for module `\$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `\$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_pmux'. Generating RTLIL representation for module `\_90_demux'. Generating RTLIL representation for module `\_90_lut'. Successfully finished Verilog frontend. 24.42.31.2. Continuing TECHMAP pass. Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C. Using template $paramod\LUT4\INIT=16'1001011010101010 for cells of type LUT4. Using extmapper simplemap for cells of type $and. Using extmapper simplemap for cells of type $not. Using extmapper simplemap for cells of type $xor. Using template $paramod\LUT2\INIT=4'1010 for cells of type LUT2. Using extmapper simplemap for cells of type $or. Using extmapper simplemap for cells of type $mux. No more expansions possible. <suppressed ~235 debug messages> 24.42.32. Executing OPT pass (performing simple optimizations). 24.42.32.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~18 debug messages> 24.42.32.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~6 debug messages> Removed a total of 2 cells. 24.42.32.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 24.42.32.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 24.42.32.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 24.42.32.6. Executing OPT_DFF pass (perform DFF optimizations). 24.42.32.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 55 unused wires. <suppressed ~1 debug messages> 24.42.32.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 24.42.32.9. Rerunning OPT passes. (Maybe there is more to do..) 24.42.32.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 24.42.32.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 24.42.32.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 24.42.32.13. Executing OPT_DFF pass (perform DFF optimizations). 24.42.32.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 24.42.32.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 24.42.32.16. Finished OPT passes. (There is nothing left to do.) 24.42.33. Executing AIGMAP pass (map logic to AIG). Module top: replaced 18 cells with 120 new cells, skipped 39 cells. replaced 3 cell types: 2 $_OR_ 2 $_XOR_ 14 $_MUX_ not replaced 3 cell types: 31 $specify2 4 $_NOT_ 4 $_AND_ 24.42.34. Executing AIGMAP pass (map logic to AIG). Module top: replaced 2180 cells with 12251 new cells, skipped 2120 cells. replaced 4 cell types: 999 $_OR_ 136 $_XOR_ 3 $_ORNOT_ 1042 $_MUX_ not replaced 43 cell types: 31 $scopeinfo 360 $_NOT_ 839 $_AND_ 6 $_TBUF_ 1 $paramod$50a3456423815ea2ad88f4cd62b0b75c0753cc69\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$242712b50c0a2a6b7d501d3b8f15d1e042886c7d\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$0ec150df0608fe9d13bbd7ba55d0b68aebde8574\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$b4055cc4c76830d75a5da93152e34111ac58d5fb\TRELLIS_DPR16X4_$abc9_byp 20 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$828eab860e7ad1344f71b7dcac93a993e09abfc2\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$3fea245e43c817e3ab409ba408c64d50b3c3410d\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$240b3d214c7091ed87f7feed01a813ca9ca1b727\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$55d7bec832f9f63c717e9458c8d5bd2bb91537b6\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$6f6b0ecb6502c3a0ff5a34ccfc87ee0dc217c0aa\TRELLIS_DPR16X4_$abc9_byp 611 TRELLIS_FF 1 $paramod$6f6b0ecb6502c3a0ff5a34ccfc87ee0dc217c0aa\TRELLIS_DPR16X4 1 $paramod$55d7bec832f9f63c717e9458c8d5bd2bb91537b6\TRELLIS_DPR16X4 1 $paramod$54859518bee4eabb76b31063a8cd09e44ba7903d\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$240b3d214c7091ed87f7feed01a813ca9ca1b727\TRELLIS_DPR16X4 1 $paramod$54859518bee4eabb76b31063a8cd09e44ba7903d\TRELLIS_DPR16X4 1 $paramod$50a3456423815ea2ad88f4cd62b0b75c0753cc69\TRELLIS_DPR16X4 1 $paramod$3cdce45cfe40dd4cba4b9a5e0edd92348d96d81f\TRELLIS_DPR16X4 1 $paramod$0ec150df0608fe9d13bbd7ba55d0b68aebde8574\TRELLIS_DPR16X4 1 $paramod$242712b50c0a2a6b7d501d3b8f15d1e042886c7d\TRELLIS_DPR16X4 16 $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$c58b622e748098fb95d7cce3391b5b90d49d749c\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$4a126fa1688fbcbb97471f2a58f335ad46a1b683\TRELLIS_DPR16X4_$abc9_byp 1 $__ABC9_SCC_BREAKER 1 $paramod$828eab860e7ad1344f71b7dcac93a993e09abfc2\TRELLIS_DPR16X4 1 $paramod$53a840446cdc2b5aa298a080f49764e881c60b99\TRELLIS_DPR16X4 1 $paramod$3fea245e43c817e3ab409ba408c64d50b3c3410d\TRELLIS_DPR16X4 1 $paramod$896c13102149326c20257183c5d146c2879d74e6\TRELLIS_DPR16X4 1 $paramod$b4055cc4c76830d75a5da93152e34111ac58d5fb\TRELLIS_DPR16X4 1 $paramod$28331dd642fda78247f997daeb218f7111f59a79\TRELLIS_DPR16X4 20 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 16 $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4 1 $paramod$c58b622e748098fb95d7cce3391b5b90d49d749c\TRELLIS_DPR16X4 1 $paramod$4a126fa1688fbcbb97471f2a58f335ad46a1b683\TRELLIS_DPR16X4 1 $paramod$3cdce45cfe40dd4cba4b9a5e0edd92348d96d81f\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$53a840446cdc2b5aa298a080f49764e881c60b99\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$896c13102149326c20257183c5d146c2879d74e6\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$28331dd642fda78247f997daeb218f7111f59a79\TRELLIS_DPR16X4_$abc9_byp 168 $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C 24.42.34.1. Executing ABC9_OPS pass (helper functions for ABC9). 24.42.34.2. Executing ABC9_OPS pass (helper functions for ABC9). 24.42.34.3. Executing XAIGER backend. <suppressed ~11 debug messages> Extracted 5375 AND gates and 15530 wires from module `top' to a netlist network with 835 inputs and 686 outputs. 24.42.34.4. Executing ABC9_EXE pass (technology mapping using ABC9). 24.42.34.5. Executing ABC9. ****** Vivado v2023.2 (64-bit) **** SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023 **** IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023 **** SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023 ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. ** Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. source run.tcl # read_verilog "main.v" Running ABC command: "<yosys-exe-dir>/yosys-abc" -s -f <abc-temp-dir>/abc.script 2>&1 ABC: ABC command line: "source <abc-temp-dir>/abc.script". ABC: ABC: + read_lut <abc-temp-dir>/input.lut ABC: + read_box <abc-temp-dir>/input.box ABC: + &read <abc-temp-dir>/input.xaig ABC: + &ps ABC: <abc-temp-dir>/input : i/o = 835/ 686 and = 4545 lev = 37 (2.31) mem = 0.12 MB box = 220 bb = 52 ABC: + &scorr ABC: Warning: The network is combinational. ABC: + &sweep ABC: + &dc2 ABC: + &dch -f ABC: + &ps ABC: <abc-temp-dir>/input : i/o = 835/ 686 and = 5707 lev = 54 (1.73) mem = 0.13 MB ch = 650 box = 220 bb = 52 ABC: + &if -W 300 -v ABC: K = 7. Memory (bytes): Truth = 0. Cut = 64. Obj = 148. Set = 672. CutMin = no ABC: Node = 5707. Ch = 611. Total mem = 1.54 MB. Peak cut mem = 0.18 MB. ABC: P: Del = 5500.00. Ar = 6480.0. Edge = 7794. Cut = 68361. T = 0.02 sec ABC: P: Del = 5492.00. Ar = 6030.0. Edge = 7536. Cut = 66718. T = 0.02 sec ABC: P: Del = 5492.00. Ar = 4534.0. Edge = 7797. Cut = 151150. T = 0.04 sec ABC: F: Del = 5492.00. Ar = 2880.0. Edge = 5664. Cut = 91040. T = 0.02 sec ABC: A: Del = 5492.00. Ar = 2486.0. Edge = 4889. Cut = 83516. T = 0.03 sec ABC: A: Del = 5492.00. Ar = 2448.0. Edge = 4812. Cut = 80694. T = 0.03 sec ABC: Total time = 0.16 sec ABC: + &write -n <abc-temp-dir>/output.aig ABC: + &mfs ABC: + &ps -l ABC: <abc-temp-dir>/input : i/o = 835/ 686 and = 4858 lev = 30 (1.71) mem = 0.12 MB box = 220 bb = 52 ABC: Mapping (K=7) : lut = 1178 edge = 4640 lev = 11 (0.77) Boxes are not in a topological order. Switching to level computation without boxes. ABC: levB = 30 mem = 0.06 MB ABC: LUT = 1178 : 2=193 16.4 % 3=352 29.9 % 4=258 21.9 % 5=174 14.8 % 6=111 9.4 % 7=90 7.6 % Ave = 3.94 ABC: + &write -n <abc-temp-dir>/output.aig ABC: + time ABC: elapse: 2.76 seconds, total: 2.76 seconds 24.42.34.6. Executing AIGER frontend. <suppressed ~3054 debug messages> Removed 7454 unused cells and 12088 unused wires. 24.42.34.7. Executing ABC9_OPS pass (helper functions for ABC9). ABC RESULTS: $lut cells: 1206 ABC RESULTS: $paramod$50a3456423815ea2ad88f4cd62b0b75c0753cc69\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$242712b50c0a2a6b7d501d3b8f15d1e042886c7d\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$0ec150df0608fe9d13bbd7ba55d0b68aebde8574\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$b4055cc4c76830d75a5da93152e34111ac58d5fb\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp cells: 20 ABC RESULTS: $paramod$828eab860e7ad1344f71b7dcac93a993e09abfc2\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$3fea245e43c817e3ab409ba408c64d50b3c3410d\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$240b3d214c7091ed87f7feed01a813ca9ca1b727\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$55d7bec832f9f63c717e9458c8d5bd2bb91537b6\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$6f6b0ecb6502c3a0ff5a34ccfc87ee0dc217c0aa\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$54859518bee4eabb76b31063a8cd09e44ba7903d\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4_$abc9_byp cells: 16 ABC RESULTS: $paramod$c58b622e748098fb95d7cce3391b5b90d49d749c\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$4a126fa1688fbcbb97471f2a58f335ad46a1b683\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$3cdce45cfe40dd4cba4b9a5e0edd92348d96d81f\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$53a840446cdc2b5aa298a080f49764e881c60b99\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$896c13102149326c20257183c5d146c2879d74e6\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$28331dd642fda78247f997daeb218f7111f59a79\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C cells: 168 ABC RESULTS: input signals: 100 ABC RESULTS: output signals: 145 Removing temp directory. 24.42.35. Executing TECHMAP pass (map to technology primitives). 24.42.35.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/abc9_unmap.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/abc9_unmap.v' to AST representation. Generating RTLIL representation for module `\$__DFF_x__$abc9_flop'. Generating RTLIL representation for module `\$__ABC9_SCC_BREAKER'. Successfully finished Verilog frontend. 24.42.35.2. Continuing TECHMAP pass. Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C. Using template $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4 for cells of type $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4. Using template $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod\$__ABC9_SCC_BREAKER\WIDTH=32'00000000000000000000000000000111 for cells of type $__ABC9_SCC_BREAKER. Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$3cdce45cfe40dd4cba4b9a5e0edd92348d96d81f\TRELLIS_DPR16X4 for cells of type $paramod$3cdce45cfe40dd4cba4b9a5e0edd92348d96d81f\TRELLIS_DPR16X4. Using template $paramod$3cdce45cfe40dd4cba4b9a5e0edd92348d96d81f\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$3cdce45cfe40dd4cba4b9a5e0edd92348d96d81f\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$828eab860e7ad1344f71b7dcac93a993e09abfc2\TRELLIS_DPR16X4 for cells of type $paramod$828eab860e7ad1344f71b7dcac93a993e09abfc2\TRELLIS_DPR16X4. Using template $paramod$828eab860e7ad1344f71b7dcac93a993e09abfc2\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$828eab860e7ad1344f71b7dcac93a993e09abfc2\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$53a840446cdc2b5aa298a080f49764e881c60b99\TRELLIS_DPR16X4 for cells of type $paramod$53a840446cdc2b5aa298a080f49764e881c60b99\TRELLIS_DPR16X4. Using template $paramod$53a840446cdc2b5aa298a080f49764e881c60b99\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$53a840446cdc2b5aa298a080f49764e881c60b99\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$50a3456423815ea2ad88f4cd62b0b75c0753cc69\TRELLIS_DPR16X4 for cells of type $paramod$50a3456423815ea2ad88f4cd62b0b75c0753cc69\TRELLIS_DPR16X4. Using template $paramod$50a3456423815ea2ad88f4cd62b0b75c0753cc69\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$50a3456423815ea2ad88f4cd62b0b75c0753cc69\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$0ec150df0608fe9d13bbd7ba55d0b68aebde8574\TRELLIS_DPR16X4 for cells of type $paramod$0ec150df0608fe9d13bbd7ba55d0b68aebde8574\TRELLIS_DPR16X4. Using template $paramod$0ec150df0608fe9d13bbd7ba55d0b68aebde8574\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$0ec150df0608fe9d13bbd7ba55d0b68aebde8574\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$55d7bec832f9f63c717e9458c8d5bd2bb91537b6\TRELLIS_DPR16X4 for cells of type $paramod$55d7bec832f9f63c717e9458c8d5bd2bb91537b6\TRELLIS_DPR16X4. Using template $paramod$55d7bec832f9f63c717e9458c8d5bd2bb91537b6\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$55d7bec832f9f63c717e9458c8d5bd2bb91537b6\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$240b3d214c7091ed87f7feed01a813ca9ca1b727\TRELLIS_DPR16X4 for cells of type $paramod$240b3d214c7091ed87f7feed01a813ca9ca1b727\TRELLIS_DPR16X4. Using template $paramod$240b3d214c7091ed87f7feed01a813ca9ca1b727\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$240b3d214c7091ed87f7feed01a813ca9ca1b727\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$6f6b0ecb6502c3a0ff5a34ccfc87ee0dc217c0aa\TRELLIS_DPR16X4 for cells of type $paramod$6f6b0ecb6502c3a0ff5a34ccfc87ee0dc217c0aa\TRELLIS_DPR16X4. Using template $paramod$6f6b0ecb6502c3a0ff5a34ccfc87ee0dc217c0aa\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$6f6b0ecb6502c3a0ff5a34ccfc87ee0dc217c0aa\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$28331dd642fda78247f997daeb218f7111f59a79\TRELLIS_DPR16X4 for cells of type $paramod$28331dd642fda78247f997daeb218f7111f59a79\TRELLIS_DPR16X4. Using template $paramod$28331dd642fda78247f997daeb218f7111f59a79\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$28331dd642fda78247f997daeb218f7111f59a79\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$54859518bee4eabb76b31063a8cd09e44ba7903d\TRELLIS_DPR16X4 for cells of type $paramod$54859518bee4eabb76b31063a8cd09e44ba7903d\TRELLIS_DPR16X4. Using template $paramod$54859518bee4eabb76b31063a8cd09e44ba7903d\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$54859518bee4eabb76b31063a8cd09e44ba7903d\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$4a126fa1688fbcbb97471f2a58f335ad46a1b683\TRELLIS_DPR16X4 for cells of type $paramod$4a126fa1688fbcbb97471f2a58f335ad46a1b683\TRELLIS_DPR16X4. Using template $paramod$4a126fa1688fbcbb97471f2a58f335ad46a1b683\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$4a126fa1688fbcbb97471f2a58f335ad46a1b683\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$b4055cc4c76830d75a5da93152e34111ac58d5fb\TRELLIS_DPR16X4 for cells of type $paramod$b4055cc4c76830d75a5da93152e34111ac58d5fb\TRELLIS_DPR16X4. Using template $paramod$b4055cc4c76830d75a5da93152e34111ac58d5fb\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$b4055cc4c76830d75a5da93152e34111ac58d5fb\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$3fea245e43c817e3ab409ba408c64d50b3c3410d\TRELLIS_DPR16X4 for cells of type $paramod$3fea245e43c817e3ab409ba408c64d50b3c3410d\TRELLIS_DPR16X4. Using template $paramod$3fea245e43c817e3ab409ba408c64d50b3c3410d\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$3fea245e43c817e3ab409ba408c64d50b3c3410d\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$242712b50c0a2a6b7d501d3b8f15d1e042886c7d\TRELLIS_DPR16X4 for cells of type $paramod$242712b50c0a2a6b7d501d3b8f15d1e042886c7d\TRELLIS_DPR16X4. Using template $paramod$242712b50c0a2a6b7d501d3b8f15d1e042886c7d\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$242712b50c0a2a6b7d501d3b8f15d1e042886c7d\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$896c13102149326c20257183c5d146c2879d74e6\TRELLIS_DPR16X4 for cells of type $paramod$896c13102149326c20257183c5d146c2879d74e6\TRELLIS_DPR16X4. Using template $paramod$896c13102149326c20257183c5d146c2879d74e6\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$896c13102149326c20257183c5d146c2879d74e6\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$c58b622e748098fb95d7cce3391b5b90d49d749c\TRELLIS_DPR16X4 for cells of type $paramod$c58b622e748098fb95d7cce3391b5b90d49d749c\TRELLIS_DPR16X4. Using template $paramod$c58b622e748098fb95d7cce3391b5b90d49d749c\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$c58b622e748098fb95d7cce3391b5b90d49d749c\TRELLIS_DPR16X4_$abc9_byp. No more expansions possible. <suppressed ~326 debug messages> Removed 194 unused cells and 17490 unused wires. 24.43. Executing TECHMAP pass (map to technology primitives). 24.43.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v' to AST representation. Generating RTLIL representation for module `\$_DFF_N_'. Generating RTLIL representation for module `\$_DFF_P_'. Generating RTLIL representation for module `\$_DFFE_NN_'. Generating RTLIL representation for module `\$_DFFE_PN_'. Generating RTLIL representation for module `\$_DFFE_NP_'. Generating RTLIL representation for module `\$_DFFE_PP_'. Generating RTLIL representation for module `\$_DFF_NP0_'. Generating RTLIL representation for module `\$_DFF_NP1_'. Generating RTLIL representation for module `\$_DFF_PP0_'. Generating RTLIL representation for module `\$_DFF_PP1_'. Generating RTLIL representation for module `\$_SDFF_NP0_'. Generating RTLIL representation for module `\$_SDFF_NP1_'. Generating RTLIL representation for module `\$_SDFF_PP0_'. Generating RTLIL representation for module `\$_SDFF_PP1_'. Generating RTLIL representation for module `\$_DFFE_NP0P_'. Generating RTLIL representation for module `\$_DFFE_NP1P_'. Generating RTLIL representation for module `\$_DFFE_PP0P_'. Generating RTLIL representation for module `\$_DFFE_PP1P_'. Generating RTLIL representation for module `\$_DFFE_NP0N_'. Generating RTLIL representation for module `\$_DFFE_NP1N_'. Generating RTLIL representation for module `\$_DFFE_PP0N_'. Generating RTLIL representation for module `\$_DFFE_PP1N_'. Generating RTLIL representation for module `\$_SDFFE_NP0P_'. Generating RTLIL representation for module `\$_SDFFE_NP1P_'. Generating RTLIL representation for module `\$_SDFFE_PP0P_'. Generating RTLIL representation for module `\$_SDFFE_PP1P_'. Generating RTLIL representation for module `\$_SDFFE_NP0N_'. Generating RTLIL representation for module `\$_SDFFE_NP1N_'. Generating RTLIL representation for module `\$_SDFFE_PP0N_'. Generating RTLIL representation for module `\$_SDFFE_PP1N_'. Generating RTLIL representation for module `\$_ALDFF_NP_'. Generating RTLIL representation for module `\$_ALDFF_PP_'. Generating RTLIL representation for module `\$_ALDFFE_NPN_'. Generating RTLIL representation for module `\$_ALDFFE_NPP_'. Generating RTLIL representation for module `\$_ALDFFE_PPN_'. Generating RTLIL representation for module `\$_ALDFFE_PPP_'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Generating RTLIL representation for module `\$lut'. Successfully finished Verilog frontend. 24.43.2. Continuing TECHMAP pass. Using template $paramod$352b9d282923ba2c96f10a02b0b3dbeb3ea752ab\$lut for cells of type $lut. Using template $paramod$272652f6c6fbe9a75eff76e45cc7e2788835518b\$lut for cells of type $lut. Using template $paramod$6d6beead1425af15cf78b27fd9b11b41b5d4bce8\$lut for cells of type $lut. Using template $paramod$b18a3edb490ff3a49fefc94182a05f36efbdbba2\$lut for cells of type $lut. Using template $paramod$e60b11de7aa20378f670a7ab1111c5cfc6aa111f\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001110 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0010 for cells of type $lut. Using template $paramod$e8ba44e4a3ee29c32776f6151b0293be3e5fa416\$lut for cells of type $lut. Using template $paramod$d2b2af60e9d9577094b2075029cb17c762b8a364\$lut for cells of type $lut. Using template $paramod$d377d3a21a6278cf14f1ae6c5341484569a09ca5\$lut for cells of type $lut. Using template $paramod$10143aca4cee2b05cf91c7eff4214fb57d3917d8\$lut for cells of type $lut. Using template $paramod$a773026f3c8396d0e7b9086f19fa7a74632725d1\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101100 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111101 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut. Using template $paramod$a8a7a7b14dd3575ec864cf6639362bd64a43d4ea\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0001 for cells of type $lut. Using template $paramod$59c595af41d4a5cce2d588c3a5f1342749ce7a77\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000100 for cells of type $lut. Using template $paramod$873c285bdccf0ac2b60d2304ea5cd14bf211d2a6\$lut for cells of type $lut. Using template $paramod$63c6d6e241e90de695ffaf0f3524784e17918f0a\$lut for cells of type $lut. Using template $paramod$ee3ba3939f6ccdb74bf420a252d58cdb86511937\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010000 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000000 for cells of type $lut. Using template $paramod$364c9ffbffac467d60dfec81bba4e18476c15602\$lut for cells of type $lut. Using template $paramod$c97bcad21440836b1df0dc8f4860bb61034e5b37\$lut for cells of type $lut. Using template $paramod$548857669b732141711635b7c142fde34b848476\$lut for cells of type $lut. Using template $paramod$eeba60b5d1876a621d2a88d84675e4edcb08ed98\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001111 for cells of type $lut. Using template $paramod$f41e2eaa89cdb82e7e3c858decb912777c69a47a\$lut for cells of type $lut. Using template $paramod$3620f2e9e7de7810971e1b6bad09847f2ec6be36\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001010 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut. Using template $paramod$41171b2adc7c7a327ab493ad475df72c2ca25f88\$lut for cells of type $lut. Using template $paramod$9f73ac69952e2ff750b2c10f309a8e82deefc571\$lut for cells of type $lut. Using template $paramod$b14581ae38a53be843ef64da0e2a8e892013ec4f\$lut for cells of type $lut. Using template $paramod$19b191f582e832a4c5237ec2185d4b5d3e91ea51\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1110 for cells of type $lut. Using template $paramod$ee4719be90cb5e99ba51526a9f283fc572670293\$lut for cells of type $lut. Using template $paramod$0ebb73d4f4905a932d7b2f968ce75f38d0712ac4\$lut for cells of type $lut. Using template $paramod$19f4fa446d94767b8a3977abee599cf6b53b2330\$lut for cells of type $lut. Using template $paramod$c001d054ed3ac1f71eaa79cfd456eebb85283872\$lut for cells of type $lut. Using template $paramod$7413c656278ade0cae0951284a3a215f6f959a80\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000000 for cells of type $lut. Using template $paramod$df5c8730c0a53792c3f54c2192a2221c27162fb5\$lut for cells of type $lut. Using template $paramod$f9c2b3b684e7baf9e9f80fa80a488cab67fe7cb1\$lut for cells of type $lut. Using template $paramod$a06c93a4d63ea2b452f1dec6185ffe7463e673a3\$lut for cells of type $lut. Using template $paramod$52d1e412bd12f078644292b145d7825721eeb433\$lut for cells of type $lut. Using template $paramod$7ee61419a55246b30630a8d3d7e8b0309cc5af4a\$lut for cells of type $lut. Using template $paramod$a4cc8037d29ca5eaaf5382500120889353be2bfe\$lut for cells of type $lut. Using template $paramod$2284c1e157c501361eae4c149237dfb93f61bfcd\$lut for cells of type $lut. Using template $paramod$fa0b238e93184392cab41e2300c2e7dcc1688636\$lut for cells of type $lut. Using template $paramod$09b35078d434d051253c6f7836ef68c0cd803347\$lut for cells of type $lut. Using template $paramod$fa29c2b7f8e6526128bd89f489b58ede030e5d52\$lut for cells of type $lut. Using template $paramod$1b21bfe3f0f701f19b91b9d9f4b2cb25c52e0379\$lut for cells of type $lut. Using template $paramod$3397dbf3ad9431aa8036dd5e595882d84fd86137\$lut for cells of type $lut. Using template $paramod$8f5fdc914e089d2b73d09cec6a94c18a555cf58e\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10011010 for cells of type $lut. Using template $paramod$b2a4860cd839ff40d9dca4c3f237b2b534267028\$lut for cells of type $lut. Using template $paramod$86af5516b211ac0a119e6bb8669dad97de88b580\$lut for cells of type $lut. Using template $paramod$4ea7c1db3a440241fdea718a41a7034d67743f59\$lut for cells of type $lut. Using template $paramod$9f09e13434c34a78cedceb44838f73055afb43ba\$lut for cells of type $lut. Using template $paramod$6e2b27a23561eba4d5d7a3612a01502854865858\$lut for cells of type $lut. Using template $paramod$c28a8b7ce0535d090c4cfb52e9c74affd52b110c\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001000 for cells of type $lut. Using template $paramod$fff7f0b0ee930ecdc11c7756ebeae5a05338d5ff\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100000 for cells of type $lut. Using template $paramod$5d05df7c2ae0f422858107ab2746d96e7a01dcbf\$lut for cells of type $lut. Using template $paramod$ce4ec03c44eb9f723efc2447e971d53a692885b6\$lut for cells of type $lut. Using template $paramod$2ea69c779d6c1b79ac5a87b0d1523c67d5628dba\$lut for cells of type $lut. Using template $paramod$e58183263e37f1cc0d15a08a56a8589b5236fac1\$lut for cells of type $lut. Using template $paramod$cb0bf18b45bb66c82d8f4f7d02c6437136ab55b6\$lut for cells of type $lut. Using template $paramod$a1d323730045824cfc84bb9f4ee8031f1c4dcc9e\$lut for cells of type $lut. Using template $paramod$d502d76693ccc2c24ca393911edd466047ab49c5\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000111 for cells of type $lut. Using template $paramod$4b23d751b3e1d7cde9cd1766bf20ceee12e38a3d\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01100000 for cells of type $lut. Using template $paramod$018d71a0fe325d6362687fe53ac13dd6340e400d\$lut for cells of type $lut. Using template $paramod$0c822c65361ce832091b6c90f1a02f1ee0b109d4\$lut for cells of type $lut. Using template $paramod$61594d0f3b142edd1b56a1b06b880d35bf44947b\$lut for cells of type $lut. Using template $paramod$f577f8feb66a0971db8188338533f973999256a1\$lut for cells of type $lut. Using template $paramod$862cd2214abf2d2a2e316f03cb27f3d66792459e\$lut for cells of type $lut. Using template $paramod$b6d7b8802225d3fe3444a1b7fbd727be1d62f151\$lut for cells of type $lut. Using template $paramod$de152032b68026bcd59a5ef2019e739a726a14bf\$lut for cells of type $lut. Using template $paramod$a5788e8bd3559e65ba7c6a1d93529c6fb76569b9\$lut for cells of type $lut. Using template $paramod$41246cfd614b41cf3961e26c4361bc57443b6533\$lut for cells of type $lut. Using template $paramod$c8f2b00a2feb859040935d06cafa51f6c4e20e0d\$lut for cells of type $lut. Using template $paramod$bc051162dfb23caab98d73c4ec086fe9a67895f2\$lut for cells of type $lut. Using template $paramod$bde6c96e44b0f8e6d9db97eafdf28d77ceaa9a96\$lut for cells of type $lut. Using template $paramod$0e7ce19e5da99c6675c7a5220f7cc55270b24ac0\$lut for cells of type $lut. Using template $paramod$8f83b20e8fa6731d08c67f8bf191329a8abcb0d7\$lut for cells of type $lut. Using template $paramod$4a6c40c0aa0151e1be6a6def67b9f99900090ccd\$lut for cells of type $lut. Using template $paramod$af10906771d8374f1f19c3cfa8d5c9b02a84c9dd\$lut for cells of type $lut. Using template $paramod$f3e1547c4b47e64c590e75cf09078b2507c8cc75\$lut for cells of type $lut. Using template $paramod$973818279bc95792902f3c09371fd2407d04a2a5\$lut for cells of type $lut. Using template $paramod$3074bcb534c958e8f4f377982ef38b69dcd626e5\$lut for cells of type $lut. Using template $paramod$6be925e633af956bf6e16abcad4d3469f4122719\$lut for cells of type $lut. Using template $paramod$5d9bdb7f5954011ff004758709112a4f3d3263f1\$lut for cells of type $lut. Using template $paramod$518e30b8a7359d40bd6c823079d2670b2aca6d5c\$lut for cells of type $lut. Using template $paramod$fa45f28daf300aaa781ee4b9baa5ce968b1d8c66\$lut for cells of type $lut. Using template $paramod$c5af5678e76c2f7359a5d42d1a07c7e309f457a6\$lut for cells of type $lut. Using template $paramod$69c279d8a97ac52ec679b06c9a583ea2ad60d83d\$lut for cells of type $lut. Using template $paramod$b7b59e3a630782b5946dc48132167622dc4e73a0\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1011 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111000 for cells of type $lut. Using template $paramod$fdcae86fcfd036c1880a04306ae771a9d7579c31\$lut for cells of type $lut. Using template $paramod$1ed20a5153e3607f5dd8631c19bf71224057ab60\$lut for cells of type $lut. Using template $paramod$3ef319efded008eed5f930491a82ee1762b3c0df\$lut for cells of type $lut. Using template $paramod$6842b8b2a2a38d0fdb35de972b4ce1a464745b17\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101000 for cells of type $lut. Using template $paramod$3402ca298146c329ef3a44985c10b436247e7a27\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100000 for cells of type $lut. Using template $paramod$eabde4761c91679426ef5401ae1b2c95bf56e107\$lut for cells of type $lut. Using template $paramod$7491e7206ae8c682d288373efe06a43b67c277cf\$lut for cells of type $lut. Using template $paramod$0b8228a994336125ac193b3efdbfd1ae1659f402\$lut for cells of type $lut. Using template $paramod$e2ae0b29450b42fcd914a8e963f7ddfd03716f94\$lut for cells of type $lut. Using template $paramod$3bb7b015790d2af03baf785d275cbd099cfe2c26\$lut for cells of type $lut. Using template $paramod$6028f7151aecc0ea3dfec92b4d002cc04d637b3e\$lut for cells of type $lut. Using template $paramod$63d2802173708b0e8025c778565be816e485dec0\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000010 for cells of type $lut. Using template $paramod$26c5052c049ac46222fd07f33e963742075bb127\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11011000 for cells of type $lut. Using template $paramod$2014354416722209de7d48370ab008bc2278a034\$lut for cells of type $lut. Using template $paramod$520f061407a91ec675c1572b2ab1e5d0e3663de0\$lut for cells of type $lut. Using template $paramod$09d329c0421f020ae471423473308dd05cea2743\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100100 for cells of type $lut. Using template $paramod$26d876869d6ab003366d0470e095daef2ccfcbd7\$lut for cells of type $lut. Using template $paramod$12b93181fde40368887ce43b59fecaa09cb41fa7\$lut for cells of type $lut. Using template $paramod$e5f53fb2cb3e702c9422ebddd3ba952e5a8f3401\$lut for cells of type $lut. Using template $paramod$02e55836878a22873310c70e8a2ed14028fabfa5\$lut for cells of type $lut. Using template $paramod$a87484dc66dd0395560aeca31066d0209aef4694\$lut for cells of type $lut. Using template $paramod$4f09540800ac966d6e31a7ccf5f32a559a8ce57a\$lut for cells of type $lut. Using template $paramod$2e0fd651ab536ddf2afd30af26b1a2532281e83a\$lut for cells of type $lut. Using template $paramod$004f370d08abb44756241396871996f35d72255b\$lut for cells of type $lut. Using template $paramod$b7f2af3b894343554c22993fa7e7d9f6371a085d\$lut for cells of type $lut. Using template $paramod$7dad2285b6a41fd718a0863efc009b14ae7d121a\$lut for cells of type $lut. Using template $paramod$c2e0f292f341b7ed9d11fd7aa21f5828a2d7a463\$lut for cells of type $lut. Using template $paramod$7c881c42be5bd27172a06fd373d21a7d4307fea2\$lut for cells of type $lut. Using template $paramod$9fd82fb245ed160b1d06c272aaeb78d4530f88b1\$lut for cells of type $lut. Using template $paramod$06e62c2045624c211a1abe4f2f36c8f22c688165\$lut for cells of type $lut. Using template $paramod$ab5f6cbda813df0763ad05c5e0cfe5a674acf259\$lut for cells of type $lut. Using template $paramod$fca4d0efc7a230e04d21d79e98def53bbfbcb034\$lut for cells of type $lut. Using template $paramod$a5516fc31d1e552de2435200bb732b4d4ad63a9c\$lut for cells of type $lut. Using template $paramod$3bc37b2484b7c566acd5c06b32a4f4b5ac79e372\$lut for cells of type $lut. Using template $paramod$6618930769199e323c69d0db02526a071b959c45\$lut for cells of type $lut. Using template $paramod$7d813eb49700f971f2635a434700eafdfa816bc3\$lut for cells of type $lut. Using template $paramod$c79aec6bf66334ca918f85c196e004c918c371ef\$lut for cells of type $lut. Using template $paramod$3dfdb778126ab011e4d5dd8bd717182a0c306ecc\$lut for cells of type $lut. Using template $paramod$b7685cb0c8a6753256bc84bc31d36a443c15fab7\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100011 for cells of type $lut. Using template $paramod$473fcd371d91799964bc73c98ad44aa026e26f19\$lut for cells of type $lut. Using template $paramod$c6364c1c44c01bd533fa2efe3a700455891e44b1\$lut for cells of type $lut. Using template $paramod$fae488a30de1e466fec322ece7e4138825f6e723\$lut for cells of type $lut. Using template $paramod$25123a5f7ea669fd5c12c2bfce9cb4e91beeb163\$lut for cells of type $lut. Using template $paramod$d5b95ef1c89d834e3e72966caf0c9ff97c5cfa95\$lut for cells of type $lut. Using template $paramod$fcff9a7b1687e357a40264efcefe8443c8b2971a\$lut for cells of type $lut. Using template $paramod$868876e6fbf32fc8a062709fbe4f313e5420f9a8\$lut for cells of type $lut. Using template $paramod$ccd3e15dc00d71b9284dff48e88ccef5be7362c8\$lut for cells of type $lut. Using template $paramod$2844c7fef2a755a9af80c70990cd830291c4b71c\$lut for cells of type $lut. Using template $paramod$891a41f121ca93eb4c2d92c44d75335036425d13\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1001 for cells of type $lut. Using template $paramod$53564a2624f743596c6b6998e19fdd2ad9db459f\$lut for cells of type $lut. Using template $paramod$8696f458b0bc45d72f187617e991118b6ed26c4f\$lut for cells of type $lut. Using template $paramod$af017abfe144c38c299d0668d79f617c7adf0e54\$lut for cells of type $lut. Using template $paramod$4329f6681456271ac847b0ed583814fe5288ac2a\$lut for cells of type $lut. Using template $paramod$6e1fae557d304fba4b3fa6f3f45c051902e19ae4\$lut for cells of type $lut. Using template $paramod$038808f48e193a9a9820805dde580bc9f42b524c\$lut for cells of type $lut. Using template $paramod$6e238df02989b317f10820a22773676e71120644\$lut for cells of type $lut. Using template $paramod$c0e395c2d0dfbafa147a6aae7cfc1897ce26affb\$lut for cells of type $lut. Using template $paramod$6edef71f6771809b6ef2eead32c35ef9b0eba3e5\$lut for cells of type $lut. Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8\$lut for cells of type $lut. Using template $paramod$47a8214374025465e226fa66bee690ff33268a25\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001101 for cells of type $lut. Using template $paramod$eb1fb9180723354dd0cbb984db5ad3ea2f924d60\$lut for cells of type $lut. Using template $paramod$72067c6381800f8c28a047ece2efd5532cddc98d\$lut for cells of type $lut. Using template $paramod$16b2988d07c42bc47d737a9045f7bb700243bce1\$lut for cells of type $lut. Using template $paramod$09c0cfb7ba7c1ccd6bbcc158637d85f80001f113\$lut for cells of type $lut. Using template $paramod$9e1833a186966f2db3a6f246584a6f2d0abc1c40\$lut for cells of type $lut. Using template $paramod$877859204cc06b766f4cb38f89dea559af1e3734\$lut for cells of type $lut. Using template $paramod$301321002cb28483434a813b17302088bf27b78e\$lut for cells of type $lut. Using template $paramod$bed770a996b91d26bd8ec11fab40ed5b998c6937\$lut for cells of type $lut. Using template $paramod$dc355c3d7ff843bc438ddbe32f12d55fa309b4a5\$lut for cells of type $lut. Using template $paramod$620586420e818d3afa7e5b51fcf19f5c6ea83ad4\$lut for cells of type $lut. Using template $paramod$af1505355cee938b11b5062beda37680a2196d57\$lut for cells of type $lut. Using template $paramod$965ebc19d8bda21d2aaa1dee7a7b1e0348b073dc\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut. Using template $paramod$fe9a0158d0352193457c4f5b6282ac86d35fb3ee\$lut for cells of type $lut. Using template $paramod$f9813472aa48e533b3838c6f2316dc2e78c66111\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111110 for cells of type $lut. Using template $paramod$7bb6a37e65823eeb4b38c370fec30ab082759a14\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111000 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11110010 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01010100 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0111 for cells of type $lut. Using template $paramod$8512f4fb47fa9596f76cdbe5b407a5b54df368e7\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10010000 for cells of type $lut. Using template $paramod$b058f043223f367483fccc310d27705643ee6eb4\$lut for cells of type $lut. Using template $paramod$33e58adf67c6b686a154c9ce8ebbc4b04b8cabc5\$lut for cells of type $lut. Using template $paramod$8d7a8d6e3356de09670738ba85f2c6b874f6b06d\$lut for cells of type $lut. Using template $paramod$857512ea84a5fe5464efcd374b77666399ea78e1\$lut for cells of type $lut. Using template $paramod$08e3f355f410914376c5bae385a1551c4a70a79c\$lut for cells of type $lut. Using template $paramod$f45429e380905f064bb0bad3a8bdb941708e63a7\$lut for cells of type $lut. Using template $paramod$a6597eda4608f36e684c1dd07ed552fcbec112b2\$lut for cells of type $lut. Using template $paramod$cffcdcfefee28cb7804202d59fcab831562282d3\$lut for cells of type $lut. Using template $paramod$cf4bf642253654bd7040ccebf66cd9b374586b24\$lut for cells of type $lut. Using template $paramod$c16c1cdadbb969d6e67ada89b4869d7bf23a5a12\$lut for cells of type $lut. Using template $paramod$5506e3402bfb03b61e61d5a57a0a68d88d352dc9\$lut for cells of type $lut. Using template $paramod$584e4a38268562e2142ef24a574198cdf8d42be8\$lut for cells of type $lut. Using template $paramod$16b7e7f72632c4c9f4a95a53cce084d3bbccb721\$lut for cells of type $lut. Using template $paramod$5ad5dab2319eaa393748d74a6ae3cf6d24e40054\$lut for cells of type $lut. Using template $paramod$332a399730bfc61adea04021a76b1c4e4030f37d\$lut for cells of type $lut. Using template $paramod$cf636f17915eeeeae830faa1c036a260dbbd8a86\$lut for cells of type $lut. Using template $paramod$26a60a4222dbdf1a37aa2fc0cdbacd076c83fc20\$lut for cells of type $lut. Using template $paramod$676e197f1a72e03437d79d473ffa88e8c6c6af53\$lut for cells of type $lut. Using template $paramod$9218f2207cf02c5e31b0fab0631813e7c244fa10\$lut for cells of type $lut. Using template $paramod$b0878fe1110407fee18c8a936649bef81b1047a4\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001011 for cells of type $lut. Using template $paramod$a9f1133a3906e1a228933cdcaf464c776493a7e0\$lut for cells of type $lut. Using template $paramod$233e88dcf46e3e0754de2daa5c2340ff0f674f84\$lut for cells of type $lut. Using template $paramod$88e49fb4b14e90085f6b3086d7d2945a452594da\$lut for cells of type $lut. Using template $paramod$9d9b2ce3e6cf90b0d986abff737b095a541c7b68\$lut for cells of type $lut. Using template $paramod$cdeb5534a916e12b90336becfd3f18f9ecbf215f\$lut for cells of type $lut. Using template $paramod$86a469bec52dab5baf3cce07be4c692a88f78ee0\$lut for cells of type $lut. Using template $paramod$273cbc892c9dd4378544f9e08b4c3c9fa418c205\$lut for cells of type $lut. Using template $paramod$2b1586a443fcbc1604d6061bee5c042a78fb20df\$lut for cells of type $lut. Using template $paramod$7a86184b88dc28a8b01f8e4a8947565f54c64f2b\$lut for cells of type $lut. Using template $paramod$d463e7a9eb778ebd758a06ef0d7fcd05bee11825\$lut for cells of type $lut. Using template $paramod$48c075c433f0eeb632afaca27db4db127ef7c56a\$lut for cells of type $lut. Using template $paramod$4210e9a5154407adafc9a62b440e561b3e0d5bd3\$lut for cells of type $lut. Using template $paramod$d645a0eb523d0ad00ed653e3ae56f87ecb7b6d32\$lut for cells of type $lut. Using template $paramod$801505694672ffaac75e70fff4a8507289f2ff9c\$lut for cells of type $lut. Using template $paramod$d211e97fd68a0a11bc667a37034e2f1e81fab7ad\$lut for cells of type $lut. Using template $paramod$daaa0bdf4cea052ff6d926014f949261c9b0443d\$lut for cells of type $lut. Using template $paramod$09075db816d8e029981aa3d70c1517e1a68edfd7\$lut for cells of type $lut. Using template $paramod$b3a21c8557fcf487b9089efb8a5c97ff7362f08f\$lut for cells of type $lut. Using template $paramod$2649632427059f17a6997e51dd7f224fd1802b32\$lut for cells of type $lut. Using template $paramod$7d71d7b8657dfe8a213d396c3422444501a26b11\$lut for cells of type $lut. Using template $paramod$6b85005f52472512b211286b920c973a28f5655b\$lut for cells of type $lut. Using template $paramod$c5966e98773f1c185668bb7f5b6385d25e498be1\$lut for cells of type $lut. Using template $paramod$6f790ee9ebcd7c0c4bb1c623267757b511a9b322\$lut for cells of type $lut. Using template $paramod$db08fd84fb3c4d6a41eaec6adfffe445fb7eb17f\$lut for cells of type $lut. Using template $paramod$154f3693d9b55ec4d0b18044a13b24cebe86b6f8\$lut for cells of type $lut. Using template $paramod$c17b147bb79f8221285f6dde80bc375dfa77ed63\$lut for cells of type $lut. Using template $paramod$c1d26e7c26dc2a9e819c0c33a0cdb8c7498cf6ba\$lut for cells of type $lut. Using template $paramod$2ccba958ad93cec1b923be8a85761911f01cc63d\$lut for cells of type $lut. Using template $paramod$47625e0d44d1185ccf6831eac035c8dd510efc5d\$lut for cells of type $lut. Using template $paramod$20ba583962918fa0136fc97b1558cc45cc91cc29\$lut for cells of type $lut. Using template $paramod$f8e8e1e1389c03e530e143893bb2f66bbf48cb04\$lut for cells of type $lut. Using template $paramod$2263324799231e2151e6596c52c766c27183d35b\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001000 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001000 for cells of type $lut. Using template $paramod$219b71aec9a19e7a27754ed85a7d6cdad9e5ec96\$lut for cells of type $lut. Using template $paramod$36e2f59040f788fa64d91bddaac16b2cc2df0ae1\$lut for cells of type $lut. Using template $paramod$b867296edadf05b3bc06ed2c89cbe73b4a0d9414\$lut for cells of type $lut. Using template $paramod$440a67a549bc8290aca0f752de19813fb83eada0\$lut for cells of type $lut. Using template $paramod$151cc61869e7cf4cf4bd07f6ebd8187604529cbc\$lut for cells of type $lut. Using template $paramod$d5bfac764aff2d218ab8c5b3373463be622a5a10\$lut for cells of type $lut. Using template $paramod$374f70bb45d38e3afc56f16b1775aa2d5d284bf3\$lut for cells of type $lut. Using template $paramod$52011043954aa7c5dbb966f6de40c389ccf166dd\$lut for cells of type $lut. Using template $paramod$0277567e04bf6ce483bb2bcb077e44dbc2f633d1\$lut for cells of type $lut. Using template $paramod$dbc8f7566d7a2b175252eaced6bdaaa2a6a6fca8\$lut for cells of type $lut. Using template $paramod$4fb8f1dcaa5ed4a214eed67956a3e222ed476351\$lut for cells of type $lut. Using template $paramod$752a1403fa0122b7f12124796371674bbd22bac7\$lut for cells of type $lut. Using template $paramod$555ff3da129f73e80c0d5d22378b0f3245a14022\$lut for cells of type $lut. Using template $paramod$18d9a337a681d13f5f6ffd0b9a3872b8e2d3363b\$lut for cells of type $lut. Using template $paramod$9616fecedc1a6ce839b990a3156875e06908d6fa\$lut for cells of type $lut. Using template $paramod$c201ac910d99b98a649229da41a66244cb356a59\$lut for cells of type $lut. Using template $paramod$ac969d9398eb9421a30a342d303d11422783b5d2\$lut for cells of type $lut. Using template $paramod$4519ab29e9217c4395f2c0c8aada1c2a4f456f04\$lut for cells of type $lut. Using template $paramod$e1b218a70f1ce0b52aa63acf8429af610d800f8f\$lut for cells of type $lut. Using template $paramod$2b701a54b1fa07caf5ad3169601441a7477ba58b\$lut for cells of type $lut. Using template $paramod$1cbc1cee8540f4dc44f97e6686cc9dd91d04ceea\$lut for cells of type $lut. Using template $paramod$611b63e33cf60e9088760395030b43b241100670\$lut for cells of type $lut. Using template $paramod$865395c0228487a64a8e4011cecafc2c64b79f2b\$lut for cells of type $lut. Using template $paramod$3f943b31daf852ed1ca222e5bb6488e4bbd6a0e6\$lut for cells of type $lut. Using template $paramod$1f575543d734f2d93dfcc8f91b30fb001334bb95\$lut for cells of type $lut. Using template $paramod$6069048ea7c45159713a0558424cdfb243a46dfe\$lut for cells of type $lut. Using template $paramod$f610396a8c1614f373f4d73e3d1e988bc93e396c\$lut for cells of type $lut. Using template $paramod$6023c671e114c4eb0467aa8a0b08e183f33ec2fd\$lut for cells of type $lut. Using template $paramod$acbcca790b0862da1bab9f8418c2bac049e67246\$lut for cells of type $lut. Using template $paramod$a988852add2bdce7c1dfac786401ba7c7bc832c1\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11101111 for cells of type $lut. Using template $paramod$2d07c1a6c53c7b878509360922c4fa5ebedc3011\$lut for cells of type $lut. Using template $paramod$2382b0dd4cb27fd4312681c40a6dd179c2a7a26a\$lut for cells of type $lut. Using template $paramod$df196ed0a1da5c4a58c5e08a1dac304fd3fccaab\$lut for cells of type $lut. Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9\$lut for cells of type $lut. Using template $paramod$5307f40f1b453046eb68ee1a10c3f82d605af6fc\$lut for cells of type $lut. Using template $paramod$9506ecf18c91672f3dae4008b6ad1f2863e8019f\$lut for cells of type $lut. Using template $paramod$1f313f85ef575d13bac75382f04905a8c8be8f57\$lut for cells of type $lut. Using template $paramod$c958b3a888f937f082b94811ff62d71e32a2b4eb\$lut for cells of type $lut. Using template $paramod$8b5cd3db939d1b72145e634c68ab25658458fb1a\$lut for cells of type $lut. Using template $paramod$46381122ff9fbd2d7c6d9cec3a84642fbaa81843\$lut for cells of type $lut. Using template $paramod$46654478f15cf9dcb3f92426e419e9c9f11a784e\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01010111 for cells of type $lut. Using template $paramod$5348912da867a611a8088b6b8b27a62d65f1de6e\$lut for cells of type $lut. Using template $paramod$50ec6039d9de561a6d0a8dc470847f22a306b04f\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1101 for cells of type $lut. Using template $paramod$40a91d420225e3605a37470a6df218085e2b1db0\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010101 for cells of type $lut. Using template $paramod$09194da5f2c8e08bed8f609fd0e254d8629b24b3\$lut for cells of type $lut. Using template $paramod$4d7f17f71543a1e7fc1835bd79c4827a43f2e844\$lut for cells of type $lut. Using template $paramod$2c56adda0f23d3add745fd9eb8ad3ffc02c981b6\$lut for cells of type $lut. Using template $paramod$e1ac894a2723e96ae103a1941dc871fbb0ccd216\$lut for cells of type $lut. Using template $paramod$75020cdf7715bd4a5f7067d80cafc74eabba6a01\$lut for cells of type $lut. Using template $paramod$f58e0d90afc57a738914697b6a4a7319b30d7e7e\$lut for cells of type $lut. Using template $paramod$c1a19a87ccbbb03d43a72335db63f692ddf82cc1\$lut for cells of type $lut. Using template $paramod$11ec7271d8e6e5aeaace08c13e4c601f10e31038\$lut for cells of type $lut. Using template $paramod$ab4188c7524eec831e9177bc675d62b21a3ccd8b\$lut for cells of type $lut. Using template $paramod$02b63907fb626de3e5f6572173cbabd407ece191\$lut for cells of type $lut. Using template $paramod$8e44661def013b6bf9fe6f8b049ef2c838d749f9\$lut for cells of type $lut. Using template $paramod$82b4a585d1edcb5c6e755dc9bd3392228a1c1304\$lut for cells of type $lut. Using template $paramod$abaf3d04c136502e97aa54b58bddbaeb3679a345\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01111111 for cells of type $lut. Using template $paramod$8449ee0478eb4b5023de27c3684abbed3eb97f13\$lut for cells of type $lut. Using template $paramod$64b84593fae19d6c4d7d26333a195e5cc6b30160\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001010 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101101 for cells of type $lut. Using template $paramod$181733d3e31dcdcea8c52d0a4fc252b3aa453564\$lut for cells of type $lut. Using template $paramod$3c113f47a14d3df8f2933a6990f1690802de34db\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11010000 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001100 for cells of type $lut. Using template $paramod$beae4210b922fc9ba2fcc4008a7474b475e38c50\$lut for cells of type $lut. Using template $paramod$f8f63b209b7230e81958663ff24fef1613156af7\$lut for cells of type $lut. Using template $paramod$dd9047df8afc1543e47f4200533bb1ad5f56e5fc\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00110001 for cells of type $lut. Using template $paramod$a33dedc8e6ceb368aee74fa64ce54f3f4713cf02\$lut for cells of type $lut. Using template $paramod$e49f6e3576ef1a6d2f58c54414dbb786af8cc869\$lut for cells of type $lut. Using template $paramod$a8b2b0f3a3fd7b01c99e8d61bb72f602bd41af54\$lut for cells of type $lut. Using template $paramod$23764ef6208c0eba4ffe4afe904943e1ed80e8a4\$lut for cells of type $lut. Using template $paramod$413d040dcd860cd74ca61a70644516a95d328ae7\$lut for cells of type $lut. Using template $paramod$23da582b86241546eace0c8bedadb42614eea4c1\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10011100 for cells of type $lut. Using template $paramod$9dfe2a25d99d8640a9f67a2438aaca85b684d257\$lut for cells of type $lut. Using template $paramod$28e055f3918a7bfe516a9785e5b7eac06b9939b6\$lut for cells of type $lut. Using template $paramod$f109125ffdede8321ac65719b1066c75ff1eaef0\$lut for cells of type $lut. Using template $paramod$410654a338494d4983a424035c9c9af4ae257a26\$lut for cells of type $lut. Using template $paramod$d546db88fc169832512e499a9cdf9a41b89ab74e\$lut for cells of type $lut. Using template $paramod$c600b4b1adc22857e1c1ba3b6aeb516fabe09da0\$lut for cells of type $lut. Using template $paramod$498daa9936ffa1c0b12d774cacc95a35d14b818e\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000001 for cells of type $lut. Using template $paramod$35059585e93e18989247e13034fd6a1ce4de9957\$lut for cells of type $lut. Using template $paramod$5502a85110dbca29ac631107f0b0635e7fade476\$lut for cells of type $lut. Using template $paramod$8921e608da57eb3483e6390a11938d2bd4d7314d\$lut for cells of type $lut. Using template $paramod$5289dac6f25369a9a495c69c724c25ee83ad0e78\$lut for cells of type $lut. Using template $paramod$011aad93f7b1a0d8616dd3430217302e58fff744\$lut for cells of type $lut. Using template $paramod$7a73f9756d5c153bcd3667a54c2eeb22386fe779\$lut for cells of type $lut. Using template $paramod$f5f41ee5d60dede31a2b59f58ec46b167939d713\$lut for cells of type $lut. Using template $paramod$ecb2c9e18dd70cc05b15a15bce027a02fa7e0243\$lut for cells of type $lut. Using template $paramod$ce9ee1b270a69279e9f7c1e44d6bc8bdffb16ce0\$lut for cells of type $lut. Using template $paramod$766f851776a2d25e13728c9147ddfe7ff70917a3\$lut for cells of type $lut. Using template $paramod$25003f26a78bb2f583f23824f1e0b8cc16b88761\$lut for cells of type $lut. Using template $paramod$d35161d1d7976dcc02e7c7d51172431be85143b4\$lut for cells of type $lut. Using template $paramod$75f001c2559d212d7f58a5b0a49f25624079d3ef\$lut for cells of type $lut. Using template $paramod$ea7f757f55049f544d723cb6b33dd04de81547d5\$lut for cells of type $lut. Using template $paramod$ce3fc22bfce5a632ce0c9661803f849e9311a539\$lut for cells of type $lut. Using template $paramod$348cd8c9a97d63f888d1a5c06852eb88becfe928\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11011111 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11101100 for cells of type $lut. Using template $paramod$92bfb5061c8c34826821b741cd57edebb855bd3c\$lut for cells of type $lut. Using template $paramod$d727bc53a65b1ea655f59e0f9f4ed34abf3ab702\$lut for cells of type $lut. Using template $paramod$619b7c9a4d44585e10b42f7fb79b16304cca97c5\$lut for cells of type $lut. Using template $paramod$ed81d56ff8b20c7bc463767da6fbf55cba3f17fc\$lut for cells of type $lut. Using template $paramod$c5f3c57a6d466a2f42208bafb8985b96ce884440\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111011 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0110 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01101010 for cells of type $lut. Using template $paramod$fb5496753f4cd235e71c284b2ffee9d41a960ca2\$lut for cells of type $lut. Using template $paramod$769bdbbde83614df0f4ab5f54e777ded51bb10ce\$lut for cells of type $lut. No more expansions possible. <suppressed ~6068 debug messages> 24.44. Executing OPT_LUT_INS pass (discard unused LUT inputs). Optimizing LUTs in top. Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42073.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42077.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42074.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42076.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42081.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$42049$lut$aiger42048$6367.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$6367.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$6367.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$42049$lut$aiger42048$6367.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$42049$lut$aiger42048$6367.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$6367.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$6354.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$42049$lut$aiger42048$6354.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$42049$lut$aiger42048$6348.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$5990.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$5255.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$42049$lut$aiger42048$5255.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$5255.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$5255.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$42049$lut$aiger42048$4416.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$4416.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$4416.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$4416.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$4416.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$4347.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$4347.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$4347.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$4347.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$4347.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$4073.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$4073.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$4073.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$4073.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$4073.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$3967.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$3967.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$3967.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$3967.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$3967.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$3861.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42129.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42129.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42129.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42129.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42129.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$4551.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$4547.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$4543.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$42049$lut$aiger42048$4543.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$4543.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$4543.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$4527.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$42049$lut$aiger42048$4523.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$4523.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$4523.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$4523.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$4523.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42130.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$4488.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$4488.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$4466.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$4466.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$4458.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$4454.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$4454.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$4454.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$4454.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$4454.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42131.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42131.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42131.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42131.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42131.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42131.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42131.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$4327.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$4327.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$4288.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$42049$lut$aiger42048$4274.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$4274.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$4274.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$4274.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$4274.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$4274.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42133.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42133.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42133.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42133.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42133.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$4247.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$4247.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$4239.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$42049$lut$aiger42048$4239.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42134.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42134.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42134.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42134.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42134.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42134.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42135.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42135.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42135.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42135.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42135.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42135.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$4138.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$4138.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$4138.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$4138.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$42049$lut$aiger42048$4138.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$4125.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$4125.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$42049$lut$aiger42048$4125.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$42049$lut$aiger42048$4125.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42136.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42136.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42136.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42136.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42136.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$4102.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$4102.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$4102.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$4102.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$4102.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42137.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42137.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42137.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42137.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42137.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42137.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$4015.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$4015.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$4015.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42138.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42138.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42138.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42138.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42138.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42138.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$3989.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$42049$lut$aiger42048$3989.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$42049$lut$aiger42048$3983.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$42049$lut$aiger42048$3983.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$3983.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$42049$lut$aiger42048$3983.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42139.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42139.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42139.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42139.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42139.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42140.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42140.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42140.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42140.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42140.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42140.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$3883.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$3883.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$3883.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$3883.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42141.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42141.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42141.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42141.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42141.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42141.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$3825.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$3825.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$3825.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$3812.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$3812.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$3812.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$3812.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$3812.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$3812.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42142.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42142.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42142.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42142.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42142.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$3775.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$3775.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$3775.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$3775.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$3743.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$42049$lut$aiger42048$3743.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42143.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42151.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42151.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42151.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42151.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42151.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42151.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42151.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$2861.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$2812.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$2745.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$2745.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$2745.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$2745.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$2745.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$2745.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$2267.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$2035.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$4430.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$4504.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$42049$lut$aiger42048$2086.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$2086.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$2086.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$2086.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$2086.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$2086.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$1820.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$1820.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$1820.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$1820.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$1820.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$1820.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$1847.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$1847.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$1847.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$1847.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$1847.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$1838.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$1838.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$1838.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$1838.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$1838.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$1838.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42208.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42208.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42214.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42214.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42214.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42214.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42214.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42218.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42148.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$3273.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$3237.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$3237.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$3237.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$3237.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$3237.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42204.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42204.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$1745.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$3149.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$3138.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$2063.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$2063.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$2063.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$2063.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$2063.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$2063.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42144.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42144.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42144.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42144.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42144.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42144.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$3543.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$42049$lut$aiger42048$3543.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$42049$lut$aiger42048$3582.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$42049$lut$aiger42048$3582.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$42049$lut$aiger42048$3582.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$42049$lut$aiger42048$3553.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$2920.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$2915.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$3596.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42202.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42202.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42202.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42202.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42202.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42202.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$42049$lut$aiger42048$2351.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$2351.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$2351.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$2351.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$2351.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$2351.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42145.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42145.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42145.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42145.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42145.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42145.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$3490.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$42049$lut$aiger42048$3490.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$42049$lut$aiger42048$3503.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$42049$lut$aiger42048$3503.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$42049$lut$aiger42048$3145.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$42049$lut$aiger42048$3515.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42198.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42198.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42198.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42198.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42198.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42198.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$42049$lut$aiger42048$2125.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$2125.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$2125.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$2125.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$2125.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$2125.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42146.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$3438.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$3438.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42196.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42196.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42196.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42196.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42196.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42196.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$42049$lut$aiger42048$2574.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$2574.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$2574.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$2574.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$2574.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$2574.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$3660.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$3660.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$3623.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$42049$lut$aiger42048$3623.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$42049$lut$aiger42048$3646.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$3642.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42200.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42200.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42200.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42200.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42200.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42200.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$42049$lut$aiger42048$2468.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$2468.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$2468.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$2468.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$2468.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$2468.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$3677.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$3677.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$3677.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$3677.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$3677.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42192.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42192.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42192.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42192.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42192.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$42049$lut$aiger42048$3307.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$42049$lut$aiger42048$3307.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$42049$lut$aiger42048$3298.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$3293.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$3341.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$42049$lut$aiger42048$3341.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$3341.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$42049$lut$aiger42048$3341.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$42049$lut$aiger42048$4398.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$4398.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$4398.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$4398.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$4398.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$4392.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$42049$lut$aiger42048$4392.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$4392.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$4392.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$42049$lut$aiger42048$4365.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$42049$lut$aiger42048$4365.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$42049$lut$aiger42048$3007.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$3617.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$42049$lut$aiger42048$3617.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$1648.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$1648.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$1648.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$1648.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$1648.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$3371.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$42049$lut$aiger42048$3371.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$42049$lut$aiger42048$2099.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$42049$lut$aiger42048$3029.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42165.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42165.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42165.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42165.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42165.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42165.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$2252.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$42049$lut$aiger42048$1797.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42168.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42168.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$1883.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$1883.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$1883.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$42049$lut$aiger42048$1883.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42187.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42187.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$2433.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$2433.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$2433.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$2433.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$42049$lut$aiger42048$2433.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$2433.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$2433.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$42049$lut$aiger42048$2513.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$2513.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$2513.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$42049$lut$aiger42048$2513.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$2513.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$2513.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42179.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42179.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42181.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42181.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42184.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42185.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42185.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42222.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42222.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$1927.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$1927.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$1927.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$1927.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$1927.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$42049$lut$aiger42048$1905.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$1905.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$1905.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$1905.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42216.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42219.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42219.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$3577.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42201.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42201.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42201.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42201.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42201.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42201.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$2398.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$42049$lut$aiger42048$1949.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$1949.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$42049$lut$aiger42048$1949.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$42049$lut$aiger42048$1949.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$42049$lut$aiger42048$1949.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$1949.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$1949.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$3572.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$2189.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$2189.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$42049$lut$aiger42048$2189.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$42049$lut$aiger42048$2189.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$42049$lut$aiger42048$2189.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$2189.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$2189.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42203.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42203.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$3688.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$3688.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$2724.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$2724.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$2724.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$2724.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$42049$lut$aiger42048$2724.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$2724.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$2724.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42220.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42220.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42220.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42220.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42220.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42220.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$2634.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$42049$lut$aiger42048$2557.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$42049$lut$aiger42048$2539.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$2539.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$3561.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$3561.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42207.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42207.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42207.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42207.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42207.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42207.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$2234.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$42049$lut$aiger42048$1994.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42221.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42224.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42224.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$3697.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$42049$lut$aiger42048$3697.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$42049$lut$aiger42048$3697.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42191.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42191.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$2609.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$2609.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$42049$lut$aiger42048$2609.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$42049$lut$aiger42048$2609.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$42049$lut$aiger42048$2609.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$2609.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$2609.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42197.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42197.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42199.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42199.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42213.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42213.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42213.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42213.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42213.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42213.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$1779.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42217.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42217.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42173.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42173.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42173.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42173.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42173.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$2448.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$42049$lut$aiger42048$2387.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$2387.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$2387.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$42049$lut$aiger42048$2387.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$2387.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$2387.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42225.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42225.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42225.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$2703.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$2689.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$2689.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$2689.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$2689.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$2281.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$2281.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$2281.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$2281.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$2281.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42189.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42193.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42193.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$2793.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$2779.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$2779.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$2779.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$2779.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$2779.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$1599.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$1624.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$42049$lut$aiger42048$1631.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$1640.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$1648.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$1648.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$1715.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$1745.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$1759.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$1779.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$1797.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$1820.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$1838.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$1847.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$1857.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$1883.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42216.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$1905.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$1927.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$1868.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$1883.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$1949.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$1958.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42214.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$1980.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$1994.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$2017.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$2035.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$1745.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$2063.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$2035.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$2086.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$2099.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$2125.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$2139.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42212.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$42049$lut$aiger42048$2169.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$2189.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$2198.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42210.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$42049$lut$aiger42048$2220.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$2234.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$2252.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$2267.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$2281.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$2295.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$2267.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$2351.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$2365.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$2398.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$2448.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$2468.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$2482.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$2525.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$2539.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$2553.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$2574.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$2588.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$2609.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$2618.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$2625.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$2634.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$2654.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$2672.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$2689.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$2703.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$2739.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$2745.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$2764.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$2779.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$2793.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$2812.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$2817.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$2915.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$2939.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$2954.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$3007.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$3029.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$2857.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$3677.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$3082.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$3012.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42150.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$3138.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$3145.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$3237.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$42049$lut$aiger42048$3237.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$3273.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$3293.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$3307.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$42049$lut$aiger42048$3307.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42189.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$3371.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42148.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$3380.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$3384.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42147.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42184.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$3543.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$3600.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$42049$lut$aiger42048$3572.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$3596.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$3642.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$3660.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42192.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$42049$lut$aiger42048$3677.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42221.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$3697.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42129.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42143.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$3743.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$3775.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$3775.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42142.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$3812.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$42049$lut$aiger42048$3825.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$3861.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$42049$lut$aiger42048$3861.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$3874.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$3892.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42140.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$3932.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$3967.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42139.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42173.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$3998.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$4015.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$4028.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$4032.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$3967.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$4073.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$42049$lut$aiger42048$4073.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$4102.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$42049$lut$aiger42048$4102.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42136.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$4129.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$42049$lut$aiger42048$4138.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42135.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$4199.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42134.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$4247.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42133.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$4274.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$42049$lut$aiger42048$4320.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$42049$lut$aiger42048$4327.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$4347.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$4356.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$4398.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$4347.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$4416.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$42049$lut$aiger42048$4416.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$4430.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$4434.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$4454.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$4466.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$4466.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42130.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$4504.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$4523.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$4561.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$2281.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42153.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$4694.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$4910.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$4972.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$5033.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$5820.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$5939.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$6004.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$6004.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$4398.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$42049$lut$auto$opt_dff.cc:219:make_patterns_logic$3080.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$42049$lut$auto$fsm_map.cc:170:map_fsm$2864[1].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42068.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42093.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42051.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42053.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42055.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42056.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42058.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42059.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42060.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42061.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42062.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42063.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42064.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42065.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42067.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42069.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42070.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42071.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42078.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42084.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42087.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42079.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42072.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42080.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42114.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$4568.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42129.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42130.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42132.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42133.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42136.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42137.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42138.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42139.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42141.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42142.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42143.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42144.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42145.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42148.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42149.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$42049$lut$aiger42048$1574.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42165.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42166.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$4504.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42168.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42169.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42170.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$2513.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42173.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42174.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$2387.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42179.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42180.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42181.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42182.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42184.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42185.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42187.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42188.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42189.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42190.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42191.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42192.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42193.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42194.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$42049$lut$aiger42048$2618.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42196.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42197.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42198.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42199.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42200.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42201.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42202.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42203.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42204.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$42049$lut$aiger42048$1958.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42206.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42207.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42208.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$42049$lut$aiger42048$2198.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42211.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42213.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42214.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42216.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42217.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42219.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42220.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42221.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42222.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$42224.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Removed 0 unused cells and 2954 unused wires. 24.45. Executing AUTONAME pass. Renamed 179476 objects in module top (248 iterations). <suppressed ~7440 debug messages> 24.46. Executing HIERARCHY pass (managing design hierarchy). 24.46.1. Analyzing design hierarchy.. Top module: \top 24.46.2. Analyzing design hierarchy.. Top module: \top Removed 0 unused modules. 24.47. Printing statistics. === top === Number of wires: 3456 Number of wire bits: 8665 Number of public wires: 3456 Number of public wire bits: 8665 Number of ports: 6 Number of port bits: 18 Number of memories: 0 Number of memory bits: 0 Number of processes: 0 Number of cells: 4329 $_TBUF_ 6 $scopeinfo 31 CCU2C 164 L6MUX21 381 LUT4 2336 PFUMX 756 TRELLIS_DPR16X4 52 TRELLIS_FF 603 24.48. Executing CHECK pass (checking for obvious problems). Checking module top... Found and reported 0 problems. 24.49. Executing JSON backend. Warnings: 451 unique messages, 452 total End of script. Logfile hash: 6ee2bfc053, CPU: user 5.40s system 0.06s, MEM: 176.08 MB peak Yosys 0.42+36 (git sha1 07daf61ae, clang++ 14.0.0-1ubuntu1.1 -fPIC -Os) Time spent: 33% 1x abc9_exe (2 sec), 13% 11x techmap (1 sec), ... [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (NextPNR) [Pipeline] sh + /eda/oss-cad-suite/bin/nextpnr-ecp5 --json ./build/out.json --write ./build/out_pnr.json --45k --lpf Risco-5/fpga/ecp5/pinout.lpf --textcfg ./build/out.config --package CABGA381 --speed 6 --lpf-allow-unconstrained Info: constraining clock net 'clk' to 25.00 MHz Info: Logic utilisation before packing: Info: Total LUT4s: 2976/43848 6% Info: logic LUTs: 2336/43848 5% Info: carry LUTs: 328/43848 0% Info: RAM LUTs: 208/ 5481 3% Info: RAMW LUTs: 104/10962 0% Info: Total DFFs: 603/43848 1% Info: Packing IOs.. Info: $gpios[5]$iobuf_i: gpios_$_TBUF__Y.Y Info: pin 'gpios[5]$tr_io' constrained to Bel 'X9/Y71/PIOB'. Info: $gpios[4]$iobuf_i: gpios_$_TBUF__Y_1.Y Info: pin 'gpios[4]$tr_io' constrained to Bel 'X4/Y71/PIOB'. Info: $gpios[3]$iobuf_i: gpios_$_TBUF__Y_2.Y Info: pin 'gpios[3]$tr_io' constrained to Bel 'X0/Y65/PIOB'. Info: $gpios[2]$iobuf_i: gpios_$_TBUF__Y_3.Y Info: pin 'gpios[2]$tr_io' constrained to Bel 'X9/Y71/PIOA'. Info: $gpios[1]$iobuf_i: gpios_$_TBUF__Y_4.Y Info: pin 'gpios[1]$tr_io' constrained to Bel 'X6/Y71/PIOA'. Info: $gpios[0]$iobuf_i: gpios_$_TBUF__Y_5.Y Info: pin 'gpios[0]$tr_io' constrained to Bel 'X4/Y71/PIOA'. Info: pin 'tx$tr_io' constrained to Bel 'X90/Y20/PIOC'. Info: pin 'rx$tr_io' constrained to Bel 'X90/Y20/PIOA'. Info: pin 'reset$tr_io' constrained to Bel 'X0/Y29/PIOA'. Info: pin 'led[7]$tr_io' constrained to Bel 'X90/Y20/PIOD'. Info: pin 'led[6]$tr_io' constrained to Bel 'X0/Y44/PIOD'. Info: pin 'led[5]$tr_io' constrained to Bel 'X0/Y59/PIOA'. Info: pin 'led[4]$tr_io' constrained to Bel 'X15/Y71/PIOB'. Info: pin 'led[3]$tr_io' constrained to Bel 'X90/Y29/PIOC'. Info: pin 'led[2]$tr_io' constrained to Bel 'X90/Y44/PIOB'. Info: pin 'led[1]$tr_io' constrained to Bel 'X0/Y44/PIOC'. Info: pin 'led[0]$tr_io' constrained to Bel 'X0/Y59/PIOC'. Info: pin 'clk$tr_io' constrained to Bel 'X0/Y68/PIOC'. Info: Packing constants.. Info: Packing carries... Info: Packing LUTs... Info: Packing LUT5-7s... Info: Packing FFs... Info: 338 FFs paired with LUTs. Info: Generating derived timing constraints... Info: Promoting globals... Info: promoting clock net clk$TRELLIS_IO_IN to global network Info: Checksum: 0xc6e142a3 Info: Device utilisation: Info: TRELLIS_IO: 18/ 245 7% Info: DCCA: 1/ 56 1% Info: DP16KD: 0/ 108 0% Info: MULT18X18D: 0/ 72 0% Info: ALU54B: 0/ 36 0% Info: EHXPLLL: 0/ 4 0% Info: EXTREFB: 0/ 2 0% Info: DCUA: 0/ 2 0% Info: PCSCLKDIV: 0/ 2 0% Info: IOLOGIC: 0/ 160 0% Info: SIOLOGIC: 0/ 85 0% Info: GSR: 0/ 1 0% Info: JTAGG: 0/ 1 0% Info: OSCG: 0/ 1 0% Info: SEDGA: 0/ 1 0% Info: DTR: 0/ 1 0% Info: USRMCLK: 0/ 1 0% Info: CLKDIVF: 0/ 4 0% Info: ECLKSYNCB: 0/ 10 0% Info: DLLDELD: 0/ 8 0% Info: DDRDLL: 0/ 4 0% Info: DQSBUFM: 0/ 10 0% Info: TRELLIS_ECLKBUF: 0/ 8 0% Info: ECLKBRIDGECS: 0/ 2 0% Info: DCSC: 0/ 2 0% Info: TRELLIS_FF: 603/ 43848 1% Info: TRELLIS_COMB: 3064/ 43848 6% Info: TRELLIS_RAMW: 52/ 5481 0% Info: Placed 18 cells based on constraints. Info: Creating initial analytic placement for 1544 cells, random placement wirelen = 139708. Info: at initial placer iter 0, wirelen = 1872 Info: at initial placer iter 1, wirelen = 1477 Info: at initial placer iter 2, wirelen = 1511 Info: at initial placer iter 3, wirelen = 1473 Info: Running main analytical placer, max placement attempts per cell = 1746580. Info: at iteration #1, type ALL: wirelen solved = 1463, spread = 19509, legal = 19759; time = 0.10s Info: at iteration #2, type ALL: wirelen solved = 2731, spread = 16377, legal = 16630; time = 0.10s Info: at iteration #3, type ALL: wirelen solved = 3414, spread = 15384, legal = 15675; time = 0.09s Info: at iteration #4, type ALL: wirelen solved = 3968, spread = 14698, legal = 15228; time = 0.06s Info: at iteration #5, type ALL: wirelen solved = 4755, spread = 13794, legal = 14147; time = 0.06s Info: at iteration #6, type ALL: wirelen solved = 5054, spread = 13906, legal = 14438; time = 0.06s Info: at iteration #7, type ALL: wirelen solved = 5802, spread = 13623, legal = 14058; time = 0.06s Info: at iteration #8, type ALL: wirelen solved = 6277, spread = 13239, legal = 13656; time = 0.06s Info: at iteration #9, type ALL: wirelen solved = 6511, spread = 13468, legal = 13770; time = 0.06s Info: at iteration #10, type ALL: wirelen solved = 7155, spread = 13345, legal = 13665; time = 0.06s Info: at iteration #11, type ALL: wirelen solved = 7311, spread = 13636, legal = 13994; time = 0.06s Info: at iteration #12, type ALL: wirelen solved = 7619, spread = 13787, legal = 14080; time = 0.06s Info: at iteration #13, type ALL: wirelen solved = 7970, spread = 12771, legal = 13221; time = 0.06s Info: at iteration #14, type ALL: wirelen solved = 7747, spread = 12611, legal = 13118; time = 0.06s Info: at iteration #15, type ALL: wirelen solved = 7837, spread = 12512, legal = 13128; time = 0.06s Info: at iteration #16, type ALL: wirelen solved = 8080, spread = 12907, legal = 13339; time = 0.06s Info: at iteration #17, type ALL: wirelen solved = 8489, spread = 13348, legal = 13646; time = 0.06s Info: at iteration #18, type ALL: wirelen solved = 8852, spread = 13650, legal = 13982; time = 0.06s Info: at iteration #19, type ALL: wirelen solved = 9194, spread = 14300, legal = 14630; time = 0.06s Info: HeAP Placer Time: 2.15s Info: of which solving equations: 1.30s Info: of which spreading cells: 0.18s Info: of which strict legalisation: 0.06s Info: Running simulated annealing placer for refinement. Info: at iteration #1: temp = 0.000000, timing cost = 2420, wirelen = 13118 read_verilog: Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1317.090 ; gain = 0.023 ; free physical = 1464 ; free virtual = 24118 # read_verilog ../../debug/reset.v # read_verilog ../../src/core/alu_control.v # read_verilog ../../src/core/alu.v # read_verilog ../../src/core/control_unit.v # read_verilog ../../src/core/core.v # read_verilog ../../src/core/immediate_generator.v # read_verilog ../../src/core/mux.v # read_verilog ../../src/core/pc.v # read_verilog ../../src/core/registers.v # read_verilog ../../src/core/csr_unit.v # read_verilog ../../src/core/mdu.v # read_verilog ../../src/peripheral/bus.v # read_verilog ../../src/peripheral/gpio.v # read_verilog ../../src/peripheral/gpios.v # read_verilog ../../src/peripheral/leds.v # read_verilog ../../src/peripheral/memory.v # read_verilog ../../src/peripheral/soc.v # read_verilog ../../src/peripheral/uart_rx.v # read_verilog ../../src/peripheral/uart_tx.v # read_verilog ../../src/peripheral/uart.v # read_verilog ../../src/peripheral/fifo.v # read_verilog ../../src/peripheral/pwm.v # read_xdc "digilent_nexys4_ddr.xdc" # set_property PROCESSING_ORDER EARLY [get_files digilent_nexys4_ddr.xdc] # synth_design -top "top" -part "xc7a100tcsg324-1" Command: synth_design -top top -part xc7a100tcsg324-1 Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7a100t' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a100t' Info: at iteration #5: temp = 0.000000, timing cost = 2126, wirelen = 11316 Info: at iteration #10: temp = 0.000000, timing cost = 2154, wirelen = 10938 INFO: [Device 21-403] Loading part xc7a100tcsg324-1 Info: at iteration #15: temp = 0.000000, timing cost = 2173, wirelen = 10710 Info: at iteration #20: temp = 0.000000, timing cost = 2031, wirelen = 10632 Info: at iteration #20: temp = 0.000000, timing cost = 2026, wirelen = 10640 Info: SA placement time 5.47s Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 46.63 MHz (PASS at 25.00 MHz) Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 7.91 ns Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 10.12 ns Info: Slack histogram: Info: legend: * represents 8 endpoint(s) Info: + represents [1,8) endpoint(s) Info: [ 18556, 19591) |**+ Info: [ 19591, 20626) |*+ Info: [ 20626, 21661) | Info: [ 21661, 22696) |+ Info: [ 22696, 23731) |**+ Info: [ 23731, 24766) |**+ Info: [ 24766, 25801) |**+ Info: [ 25801, 26836) |+ Info: [ 26836, 27871) |*****+ Info: [ 27871, 28906) |*********************+ Info: [ 28906, 29941) |************************************************************ Info: [ 29941, 30976) |**************+ Info: [ 30976, 32011) |*********+ Info: [ 32011, 33046) |********+ Info: [ 33046, 34081) |******************+ Info: [ 34081, 35116) |*******************+ Info: [ 35116, 36151) |*************************************************+ Info: [ 36151, 37186) |*****************************************+ Info: [ 37186, 38221) |************************************+ Info: [ 38221, 39256) |****************+ Info: Checksum: 0x78216731 Info: Routing globals... Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0 Info: Routing.. Info: Setting up routing queue. Info: Routing 13102 arcs. Info: | (re-)routed arcs | delta | remaining| time spent | Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)| INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes. INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes INFO: [Synth 8-7075] Helper process launched with PID 892793 Info: 1000 | 361 638 | 361 638 | 12626| 0.38 0.38| Info: 2000 | 681 1318 | 320 680 | 12026| 0.25 0.63| Info: 3000 | 1123 1876 | 442 558 | 11599| 0.25 0.88| Info: 4000 | 1535 2464 | 412 588 | 11088| 0.28 1.15| Info: 5000 | 1996 3003 | 461 539 | 10631| 0.28 1.43| Info: 6000 | 2391 3608 | 395 605 | 10133| 0.27 1.70| Info: 7000 | 2777 4222 | 386 614 | 9566| 0.26 1.96| Info: 8000 | 3171 4828 | 394 606 | 9111| 0.28 2.24| Info: 9000 | 3595 5404 | 424 576 | 8611| 0.31 2.55| [80%] Tech-Mapping Phase 3 completed [90%] Tech-Mapping Phase 4 completed WARN (NL0002) : The module "ALU_Control" instantiated to "ALU_Control" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":261) WARN (NL0002) : The module "Immediate_Generator" instantiated to "Immediate_Generator" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":285) WARN (NL0002) : The module "GPIOS" instantiated to "GPIOS" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":159) WARN (NL0002) : The module "GPIO" instantiated to "Gpios[0]" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":45) WARN (NL0002) : The module "GPIO" instantiated to "Gpios[1]" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":45) WARN (NL0002) : The module "GPIO" instantiated to "Gpios[2]" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":45) WARN (NL0002) : The module "GPIO" instantiated to "Gpios[3]" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":45) WARN (NL0002) : The module "GPIO" instantiated to "Gpios[4]" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":45) WARN (NL0002) : The module "PWM" instantiated to "Pwm0" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":53) WARN (NL0002) : The module "PWM" instantiated to "Pwm1" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":61) WARN (NL0002) : The module "LEDs" instantiated to "Leds" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":121) [95%] Generate netlist file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/gwsynthesis/project.vg" completed [100%] Generate report file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/gwsynthesis/project_syn.rpt.html" completed GowinSynthesis finish Info: 10000 | 3986 6013 | 391 609 | 8112| 0.28 2.83| Reading netlist file: "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/gwsynthesis/project.vg" Info: 11000 | 4414 6585 | 428 572 | 7686| 0.29 3.13| Parsing netlist file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/gwsynthesis/project.vg" completed Info: 12000 | 4878 7121 | 464 536 | 7330| 0.30 3.43| Processing netlist completed Reading constraint file: "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/pinout.cst" Physical Constraint parsed completed Info: 13000 | 5326 7673 | 448 552 | 6975| 0.30 3.72| Running placement...... Info: 14000 | 5818 8181 | 492 508 | 6587| 0.28 4.00| Info: 15000 | 6204 8753 | 386 572 | 6052| 0.26 4.27| Info: 16000 | 6525 9247 | 321 494 | 5422| 0.17 4.44| Info: 17000 | 6721 9831 | 196 584 | 4661| 0.15 4.59| Info: 18000 | 7015 10473 | 294 642 | 4013| 0.22 4.81| Info: 19000 | 7095 11365 | 80 892 | 3113| 0.20 5.01| Info: 20000 | 7194 12216 | 99 851 | 2229| 0.21 5.21| --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2028.781 ; gain = 403.715 ; free physical = 424 ; free virtual = 23080 --------------------------------------------------------------------------------- Info: 21000 | 7286 13081 | 92 865 | 1339| 0.22 5.44| Info: 22000 | 7358 13920 | 72 839 | 434| 0.20 5.63| Info: 22433 | 7358 14115 | 0 195 | 0| 0.08 5.71| Info: Routing complete. Info: Router1 time 5.71s Info: Checksum: 0xf7bfca53 Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge): Info: curr total Info: 0.5 0.5 Source SOC.Core.instruction_register_TRELLIS_FF_Q_28.Q Info: 1.1 1.7 Net SOC.Core.instruction_register[2] (6,29) -> (5,30) Info: Sink SOC.Core.Control_Unit.func7_lsb_bit_LUT4_A_3_D_LUT4_Z.B Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.2 1.9 Source SOC.Core.Control_Unit.func7_lsb_bit_LUT4_A_3_D_LUT4_Z.F Info: 0.7 2.6 Net SOC.Core.Control_Unit.func7_lsb_bit_LUT4_A_3_D[4] (5,30) -> (6,30) Info: Sink SOC.Core.Control_Unit.func7_lsb_bit_LUT4_A_3_D_L6MUX21_SD_D1_PFUMX_Z_ALUT_LUT4_Z.M Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.3 2.8 Source SOC.Core.Control_Unit.func7_lsb_bit_LUT4_A_3_D_L6MUX21_SD_D1_PFUMX_Z_ALUT_LUT4_Z.OFX Info: 0.0 2.8 Net SOC.Core.Control_Unit.func7_lsb_bit_LUT4_A_3_D_L6MUX21_SD_Z (6,30) -> (6,30) Info: Sink SOC.Core.Control_Unit.func7_lsb_bit_LUT4_A_3_D_L6MUX21_SD_D0_PFUMX_Z_ALUT_LUT4_Z.FXB Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:157.70-157.72 Info: 0.2 3.1 Source SOC.Core.Control_Unit.func7_lsb_bit_LUT4_A_3_D_L6MUX21_SD_D0_PFUMX_Z_ALUT_LUT4_Z.OFX Info: 1.7 4.7 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_1_C_LUT4_Z_D_CCU2C_S1_B1_LUT4_D_Z_LUT4_Z_1_C[2] (6,30) -> (13,41) Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_1_C_LUT4_Z_D_CCU2C_S1_B1_LUT4_D_Z_LUT4_Z_D_LUT4_C_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_B_3_Z_LUT4_Z.D Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.2 5.0 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_1_C_LUT4_Z_D_CCU2C_S1_B1_LUT4_D_Z_LUT4_Z_D_LUT4_C_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_B_3_Z_LUT4_Z.F Info: 1.5 6.5 Net SOC.Core.Alu.ALU_out_S_L6MUX21_Z_1_SD_PFUMX_Z_C0_PFUMX_Z_C0[3] (13,41) -> (12,36) Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_A_LUT4_Z_D_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.B Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.4 6.9 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_A_LUT4_Z_D_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO Info: 0.0 6.9 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_A_LUT4_Z_D_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (12,36) -> (12,36) Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_A_LUT4_Z_D_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI Info: 0.0 6.9 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_A_LUT4_Z_D_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO Info: 0.0 6.9 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_A_LUT4_Z_D_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (12,36) -> (12,36) Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_A_LUT4_Z_D_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI Info: Defined in: Info: Risco-5/src/core/alu.v:35.26-35.45 Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4 Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13 Info: 0.1 7.0 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_A_LUT4_Z_D_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO Info: 0.0 7.0 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_A_LUT4_Z_D_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (12,36) -> (12,36) Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_A_LUT4_Z_D_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI Info: 0.0 7.0 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_A_LUT4_Z_D_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO Info: 0.0 7.0 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_A_LUT4_Z_D_CCU2C_S1_CIN_CCU2C_COUT_CIN (12,36) -> (12,36) Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_A_LUT4_Z_D_CCU2C_S1_CIN_CCU2C_COUT$CCU2_COMB0.FCI Info: Defined in: Info: Risco-5/src/core/alu.v:35.26-35.45 Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4 Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13 Info: 0.1 7.0 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_A_LUT4_Z_D_CCU2C_S1_CIN_CCU2C_COUT$CCU2_COMB0.FCO Info: 0.0 7.0 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_A_LUT4_Z_D_CCU2C_S1_CIN_CCU2C_COUT$CCU2_FCI_INT (12,36) -> (12,36) Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_A_LUT4_Z_D_CCU2C_S1_CIN_CCU2C_COUT$CCU2_COMB1.FCI Info: 0.0 7.0 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_A_LUT4_Z_D_CCU2C_S1_CIN_CCU2C_COUT$CCU2_COMB1.FCO Info: 0.0 7.0 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_A_LUT4_Z_D_CCU2C_S1_CIN (12,36) -> (13,36) Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_A_LUT4_Z_D_CCU2C_S1$CCU2_COMB0.FCI Info: Defined in: Info: Risco-5/src/core/alu.v:35.26-35.45 Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4 Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13 Info: 0.1 7.1 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_A_LUT4_Z_D_CCU2C_S1$CCU2_COMB0.FCO Info: 0.0 7.1 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_A_LUT4_Z_D_CCU2C_S1$CCU2_FCI_INT (13,36) -> (13,36) Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_A_LUT4_Z_D_CCU2C_S1$CCU2_COMB1.FCI Info: 0.0 7.1 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_A_LUT4_Z_D_CCU2C_S1$CCU2_COMB1.FCO Info: 0.0 7.1 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_A_LUT4_Z_D_CCU2C_S1_COUT (13,36) -> (13,36) Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_A_LUT4_Z_D_CCU2C_S1_COUT_CCU2C_CIN$CCU2_COMB0.FCI Info: Defined in: Info: Risco-5/src/core/alu.v:35.26-35.45 Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4 Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13 Info: 0.4 7.6 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_A_LUT4_Z_D_CCU2C_S1_COUT_CCU2C_CIN$CCU2_COMB0.F Info: 1.3 8.8 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_A_LUT4_Z_D_CCU2C_S1_COUT_CCU2C_CIN_S0[5] (13,36) -> (12,31) Info: Sink SOC.Core.Alu.ALU_out_S_L6MUX21_Z_6_SD_L6MUX21_Z_2_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.M Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.3 9.1 Source SOC.Core.Alu.ALU_out_S_L6MUX21_Z_6_SD_L6MUX21_Z_2_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX Info: 0.0 9.1 Net SOC.Core.Alu.ALU_out_S_L6MUX21_Z_6_SD_L6MUX21_Z_2_D1 (12,31) -> (12,31) Info: Sink SOC.Core.Alu.ALU_out_S_L6MUX21_Z_6_SD_L6MUX21_Z_2_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.FXB Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:157.70-157.72 Info: 0.2 9.3 Source SOC.Core.Alu.ALU_out_S_L6MUX21_Z_6_SD_L6MUX21_Z_2_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX Info: 1.5 10.9 Net SOC.Core.Alu.ALU_out_S_L6MUX21_Z_6_SD[6] (12,31) -> (12,43) Info: Sink SOC.Core.Alu.ALU_out_S_L6MUX21_Z_6_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.M Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.3 11.1 Source SOC.Core.Alu.ALU_out_S_L6MUX21_Z_6_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX Info: 1.0 12.1 Net SOC.Core.alu_out[8] (12,43) -> (12,37) Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_1_D_LUT4_A_Z_LUT4_Z.D Info: Defined in: Info: Risco-5/src/core/core.v:60.31-60.38 Info: 0.2 12.4 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_1_D_LUT4_A_Z_LUT4_Z.F Info: 0.5 12.8 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_1_D_LUT4_A_Z[2] (12,37) -> (15,37) Info: Sink SOC.Core.Pc.load_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.C Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.2 13.1 Source SOC.Core.Pc.load_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.F Info: 0.0 13.1 Net SOC.Core.Pc.load_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT (15,37) -> (15,37) Info: Sink SOC.Core.Pc.load_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.F1 Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:157.46-157.48 Info: 0.2 13.2 Source SOC.Core.Pc.load_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.OFX Info: 0.0 13.2 Net SOC.Core.Pc.load_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D1 (15,37) -> (15,37) Info: Sink SOC.Core.Pc.load_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.FXB Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:157.62-157.64 Info: 0.2 13.5 Source SOC.Core.Pc.load_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX Info: 0.0 13.5 Net SOC.Core.Pc.load_LUT4_Z_A_L6MUX21_Z_D1 (15,37) -> (15,37) Info: Sink SOC.Core.Pc.load_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.FXB Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:157.70-157.72 Info: 0.2 13.7 Source SOC.Core.Pc.load_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX Info: 0.8 14.5 Net SOC.Core.Pc.load_LUT4_Z_A[3] (15,37) -> (16,37) Info: Sink SOC.Core.Pc.load_LUT4_Z.D Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.2 14.7 Source SOC.Core.Pc.load_LUT4_Z.F Info: 1.6 16.3 Net SOC.Core.pc_load (16,37) -> (8,32) Info: Sink SOC.Core.Pc.Output_TRELLIS_FF_Q_21.CE Info: Defined in: Info: Risco-5/src/core/core.v:51.32-51.39 Info: 0.0 16.3 Setup SOC.Core.Pc.Output_TRELLIS_FF_Q_21.CE Info: 4.7 ns logic, 11.6 ns routing Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN': Info: curr total Info: 0.0 0.0 Source gpios[0]$tr_io.O Info: 2.3 2.3 Net gpios[0]$TRELLIS_IO_IN (4,71) -> (4,49) Info: Sink SOC.GPIOS.Gpios[0].data_in_LUT4_C.A Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.2 2.5 Source SOC.GPIOS.Gpios[0].data_in_LUT4_C.F Info: 1.3 3.8 Net SOC.GPIOS.Gpios[0].data_in_LUT4_C_Z[3] (4,49) -> (6,42) Info: Sink SOC.Core.read_data_LUT4_Z_D_LUT4_Z.D Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.2 4.0 Source SOC.Core.read_data_LUT4_Z_D_LUT4_Z.F Info: 0.6 4.7 Net SOC.Core.read_data_LUT4_Z_D[2] (6,42) -> (6,42) Info: Sink SOC.Core.read_data_LUT4_Z.D Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.2 4.9 Source SOC.Core.read_data_LUT4_Z.F Info: 1.4 6.3 Net SOC.read_data[0] (6,42) -> (5,30) Info: Sink SOC.Core.instruction_register_TRELLIS_FF_Q_30.M Info: Defined in: Info: Risco-5/src/peripheral/soc.v:24.34-24.43 Info: 0.0 6.3 Setup SOC.Core.instruction_register_TRELLIS_FF_Q_30.M Info: 0.7 ns logic, 5.6 ns routing Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>': Info: curr total Info: 0.5 0.5 Source SOC.Leds.data_TRELLIS_FF_Q_24.Q Info: 4.4 4.9 Net SOC.Core.read_data_LUT4_Z_6_C[0] (9,28) -> (84,27) Info: Sink led_LUT4_Z.D Info: Defined in: Info: Risco-5/src/peripheral/leds.v:19.12-19.16 Info: 0.2 5.1 Source led_LUT4_Z.F Info: 1.2 6.3 Net led[7]$TRELLIS_IO_OUT (84,27) -> (90,20) Info: Sink led[7]$tr_io.I Info: Defined in: Info: Risco-5/fpga/ecp5/main.v:6.22-6.25 Info: 0.8 ns logic, 5.6 ns routing Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 61.24 MHz (PASS at 25.00 MHz) Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 6.29 ns Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 6.35 ns Info: Slack histogram: Info: legend: * represents 8 endpoint(s) Info: + represents [1,8) endpoint(s) Info: [ 23671, 24441) |**+ Info: [ 24441, 25211) |+ Info: [ 25211, 25981) | Info: [ 25981, 26751) |+ Info: [ 26751, 27521) |*+ Info: [ 27521, 28291) |****+ Info: [ 28291, 29061) |*+ Info: [ 29061, 29831) |*+ Info: [ 29831, 30601) |***********+ Info: [ 30601, 31371) |*****************************************+ Info: [ 31371, 32141) |*********************************************+ Info: [ 32141, 32911) |*************+ Info: [ 32911, 33681) |*************+ Info: [ 33681, 34451) |**********************+ Info: [ 34451, 35221) |**********+ Info: [ 35221, 35991) |***************+ Info: [ 35991, 36761) |*********************+ Info: [ 36761, 37531) |************************************************************ Info: [ 37531, 38301) |*****************************************+ Info: [ 38301, 39071) |*********************+ INFO: [Synth 8-11241] undeclared symbol 'second_block_write_src_b', assumed default net type 'wire' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v:114] INFO: [Synth 8-11241] undeclared symbol 'pc_source', assumed default net type 'wire' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:187] WARNING: [Synth 8-9400] empty statement in sequential block [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v:54] INFO: [Synth 8-6157] synthesizing module 'top' [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/main.v:1] INFO: [Synth 8-6157] synthesizing module 'ResetBootSystem' [/var/lib/jenkins/workspace/Risco_5/Risco-5/debug/reset.v:1] Parameter CYCLES bound to: 20 - type: integer INFO: [Synth 8-6155] done synthesizing module 'ResetBootSystem' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/debug/reset.v:1] WARNING: [Synth 8-7071] port 'resetn_o' of module 'ResetBootSystem' is unconnected for instance 'ResetBootSystem' [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/main.v:24] WARNING: [Synth 8-7023] instance 'ResetBootSystem' of module 'ResetBootSystem' has 3 connections declared, but only 2 given [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/main.v:24] INFO: [Synth 8-6157] synthesizing module 'Risco_5_SOC' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:3] Parameter CLOCK_FREQ bound to: 50000000 - type: integer Parameter BIT_RATE bound to: 115200 - type: integer Parameter MEMORY_SIZE bound to: 2048 - type: integer Parameter MEMORY_FILE bound to: ../../software/memory/teste_uart_fpga.hex - type: string Parameter GPIO_WIDHT bound to: 8 - type: integer Parameter UART_BUFFER_SIZE bound to: 16 - type: integer INFO: [Synth 8-6157] synthesizing module 'Core' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:2] Parameter BOOT_ADDRESS bound to: 0 - type: integer INFO: [Synth 8-6157] synthesizing module 'PC' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/pc.v:1] INFO: [Synth 8-6155] done synthesizing module 'PC' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/pc.v:1] INFO: [Synth 8-6157] synthesizing module 'MUX' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/mux.v:1] INFO: [Synth 8-226] default block is never used [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/mux.v:15] INFO: [Synth 8-6155] done synthesizing module 'MUX' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/mux.v:1] WARNING: [Synth 8-7071] port 'C' of module 'MUX' is unconnected for instance 'MemoryAddressMUX' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:109] WARNING: [Synth 8-7071] port 'D' of module 'MUX' is unconnected for instance 'MemoryAddressMUX' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:109] WARNING: [Synth 8-7071] port 'E' of module 'MUX' is unconnected for instance 'MemoryAddressMUX' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:109] WARNING: [Synth 8-7071] port 'F' of module 'MUX' is unconnected for instance 'MemoryAddressMUX' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:109] WARNING: [Synth 8-7071] port 'G' of module 'MUX' is unconnected for instance 'MemoryAddressMUX' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:109] WARNING: [Synth 8-7071] port 'H' of module 'MUX' is unconnected for instance 'MemoryAddressMUX' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:109] WARNING: [Synth 8-7023] instance 'MemoryAddressMUX' of module 'MUX' has 10 connections declared, but only 4 given [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:109] WARNING: [Synth 8-7071] port 'C' of module 'MUX' is unconnected for instance 'MemoryDataMUX' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:119] WARNING: [Synth 8-7023] instance 'MemoryDataMUX' of module 'MUX' has 10 connections declared, but only 9 given [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:119] WARNING: [Synth 8-7071] port 'G' of module 'MUX' is unconnected for instance 'AluInputAMUX' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:140] WARNING: [Synth 8-7071] port 'H' of module 'MUX' is unconnected for instance 'AluInputAMUX' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:140] WARNING: [Synth 8-7023] instance 'AluInputAMUX' of module 'MUX' has 10 connections declared, but only 8 given [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:140] WARNING: [Synth 8-7071] port 'D' of module 'MUX' is unconnected for instance 'AluInputBMUX' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:156] WARNING: [Synth 8-7071] port 'E' of module 'MUX' is unconnected for instance 'AluInputBMUX' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:156] WARNING: [Synth 8-7071] port 'F' of module 'MUX' is unconnected for instance 'AluInputBMUX' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:156] WARNING: [Synth 8-7071] port 'G' of module 'MUX' is unconnected for instance 'AluInputBMUX' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:156] WARNING: [Synth 8-7071] port 'H' of module 'MUX' is unconnected for instance 'AluInputBMUX' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:156] WARNING: [Synth 8-7023] instance 'AluInputBMUX' of module 'MUX' has 10 connections declared, but only 5 given [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:156] INFO: [Synth 8-6157] synthesizing module 'Registers' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/registers.v:2] INFO: [Synth 8-6155] done synthesizing module 'Registers' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/registers.v:2] INFO: [Synth 8-6157] synthesizing module 'Control_Unit' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v:2] INFO: [Synth 8-155] case statement is not full and has no default [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v:171] INFO: [Synth 8-155] case statement is not full and has no default [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v:383] INFO: [Synth 8-6155] done synthesizing module 'Control_Unit' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v:2] WARNING: [Synth 8-7071] port 'last_bits_saved_address' of module 'Control_Unit' is unconnected for instance 'Control_Unit' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:215] WARNING: [Synth 8-7023] instance 'Control_Unit' of module 'Control_Unit' has 33 connections declared, but only 32 given [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:215] INFO: [Synth 8-6157] synthesizing module 'ALU_Control' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v:1] INFO: [Synth 8-226] default block is never used [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v:34] INFO: [Synth 8-155] case statement is not full and has no default [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v:11] INFO: [Synth 8-6155] done synthesizing module 'ALU_Control' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v:1] INFO: [Synth 8-6157] synthesizing module 'Alu' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu.v:1] INFO: [Synth 8-6155] done synthesizing module 'Alu' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu.v:1] INFO: [Synth 8-6157] synthesizing module 'Immediate_Generator' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/immediate_generator.v:1] INFO: [Synth 8-6155] done synthesizing module 'Immediate_Generator' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/immediate_generator.v:1] INFO: [Synth 8-6155] done synthesizing module 'Core' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:2] WARNING: [Synth 8-7071] port 'halt' of module 'Core' is unconnected for instance 'Core' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:35] WARNING: [Synth 8-7071] port 'interruption_request_external' of module 'Core' is unconnected for instance 'Core' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:35] WARNING: [Synth 8-7071] port 'interruption_request_timer' of module 'Core' is unconnected for instance 'Core' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:35] WARNING: [Synth 8-7071] port 'interruption_request_software' of module 'Core' is unconnected for instance 'Core' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:35] WARNING: [Synth 8-7071] port 'interruption_request_fast' of module 'Core' is unconnected for instance 'Core' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:35] WARNING: [Synth 8-7023] instance 'Core' of module 'Core' has 14 connections declared, but only 9 given [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:35] INFO: [Synth 8-6157] synthesizing module 'Memory' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v:1] Parameter MEMORY_FILE bound to: ../../software/memory/teste_uart_fpga.hex - type: string Parameter MEMORY_SIZE bound to: 2048 - type: integer INFO: [Synth 8-3876] $readmem data file '../../software/memory/teste_uart_fpga.hex' is read successfully [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v:35] INFO: [Synth 8-6155] done synthesizing module 'Memory' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v:1] INFO: [Synth 8-6157] synthesizing module 'BUS' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/bus.v:1] INFO: [Synth 8-6155] done synthesizing module 'BUS' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/bus.v:1] INFO: [Synth 8-6157] synthesizing module 'LEDs' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/leds.v:5] INFO: [Synth 8-6155] done synthesizing module 'LEDs' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/leds.v:5] INFO: [Synth 8-6157] synthesizing module 'UART' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart.v:4] Parameter CLK_FREQ bound to: 50000000 - type: integer Parameter BIT_RATE bound to: 115200 - type: integer Parameter BUFFER_SIZE bound to: 16 - type: integer INFO: [Synth 8-6157] synthesizing module 'FIFO' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/fifo.v:4] Parameter DEPTH bound to: 16 - type: integer Parameter WIDTH bound to: 8 - type: integer INFO: [Synth 8-6155] done synthesizing module 'FIFO' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/fifo.v:4] INFO: [Synth 8-6157] synthesizing module 'uart_tool_rx' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_rx.v:13] Parameter BIT_RATE bound to: 115200 - type: integer Parameter CLK_HZ bound to: 50000000 - type: integer Parameter PAYLOAD_BITS bound to: 8 - type: integer INFO: [Synth 8-6155] done synthesizing module 'uart_tool_rx' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_rx.v:13] INFO: [Synth 8-6157] synthesizing module 'uart_tool_tx' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_tx.v:13] Parameter BIT_RATE bound to: 115200 - type: integer Parameter CLK_HZ bound to: 50000000 - type: integer Parameter PAYLOAD_BITS bound to: 8 - type: integer INFO: [Synth 8-6155] done synthesizing module 'uart_tool_tx' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_tx.v:13] INFO: [Synth 8-6155] done synthesizing module 'UART' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart.v:4] INFO: [Synth 8-6157] synthesizing module 'GPIOS' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v:4] Parameter WIDHT bound to: 8 - type: integer INFO: [Synth 8-6157] synthesizing module 'GPIO' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpio.v:5] INFO: [Synth 8-6155] done synthesizing module 'GPIO' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpio.v:5] INFO: [Synth 8-6157] synthesizing module 'PWM' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/pwm.v:5] INFO: [Synth 8-6155] done synthesizing module 'PWM' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/pwm.v:5] INFO: [Synth 8-155] case statement is not full and has no default [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v:68] INFO: [Synth 8-6155] done synthesizing module 'GPIOS' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v:4] INFO: [Synth 8-6155] done synthesizing module 'Risco_5_SOC' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:3] INFO: [Synth 8-6155] done synthesizing module 'top' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/main.v:1] Info: Program finished normally. WARNING: [Synth 8-3848] Net mdu_done in module/entity Core does not have driver. [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:55] WARNING: [Synth 8-6014] Unused sequential element tx_fifo_read_reg was removed. [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart.v:163] [Pipeline] } [Pipeline] // stage WARNING: [Synth 8-7129] Port address[31] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[30] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[29] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[28] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[27] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[26] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[25] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[24] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[23] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[22] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[21] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[20] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[19] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[18] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[17] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[16] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[15] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[14] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[13] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[12] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[11] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[10] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[9] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[8] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[31] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[30] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[29] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[28] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[27] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[26] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[25] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[24] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[23] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[22] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[21] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[20] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[19] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[18] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[17] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[31] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[30] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[29] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[28] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[27] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[26] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[25] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[24] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[23] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[22] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[21] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[20] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[19] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[18] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[17] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[16] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[15] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[14] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[13] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[12] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[11] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[10] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[9] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[8] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[7] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[6] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[5] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[1] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[0] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[31] in module LEDs is either unconnected or has no load WARNING: [Synth 8-7129] Port address[30] in module LEDs is either unconnected or has no load WARNING: [Synth 8-7129] Port address[29] in module LEDs is either unconnected or has no load WARNING: [Synth 8-7129] Port address[28] in module LEDs is either unconnected or has no load WARNING: [Synth 8-7129] Port address[27] in module LEDs is either unconnected or has no load WARNING: [Synth 8-7129] Port address[26] in module LEDs is either unconnected or has no load WARNING: [Synth 8-7129] Port address[25] in module LEDs is either unconnected or has no load WARNING: [Synth 8-7129] Port address[24] in module LEDs is either unconnected or has no load WARNING: [Synth 8-7129] Port address[23] in module LEDs is either unconnected or has no load WARNING: [Synth 8-7129] Port address[22] in module LEDs is either unconnected or has no load WARNING: [Synth 8-7129] Port address[21] in module LEDs is either unconnected or has no load WARNING: [Synth 8-7129] Port address[20] in module LEDs is either unconnected or has no load WARNING: [Synth 8-7129] Port address[19] in module LEDs is either unconnected or has no load WARNING: [Synth 8-7129] Port address[18] in module LEDs is either unconnected or has no load WARNING: [Synth 8-7129] Port address[17] in module LEDs is either unconnected or has no load WARNING: [Synth 8-7129] Port address[16] in module LEDs is either unconnected or has no load WARNING: [Synth 8-7129] Port address[15] in module LEDs is either unconnected or has no load WARNING: [Synth 8-7129] Port address[14] in module LEDs is either unconnected or has no load WARNING: [Synth 8-7129] Port address[13] in module LEDs is either unconnected or has no load WARNING: [Synth 8-7129] Port address[12] in module LEDs is either unconnected or has no load WARNING: [Synth 8-7129] Port address[11] in module LEDs is either unconnected or has no load WARNING: [Synth 8-7129] Port address[10] in module LEDs is either unconnected or has no load WARNING: [Synth 8-7129] Port address[9] in module LEDs is either unconnected or has no load WARNING: [Synth 8-7129] Port address[8] in module LEDs is either unconnected or has no load WARNING: [Synth 8-7129] Port address[7] in module LEDs is either unconnected or has no load WARNING: [Synth 8-7129] Port address[6] in module LEDs is either unconnected or has no load WARNING: [Synth 8-7129] Port address[5] in module LEDs is either unconnected or has no load WARNING: [Synth 8-7129] Port address[4] in module LEDs is either unconnected or has no load WARNING: [Synth 8-7129] Port address[3] in module LEDs is either unconnected or has no load WARNING: [Synth 8-7129] Port address[2] in module LEDs is either unconnected or has no load WARNING: [Synth 8-7129] Port address[1] in module LEDs is either unconnected or has no load WARNING: [Synth 8-7129] Port address[0] in module LEDs is either unconnected or has no load INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2112.750 ; gain = 487.684 ; free physical = 549 ; free virtual = 23193 --------------------------------------------------------------------------------- [10%] Placement Phase 0 completed --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2127.594 ; gain = 502.527 ; free physical = 525 ; free virtual = 23169 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2127.594 ; gain = 502.527 ; free physical = 525 ; free virtual = 23169 --------------------------------------------------------------------------------- [Pipeline] stage [Pipeline] { (ECPPACK) Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2127.594 ; gain = 0.000 ; free physical = 511 ; free virtual = 23154 [Pipeline] sh + /eda/oss-cad-suite/bin/ecppack --compress --input ./build/out.config --bit ./build/out.bit [20%] Placement Phase 1 completed [Pipeline] } INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine [Pipeline] // stage Parsing XDC File [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc] [Pipeline] } [Pipeline] // stage Finished Parsing XDC File [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc] INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Completed Processing XDC Constraints Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2278.344 ; gain = 0.000 ; free physical = 483 ; free virtual = 23127 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2278.379 ; gain = 0.000 ; free physical = 493 ; free virtual = 23137 [Pipeline] } --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 2278.379 ; gain = 653.312 ; free physical = 491 ; free virtual = 23135 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7a100tcsg324-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 2278.379 ; gain = 653.312 ; free physical = 491 ; free virtual = 23135 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 2278.379 ; gain = 653.312 ; free physical = 491 ; free virtual = 23135 --------------------------------------------------------------------------------- INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'ResetBootSystem' INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'Control_Unit' INFO: [Synth 8-802] inferred FSM for state register 'fsm_state_reg' in module 'uart_tool_rx' [30%] Placement Phase 2 completed INFO: [Synth 8-802] inferred FSM for state register 'fsm_state_reg' in module 'uart_tool_tx' INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'UART' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- RESET_COUNTER | 00 | 01 IDLE | 01 | 10 INIT | 10 | 00 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'ResetBootSystem' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- FETCH | 00000000000000001 | 000000 VALIDATE_FETCH | 00000000000000010 | 101110 DECODE | 00000000000000100 | 000001 MEMADR | 00000000000001000 | 000010 MEMREAD | 00000000000010000 | 000011 MEMWB | 00000000000100000 | 000100 MEMWRITE | 00000000001000000 | 000101 EXECUTER | 00000000010000000 | 000110 EXECUTEI | 00000000100000000 | 001000 JAL | 00000001000000000 | 001001 BRANCH | 00000010000000000 | 001010 AUIPC | 00000100000000000 | 001100 LUI | 00001000000000000 | 001101 JALR_PC | 00010000000000000 | 001110 JALR | 00100000000000000 | 001011 ALUWB | 01000000000000000 | 000111 EXECUTECSR | 10000000000000000 | 001111 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'Control_Unit' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- FSM_IDLE | 00 | 000 FSM_START | 11 | 001 FSM_RECV | 10 | 010 FSM_STOP | 01 | 011 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'fsm_state_reg' using encoding 'sequential' in module 'uart_tool_rx' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- FSM_IDLE | 00 | 000 FSM_START | 11 | 001 FSM_SEND | 10 | 010 FSM_STOP | 01 | 011 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'fsm_state_reg' using encoding 'sequential' in module 'uart_tool_tx' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- IDLE | 0000 | 0000 COPY_WRITE_BUFFER | 0001 | 0100 WRITE | 0010 | 0010 READ | 0011 | 0001 READ_RX_FIFO_EMPTY | 0100 | 0110 READ_TX_FIFO_EMPTY | 0101 | 0111 READ_RX_FIFO_FULL | 0110 | 1000 READ_TX_FIFO_FULL | 0111 | 1001 WB | 1000 | 0101 FINISH | 1001 | 0011 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'UART' --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 2278.379 ; gain = 653.312 ; free physical = 489 ; free virtual = 23134 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Adders : 2 Input 32 Bit Adders := 1 3 Input 32 Bit Adders := 1 2 Input 10 Bit Adders := 2 2 Input 6 Bit Adders := 6 2 Input 5 Bit Adders := 1 2 Input 4 Bit Adders := 2 2 Input 3 Bit Adders := 1 +---XORs : 2 Input 32 Bit XORs := 1 +---Registers : 32 Bit Registers := 42 16 Bit Registers := 4 10 Bit Registers := 2 8 Bit Registers := 8 6 Bit Registers := 5 4 Bit Registers := 2 3 Bit Registers := 1 2 Bit Registers := 1 1 Bit Registers := 15 +---RAMs : 16K Bit (512 X 32 bit) RAMs := 1 128 Bit (16 X 8 bit) RAMs := 2 +---Muxes : 2 Input 32 Bit Muxes := 4 8 Input 32 Bit Muxes := 1 3 Input 32 Bit Muxes := 1 6 Input 32 Bit Muxes := 1 4 Input 32 Bit Muxes := 1 10 Input 32 Bit Muxes := 2 17 Input 17 Bit Muxes := 1 2 Input 17 Bit Muxes := 4 11 Input 17 Bit Muxes := 1 2 Input 8 Bit Muxes := 3 3 Input 6 Bit Muxes := 1 2 Input 6 Bit Muxes := 4 2 Input 5 Bit Muxes := 1 9 Input 4 Bit Muxes := 1 10 Input 4 Bit Muxes := 2 2 Input 4 Bit Muxes := 2 6 Input 4 Bit Muxes := 1 10 Input 3 Bit Muxes := 2 2 Input 3 Bit Muxes := 1 3 Input 2 Bit Muxes := 1 2 Input 2 Bit Muxes := 16 17 Input 2 Bit Muxes := 4 4 Input 2 Bit Muxes := 4 3 Input 1 Bit Muxes := 6 2 Input 1 Bit Muxes := 72 17 Input 1 Bit Muxes := 5 4 Input 1 Bit Muxes := 2 10 Input 1 Bit Muxes := 8 6 Input 1 Bit Muxes := 7 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 240 (col length:80) BRAMs: 270 (col length: RAMB18 80 RAMB36 40) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- WARNING: [Synth 8-7080] Parallel synthesis criteria is not met INFO: [Synth 8-6851] RAM (SOC/Memory/memory_reg) has partial Byte Wide Write Enable pattern, however no output register found in fanout of RAM. Recommended to use supported Byte Wide Write Enable template. --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:25 ; elapsed = 00:00:25 . Memory (MB): peak = 2278.379 ; gain = 653.312 ; free physical = 423 ; free virtual = 23074 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- Distributed RAM: Preliminary Mapping Report (see note below) +------------+-----------------------------+-----------+----------------------+-----------------+ |Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | +------------+-----------------------------+-----------+----------------------+-----------------+ |top | SOC/Memory/memory_reg | Implied | 512 x 32 | RAM256X1S x 64 | |top | SOC/Uart/RX_FIFO/memory_reg | Implied | 16 x 8 | RAM32M x 2 | |top | SOC/Uart/TX_FIFO/memory_reg | Implied | 16 x 8 | RAM32M x 2 | +------------+-----------------------------+-----------+----------------------+-----------------+ Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once. --------------------------------------------------------------------------------- Finished ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:29 ; elapsed = 00:00:29 . Memory (MB): peak = 2278.379 ; gain = 653.312 ; free physical = 421 ; free virtual = 23072 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:31 ; elapsed = 00:00:31 . Memory (MB): peak = 2278.379 ; gain = 653.312 ; free physical = 420 ; free virtual = 23071 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- Distributed RAM: Final Mapping Report +------------+-----------------------------+-----------+----------------------+-----------------+ |Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | +------------+-----------------------------+-----------+----------------------+-----------------+ |top | SOC/Memory/memory_reg | Implied | 512 x 32 | RAM256X1S x 64 | |top | SOC/Uart/RX_FIFO/memory_reg | Implied | 16 x 8 | RAM32M x 2 | |top | SOC/Uart/TX_FIFO/memory_reg | Implied | 16 x 8 | RAM32M x 2 | +------------+-----------------------------+-----------+----------------------+-----------------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- [50%] Placement Phase 3 completed Running routing...... --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:32 ; elapsed = 00:00:33 . Memory (MB): peak = 2278.379 ; gain = 653.312 ; free physical = 420 ; free virtual = 23071 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- [60%] Routing Phase 0 completed --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:36 ; elapsed = 00:00:37 . Memory (MB): peak = 2278.379 ; gain = 653.312 ; free physical = 360 ; free virtual = 23012 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:37 ; elapsed = 00:00:37 . Memory (MB): peak = 2278.379 ; gain = 653.312 ; free physical = 360 ; free virtual = 23012 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:37 ; elapsed = 00:00:37 . Memory (MB): peak = 2278.379 ; gain = 653.312 ; free physical = 360 ; free virtual = 23012 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:37 ; elapsed = 00:00:37 . Memory (MB): peak = 2278.379 ; gain = 653.312 ; free physical = 360 ; free virtual = 23012 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:37 ; elapsed = 00:00:37 . Memory (MB): peak = 2278.379 ; gain = 653.312 ; free physical = 361 ; free virtual = 23013 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:37 ; elapsed = 00:00:37 . Memory (MB): peak = 2278.379 ; gain = 653.312 ; free physical = 361 ; free virtual = 23013 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+----------+------+ | |Cell |Count | +------+----------+------+ |1 |BUFG | 2| |2 |CARRY4 | 55| |3 |LUT1 | 13| |4 |LUT2 | 111| |5 |LUT3 | 150| |6 |LUT4 | 238| |7 |LUT5 | 234| |8 |LUT6 | 1028| |9 |MUXF7 | 291| |10 |RAM256X1S | 64| |11 |RAM32M | 2| |12 |RAM32X1D | 4| |13 |FDRE | 1611| |14 |FDSE | 4| |15 |IBUF | 3| |16 |IOBUF | 8| |17 |OBUF | 9| +------+----------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:37 ; elapsed = 00:00:37 . Memory (MB): peak = 2278.379 ; gain = 653.312 ; free physical = 361 ; free virtual = 23013 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 30 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:35 ; elapsed = 00:00:35 . Memory (MB): peak = 2278.379 ; gain = 502.527 ; free physical = 360 ; free virtual = 23012 Synthesis Optimization Complete : Time (s): cpu = 00:00:37 ; elapsed = 00:00:37 . Memory (MB): peak = 2278.379 ; gain = 653.312 ; free physical = 360 ; free virtual = 23012 INFO: [Project 1-571] Translating synthesized netlist Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2278.379 ; gain = 0.000 ; free physical = 633 ; free virtual = 23286 INFO: [Netlist 29-17] Analyzing 424 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization Parsing XDC File [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc] Finished Parsing XDC File [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc] INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2342.375 ; gain = 0.000 ; free physical = 633 ; free virtual = 23286 INFO: [Project 1-111] Unisim Transformation Summary: A total of 78 instances were transformed. IOBUF => IOBUF (IBUF, OBUFT): 8 instances RAM256X1S => RAM256X1S (MUXF7(x2), MUXF8, RAMS64E(x4)): 64 instances RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 2 instances RAM32X1D => RAM32X1D (RAMD32(x2)): 4 instances Synth Design complete | Checksum: e175bf3 INFO: [Common 17-83] Releasing license: Synthesis 78 Infos, 132 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:46 ; elapsed = 00:00:44 . Memory (MB): peak = 2342.410 ; gain = 1025.320 ; free physical = 618 ; free virtual = 23271 INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 2023.538; main = 1744.341; forked = 422.487 INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3215.988; main = 2342.379; forked = 969.656 # opt_design Command: opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' Running DRC as a precondition to command opt_design Starting DRC Task INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Project 1-461] DRC finished with 0 Errors INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.79 . Memory (MB): peak = 2406.406 ; gain = 63.996 ; free physical = 620 ; free virtual = 23273 Starting Cache Timing Information Task [70%] Routing Phase 1 completed INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Cache Timing Information Task | Checksum: 11783c073 Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2520.219 ; gain = 113.812 ; free physical = 557 ; free virtual = 23210 Starting Logic Optimization Task Phase 1 Initialization Phase 1.1 Core Generation And Design Setup Phase 1.1 Core Generation And Design Setup | Checksum: 11783c073 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2766.156 ; gain = 0.000 ; free physical = 381 ; free virtual = 23002 Phase 1.2 Setup Constraints And Sort Netlist Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 11783c073 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2766.156 ; gain = 0.000 ; free physical = 381 ; free virtual = 23002 Phase 1 Initialization | Checksum: 11783c073 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2766.156 ; gain = 0.000 ; free physical = 381 ; free virtual = 23002 Phase 2 Timer Update And Timing Data Collection Phase 2.1 Timer Update Phase 2.1 Timer Update | Checksum: 11783c073 Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2766.156 ; gain = 0.000 ; free physical = 381 ; free virtual = 23002 Phase 2.2 Timing Data Collection Phase 2.2 Timing Data Collection | Checksum: 11783c073 Time (s): cpu = 00:00:00.15 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2766.156 ; gain = 0.000 ; free physical = 381 ; free virtual = 23002 Phase 2 Timer Update And Timing Data Collection | Checksum: 11783c073 Time (s): cpu = 00:00:00.15 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2766.156 ; gain = 0.000 ; free physical = 381 ; free virtual = 23002 Phase 3 Retarget INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Opt 31-49] Retargeted 0 cell(s). Phase 3 Retarget | Checksum: 11783c073 Time (s): cpu = 00:00:00.19 ; elapsed = 00:00:00.1 . Memory (MB): peak = 2766.156 ; gain = 0.000 ; free physical = 381 ; free virtual = 23002 Retarget | Checksum: 11783c073 INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells Phase 4 Constant propagation INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 4 Constant propagation | Checksum: 1256b1c95 Time (s): cpu = 00:00:00.26 ; elapsed = 00:00:00.17 . Memory (MB): peak = 2766.156 ; gain = 0.000 ; free physical = 381 ; free virtual = 23002 Constant propagation | Checksum: 1256b1c95 INFO: [Opt 31-389] Phase Constant propagation created 36 cells and removed 169 cells Phase 5 Sweep Phase 5 Sweep | Checksum: 184af889d Time (s): cpu = 00:00:00.3 ; elapsed = 00:00:00.21 . Memory (MB): peak = 2766.156 ; gain = 0.000 ; free physical = 381 ; free virtual = 23002 Sweep | Checksum: 184af889d INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 17 cells Phase 6 BUFG optimization Phase 6 BUFG optimization | Checksum: 184af889d Time (s): cpu = 00:00:00.37 ; elapsed = 00:00:00.25 . Memory (MB): peak = 2798.172 ; gain = 32.016 ; free physical = 381 ; free virtual = 23002 BUFG optimization | Checksum: 184af889d INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. Phase 7 Shift Register Optimization INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs Phase 7 Shift Register Optimization | Checksum: 184af889d Time (s): cpu = 00:00:00.37 ; elapsed = 00:00:00.25 . Memory (MB): peak = 2798.172 ; gain = 32.016 ; free physical = 381 ; free virtual = 23002 Shift Register Optimization | Checksum: 184af889d INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells Phase 8 Post Processing Netlist Phase 8 Post Processing Netlist | Checksum: 184af889d Time (s): cpu = 00:00:00.38 ; elapsed = 00:00:00.26 . Memory (MB): peak = 2798.172 ; gain = 32.016 ; free physical = 381 ; free virtual = 23002 Post Processing Netlist | Checksum: 184af889d INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells Phase 9 Finalization Phase 9.1 Finalizing Design Cores and Updating Shapes Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 18b0907d0 Time (s): cpu = 00:00:00.45 ; elapsed = 00:00:00.3 . Memory (MB): peak = 2798.172 ; gain = 32.016 ; free physical = 381 ; free virtual = 23002 Phase 9.2 Verifying Netlist Connectivity Starting Connectivity Check Task Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2798.172 ; gain = 0.000 ; free physical = 381 ; free virtual = 23002 Phase 9.2 Verifying Netlist Connectivity | Checksum: 18b0907d0 Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:00.31 . Memory (MB): peak = 2798.172 ; gain = 32.016 ; free physical = 381 ; free virtual = 23002 Phase 9 Finalization | Checksum: 18b0907d0 Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:00.31 . Memory (MB): peak = 2798.172 ; gain = 32.016 ; free physical = 381 ; free virtual = 23002 Opt_design Change Summary ========================= ------------------------------------------------------------------------------------------------------------------------- | Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | ------------------------------------------------------------------------------------------------------------------------- | Retarget | 0 | 0 | 0 | | Constant propagation | 36 | 169 | 0 | | Sweep | 0 | 17 | 0 | | BUFG optimization | 0 | 0 | 0 | | Shift Register Optimization | 0 | 0 | 0 | | Post Processing Netlist | 0 | 0 | 0 | ------------------------------------------------------------------------------------------------------------------------- Ending Logic Optimization Task | Checksum: 18b0907d0 Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:00.31 . Memory (MB): peak = 2798.172 ; gain = 32.016 ; free physical = 381 ; free virtual = 23002 INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8 Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2798.172 ; gain = 0.000 ; free physical = 381 ; free virtual = 23002 Starting Power Optimization Task INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. Ending Power Optimization Task | Checksum: 18b0907d0 Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2798.172 ; gain = 0.000 ; free physical = 381 ; free virtual = 23002 Starting Final Cleanup Task Ending Final Cleanup Task | Checksum: 18b0907d0 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2798.172 ; gain = 0.000 ; free physical = 381 ; free virtual = 23002 Starting Netlist Obfuscation Task Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2798.172 ; gain = 0.000 ; free physical = 381 ; free virtual = 23002 Ending Netlist Obfuscation Task | Checksum: 18b0907d0 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2798.172 ; gain = 0.000 ; free physical = 381 ; free virtual = 23002 INFO: [Common 17-83] Releasing license: Implementation 18 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. opt_design completed successfully opt_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 2798.172 ; gain = 455.762 ; free physical = 381 ; free virtual = 23002 # place_design Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' INFO: [Common 17-83] Releasing license: Implementation INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Starting Placer Task Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2830.188 ; gain = 0.000 ; free physical = 425 ; free virtual = 23031 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 111b3e1be Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2830.188 ; gain = 0.000 ; free physical = 425 ; free virtual = 23031 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2830.188 ; gain = 0.000 ; free physical = 425 ; free virtual = 23031 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: eaba1a74 Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.79 . Memory (MB): peak = 2830.188 ; gain = 0.000 ; free physical = 424 ; free virtual = 23030 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 171709274 Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 2837.215 ; gain = 7.027 ; free physical = 424 ; free virtual = 23030 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 171709274 Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 2837.215 ; gain = 7.027 ; free physical = 424 ; free virtual = 23030 Phase 1 Placer Initialization | Checksum: 171709274 Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 2837.215 ; gain = 7.027 ; free physical = 424 ; free virtual = 23030 Phase 2 Global Placement Phase 2.1 Floorplanning Phase 2.1 Floorplanning | Checksum: f742582f Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2837.215 ; gain = 7.027 ; free physical = 419 ; free virtual = 23025 Phase 2.2 Update Timing before SLR Path Opt Phase 2.2 Update Timing before SLR Path Opt | Checksum: 1b10be20d Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2837.215 ; gain = 7.027 ; free physical = 419 ; free virtual = 23025 Phase 2.3 Post-Processing in Floorplanning Phase 2.3 Post-Processing in Floorplanning | Checksum: 1b10be20d Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2837.215 ; gain = 7.027 ; free physical = 419 ; free virtual = 23025 Phase 2.4 Global Placement Core Phase 2.4.1 UpdateTiming Before Physical Synthesis Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 1a782b84c Time (s): cpu = 00:00:14 ; elapsed = 00:00:04 . Memory (MB): peak = 2837.215 ; gain = 7.027 ; free physical = 433 ; free virtual = 23028 Phase 2.4.2 Physical Synthesis In Placer INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 61 LUT instances to create LUTNM shape INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0 INFO: [Physopt 32-1138] End 1 Pass. Optimized 28 nets or LUTs. Breaked 0 LUT, combined 28 existing LUTs and moved 0 existing LUT INFO: [Physopt 32-65] No nets found for high-fanout optimization. INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed. INFO: [Physopt 32-670] No setup violation found. Shift Register to Pipeline Optimization was not performed. INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed. INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed. INFO: [Physopt 32-670] No setup violation found. URAM Register Optimization was not performed. INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2837.215 ; gain = 0.000 ; free physical = 433 ; free virtual = 23027 Summary of Physical Synthesis Optimizations ============================================ ----------------------------------------------------------------------------------------------------------------------------------------------------------- | Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ----------------------------------------------------------------------------------------------------------------------------------------------------------- | LUT Combining | 0 | 28 | 28 | 0 | 1 | 00:00:00 | | Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | Shift Register to Pipeline | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | URAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Total | 0 | 28 | 28 | 0 | 4 | 00:00:00 | ----------------------------------------------------------------------------------------------------------------------------------------------------------- Phase 2.4.2 Physical Synthesis In Placer | Checksum: 13a1e5681 Time (s): cpu = 00:00:15 ; elapsed = 00:00:04 . Memory (MB): peak = 2837.215 ; gain = 7.027 ; free physical = 433 ; free virtual = 23027 Phase 2.4 Global Placement Core | Checksum: 18860a67c Time (s): cpu = 00:00:19 ; elapsed = 00:00:05 . Memory (MB): peak = 2837.215 ; gain = 7.027 ; free physical = 433 ; free virtual = 23027 Phase 2 Global Placement | Checksum: 18860a67c Time (s): cpu = 00:00:19 ; elapsed = 00:00:05 . Memory (MB): peak = 2837.215 ; gain = 7.027 ; free physical = 433 ; free virtual = 23027 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: d1800fe4 Time (s): cpu = 00:00:19 ; elapsed = 00:00:05 . Memory (MB): peak = 2837.215 ; gain = 7.027 ; free physical = 433 ; free virtual = 23027 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: e7cdfb80 Time (s): cpu = 00:00:19 ; elapsed = 00:00:05 . Memory (MB): peak = 2837.215 ; gain = 7.027 ; free physical = 433 ; free virtual = 23027 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 120909787 Time (s): cpu = 00:00:20 ; elapsed = 00:00:05 . Memory (MB): peak = 2837.215 ; gain = 7.027 ; free physical = 433 ; free virtual = 23027 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: f5190b7e Time (s): cpu = 00:00:20 ; elapsed = 00:00:05 . Memory (MB): peak = 2837.215 ; gain = 7.027 ; free physical = 433 ; free virtual = 23027 Phase 3.5 Small Shape Detail Placement Phase 3.5 Small Shape Detail Placement | Checksum: 1fbd7da2b Time (s): cpu = 00:00:21 ; elapsed = 00:00:06 . Memory (MB): peak = 2837.215 ; gain = 7.027 ; free physical = 440 ; free virtual = 23032 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 1f17b4150 Time (s): cpu = 00:00:21 ; elapsed = 00:00:06 . Memory (MB): peak = 2837.215 ; gain = 7.027 ; free physical = 440 ; free virtual = 23032 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 21512b531 Time (s): cpu = 00:00:21 ; elapsed = 00:00:06 . Memory (MB): peak = 2837.215 ; gain = 7.027 ; free physical = 440 ; free virtual = 23032 Phase 3 Detail Placement | Checksum: 21512b531 Time (s): cpu = 00:00:21 ; elapsed = 00:00:06 . Memory (MB): peak = 2837.215 ; gain = 7.027 ; free physical = 440 ; free virtual = 23032 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization [80%] Routing Phase 2 completed INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 4.1.1 Post Placement Optimization Post Placement Optimization Initialization | Checksum: 1ad83c62b Phase 4.1.1.1 BUFG Insertion Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=9.081 | TNS=0.000 | Phase 1 Physical Synthesis Initialization | Checksum: 175eead4b Time (s): cpu = 00:00:00.16 ; elapsed = 00:00:00.06 . Memory (MB): peak = 2837.215 ; gain = 0.000 ; free physical = 440 ; free virtual = 23032 INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0. Ending Physical Synthesis Task | Checksum: 175eead4b Time (s): cpu = 00:00:00.19 ; elapsed = 00:00:00.1 . Memory (MB): peak = 2837.215 ; gain = 0.000 ; free physical = 440 ; free virtual = 23032 Phase 4.1.1.1 BUFG Insertion | Checksum: 1ad83c62b Time (s): cpu = 00:00:23 ; elapsed = 00:00:07 . Memory (MB): peak = 2837.215 ; gain = 7.027 ; free physical = 440 ; free virtual = 23032 Phase 4.1.1.2 Post Placement Timing Optimization INFO: [Place 30-746] Post Placement Timing Summary WNS=9.081. For the most accurate timing information please run report_timing. Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 1b2b96e0e Time (s): cpu = 00:00:23 ; elapsed = 00:00:07 . Memory (MB): peak = 2837.215 ; gain = 7.027 ; free physical = 440 ; free virtual = 23032 Time (s): cpu = 00:00:23 ; elapsed = 00:00:07 . Memory (MB): peak = 2837.215 ; gain = 7.027 ; free physical = 440 ; free virtual = 23032 Phase 4.1 Post Commit Optimization | Checksum: 1b2b96e0e Time (s): cpu = 00:00:23 ; elapsed = 00:00:07 . Memory (MB): peak = 2837.215 ; gain = 7.027 ; free physical = 440 ; free virtual = 23032 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 1b2b96e0e Time (s): cpu = 00:00:24 ; elapsed = 00:00:07 . Memory (MB): peak = 2837.215 ; gain = 7.027 ; free physical = 440 ; free virtual = 23032 Phase 4.3 Placer Reporting Phase 4.3.1 Print Estimated Congestion INFO: [Place 30-612] Post-Placement Estimated Congestion ____________________________________________________ | | Global Congestion | Short Congestion | | Direction | Region Size | Region Size | |___________|___________________|___________________| | North| 1x1| 2x2| |___________|___________________|___________________| | South| 1x1| 1x1| |___________|___________________|___________________| | East| 1x1| 1x1| |___________|___________________|___________________| | West| 1x1| 1x1| |___________|___________________|___________________| Phase 4.3.1 Print Estimated Congestion | Checksum: 1b2b96e0e Time (s): cpu = 00:00:24 ; elapsed = 00:00:07 . Memory (MB): peak = 2837.215 ; gain = 7.027 ; free physical = 440 ; free virtual = 23032 Phase 4.3 Placer Reporting | Checksum: 1b2b96e0e Time (s): cpu = 00:00:24 ; elapsed = 00:00:07 . Memory (MB): peak = 2837.215 ; gain = 7.027 ; free physical = 440 ; free virtual = 23032 Phase 4.4 Final Placement Cleanup Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2837.215 ; gain = 0.000 ; free physical = 440 ; free virtual = 23032 Time (s): cpu = 00:00:24 ; elapsed = 00:00:07 . Memory (MB): peak = 2837.215 ; gain = 7.027 ; free physical = 440 ; free virtual = 23032 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 21f6871c5 Time (s): cpu = 00:00:24 ; elapsed = 00:00:07 . Memory (MB): peak = 2837.215 ; gain = 7.027 ; free physical = 440 ; free virtual = 23032 Ending Placer Task | Checksum: 169488af0 Time (s): cpu = 00:00:24 ; elapsed = 00:00:07 . Memory (MB): peak = 2837.215 ; gain = 7.027 ; free physical = 440 ; free virtual = 23032 29 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:25 ; elapsed = 00:00:08 . Memory (MB): peak = 2837.215 ; gain = 39.043 ; free physical = 440 ; free virtual = 23032 # report_utilization -hierarchical -file digilent_nexys4ddr_utilization_hierarchical_place.rpt # report_utilization -file digilent_nexys4ddr_utilization_place.rpt # report_io -file digilent_nexys4ddr_io.rpt report_io: Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.16 . Memory (MB): peak = 2837.215 ; gain = 0.000 ; free physical = 436 ; free virtual = 23027 # report_control_sets -verbose -file digilent_nexys4ddr_control_sets.rpt report_control_sets: Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.1 . Memory (MB): peak = 2837.215 ; gain = 0.000 ; free physical = 435 ; free virtual = 23026 # report_clock_utilization -file digilent_nexys4ddr_clock_utilization.rpt # route_design Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' Running DRC as a precondition to command route_design INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Phase 1 Build RT Design Checksum: PlaceDB: e631b481 ConstDB: 0 ShapeSum: 8316d66f RouteDB: 0 WARN (PR1014) : Generic routing resource will be used to clock signal 'clk_d' by the specified constraint. And then it may lead to the excessive delay or skew [90%] Routing Phase 3 completed Running timing analysis...... [95%] Timing analysis completed Placement and routing completed Bitstream generation in progress...... Bitstream generation completed Running power analysis...... [100%] Power analysis completed Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.power.html" completed Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.pin.html" completed Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.rpt.html" completed Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.rpt.txt" completed Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.tr.html" completed Tue Jul 30 02:06:33 2024 [Pipeline] } [Pipeline] // stage [Pipeline] } Post Restoration Checksum: NetGraph: 41eeb984 | NumContArr: cddfc438 | Constraints: c2a8fa9d | Timing: c2a8fa9d Phase 1 Build RT Design | Checksum: 2952072f6 Time (s): cpu = 00:00:32 ; elapsed = 00:00:27 . Memory (MB): peak = 2837.215 ; gain = 0.000 ; free physical = 766 ; free virtual = 23342 Phase 2 Router Initialization Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 2952072f6 Time (s): cpu = 00:00:32 ; elapsed = 00:00:27 . Memory (MB): peak = 2837.215 ; gain = 0.000 ; free physical = 783 ; free virtual = 23359 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 2952072f6 Time (s): cpu = 00:00:32 ; elapsed = 00:00:27 . Memory (MB): peak = 2837.215 ; gain = 0.000 ; free physical = 782 ; free virtual = 23359 Number of Nodes with overlaps = 0 Phase 2.3 Update Timing Phase 2.3 Update Timing | Checksum: 1f3ce5af8 Time (s): cpu = 00:00:36 ; elapsed = 00:00:28 . Memory (MB): peak = 2837.215 ; gain = 0.000 ; free physical = 750 ; free virtual = 23327 INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.996 | TNS=0.000 | WHS=-0.066 | THS=-0.066 | Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 7.10429e-05 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 2724 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 2723 Number of Partially Routed Nets = 1 Number of Node Overlaps = 0 Phase 2 Router Initialization | Checksum: 27328a6fb Time (s): cpu = 00:00:37 ; elapsed = 00:00:28 . Memory (MB): peak = 2837.215 ; gain = 0.000 ; free physical = 745 ; free virtual = 23322 Phase 3 Initial Routing Phase 3.1 Global Routing Phase 3.1 Global Routing | Checksum: 27328a6fb Time (s): cpu = 00:00:37 ; elapsed = 00:00:28 . Memory (MB): peak = 2837.215 ; gain = 0.000 ; free physical = 745 ; free virtual = 23322 Phase 3.2 Initial Net Routing Phase 3.2 Initial Net Routing | Checksum: 1dbe5b1fe Time (s): cpu = 00:00:38 ; elapsed = 00:00:28 . Memory (MB): peak = 2837.215 ; gain = 0.000 ; free physical = 745 ; free virtual = 23322 Phase 3 Initial Routing | Checksum: 1dbe5b1fe Time (s): cpu = 00:00:38 ; elapsed = 00:00:28 . Memory (MB): peak = 2837.215 ; gain = 0.000 ; free physical = 745 ; free virtual = 23322 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Number of Nodes with overlaps = 366 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.988 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 4.1 Global Iteration 0 | Checksum: 233427a93 Time (s): cpu = 00:00:41 ; elapsed = 00:00:29 . Memory (MB): peak = 2837.215 ; gain = 0.000 ; free physical = 745 ; free virtual = 23321 Phase 4 Rip-up And Reroute | Checksum: 233427a93 Time (s): cpu = 00:00:41 ; elapsed = 00:00:29 . Memory (MB): peak = 2837.215 ; gain = 0.000 ; free physical = 744 ; free virtual = 23320 Phase 5 Delay and Skew Optimization Phase 5.1 Delay CleanUp Phase 5.1 Delay CleanUp | Checksum: 233427a93 Time (s): cpu = 00:00:41 ; elapsed = 00:00:29 . Memory (MB): peak = 2837.215 ; gain = 0.000 ; free physical = 744 ; free virtual = 23320 Phase 5.2 Clock Skew Optimization Phase 5.2 Clock Skew Optimization | Checksum: 233427a93 Time (s): cpu = 00:00:41 ; elapsed = 00:00:29 . Memory (MB): peak = 2837.215 ; gain = 0.000 ; free physical = 743 ; free virtual = 23320 Phase 5 Delay and Skew Optimization | Checksum: 233427a93 Time (s): cpu = 00:00:41 ; elapsed = 00:00:29 . Memory (MB): peak = 2837.215 ; gain = 0.000 ; free physical = 743 ; free virtual = 23320 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1.1 Update Timing Phase 6.1.1 Update Timing | Checksum: 2c3d08406 Time (s): cpu = 00:00:41 ; elapsed = 00:00:29 . Memory (MB): peak = 2837.215 ; gain = 0.000 ; free physical = 741 ; free virtual = 23318 INFO: [Route 35-416] Intermediate Timing Summary | WNS=9.084 | TNS=0.000 | WHS=0.194 | THS=0.000 | Phase 6.1 Hold Fix Iter | Checksum: 2c3d08406 Time (s): cpu = 00:00:41 ; elapsed = 00:00:29 . Memory (MB): peak = 2837.215 ; gain = 0.000 ; free physical = 741 ; free virtual = 23317 Phase 6 Post Hold Fix | Checksum: 2c3d08406 Time (s): cpu = 00:00:41 ; elapsed = 00:00:29 . Memory (MB): peak = 2837.215 ; gain = 0.000 ; free physical = 741 ; free virtual = 23317 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.484659 % Global Horizontal Routing Utilization = 0.671853 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 7 Route finalize | Checksum: 2c3d08406 Time (s): cpu = 00:00:41 ; elapsed = 00:00:29 . Memory (MB): peak = 2837.215 ; gain = 0.000 ; free physical = 749 ; free virtual = 23326 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 2c3d08406 Time (s): cpu = 00:00:41 ; elapsed = 00:00:29 . Memory (MB): peak = 2837.215 ; gain = 0.000 ; free physical = 749 ; free virtual = 23326 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 2283b9c7c Time (s): cpu = 00:00:42 ; elapsed = 00:00:30 . Memory (MB): peak = 2837.215 ; gain = 0.000 ; free physical = 742 ; free virtual = 23318 Phase 10 Post Router Timing INFO: [Route 35-57] Estimated Timing Summary | WNS=9.084 | TNS=0.000 | WHS=0.194 | THS=0.000 | INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary. Phase 10 Post Router Timing | Checksum: 2283b9c7c Time (s): cpu = 00:00:42 ; elapsed = 00:00:30 . Memory (MB): peak = 2837.215 ; gain = 0.000 ; free physical = 741 ; free virtual = 23318 INFO: [Route 35-16] Router Completed Successfully Phase 11 Post-Route Event Processing Phase 11 Post-Route Event Processing | Checksum: 1c780b804 Time (s): cpu = 00:00:42 ; elapsed = 00:00:30 . Memory (MB): peak = 2837.215 ; gain = 0.000 ; free physical = 740 ; free virtual = 23317 Ending Routing Task | Checksum: 1c780b804 Time (s): cpu = 00:00:42 ; elapsed = 00:00:30 . Memory (MB): peak = 2837.215 ; gain = 0.000 ; free physical = 739 ; free virtual = 23315 Routing Is Done. INFO: [Common 17-83] Releasing license: Implementation 12 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:43 ; elapsed = 00:00:30 . Memory (MB): peak = 2837.215 ; gain = 0.000 ; free physical = 738 ; free virtual = 23315 # report_timing_summary -no_header -no_detailed_paths INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs ------------------------------------------------------------------------------------------------ | Timer Settings | -------------- ------------------------------------------------------------------------------------------------ Enable Multi Corner Analysis : Yes Enable Pessimism Removal : Yes Pessimism Removal Resolution : Nearest Common Node Enable Input Delay Default Clock : No Enable Preset / Clear Arcs : No Disable Flight Delays : No Ignore I/O Paths : No Timing Early Launch at Borrowing Latches : No Borrow Time for Max Delay Exceptions : Yes Merge Timing Exceptions : Yes Inter-SLR Compensation : Conservative Corner Analyze Analyze Name Max Paths Min Paths ------ --------- --------- Slow Yes Yes Fast Yes Yes ------------------------------------------------------------------------------------------------ | Report Methodology | ------------------ ------------------------------------------------------------------------------------------------ No report available as report_methodology has not been run prior. Run report_methodology on the current design for the summary of methodology violations. check_timing report Table of Contents ----------------- 1. checking no_clock (1813) 2. checking constant_clock (0) 3. checking pulse_width_clock (0) 4. checking unconstrained_internal_endpoints (6425) 5. checking no_input_delay (2) 6. checking no_output_delay (3) 7. checking multiple_clock (0) 8. checking generated_clocks (0) 9. checking loops (0) 10. checking partial_input_delay (0) 11. checking partial_output_delay (0) 12. checking latch_loops (0) 1. checking no_clock (1813) --------------------------- There are 1813 register/latch pins with no clock driven by root clock pin: clk_o_reg/Q (HIGH) 2. checking constant_clock (0) ------------------------------ There are 0 register/latch pins with constant_clock. 3. checking pulse_width_clock (0) --------------------------------- There are 0 register/latch pins which need pulse_width check 4. checking unconstrained_internal_endpoints (6425) --------------------------------------------------- There are 6425 pins that are not constrained for maximum delay. (HIGH) There are 0 pins that are not constrained for maximum delay due to constant clock. 5. checking no_input_delay (2) ------------------------------ There are 2 input ports with no input delay specified. (HIGH) There are 0 input ports with no input delay but user has a false path constraint. 6. checking no_output_delay (3) ------------------------------- There are 3 ports with no output delay specified. (HIGH) There are 0 ports with no output delay but user has a false path constraint There are 0 ports with no output delay but with a timing clock defined on it or propagating through it 7. checking multiple_clock (0) ------------------------------ There are 0 register/latch pins with multiple clocks. 8. checking generated_clocks (0) -------------------------------- There are 0 generated clocks that are not connected to a clock source. 9. checking loops (0) --------------------- There are 0 combinational loops in the design. 10. checking partial_input_delay (0) ------------------------------------ There are 0 input ports with partial input delay specified. 11. checking partial_output_delay (0) ------------------------------------- There are 0 ports with partial output delay specified. 12. checking latch_loops (0) ---------------------------- There are 0 combinational latch loops in the design through latch input ------------------------------------------------------------------------------------------------ | Design Timing Summary | --------------------- ------------------------------------------------------------------------------------------------ WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- 9.109 0.000 0 1 0.210 0.000 0 1 4.500 0.000 0 3 All user specified timing constraints are met. ------------------------------------------------------------------------------------------------ | Clock Summary | ------------- ------------------------------------------------------------------------------------------------ Clock Waveform(ns) Period(ns) Frequency(MHz) ----- ------------ ---------- -------------- sys_clk_pin {0.000 5.000} 10.000 100.000 ------------------------------------------------------------------------------------------------ | Intra Clock Table | ----------------- ------------------------------------------------------------------------------------------------ Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- sys_clk_pin 9.109 0.000 0 1 0.210 0.000 0 1 4.500 0.000 0 3 ------------------------------------------------------------------------------------------------ | Inter Clock Table | ----------------- ------------------------------------------------------------------------------------------------ From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- ------------------------------------------------------------------------------------------------ | Other Path Groups Table | ----------------------- ------------------------------------------------------------------------------------------------ Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- # report_route_status -file digilent_nexys4ddr_route_status.rpt # report_drc -file digilent_nexys4ddr_drc.rpt Command: report_drc -file digilent_nexys4ddr_drc.rpt INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/eda/vivado/Vivado/2023.2/data/ip'. INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado_Tcl 2-168] The results of DRC are in file /var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4ddr_drc.rpt. report_drc completed successfully # report_timing_summary -datasheet -max_paths 10 -file digilent_nexys4ddr_timing.rpt INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs # report_power -file digilent_nexys4ddr_power.rpt Command: report_power -file digilent_nexys4ddr_power.rpt Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis. Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report. 0 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. report_power completed successfully # write_bitstream -force "./build/out.bit" Command: write_bitstream -force ./build/out.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' Running DRC as a precondition to command write_bitstream INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC BUFC-1] Input Buffer Connections: Input buffer gpio_IOBUF[0]_inst/IBUF has no loads. It is recommended to have an input buffer drive an internal load. WARNING: [DRC BUFC-1] Input Buffer Connections: Input buffer gpio_IOBUF[1]_inst/IBUF has no loads. It is recommended to have an input buffer drive an internal load. WARNING: [DRC BUFC-1] Input Buffer Connections: Input buffer gpio_IOBUF[2]_inst/IBUF has no loads. It is recommended to have an input buffer drive an internal load. WARNING: [DRC BUFC-1] Input Buffer Connections: Input buffer gpio_IOBUF[3]_inst/IBUF has no loads. It is recommended to have an input buffer drive an internal load. WARNING: [DRC BUFC-1] Input Buffer Connections: Input buffer gpio_IOBUF[4]_inst/IBUF has no loads. It is recommended to have an input buffer drive an internal load. WARNING: [DRC BUFC-1] Input Buffer Connections: Input buffer gpio_IOBUF[5]_inst/IBUF has no loads. It is recommended to have an input buffer drive an internal load. WARNING: [DRC BUFC-1] Input Buffer Connections: Input buffer gpio_IOBUF[6]_inst/IBUF has no loads. It is recommended to have an input buffer drive an internal load. WARNING: [DRC BUFC-1] Input Buffer Connections: Input buffer gpio_IOBUF[7]_inst/IBUF has no loads. It is recommended to have an input buffer drive an internal load. WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: set_property CFGBVS value1 [current_design] #where value1 is either VCCO or GND set_property CONFIG_VOLTAGE value2 [current_design] #where value2 is the voltage provided to configuration bank 0 Refer to the device configuration user guide for more information. INFO: [Vivado 12-3199] DRC finished with 0 Errors, 9 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... Loading site data... Loading route data... Processing options... Creating bitmap... Creating bitstream... Writing bitstream ./build/out.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-1876] WebTalk data collection is mandatory when using a ULT device. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Common 17-83] Releasing license: Implementation 9 Infos, 9 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:14 ; elapsed = 00:00:18 . Memory (MB): peak = 3145.262 ; gain = 246.207 ; free physical = 555 ; free virtual = 23074 INFO: [Common 17-206] Exiting Vivado at Tue Jul 30 02:07:12 2024... [Pipeline] } [Pipeline] // stage [Pipeline] } [Pipeline] // parallel [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (FPGA Flash) [Pipeline] parallel [Pipeline] { (Branch: openFPGAloader ECP5) [Pipeline] { (Branch: openFPGAloader Tangnano 20k) [Pipeline] { (Branch: openFPGAloader Nexys 4 DDR) [Pipeline] stage [Pipeline] { (openFPGAloader ECP5) [Pipeline] stage [Pipeline] { (openFPGAloader Tangnano 20k) [Pipeline] stage [Pipeline] { (openFPGAloader Nexys 4 DDR) [Pipeline] script [Pipeline] { [Pipeline] script [Pipeline] { [Pipeline] script [Pipeline] { [Pipeline] lock Trying to acquire lock on [Resource: ecp5] Resource [ecp5] did not exist. Created. Lock acquired on [Resource: ecp5] [Pipeline] { [Pipeline] lock Trying to acquire lock on [Resource: tangnano20k] Resource [tangnano20k] did not exist. Created. Lock acquired on [Resource: tangnano20k] [Pipeline] { [Pipeline] lock Trying to acquire lock on [Resource: nexys4] Resource [nexys4] did not exist. Created. Lock acquired on [Resource: nexys4] [Pipeline] { [Pipeline] echo FPGA ECP5 Broqueada [Pipeline] sh [Pipeline] echo FPGA TangNano Broqueada + /eda/oss-cad-suite/bin/openFPGALoader -b colorlight-i9 ./build/out.bit empty Found 1 compatible device: 0x0d28 0x0204 0x3 DAPLink CMSIS-DAP Open file: DONE b3bdffff Parse file: DONE Enable configuration: DONE SRAM erase: DONE [Pipeline] sh [Pipeline] echo FPGA Nexys 4 Broqueada + echo gravando na tang nano gravando na tang nano [Pipeline] sh [Pipeline] } + cd Risco-5/fpga/nexys4_ddr + /eda/oss-cad-suite/bin/openFPGALoader -b nexys_a7_100 ./build/out.bit empty Jtag frequency : requested 6.00MHz -> real 6.00MHz Open file DONE Parse file DONE load program Lock released on resource [Resource: tangnano20k] [Pipeline] // lock [Pipeline] } [Pipeline] // script Loading: [======= ] 13.66%[Pipeline] } Load SRAM: [========= ] 18.00%[Pipeline] // stage [Pipeline] } Loading: [============== ] 27.33% Load SRAM: [=================== ] 38.00% Loading: [===================== ] 40.99% Load SRAM: [============================= ] 58.00% Loading: [============================ ] 54.65% Load SRAM: [======================================= ] 78.00% Loading: [=================================== ] 68.31% Load SRAM: [================================================= ] 98.00% Load SRAM: [===================================================] 100.00% Done Shift IR 35 ir: 1 isc_done 1 isc_ena 0 init 1 done 1 [Pipeline] } Loading: [========================================= ] 81.98%Lock released on resource [Resource: nexys4] [Pipeline] // lock [Pipeline] } [Pipeline] // script Loading: [================================================ ] 95.64%[Pipeline] } Loading: [==================================================] 100.00% Done Disable configuration: [Pipeline] // stage [Pipeline] } DONE [Pipeline] } Lock released on resource [Resource: ecp5] [Pipeline] // lock [Pipeline] } [Pipeline] // script [Pipeline] } [Pipeline] // stage [Pipeline] } [Pipeline] // parallel [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Testes) [Pipeline] parallel [Pipeline] { (Branch: ECP5 - Testes) [Pipeline] { (Branch: TangNano - Testes) [Pipeline] { (Branch: Nexys 4 - Testes) [Pipeline] stage [Pipeline] { (ECP5 - Testes) [Pipeline] stage [Pipeline] { (TangNano - Testes) [Pipeline] stage [Pipeline] { (Nexys 4 - Testes) [Pipeline] script [Pipeline] { [Pipeline] script [Pipeline] { [Pipeline] script [Pipeline] { [Pipeline] echo Rodando teste na ECP5 [Pipeline] lock Trying to acquire lock on [Resource: ecp5] Resource [ecp5] did not exist. Created. Lock acquired on [Resource: ecp5] [Pipeline] { [Pipeline] echo Rodando teste na tang nano [Pipeline] lock Trying to acquire lock on [Resource: tangnano20k] Resource [tangnano20k] did not exist. Created. Lock acquired on [Resource: tangnano20k] [Pipeline] { [Pipeline] echo Rodando teste na Nexys 4 [Pipeline] lock Trying to acquire lock on [Resource: nexys4] Resource [nexys4] did not exist. Created. Lock acquired on [Resource: nexys4] [Pipeline] { [Pipeline] echo FPGA ECP5 Broqueada [Pipeline] sh [Pipeline] echo FPGA TangNano Broqueada + echo testando na ecp5 testando na ecp5 [Pipeline] sh [Pipeline] echo FPGA Nexys 4 Broqueada + echo testando na tang nano testando na tang nano [Pipeline] sh [Pipeline] } + echo testando na tang nano testando na tang nano Lock released on resource [Resource: ecp5] [Pipeline] } Lock released on resource [Resource: tangnano20k] [Pipeline] // lock [Pipeline] // lock [Pipeline] echo ECP5 liberada [Pipeline] } [Pipeline] echo TangNano liberada [Pipeline] } [Pipeline] } Lock released on resource [Resource: nexys4] [Pipeline] // script [Pipeline] // script [Pipeline] // lock [Pipeline] } [Pipeline] } [Pipeline] echo TangNano liberada [Pipeline] } [Pipeline] // stage [Pipeline] // stage [Pipeline] // script [Pipeline] } [Pipeline] } [Pipeline] } [Pipeline] // stage [Pipeline] } [Pipeline] // parallel [Pipeline] } [Pipeline] // stage [Pipeline] } [Pipeline] // node [Pipeline] End of Pipeline Finished: SUCCESS