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Info: 15000 | 6204 8753 | 386 572 | 6052| 0.26 4.27|
Info: 16000 | 6525 9247 | 321 494 | 5422| 0.17 4.44|
Info: 17000 | 6721 9831 | 196 584 | 4661| 0.15 4.59|
Info: 18000 | 7015 10473 | 294 642 | 4013| 0.22 4.81|
Info: 19000 | 7095 11365 | 80 892 | 3113| 0.20 5.01|
Info: 20000 | 7194 12216 | 99 851 | 2229| 0.21 5.21|
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2028.781 ; gain = 403.715 ; free physical = 424 ; free virtual = 23080
---------------------------------------------------------------------------------
Info: 21000 | 7286 13081 | 92 865 | 1339| 0.22 5.44|
Info: 22000 | 7358 13920 | 72 839 | 434| 0.20 5.63|
Info: 22433 | 7358 14115 | 0 195 | 0| 0.08 5.71|
Info: Routing complete.
Info: Router1 time 5.71s
Info: Checksum: 0xf7bfca53
Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
Info: curr total
Info: 0.5 0.5 Source SOC.Core.instruction_register_TRELLIS_FF_Q_28.Q
Info: 1.1 1.7 Net SOC.Core.instruction_register[2] (6,29) -> (5,30)
Info: Sink SOC.Core.Control_Unit.func7_lsb_bit_LUT4_A_3_D_LUT4_Z.B
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 1.9 Source SOC.Core.Control_Unit.func7_lsb_bit_LUT4_A_3_D_LUT4_Z.F
Info: 0.7 2.6 Net SOC.Core.Control_Unit.func7_lsb_bit_LUT4_A_3_D[4] (5,30) -> (6,30)
Info: Sink SOC.Core.Control_Unit.func7_lsb_bit_LUT4_A_3_D_L6MUX21_SD_D1_PFUMX_Z_ALUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 2.8 Source SOC.Core.Control_Unit.func7_lsb_bit_LUT4_A_3_D_L6MUX21_SD_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: 0.0 2.8 Net SOC.Core.Control_Unit.func7_lsb_bit_LUT4_A_3_D_L6MUX21_SD_Z (6,30) -> (6,30)
Info: Sink SOC.Core.Control_Unit.func7_lsb_bit_LUT4_A_3_D_L6MUX21_SD_D0_PFUMX_Z_ALUT_LUT4_Z.FXB
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:157.70-157.72
Info: 0.2 3.1 Source SOC.Core.Control_Unit.func7_lsb_bit_LUT4_A_3_D_L6MUX21_SD_D0_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: 1.7 4.7 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_1_C_LUT4_Z_D_CCU2C_S1_B1_LUT4_D_Z_LUT4_Z_1_C[2] (6,30) -> (13,41)
Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_1_C_LUT4_Z_D_CCU2C_S1_B1_LUT4_D_Z_LUT4_Z_D_LUT4_C_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_B_3_Z_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 5.0 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_1_C_LUT4_Z_D_CCU2C_S1_B1_LUT4_D_Z_LUT4_Z_D_LUT4_C_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_B_3_Z_LUT4_Z.F
Info: 1.5 6.5 Net SOC.Core.Alu.ALU_out_S_L6MUX21_Z_1_SD_PFUMX_Z_C0_PFUMX_Z_C0[3] (13,41) -> (12,36)
Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_A_LUT4_Z_D_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.B
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.4 6.9 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_A_LUT4_Z_D_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: 0.0 6.9 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_A_LUT4_Z_D_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (12,36) -> (12,36)
Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_A_LUT4_Z_D_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: 0.0 6.9 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_A_LUT4_Z_D_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: 0.0 6.9 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_A_LUT4_Z_D_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (12,36) -> (12,36)
Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_A_LUT4_Z_D_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/src/core/alu.v:35.26-35.45
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 7.0 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_A_LUT4_Z_D_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: 0.0 7.0 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_A_LUT4_Z_D_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (12,36) -> (12,36)
Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_A_LUT4_Z_D_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: 0.0 7.0 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_A_LUT4_Z_D_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: 0.0 7.0 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_A_LUT4_Z_D_CCU2C_S1_CIN_CCU2C_COUT_CIN (12,36) -> (12,36)
Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_A_LUT4_Z_D_CCU2C_S1_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/src/core/alu.v:35.26-35.45
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 7.0 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_A_LUT4_Z_D_CCU2C_S1_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: 0.0 7.0 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_A_LUT4_Z_D_CCU2C_S1_CIN_CCU2C_COUT$CCU2_FCI_INT (12,36) -> (12,36)
Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_A_LUT4_Z_D_CCU2C_S1_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: 0.0 7.0 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_A_LUT4_Z_D_CCU2C_S1_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: 0.0 7.0 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_A_LUT4_Z_D_CCU2C_S1_CIN (12,36) -> (13,36)
Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_A_LUT4_Z_D_CCU2C_S1$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/src/core/alu.v:35.26-35.45
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 7.1 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_A_LUT4_Z_D_CCU2C_S1$CCU2_COMB0.FCO
Info: 0.0 7.1 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_A_LUT4_Z_D_CCU2C_S1$CCU2_FCI_INT (13,36) -> (13,36)
Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_A_LUT4_Z_D_CCU2C_S1$CCU2_COMB1.FCI
Info: 0.0 7.1 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_A_LUT4_Z_D_CCU2C_S1$CCU2_COMB1.FCO
Info: 0.0 7.1 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_A_LUT4_Z_D_CCU2C_S1_COUT (13,36) -> (13,36)
Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_A_LUT4_Z_D_CCU2C_S1_COUT_CCU2C_CIN$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/src/core/alu.v:35.26-35.45
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.4 7.6 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_A_LUT4_Z_D_CCU2C_S1_COUT_CCU2C_CIN$CCU2_COMB0.F
Info: 1.3 8.8 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_A_LUT4_Z_D_CCU2C_S1_COUT_CCU2C_CIN_S0[5] (13,36) -> (12,31)
Info: Sink SOC.Core.Alu.ALU_out_S_L6MUX21_Z_6_SD_L6MUX21_Z_2_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 9.1 Source SOC.Core.Alu.ALU_out_S_L6MUX21_Z_6_SD_L6MUX21_Z_2_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: 0.0 9.1 Net SOC.Core.Alu.ALU_out_S_L6MUX21_Z_6_SD_L6MUX21_Z_2_D1 (12,31) -> (12,31)
Info: Sink SOC.Core.Alu.ALU_out_S_L6MUX21_Z_6_SD_L6MUX21_Z_2_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.FXB
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:157.70-157.72
Info: 0.2 9.3 Source SOC.Core.Alu.ALU_out_S_L6MUX21_Z_6_SD_L6MUX21_Z_2_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: 1.5 10.9 Net SOC.Core.Alu.ALU_out_S_L6MUX21_Z_6_SD[6] (12,31) -> (12,43)
Info: Sink SOC.Core.Alu.ALU_out_S_L6MUX21_Z_6_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 11.1 Source SOC.Core.Alu.ALU_out_S_L6MUX21_Z_6_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: 1.0 12.1 Net SOC.Core.alu_out[8] (12,43) -> (12,37)
Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_1_D_LUT4_A_Z_LUT4_Z.D
Info: Defined in:
Info: Risco-5/src/core/core.v:60.31-60.38
Info: 0.2 12.4 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_1_D_LUT4_A_Z_LUT4_Z.F
Info: 0.5 12.8 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_1_D_LUT4_A_Z[2] (12,37) -> (15,37)
Info: Sink SOC.Core.Pc.load_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.C
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 13.1 Source SOC.Core.Pc.load_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.F
Info: 0.0 13.1 Net SOC.Core.Pc.load_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT (15,37) -> (15,37)
Info: Sink SOC.Core.Pc.load_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.F1
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:157.46-157.48
Info: 0.2 13.2 Source SOC.Core.Pc.load_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: 0.0 13.2 Net SOC.Core.Pc.load_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D1 (15,37) -> (15,37)
Info: Sink SOC.Core.Pc.load_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.FXB
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:157.62-157.64
Info: 0.2 13.5 Source SOC.Core.Pc.load_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: 0.0 13.5 Net SOC.Core.Pc.load_LUT4_Z_A_L6MUX21_Z_D1 (15,37) -> (15,37)
Info: Sink SOC.Core.Pc.load_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.FXB
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:157.70-157.72
Info: 0.2 13.7 Source SOC.Core.Pc.load_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: 0.8 14.5 Net SOC.Core.Pc.load_LUT4_Z_A[3] (15,37) -> (16,37)
Info: Sink SOC.Core.Pc.load_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 14.7 Source SOC.Core.Pc.load_LUT4_Z.F
Info: 1.6 16.3 Net SOC.Core.pc_load (16,37) -> (8,32)
Info: Sink SOC.Core.Pc.Output_TRELLIS_FF_Q_21.CE
Info: Defined in:
Info: Risco-5/src/core/core.v:51.32-51.39
Info: 0.0 16.3 Setup SOC.Core.Pc.Output_TRELLIS_FF_Q_21.CE
Info: 4.7 ns logic, 11.6 ns routing
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
Info: curr total
Info: 0.0 0.0 Source gpios[0]$tr_io.O
Info: 2.3 2.3 Net gpios[0]$TRELLIS_IO_IN (4,71) -> (4,49)
Info: Sink SOC.GPIOS.Gpios[0].data_in_LUT4_C.A
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 2.5 Source SOC.GPIOS.Gpios[0].data_in_LUT4_C.F
Info: 1.3 3.8 Net SOC.GPIOS.Gpios[0].data_in_LUT4_C_Z[3] (4,49) -> (6,42)
Info: Sink SOC.Core.read_data_LUT4_Z_D_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 4.0 Source SOC.Core.read_data_LUT4_Z_D_LUT4_Z.F
Info: 0.6 4.7 Net SOC.Core.read_data_LUT4_Z_D[2] (6,42) -> (6,42)
Info: Sink SOC.Core.read_data_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 4.9 Source SOC.Core.read_data_LUT4_Z.F
Info: 1.4 6.3 Net SOC.read_data[0] (6,42) -> (5,30)
Info: Sink SOC.Core.instruction_register_TRELLIS_FF_Q_30.M
Info: Defined in:
Info: Risco-5/src/peripheral/soc.v:24.34-24.43
Info: 0.0 6.3 Setup SOC.Core.instruction_register_TRELLIS_FF_Q_30.M
Info: 0.7 ns logic, 5.6 ns routing
Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
Info: curr total
Info: 0.5 0.5 Source SOC.Leds.data_TRELLIS_FF_Q_24.Q
Info: 4.4 4.9 Net SOC.Core.read_data_LUT4_Z_6_C[0] (9,28) -> (84,27)
Info: Sink led_LUT4_Z.D
Info: Defined in:
Info: Risco-5/src/peripheral/leds.v:19.12-19.16
Info: 0.2 5.1 Source led_LUT4_Z.F
Info: 1.2 6.3 Net led[7]$TRELLIS_IO_OUT (84,27) -> (90,20)
Info: Sink led[7]$tr_io.I
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:6.22-6.25
Info: 0.8 ns logic, 5.6 ns routing
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 61.24 MHz (PASS at 25.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 6.29 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 6.35 ns
Info: Slack histogram:
Info: legend: * represents 8 endpoint(s)
Info: + represents [1,8) endpoint(s)
Info: [ 23671, 24441) |**+
Info: [ 24441, 25211) |+
Info: [ 25211, 25981) |
Info: [ 25981, 26751) |+
Info: [ 26751, 27521) |*+
Info: [ 27521, 28291) |****+
Info: [ 28291, 29061) |*+
Info: [ 29061, 29831) |*+
Info: [ 29831, 30601) |***********+
Info: [ 30601, 31371) |*****************************************+
Info: [ 31371, 32141) |*********************************************+
Info: [ 32141, 32911) |*************+
Info: [ 32911, 33681) |*************+
Info: [ 33681, 34451) |**********************+
Info: [ 34451, 35221) |**********+
Info: [ 35221, 35991) |***************+
Info: [ 35991, 36761) |*********************+
Info: [ 36761, 37531) |************************************************************
Info: [ 37531, 38301) |*****************************************+
Info: [ 38301, 39071) |*********************+
INFO: [Synth 8-11241] undeclared symbol 'second_block_write_src_b', assumed default net type 'wire' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v:114]
INFO: [Synth 8-11241] undeclared symbol 'pc_source', assumed default net type 'wire' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:187]
WARNING: [Synth 8-9400] empty statement in sequential block [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v:54]
INFO: [Synth 8-6157] synthesizing module 'top' [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/main.v:1]
INFO: [Synth 8-6157] synthesizing module 'ResetBootSystem' [/var/lib/jenkins/workspace/Risco_5/Risco-5/debug/reset.v:1]
Parameter CYCLES bound to: 20 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'ResetBootSystem' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/debug/reset.v:1]
WARNING: [Synth 8-7071] port 'resetn_o' of module 'ResetBootSystem' is unconnected for instance 'ResetBootSystem' [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/main.v:24]
WARNING: [Synth 8-7023] instance 'ResetBootSystem' of module 'ResetBootSystem' has 3 connections declared, but only 2 given [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/main.v:24]
INFO: [Synth 8-6157] synthesizing module 'Risco_5_SOC' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:3]
Parameter CLOCK_FREQ bound to: 50000000 - type: integer
Parameter BIT_RATE bound to: 115200 - type: integer
Parameter MEMORY_SIZE bound to: 2048 - type: integer
Parameter MEMORY_FILE bound to: ../../software/memory/teste_uart_fpga.hex - type: string
Parameter GPIO_WIDHT bound to: 8 - type: integer
Parameter UART_BUFFER_SIZE bound to: 16 - type: integer
INFO: [Synth 8-6157] synthesizing module 'Core' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:2]
Parameter BOOT_ADDRESS bound to: 0 - type: integer
INFO: [Synth 8-6157] synthesizing module 'PC' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/pc.v:1]
INFO: [Synth 8-6155] done synthesizing module 'PC' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/pc.v:1]
INFO: [Synth 8-6157] synthesizing module 'MUX' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/mux.v:1]
INFO: [Synth 8-226] default block is never used [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/mux.v:15]
INFO: [Synth 8-6155] done synthesizing module 'MUX' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/mux.v:1]
WARNING: [Synth 8-7071] port 'C' of module 'MUX' is unconnected for instance 'MemoryAddressMUX' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:109]
WARNING: [Synth 8-7071] port 'D' of module 'MUX' is unconnected for instance 'MemoryAddressMUX' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:109]
WARNING: [Synth 8-7071] port 'E' of module 'MUX' is unconnected for instance 'MemoryAddressMUX' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:109]
WARNING: [Synth 8-7071] port 'F' of module 'MUX' is unconnected for instance 'MemoryAddressMUX' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:109]
WARNING: [Synth 8-7071] port 'G' of module 'MUX' is unconnected for instance 'MemoryAddressMUX' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:109]
WARNING: [Synth 8-7071] port 'H' of module 'MUX' is unconnected for instance 'MemoryAddressMUX' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:109]
WARNING: [Synth 8-7023] instance 'MemoryAddressMUX' of module 'MUX' has 10 connections declared, but only 4 given [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:109]
WARNING: [Synth 8-7071] port 'C' of module 'MUX' is unconnected for instance 'MemoryDataMUX' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:119]
WARNING: [Synth 8-7023] instance 'MemoryDataMUX' of module 'MUX' has 10 connections declared, but only 9 given [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:119]
WARNING: [Synth 8-7071] port 'G' of module 'MUX' is unconnected for instance 'AluInputAMUX' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:140]
WARNING: [Synth 8-7071] port 'H' of module 'MUX' is unconnected for instance 'AluInputAMUX' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:140]
WARNING: [Synth 8-7023] instance 'AluInputAMUX' of module 'MUX' has 10 connections declared, but only 8 given [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:140]
WARNING: [Synth 8-7071] port 'D' of module 'MUX' is unconnected for instance 'AluInputBMUX' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:156]
WARNING: [Synth 8-7071] port 'E' of module 'MUX' is unconnected for instance 'AluInputBMUX' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:156]
WARNING: [Synth 8-7071] port 'F' of module 'MUX' is unconnected for instance 'AluInputBMUX' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:156]
WARNING: [Synth 8-7071] port 'G' of module 'MUX' is unconnected for instance 'AluInputBMUX' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:156]
WARNING: [Synth 8-7071] port 'H' of module 'MUX' is unconnected for instance 'AluInputBMUX' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:156]
WARNING: [Synth 8-7023] instance 'AluInputBMUX' of module 'MUX' has 10 connections declared, but only 5 given [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:156]
INFO: [Synth 8-6157] synthesizing module 'Registers' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/registers.v:2]
INFO: [Synth 8-6155] done synthesizing module 'Registers' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/registers.v:2]
INFO: [Synth 8-6157] synthesizing module 'Control_Unit' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v:2]
INFO: [Synth 8-155] case statement is not full and has no default [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v:171]
INFO: [Synth 8-155] case statement is not full and has no default [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v:383]
INFO: [Synth 8-6155] done synthesizing module 'Control_Unit' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v:2]
WARNING: [Synth 8-7071] port 'last_bits_saved_address' of module 'Control_Unit' is unconnected for instance 'Control_Unit' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:215]
WARNING: [Synth 8-7023] instance 'Control_Unit' of module 'Control_Unit' has 33 connections declared, but only 32 given [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:215]
INFO: [Synth 8-6157] synthesizing module 'ALU_Control' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v:1]
INFO: [Synth 8-226] default block is never used [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v:34]
INFO: [Synth 8-155] case statement is not full and has no default [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v:11]
INFO: [Synth 8-6155] done synthesizing module 'ALU_Control' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v:1]
INFO: [Synth 8-6157] synthesizing module 'Alu' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu.v:1]
INFO: [Synth 8-6155] done synthesizing module 'Alu' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu.v:1]
INFO: [Synth 8-6157] synthesizing module 'Immediate_Generator' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/immediate_generator.v:1]
INFO: [Synth 8-6155] done synthesizing module 'Immediate_Generator' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/immediate_generator.v:1]
INFO: [Synth 8-6155] done synthesizing module 'Core' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:2]
WARNING: [Synth 8-7071] port 'halt' of module 'Core' is unconnected for instance 'Core' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:35]
WARNING: [Synth 8-7071] port 'interruption_request_external' of module 'Core' is unconnected for instance 'Core' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:35]
WARNING: [Synth 8-7071] port 'interruption_request_timer' of module 'Core' is unconnected for instance 'Core' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:35]
WARNING: [Synth 8-7071] port 'interruption_request_software' of module 'Core' is unconnected for instance 'Core' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:35]
WARNING: [Synth 8-7071] port 'interruption_request_fast' of module 'Core' is unconnected for instance 'Core' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:35]
WARNING: [Synth 8-7023] instance 'Core' of module 'Core' has 14 connections declared, but only 9 given [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:35]
INFO: [Synth 8-6157] synthesizing module 'Memory' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v:1]
Parameter MEMORY_FILE bound to: ../../software/memory/teste_uart_fpga.hex - type: string
Parameter MEMORY_SIZE bound to: 2048 - type: integer
INFO: [Synth 8-3876] $readmem data file '../../software/memory/teste_uart_fpga.hex' is read successfully [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v:35]
INFO: [Synth 8-6155] done synthesizing module 'Memory' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v:1]
INFO: [Synth 8-6157] synthesizing module 'BUS' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/bus.v:1]
INFO: [Synth 8-6155] done synthesizing module 'BUS' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/bus.v:1]
INFO: [Synth 8-6157] synthesizing module 'LEDs' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/leds.v:5]
INFO: [Synth 8-6155] done synthesizing module 'LEDs' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/leds.v:5]
INFO: [Synth 8-6157] synthesizing module 'UART' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart.v:4]
Parameter CLK_FREQ bound to: 50000000 - type: integer
Parameter BIT_RATE bound to: 115200 - type: integer
Parameter BUFFER_SIZE bound to: 16 - type: integer
INFO: [Synth 8-6157] synthesizing module 'FIFO' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/fifo.v:4]
Parameter DEPTH bound to: 16 - type: integer
Parameter WIDTH bound to: 8 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'FIFO' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/fifo.v:4]
INFO: [Synth 8-6157] synthesizing module 'uart_tool_rx' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_rx.v:13]
Parameter BIT_RATE bound to: 115200 - type: integer
Parameter CLK_HZ bound to: 50000000 - type: integer
Parameter PAYLOAD_BITS bound to: 8 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'uart_tool_rx' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_rx.v:13]
INFO: [Synth 8-6157] synthesizing module 'uart_tool_tx' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_tx.v:13]
Parameter BIT_RATE bound to: 115200 - type: integer
Parameter CLK_HZ bound to: 50000000 - type: integer
Parameter PAYLOAD_BITS bound to: 8 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'uart_tool_tx' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_tx.v:13]
INFO: [Synth 8-6155] done synthesizing module 'UART' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart.v:4]
INFO: [Synth 8-6157] synthesizing module 'GPIOS' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v:4]
Parameter WIDHT bound to: 8 - type: integer
INFO: [Synth 8-6157] synthesizing module 'GPIO' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpio.v:5]
INFO: [Synth 8-6155] done synthesizing module 'GPIO' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpio.v:5]
INFO: [Synth 8-6157] synthesizing module 'PWM' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/pwm.v:5]
INFO: [Synth 8-6155] done synthesizing module 'PWM' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/pwm.v:5]
INFO: [Synth 8-155] case statement is not full and has no default [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v:68]
INFO: [Synth 8-6155] done synthesizing module 'GPIOS' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v:4]
INFO: [Synth 8-6155] done synthesizing module 'Risco_5_SOC' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:3]
INFO: [Synth 8-6155] done synthesizing module 'top' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/main.v:1]
Info: Program finished normally.
WARNING: [Synth 8-3848] Net mdu_done in module/entity Core does not have driver. [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:55]
WARNING: [Synth 8-6014] Unused sequential element tx_fifo_read_reg was removed. [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart.v:163]
[Pipeline] }
[Pipeline] // stage
WARNING: [Synth 8-7129] Port address[31] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[30] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[29] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[28] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[27] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[26] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[25] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[24] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[23] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[22] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[21] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[20] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[19] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[18] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[17] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[16] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[15] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[14] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[13] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[12] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[11] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[10] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[9] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[8] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[31] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[30] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[29] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[28] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[27] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[26] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[25] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[24] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[23] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[22] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[21] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[20] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[19] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[18] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[17] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[31] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[30] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[29] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[28] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[27] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[26] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[25] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[24] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[23] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[22] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[21] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[20] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[19] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[18] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[17] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[16] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[15] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[14] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[13] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[12] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[11] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[10] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[9] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[8] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[7] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[6] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[5] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[1] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[0] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[31] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[30] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[29] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[28] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[27] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[26] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[25] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[24] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[23] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[22] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[21] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[20] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[19] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[18] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[17] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[16] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[15] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[14] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[13] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[12] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[11] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[10] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[9] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[8] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[7] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[6] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[5] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[4] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[3] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[2] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[1] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[0] in module LEDs is either unconnected or has no load
INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2112.750 ; gain = 487.684 ; free physical = 549 ; free virtual = 23193
---------------------------------------------------------------------------------
[10%] Placement Phase 0 completed
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2127.594 ; gain = 502.527 ; free physical = 525 ; free virtual = 23169
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2127.594 ; gain = 502.527 ; free physical = 525 ; free virtual = 23169
---------------------------------------------------------------------------------
[Pipeline] stage
[Pipeline] { (ECPPACK)
Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2127.594 ; gain = 0.000 ; free physical = 511 ; free virtual = 23154
[Pipeline] sh
+ /eda/oss-cad-suite/bin/ecppack --compress --input ./build/out.config --bit ./build/out.bit
[20%] Placement Phase 1 completed
[Pipeline] }
INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints
Initializing timing engine
[Pipeline] // stage
Parsing XDC File [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc]
[Pipeline] }
[Pipeline] // stage
Finished Parsing XDC File [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc]
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Completed Processing XDC Constraints
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2278.344 ; gain = 0.000 ; free physical = 483 ; free virtual = 23127
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2278.379 ; gain = 0.000 ; free physical = 493 ; free virtual = 23137
[Pipeline] }
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 2278.379 ; gain = 653.312 ; free physical = 491 ; free virtual = 23135
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7a100tcsg324-1
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 2278.379 ; gain = 653.312 ; free physical = 491 ; free virtual = 23135
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 2278.379 ; gain = 653.312 ; free physical = 491 ; free virtual = 23135
---------------------------------------------------------------------------------
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'ResetBootSystem'
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'Control_Unit'
INFO: [Synth 8-802] inferred FSM for state register 'fsm_state_reg' in module 'uart_tool_rx'
[30%] Placement Phase 2 completed
INFO: [Synth 8-802] inferred FSM for state register 'fsm_state_reg' in module 'uart_tool_tx'
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'UART'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
RESET_COUNTER | 00 | 01
IDLE | 01 | 10
INIT | 10 | 00
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'ResetBootSystem'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
FETCH | 00000000000000001 | 000000
VALIDATE_FETCH | 00000000000000010 | 101110
DECODE | 00000000000000100 | 000001
MEMADR | 00000000000001000 | 000010
MEMREAD | 00000000000010000 | 000011
MEMWB | 00000000000100000 | 000100
MEMWRITE | 00000000001000000 | 000101
EXECUTER | 00000000010000000 | 000110
EXECUTEI | 00000000100000000 | 001000
JAL | 00000001000000000 | 001001
BRANCH | 00000010000000000 | 001010
AUIPC | 00000100000000000 | 001100
LUI | 00001000000000000 | 001101
JALR_PC | 00010000000000000 | 001110
JALR | 00100000000000000 | 001011
ALUWB | 01000000000000000 | 000111
EXECUTECSR | 10000000000000000 | 001111
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'Control_Unit'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
FSM_IDLE | 00 | 000
FSM_START | 11 | 001
FSM_RECV | 10 | 010
FSM_STOP | 01 | 011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'fsm_state_reg' using encoding 'sequential' in module 'uart_tool_rx'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
FSM_IDLE | 00 | 000
FSM_START | 11 | 001
FSM_SEND | 10 | 010
FSM_STOP | 01 | 011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'fsm_state_reg' using encoding 'sequential' in module 'uart_tool_tx'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
IDLE | 0000 | 0000
COPY_WRITE_BUFFER | 0001 | 0100
WRITE | 0010 | 0010
READ | 0011 | 0001
READ_RX_FIFO_EMPTY | 0100 | 0110
READ_TX_FIFO_EMPTY | 0101 | 0111
READ_RX_FIFO_FULL | 0110 | 1000
READ_TX_FIFO_FULL | 0111 | 1001
WB | 1000 | 0101
FINISH | 1001 | 0011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'UART'
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 2278.379 ; gain = 653.312 ; free physical = 489 ; free virtual = 23134
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Component Statistics
---------------------------------------------------------------------------------
Detailed RTL Component Info :
+---Adders :
2 Input 32 Bit Adders := 1
3 Input 32 Bit Adders := 1
2 Input 10 Bit Adders := 2
2 Input 6 Bit Adders := 6
2 Input 5 Bit Adders := 1
2 Input 4 Bit Adders := 2
2 Input 3 Bit Adders := 1
+---XORs :
2 Input 32 Bit XORs := 1
+---Registers :
32 Bit Registers := 42
16 Bit Registers := 4
10 Bit Registers := 2
8 Bit Registers := 8
6 Bit Registers := 5
4 Bit Registers := 2
3 Bit Registers := 1
2 Bit Registers := 1
1 Bit Registers := 15
+---RAMs :
16K Bit (512 X 32 bit) RAMs := 1
128 Bit (16 X 8 bit) RAMs := 2
+---Muxes :
2 Input 32 Bit Muxes := 4
8 Input 32 Bit Muxes := 1
3 Input 32 Bit Muxes := 1
6 Input 32 Bit Muxes := 1
4 Input 32 Bit Muxes := 1
10 Input 32 Bit Muxes := 2
17 Input 17 Bit Muxes := 1
2 Input 17 Bit Muxes := 4
11 Input 17 Bit Muxes := 1
2 Input 8 Bit Muxes := 3
3 Input 6 Bit Muxes := 1
2 Input 6 Bit Muxes := 4
2 Input 5 Bit Muxes := 1
9 Input 4 Bit Muxes := 1
10 Input 4 Bit Muxes := 2
2 Input 4 Bit Muxes := 2
6 Input 4 Bit Muxes := 1
10 Input 3 Bit Muxes := 2
2 Input 3 Bit Muxes := 1
3 Input 2 Bit Muxes := 1
2 Input 2 Bit Muxes := 16
17 Input 2 Bit Muxes := 4
4 Input 2 Bit Muxes := 4
3 Input 1 Bit Muxes := 6
2 Input 1 Bit Muxes := 72
17 Input 1 Bit Muxes := 5
4 Input 1 Bit Muxes := 2
10 Input 1 Bit Muxes := 8
6 Input 1 Bit Muxes := 7
---------------------------------------------------------------------------------
Finished RTL Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 240 (col length:80)
BRAMs: 270 (col length: RAMB18 80 RAMB36 40)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
INFO: [Synth 8-6851] RAM (SOC/Memory/memory_reg) has partial Byte Wide Write Enable pattern, however no output register found in fanout of RAM. Recommended to use supported Byte Wide Write Enable template.
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:25 ; elapsed = 00:00:25 . Memory (MB): peak = 2278.379 ; gain = 653.312 ; free physical = 423 ; free virtual = 23074
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
Distributed RAM: Preliminary Mapping Report (see note below)
+------------+-----------------------------+-----------+----------------------+-----------------+
|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
+------------+-----------------------------+-----------+----------------------+-----------------+
|top | SOC/Memory/memory_reg | Implied | 512 x 32 | RAM256X1S x 64 |
|top | SOC/Uart/RX_FIFO/memory_reg | Implied | 16 x 8 | RAM32M x 2 |
|top | SOC/Uart/TX_FIFO/memory_reg | Implied | 16 x 8 | RAM32M x 2 |
+------------+-----------------------------+-----------+----------------------+-----------------+
Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once.
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:29 ; elapsed = 00:00:29 . Memory (MB): peak = 2278.379 ; gain = 653.312 ; free physical = 421 ; free virtual = 23072
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:00:31 ; elapsed = 00:00:31 . Memory (MB): peak = 2278.379 ; gain = 653.312 ; free physical = 420 ; free virtual = 23071
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
Distributed RAM: Final Mapping Report
+------------+-----------------------------+-----------+----------------------+-----------------+
|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
+------------+-----------------------------+-----------+----------------------+-----------------+
|top | SOC/Memory/memory_reg | Implied | 512 x 32 | RAM256X1S x 64 |
|top | SOC/Uart/RX_FIFO/memory_reg | Implied | 16 x 8 | RAM32M x 2 |
|top | SOC/Uart/TX_FIFO/memory_reg | Implied | 16 x 8 | RAM32M x 2 |
+------------+-----------------------------+-----------+----------------------+-----------------+
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
[50%] Placement Phase 3 completed
Running routing......
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:00:32 ; elapsed = 00:00:33 . Memory (MB): peak = 2278.379 ; gain = 653.312 ; free physical = 420 ; free virtual = 23071
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
[60%] Routing Phase 0 completed
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:00:36 ; elapsed = 00:00:37 . Memory (MB): peak = 2278.379 ; gain = 653.312 ; free physical = 360 ; free virtual = 23012
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:00:37 ; elapsed = 00:00:37 . Memory (MB): peak = 2278.379 ; gain = 653.312 ; free physical = 360 ; free virtual = 23012
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:37 ; elapsed = 00:00:37 . Memory (MB): peak = 2278.379 ; gain = 653.312 ; free physical = 360 ; free virtual = 23012
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:00:37 ; elapsed = 00:00:37 . Memory (MB): peak = 2278.379 ; gain = 653.312 ; free physical = 360 ; free virtual = 23012
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:37 ; elapsed = 00:00:37 . Memory (MB): peak = 2278.379 ; gain = 653.312 ; free physical = 361 ; free virtual = 23013
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:00:37 ; elapsed = 00:00:37 . Memory (MB): peak = 2278.379 ; gain = 653.312 ; free physical = 361 ; free virtual = 23013
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------
Report BlackBoxes:
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+
Report Cell Usage:
+------+----------+------+
| |Cell |Count |
+------+----------+------+
|1 |BUFG | 2|
|2 |CARRY4 | 55|
|3 |LUT1 | 13|
|4 |LUT2 | 111|
|5 |LUT3 | 150|
|6 |LUT4 | 238|
|7 |LUT5 | 234|
|8 |LUT6 | 1028|
|9 |MUXF7 | 291|
|10 |RAM256X1S | 64|
|11 |RAM32M | 2|
|12 |RAM32X1D | 4|
|13 |FDRE | 1611|
|14 |FDSE | 4|
|15 |IBUF | 3|
|16 |IOBUF | 8|
|17 |OBUF | 9|
+------+----------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:37 ; elapsed = 00:00:37 . Memory (MB): peak = 2278.379 ; gain = 653.312 ; free physical = 361 ; free virtual = 23013
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 30 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:35 ; elapsed = 00:00:35 . Memory (MB): peak = 2278.379 ; gain = 502.527 ; free physical = 360 ; free virtual = 23012
Synthesis Optimization Complete : Time (s): cpu = 00:00:37 ; elapsed = 00:00:37 . Memory (MB): peak = 2278.379 ; gain = 653.312 ; free physical = 360 ; free virtual = 23012
INFO: [Project 1-571] Translating synthesized netlist
Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2278.379 ; gain = 0.000 ; free physical = 633 ; free virtual = 23286
INFO: [Netlist 29-17] Analyzing 424 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc]
Finished Parsing XDC File [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2342.375 ; gain = 0.000 ; free physical = 633 ; free virtual = 23286
INFO: [Project 1-111] Unisim Transformation Summary:
A total of 78 instances were transformed.
IOBUF => IOBUF (IBUF, OBUFT): 8 instances
RAM256X1S => RAM256X1S (MUXF7(x2), MUXF8, RAMS64E(x4)): 64 instances
RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 2 instances
RAM32X1D => RAM32X1D (RAMD32(x2)): 4 instances
Synth Design complete | Checksum: e175bf3
INFO: [Common 17-83] Releasing license: Synthesis
78 Infos, 132 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:46 ; elapsed = 00:00:44 . Memory (MB): peak = 2342.410 ; gain = 1025.320 ; free physical = 618 ; free virtual = 23271
INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 2023.538; main = 1744.341; forked = 422.487
INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3215.988; main = 2342.379; forked = 969.656
# opt_design
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command opt_design
Starting DRC Task
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.79 . Memory (MB): peak = 2406.406 ; gain = 63.996 ; free physical = 620 ; free virtual = 23273
Starting Cache Timing Information Task
[70%] Routing Phase 1 completed
INFO: [Timing 38-35] Done setting XDC timing constraints.
Ending Cache Timing Information Task | Checksum: 11783c073
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2520.219 ; gain = 113.812 ; free physical = 557 ; free virtual = 23210
Starting Logic Optimization Task
Phase 1 Initialization
Phase 1.1 Core Generation And Design Setup
Phase 1.1 Core Generation And Design Setup | Checksum: 11783c073
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2766.156 ; gain = 0.000 ; free physical = 381 ; free virtual = 23002
Phase 1.2 Setup Constraints And Sort Netlist
Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 11783c073
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2766.156 ; gain = 0.000 ; free physical = 381 ; free virtual = 23002
Phase 1 Initialization | Checksum: 11783c073
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2766.156 ; gain = 0.000 ; free physical = 381 ; free virtual = 23002
Phase 2 Timer Update And Timing Data Collection
Phase 2.1 Timer Update
Phase 2.1 Timer Update | Checksum: 11783c073
Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2766.156 ; gain = 0.000 ; free physical = 381 ; free virtual = 23002
Phase 2.2 Timing Data Collection
Phase 2.2 Timing Data Collection | Checksum: 11783c073
Time (s): cpu = 00:00:00.15 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2766.156 ; gain = 0.000 ; free physical = 381 ; free virtual = 23002
Phase 2 Timer Update And Timing Data Collection | Checksum: 11783c073
Time (s): cpu = 00:00:00.15 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2766.156 ; gain = 0.000 ; free physical = 381 ; free virtual = 23002
Phase 3 Retarget
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 3 Retarget | Checksum: 11783c073
Time (s): cpu = 00:00:00.19 ; elapsed = 00:00:00.1 . Memory (MB): peak = 2766.156 ; gain = 0.000 ; free physical = 381 ; free virtual = 23002
Retarget | Checksum: 11783c073
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells
Phase 4 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 4 Constant propagation | Checksum: 1256b1c95
Time (s): cpu = 00:00:00.26 ; elapsed = 00:00:00.17 . Memory (MB): peak = 2766.156 ; gain = 0.000 ; free physical = 381 ; free virtual = 23002
Constant propagation | Checksum: 1256b1c95
INFO: [Opt 31-389] Phase Constant propagation created 36 cells and removed 169 cells
Phase 5 Sweep
Phase 5 Sweep | Checksum: 184af889d
Time (s): cpu = 00:00:00.3 ; elapsed = 00:00:00.21 . Memory (MB): peak = 2766.156 ; gain = 0.000 ; free physical = 381 ; free virtual = 23002
Sweep | Checksum: 184af889d
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 17 cells
Phase 6 BUFG optimization
Phase 6 BUFG optimization | Checksum: 184af889d
Time (s): cpu = 00:00:00.37 ; elapsed = 00:00:00.25 . Memory (MB): peak = 2798.172 ; gain = 32.016 ; free physical = 381 ; free virtual = 23002
BUFG optimization | Checksum: 184af889d
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
Phase 7 Shift Register Optimization
INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
Phase 7 Shift Register Optimization | Checksum: 184af889d
Time (s): cpu = 00:00:00.37 ; elapsed = 00:00:00.25 . Memory (MB): peak = 2798.172 ; gain = 32.016 ; free physical = 381 ; free virtual = 23002
Shift Register Optimization | Checksum: 184af889d
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
Phase 8 Post Processing Netlist
Phase 8 Post Processing Netlist | Checksum: 184af889d
Time (s): cpu = 00:00:00.38 ; elapsed = 00:00:00.26 . Memory (MB): peak = 2798.172 ; gain = 32.016 ; free physical = 381 ; free virtual = 23002
Post Processing Netlist | Checksum: 184af889d
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
Phase 9 Finalization
Phase 9.1 Finalizing Design Cores and Updating Shapes
Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 18b0907d0
Time (s): cpu = 00:00:00.45 ; elapsed = 00:00:00.3 . Memory (MB): peak = 2798.172 ; gain = 32.016 ; free physical = 381 ; free virtual = 23002
Phase 9.2 Verifying Netlist Connectivity
Starting Connectivity Check Task
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2798.172 ; gain = 0.000 ; free physical = 381 ; free virtual = 23002
Phase 9.2 Verifying Netlist Connectivity | Checksum: 18b0907d0
Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:00.31 . Memory (MB): peak = 2798.172 ; gain = 32.016 ; free physical = 381 ; free virtual = 23002
Phase 9 Finalization | Checksum: 18b0907d0
Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:00.31 . Memory (MB): peak = 2798.172 ; gain = 32.016 ; free physical = 381 ; free virtual = 23002
Opt_design Change Summary
=========================
-------------------------------------------------------------------------------------------------------------------------
| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
-------------------------------------------------------------------------------------------------------------------------
| Retarget | 0 | 0 | 0 |
| Constant propagation | 36 | 169 | 0 |
| Sweep | 0 | 17 | 0 |
| BUFG optimization | 0 | 0 | 0 |
| Shift Register Optimization | 0 | 0 | 0 |
| Post Processing Netlist | 0 | 0 | 0 |
-------------------------------------------------------------------------------------------------------------------------
Ending Logic Optimization Task | Checksum: 18b0907d0
Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:00.31 . Memory (MB): peak = 2798.172 ; gain = 32.016 ; free physical = 381 ; free virtual = 23002
INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8
Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2798.172 ; gain = 0.000 ; free physical = 381 ; free virtual = 23002
Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
Ending Power Optimization Task | Checksum: 18b0907d0
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2798.172 ; gain = 0.000 ; free physical = 381 ; free virtual = 23002
Starting Final Cleanup Task
Ending Final Cleanup Task | Checksum: 18b0907d0
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2798.172 ; gain = 0.000 ; free physical = 381 ; free virtual = 23002
Starting Netlist Obfuscation Task
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2798.172 ; gain = 0.000 ; free physical = 381 ; free virtual = 23002
Ending Netlist Obfuscation Task | Checksum: 18b0907d0
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2798.172 ; gain = 0.000 ; free physical = 381 ; free virtual = 23002
INFO: [Common 17-83] Releasing license: Implementation
18 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 2798.172 ; gain = 455.762 ; free physical = 381 ; free virtual = 23002
# place_design
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-83] Releasing license: Implementation
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs
Starting Placer Task
Phase 1 Placer Initialization
Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2830.188 ; gain = 0.000 ; free physical = 425 ; free virtual = 23031
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 111b3e1be
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2830.188 ; gain = 0.000 ; free physical = 425 ; free virtual = 23031
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2830.188 ; gain = 0.000 ; free physical = 425 ; free virtual = 23031
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: eaba1a74
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.79 . Memory (MB): peak = 2830.188 ; gain = 0.000 ; free physical = 424 ; free virtual = 23030
Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: 171709274
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 2837.215 ; gain = 7.027 ; free physical = 424 ; free virtual = 23030
Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: 171709274
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 2837.215 ; gain = 7.027 ; free physical = 424 ; free virtual = 23030
Phase 1 Placer Initialization | Checksum: 171709274
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 2837.215 ; gain = 7.027 ; free physical = 424 ; free virtual = 23030
Phase 2 Global Placement
Phase 2.1 Floorplanning
Phase 2.1 Floorplanning | Checksum: f742582f
Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2837.215 ; gain = 7.027 ; free physical = 419 ; free virtual = 23025
Phase 2.2 Update Timing before SLR Path Opt
Phase 2.2 Update Timing before SLR Path Opt | Checksum: 1b10be20d
Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2837.215 ; gain = 7.027 ; free physical = 419 ; free virtual = 23025
Phase 2.3 Post-Processing in Floorplanning
Phase 2.3 Post-Processing in Floorplanning | Checksum: 1b10be20d
Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2837.215 ; gain = 7.027 ; free physical = 419 ; free virtual = 23025
Phase 2.4 Global Placement Core
Phase 2.4.1 UpdateTiming Before Physical Synthesis
Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 1a782b84c
Time (s): cpu = 00:00:14 ; elapsed = 00:00:04 . Memory (MB): peak = 2837.215 ; gain = 7.027 ; free physical = 433 ; free virtual = 23028
Phase 2.4.2 Physical Synthesis In Placer
INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 61 LUT instances to create LUTNM shape
INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0
INFO: [Physopt 32-1138] End 1 Pass. Optimized 28 nets or LUTs. Breaked 0 LUT, combined 28 existing LUTs and moved 0 existing LUT
INFO: [Physopt 32-65] No nets found for high-fanout optimization.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found. Shift Register to Pipeline Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found. URAM Register Optimization was not performed.
INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2837.215 ; gain = 0.000 ; free physical = 433 ; free virtual = 23027
Summary of Physical Synthesis Optimizations
============================================
-----------------------------------------------------------------------------------------------------------------------------------------------------------
| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |
-----------------------------------------------------------------------------------------------------------------------------------------------------------
| LUT Combining | 0 | 28 | 28 | 0 | 1 | 00:00:00 |
| Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| Shift Register to Pipeline | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| URAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| Total | 0 | 28 | 28 | 0 | 4 | 00:00:00 |
-----------------------------------------------------------------------------------------------------------------------------------------------------------
Phase 2.4.2 Physical Synthesis In Placer | Checksum: 13a1e5681
Time (s): cpu = 00:00:15 ; elapsed = 00:00:04 . Memory (MB): peak = 2837.215 ; gain = 7.027 ; free physical = 433 ; free virtual = 23027
Phase 2.4 Global Placement Core | Checksum: 18860a67c
Time (s): cpu = 00:00:19 ; elapsed = 00:00:05 . Memory (MB): peak = 2837.215 ; gain = 7.027 ; free physical = 433 ; free virtual = 23027
Phase 2 Global Placement | Checksum: 18860a67c
Time (s): cpu = 00:00:19 ; elapsed = 00:00:05 . Memory (MB): peak = 2837.215 ; gain = 7.027 ; free physical = 433 ; free virtual = 23027
Phase 3 Detail Placement
Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: d1800fe4
Time (s): cpu = 00:00:19 ; elapsed = 00:00:05 . Memory (MB): peak = 2837.215 ; gain = 7.027 ; free physical = 433 ; free virtual = 23027
Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: e7cdfb80
Time (s): cpu = 00:00:19 ; elapsed = 00:00:05 . Memory (MB): peak = 2837.215 ; gain = 7.027 ; free physical = 433 ; free virtual = 23027
Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 120909787
Time (s): cpu = 00:00:20 ; elapsed = 00:00:05 . Memory (MB): peak = 2837.215 ; gain = 7.027 ; free physical = 433 ; free virtual = 23027
Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: f5190b7e
Time (s): cpu = 00:00:20 ; elapsed = 00:00:05 . Memory (MB): peak = 2837.215 ; gain = 7.027 ; free physical = 433 ; free virtual = 23027
Phase 3.5 Small Shape Detail Placement
Phase 3.5 Small Shape Detail Placement | Checksum: 1fbd7da2b
Time (s): cpu = 00:00:21 ; elapsed = 00:00:06 . Memory (MB): peak = 2837.215 ; gain = 7.027 ; free physical = 440 ; free virtual = 23032
Phase 3.6 Re-assign LUT pins
Phase 3.6 Re-assign LUT pins | Checksum: 1f17b4150
Time (s): cpu = 00:00:21 ; elapsed = 00:00:06 . Memory (MB): peak = 2837.215 ; gain = 7.027 ; free physical = 440 ; free virtual = 23032
Phase 3.7 Pipeline Register Optimization
Phase 3.7 Pipeline Register Optimization | Checksum: 21512b531
Time (s): cpu = 00:00:21 ; elapsed = 00:00:06 . Memory (MB): peak = 2837.215 ; gain = 7.027 ; free physical = 440 ; free virtual = 23032
Phase 3 Detail Placement | Checksum: 21512b531
Time (s): cpu = 00:00:21 ; elapsed = 00:00:06 . Memory (MB): peak = 2837.215 ; gain = 7.027 ; free physical = 440 ; free virtual = 23032
Phase 4 Post Placement Optimization and Clean-Up
Phase 4.1 Post Commit Optimization
[80%] Routing Phase 2 completed
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 4.1.1 Post Placement Optimization
Post Placement Optimization Initialization | Checksum: 1ad83c62b
Phase 4.1.1.1 BUFG Insertion
Starting Physical Synthesis Task
Phase 1 Physical Synthesis Initialization
INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=9.081 | TNS=0.000 |
Phase 1 Physical Synthesis Initialization | Checksum: 175eead4b
Time (s): cpu = 00:00:00.16 ; elapsed = 00:00:00.06 . Memory (MB): peak = 2837.215 ; gain = 0.000 ; free physical = 440 ; free virtual = 23032
INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0.
Ending Physical Synthesis Task | Checksum: 175eead4b
Time (s): cpu = 00:00:00.19 ; elapsed = 00:00:00.1 . Memory (MB): peak = 2837.215 ; gain = 0.000 ; free physical = 440 ; free virtual = 23032
Phase 4.1.1.1 BUFG Insertion | Checksum: 1ad83c62b
Time (s): cpu = 00:00:23 ; elapsed = 00:00:07 . Memory (MB): peak = 2837.215 ; gain = 7.027 ; free physical = 440 ; free virtual = 23032
Phase 4.1.1.2 Post Placement Timing Optimization
INFO: [Place 30-746] Post Placement Timing Summary WNS=9.081. For the most accurate timing information please run report_timing.
Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 1b2b96e0e
Time (s): cpu = 00:00:23 ; elapsed = 00:00:07 . Memory (MB): peak = 2837.215 ; gain = 7.027 ; free physical = 440 ; free virtual = 23032
Time (s): cpu = 00:00:23 ; elapsed = 00:00:07 . Memory (MB): peak = 2837.215 ; gain = 7.027 ; free physical = 440 ; free virtual = 23032
Phase 4.1 Post Commit Optimization | Checksum: 1b2b96e0e
Time (s): cpu = 00:00:23 ; elapsed = 00:00:07 . Memory (MB): peak = 2837.215 ; gain = 7.027 ; free physical = 440 ; free virtual = 23032
Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: 1b2b96e0e
Time (s): cpu = 00:00:24 ; elapsed = 00:00:07 . Memory (MB): peak = 2837.215 ; gain = 7.027 ; free physical = 440 ; free virtual = 23032
Phase 4.3 Placer Reporting
Phase 4.3.1 Print Estimated Congestion
INFO: [Place 30-612] Post-Placement Estimated Congestion
____________________________________________________
| | Global Congestion | Short Congestion |
| Direction | Region Size | Region Size |
|___________|___________________|___________________|
| North| 1x1| 2x2|
|___________|___________________|___________________|
| South| 1x1| 1x1|
|___________|___________________|___________________|
| East| 1x1| 1x1|
|___________|___________________|___________________|
| West| 1x1| 1x1|
|___________|___________________|___________________|
Phase 4.3.1 Print Estimated Congestion | Checksum: 1b2b96e0e
Time (s): cpu = 00:00:24 ; elapsed = 00:00:07 . Memory (MB): peak = 2837.215 ; gain = 7.027 ; free physical = 440 ; free virtual = 23032
Phase 4.3 Placer Reporting | Checksum: 1b2b96e0e
Time (s): cpu = 00:00:24 ; elapsed = 00:00:07 . Memory (MB): peak = 2837.215 ; gain = 7.027 ; free physical = 440 ; free virtual = 23032
Phase 4.4 Final Placement Cleanup
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2837.215 ; gain = 0.000 ; free physical = 440 ; free virtual = 23032
Time (s): cpu = 00:00:24 ; elapsed = 00:00:07 . Memory (MB): peak = 2837.215 ; gain = 7.027 ; free physical = 440 ; free virtual = 23032
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 21f6871c5
Time (s): cpu = 00:00:24 ; elapsed = 00:00:07 . Memory (MB): peak = 2837.215 ; gain = 7.027 ; free physical = 440 ; free virtual = 23032
Ending Placer Task | Checksum: 169488af0
Time (s): cpu = 00:00:24 ; elapsed = 00:00:07 . Memory (MB): peak = 2837.215 ; gain = 7.027 ; free physical = 440 ; free virtual = 23032
29 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
place_design: Time (s): cpu = 00:00:25 ; elapsed = 00:00:08 . Memory (MB): peak = 2837.215 ; gain = 39.043 ; free physical = 440 ; free virtual = 23032
# report_utilization -hierarchical -file digilent_nexys4ddr_utilization_hierarchical_place.rpt
# report_utilization -file digilent_nexys4ddr_utilization_place.rpt
# report_io -file digilent_nexys4ddr_io.rpt
report_io: Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.16 . Memory (MB): peak = 2837.215 ; gain = 0.000 ; free physical = 436 ; free virtual = 23027
# report_control_sets -verbose -file digilent_nexys4ddr_control_sets.rpt
report_control_sets: Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.1 . Memory (MB): peak = 2837.215 ; gain = 0.000 ; free physical = 435 ; free virtual = 23026
# report_clock_utilization -file digilent_nexys4ddr_clock_utilization.rpt
# route_design
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command route_design
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs
Phase 1 Build RT Design
Checksum: PlaceDB: e631b481 ConstDB: 0 ShapeSum: 8316d66f RouteDB: 0
WARN (PR1014) : Generic routing resource will be used to clock signal 'clk_d' by the specified constraint. And then it may lead to the excessive delay or skew
[90%] Routing Phase 3 completed
Running timing analysis......
[95%] Timing analysis completed
Placement and routing completed
Bitstream generation in progress......
Bitstream generation completed
Running power analysis......
[100%] Power analysis completed
Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.power.html" completed
Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.pin.html" completed
Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.rpt.html" completed
Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.rpt.txt" completed
Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.tr.html" completed
Tue Jul 30 02:06:33 2024
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Post Restoration Checksum: NetGraph: 41eeb984 | NumContArr: cddfc438 | Constraints: c2a8fa9d | Timing: c2a8fa9d
Phase 1 Build RT Design | Checksum: 2952072f6
Time (s): cpu = 00:00:32 ; elapsed = 00:00:27 . Memory (MB): peak = 2837.215 ; gain = 0.000 ; free physical = 766 ; free virtual = 23342
Phase 2 Router Initialization
Phase 2.1 Fix Topology Constraints
Phase 2.1 Fix Topology Constraints | Checksum: 2952072f6
Time (s): cpu = 00:00:32 ; elapsed = 00:00:27 . Memory (MB): peak = 2837.215 ; gain = 0.000 ; free physical = 783 ; free virtual = 23359
Phase 2.2 Pre Route Cleanup
Phase 2.2 Pre Route Cleanup | Checksum: 2952072f6
Time (s): cpu = 00:00:32 ; elapsed = 00:00:27 . Memory (MB): peak = 2837.215 ; gain = 0.000 ; free physical = 782 ; free virtual = 23359
Number of Nodes with overlaps = 0
Phase 2.3 Update Timing
Phase 2.3 Update Timing | Checksum: 1f3ce5af8
Time (s): cpu = 00:00:36 ; elapsed = 00:00:28 . Memory (MB): peak = 2837.215 ; gain = 0.000 ; free physical = 750 ; free virtual = 23327
INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.996 | TNS=0.000 | WHS=-0.066 | THS=-0.066 |
Router Utilization Summary
Global Vertical Routing Utilization = 0 %
Global Horizontal Routing Utilization = 7.10429e-05 %
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
Number of Failed Nets = 2724
(Failed Nets is the sum of unrouted and partially routed nets)
Number of Unrouted Nets = 2723
Number of Partially Routed Nets = 1
Number of Node Overlaps = 0
Phase 2 Router Initialization | Checksum: 27328a6fb
Time (s): cpu = 00:00:37 ; elapsed = 00:00:28 . Memory (MB): peak = 2837.215 ; gain = 0.000 ; free physical = 745 ; free virtual = 23322
Phase 3 Initial Routing
Phase 3.1 Global Routing
Phase 3.1 Global Routing | Checksum: 27328a6fb
Time (s): cpu = 00:00:37 ; elapsed = 00:00:28 . Memory (MB): peak = 2837.215 ; gain = 0.000 ; free physical = 745 ; free virtual = 23322
Phase 3.2 Initial Net Routing
Phase 3.2 Initial Net Routing | Checksum: 1dbe5b1fe
Time (s): cpu = 00:00:38 ; elapsed = 00:00:28 . Memory (MB): peak = 2837.215 ; gain = 0.000 ; free physical = 745 ; free virtual = 23322
Phase 3 Initial Routing | Checksum: 1dbe5b1fe
Time (s): cpu = 00:00:38 ; elapsed = 00:00:28 . Memory (MB): peak = 2837.215 ; gain = 0.000 ; free physical = 745 ; free virtual = 23322
Phase 4 Rip-up And Reroute
Phase 4.1 Global Iteration 0
Number of Nodes with overlaps = 366
Number of Nodes with overlaps = 2
Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.988 | TNS=0.000 | WHS=N/A | THS=N/A |
Phase 4.1 Global Iteration 0 | Checksum: 233427a93
Time (s): cpu = 00:00:41 ; elapsed = 00:00:29 . Memory (MB): peak = 2837.215 ; gain = 0.000 ; free physical = 745 ; free virtual = 23321
Phase 4 Rip-up And Reroute | Checksum: 233427a93
Time (s): cpu = 00:00:41 ; elapsed = 00:00:29 . Memory (MB): peak = 2837.215 ; gain = 0.000 ; free physical = 744 ; free virtual = 23320
Phase 5 Delay and Skew Optimization
Phase 5.1 Delay CleanUp
Phase 5.1 Delay CleanUp | Checksum: 233427a93
Time (s): cpu = 00:00:41 ; elapsed = 00:00:29 . Memory (MB): peak = 2837.215 ; gain = 0.000 ; free physical = 744 ; free virtual = 23320
Phase 5.2 Clock Skew Optimization
Phase 5.2 Clock Skew Optimization | Checksum: 233427a93
Time (s): cpu = 00:00:41 ; elapsed = 00:00:29 . Memory (MB): peak = 2837.215 ; gain = 0.000 ; free physical = 743 ; free virtual = 23320
Phase 5 Delay and Skew Optimization | Checksum: 233427a93
Time (s): cpu = 00:00:41 ; elapsed = 00:00:29 . Memory (MB): peak = 2837.215 ; gain = 0.000 ; free physical = 743 ; free virtual = 23320
Phase 6 Post Hold Fix
Phase 6.1 Hold Fix Iter
Phase 6.1.1 Update Timing
Phase 6.1.1 Update Timing | Checksum: 2c3d08406
Time (s): cpu = 00:00:41 ; elapsed = 00:00:29 . Memory (MB): peak = 2837.215 ; gain = 0.000 ; free physical = 741 ; free virtual = 23318
INFO: [Route 35-416] Intermediate Timing Summary | WNS=9.084 | TNS=0.000 | WHS=0.194 | THS=0.000 |
Phase 6.1 Hold Fix Iter | Checksum: 2c3d08406
Time (s): cpu = 00:00:41 ; elapsed = 00:00:29 . Memory (MB): peak = 2837.215 ; gain = 0.000 ; free physical = 741 ; free virtual = 23317
Phase 6 Post Hold Fix | Checksum: 2c3d08406
Time (s): cpu = 00:00:41 ; elapsed = 00:00:29 . Memory (MB): peak = 2837.215 ; gain = 0.000 ; free physical = 741 ; free virtual = 23317
Phase 7 Route finalize
Router Utilization Summary
Global Vertical Routing Utilization = 0.484659 %
Global Horizontal Routing Utilization = 0.671853 %
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
Number of Failed Nets = 0
(Failed Nets is the sum of unrouted and partially routed nets)
Number of Unrouted Nets = 0
Number of Partially Routed Nets = 0
Number of Node Overlaps = 0
Phase 7 Route finalize | Checksum: 2c3d08406
Time (s): cpu = 00:00:41 ; elapsed = 00:00:29 . Memory (MB): peak = 2837.215 ; gain = 0.000 ; free physical = 749 ; free virtual = 23326
Phase 8 Verifying routed nets
Verification completed successfully
Phase 8 Verifying routed nets | Checksum: 2c3d08406
Time (s): cpu = 00:00:41 ; elapsed = 00:00:29 . Memory (MB): peak = 2837.215 ; gain = 0.000 ; free physical = 749 ; free virtual = 23326
Phase 9 Depositing Routes
Phase 9 Depositing Routes | Checksum: 2283b9c7c
Time (s): cpu = 00:00:42 ; elapsed = 00:00:30 . Memory (MB): peak = 2837.215 ; gain = 0.000 ; free physical = 742 ; free virtual = 23318
Phase 10 Post Router Timing
INFO: [Route 35-57] Estimated Timing Summary | WNS=9.084 | TNS=0.000 | WHS=0.194 | THS=0.000 |
INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
Phase 10 Post Router Timing | Checksum: 2283b9c7c
Time (s): cpu = 00:00:42 ; elapsed = 00:00:30 . Memory (MB): peak = 2837.215 ; gain = 0.000 ; free physical = 741 ; free virtual = 23318
INFO: [Route 35-16] Router Completed Successfully
Phase 11 Post-Route Event Processing
Phase 11 Post-Route Event Processing | Checksum: 1c780b804
Time (s): cpu = 00:00:42 ; elapsed = 00:00:30 . Memory (MB): peak = 2837.215 ; gain = 0.000 ; free physical = 740 ; free virtual = 23317
Ending Routing Task | Checksum: 1c780b804
Time (s): cpu = 00:00:42 ; elapsed = 00:00:30 . Memory (MB): peak = 2837.215 ; gain = 0.000 ; free physical = 739 ; free virtual = 23315
Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
12 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:00:43 ; elapsed = 00:00:30 . Memory (MB): peak = 2837.215 ; gain = 0.000 ; free physical = 738 ; free virtual = 23315
# report_timing_summary -no_header -no_detailed_paths
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------
Enable Multi Corner Analysis : Yes
Enable Pessimism Removal : Yes
Pessimism Removal Resolution : Nearest Common Node
Enable Input Delay Default Clock : No
Enable Preset / Clear Arcs : No
Disable Flight Delays : No
Ignore I/O Paths : No
Timing Early Launch at Borrowing Latches : No
Borrow Time for Max Delay Exceptions : Yes
Merge Timing Exceptions : Yes
Inter-SLR Compensation : Conservative
Corner Analyze Analyze
Name Max Paths Min Paths
------ --------- ---------
Slow Yes Yes
Fast Yes Yes
------------------------------------------------------------------------------------------------
| Report Methodology
| ------------------
------------------------------------------------------------------------------------------------
No report available as report_methodology has not been run prior. Run report_methodology on the current design for the summary of methodology violations.
check_timing report
Table of Contents
-----------------
1. checking no_clock (1813)
2. checking constant_clock (0)
3. checking pulse_width_clock (0)
4. checking unconstrained_internal_endpoints (6425)
5. checking no_input_delay (2)
6. checking no_output_delay (3)
7. checking multiple_clock (0)
8. checking generated_clocks (0)
9. checking loops (0)
10. checking partial_input_delay (0)
11. checking partial_output_delay (0)
12. checking latch_loops (0)
1. checking no_clock (1813)
---------------------------
There are 1813 register/latch pins with no clock driven by root clock pin: clk_o_reg/Q (HIGH)
2. checking constant_clock (0)
------------------------------
There are 0 register/latch pins with constant_clock.
3. checking pulse_width_clock (0)
---------------------------------
There are 0 register/latch pins which need pulse_width check
4. checking unconstrained_internal_endpoints (6425)
---------------------------------------------------
There are 6425 pins that are not constrained for maximum delay. (HIGH)
There are 0 pins that are not constrained for maximum delay due to constant clock.
5. checking no_input_delay (2)
------------------------------
There are 2 input ports with no input delay specified. (HIGH)
There are 0 input ports with no input delay but user has a false path constraint.
6. checking no_output_delay (3)
-------------------------------
There are 3 ports with no output delay specified. (HIGH)
There are 0 ports with no output delay but user has a false path constraint
There are 0 ports with no output delay but with a timing clock defined on it or propagating through it
7. checking multiple_clock (0)
------------------------------
There are 0 register/latch pins with multiple clocks.
8. checking generated_clocks (0)
--------------------------------
There are 0 generated clocks that are not connected to a clock source.
9. checking loops (0)
---------------------
There are 0 combinational loops in the design.
10. checking partial_input_delay (0)
------------------------------------
There are 0 input ports with partial input delay specified.
11. checking partial_output_delay (0)
-------------------------------------
There are 0 ports with partial output delay specified.
12. checking latch_loops (0)
----------------------------
There are 0 combinational latch loops in the design through latch input
------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------
WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
9.109 0.000 0 1 0.210 0.000 0 1 4.500 0.000 0 3
All user specified timing constraints are met.
------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------
Clock Waveform(ns) Period(ns) Frequency(MHz)
----- ------------ ---------- --------------
sys_clk_pin {0.000 5.000} 10.000 100.000
------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------
Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
sys_clk_pin 9.109 0.000 0 1 0.210 0.000 0 1 4.500 0.000 0 3
------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------
From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------
Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
# report_route_status -file digilent_nexys4ddr_route_status.rpt
# report_drc -file digilent_nexys4ddr_drc.rpt
Command: report_drc -file digilent_nexys4ddr_drc.rpt
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/eda/vivado/Vivado/2023.2/data/ip'.
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 2-168] The results of DRC are in file /var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4ddr_drc.rpt.
report_drc completed successfully
# report_timing_summary -datasheet -max_paths 10 -file digilent_nexys4ddr_timing.rpt
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
# report_power -file digilent_nexys4ddr_power.rpt
Command: report_power -file digilent_nexys4ddr_power.rpt
Running Vector-less Activity Propagation...
Finished Running Vector-less Activity Propagation
WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis.
Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report.
0 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
# write_bitstream -force "./build/out.bit"
Command: write_bitstream -force ./build/out.bit
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command write_bitstream
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [DRC 23-27] Running DRC with 8 threads
WARNING: [DRC BUFC-1] Input Buffer Connections: Input buffer gpio_IOBUF[0]_inst/IBUF has no loads. It is recommended to have an input buffer drive an internal load.
WARNING: [DRC BUFC-1] Input Buffer Connections: Input buffer gpio_IOBUF[1]_inst/IBUF has no loads. It is recommended to have an input buffer drive an internal load.
WARNING: [DRC BUFC-1] Input Buffer Connections: Input buffer gpio_IOBUF[2]_inst/IBUF has no loads. It is recommended to have an input buffer drive an internal load.
WARNING: [DRC BUFC-1] Input Buffer Connections: Input buffer gpio_IOBUF[3]_inst/IBUF has no loads. It is recommended to have an input buffer drive an internal load.
WARNING: [DRC BUFC-1] Input Buffer Connections: Input buffer gpio_IOBUF[4]_inst/IBUF has no loads. It is recommended to have an input buffer drive an internal load.
WARNING: [DRC BUFC-1] Input Buffer Connections: Input buffer gpio_IOBUF[5]_inst/IBUF has no loads. It is recommended to have an input buffer drive an internal load.
WARNING: [DRC BUFC-1] Input Buffer Connections: Input buffer gpio_IOBUF[6]_inst/IBUF has no loads. It is recommended to have an input buffer drive an internal load.
WARNING: [DRC BUFC-1] Input Buffer Connections: Input buffer gpio_IOBUF[7]_inst/IBUF has no loads. It is recommended to have an input buffer drive an internal load.
WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
set_property CFGBVS value1 [current_design]
#where value1 is either VCCO or GND
set_property CONFIG_VOLTAGE value2 [current_design]
#where value2 is the voltage provided to configuration bank 0
Refer to the device configuration user guide for more information.
INFO: [Vivado 12-3199] DRC finished with 0 Errors, 9 Warnings
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
INFO: [Designutils 20-2272] Running write_bitstream with 8 threads.
Loading data files...
Loading site data...
Loading route data...
Processing options...
Creating bitmap...
Creating bitstream...
Writing bitstream ./build/out.bit...
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
INFO: [Project 1-1876] WebTalk data collection is mandatory when using a ULT device. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
INFO: [Common 17-83] Releasing license: Implementation
9 Infos, 9 Warnings, 0 Critical Warnings and 0 Errors encountered.
write_bitstream completed successfully
write_bitstream: Time (s): cpu = 00:00:14 ; elapsed = 00:00:18 . Memory (MB): peak = 3145.262 ; gain = 246.207 ; free physical = 555 ; free virtual = 23074
INFO: [Common 17-206] Exiting Vivado at Tue Jul 30 02:07:12 2024...
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (FPGA Flash)
[Pipeline] parallel
[Pipeline] { (Branch: openFPGAloader ECP5)
[Pipeline] { (Branch: openFPGAloader Tangnano 20k)
[Pipeline] { (Branch: openFPGAloader Nexys 4 DDR)
[Pipeline] stage
[Pipeline] { (openFPGAloader ECP5)
[Pipeline] stage
[Pipeline] { (openFPGAloader Tangnano 20k)
[Pipeline] stage
[Pipeline] { (openFPGAloader Nexys 4 DDR)
[Pipeline] script
[Pipeline] {
[Pipeline] script
[Pipeline] {
[Pipeline] script
[Pipeline] {
[Pipeline] lock
Trying to acquire lock on [Resource: ecp5]
Resource [ecp5] did not exist. Created.
Lock acquired on [Resource: ecp5]
[Pipeline] {
[Pipeline] lock
Trying to acquire lock on [Resource: tangnano20k]
Resource [tangnano20k] did not exist. Created.
Lock acquired on [Resource: tangnano20k]
[Pipeline] {
[Pipeline] lock
Trying to acquire lock on [Resource: nexys4]
Resource [nexys4] did not exist. Created.
Lock acquired on [Resource: nexys4]
[Pipeline] {
[Pipeline] echo
FPGA ECP5 Broqueada
[Pipeline] sh
[Pipeline] echo
FPGA TangNano Broqueada
+ /eda/oss-cad-suite/bin/openFPGALoader -b colorlight-i9 ./build/out.bit
empty
Found 1 compatible device:
0x0d28 0x0204 0x3 DAPLink CMSIS-DAP
Open file: DONE
b3bdffff
Parse file: DONE
Enable configuration: DONE
SRAM erase: DONE
[Pipeline] sh
[Pipeline] echo
FPGA Nexys 4 Broqueada
+ echo gravando na tang nano
gravando na tang nano
[Pipeline] sh
[Pipeline] }
+ cd Risco-5/fpga/nexys4_ddr
+ /eda/oss-cad-suite/bin/openFPGALoader -b nexys_a7_100 ./build/out.bit
empty
Jtag frequency : requested 6.00MHz -> real 6.00MHz
Open file DONE
Parse file DONE
load program
Lock released on resource [Resource: tangnano20k]
[Pipeline] // lock
[Pipeline] }
[Pipeline] // script
Loading: [======= ] 13.66%[Pipeline] }
Load SRAM: [========= ] 18.00%[Pipeline] // stage
[Pipeline] }
Loading: [============== ] 27.33%
Load SRAM: [=================== ] 38.00%
Loading: [===================== ] 40.99%
Load SRAM: [============================= ] 58.00%
Loading: [============================ ] 54.65%
Load SRAM: [======================================= ] 78.00%
Loading: [=================================== ] 68.31%
Load SRAM: [================================================= ] 98.00%
Load SRAM: [===================================================] 100.00%
Done
Shift IR 35
ir: 1 isc_done 1 isc_ena 0 init 1 done 1
[Pipeline] }
Loading: [========================================= ] 81.98%Lock released on resource [Resource: nexys4]
[Pipeline] // lock
[Pipeline] }
[Pipeline] // script
Loading: [================================================ ] 95.64%[Pipeline] }
Loading: [==================================================] 100.00%
Done
Disable configuration: [Pipeline] // stage
[Pipeline] }
DONE
[Pipeline] }
Lock released on resource [Resource: ecp5]
[Pipeline] // lock
[Pipeline] }
[Pipeline] // script
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Testes)
[Pipeline] parallel
[Pipeline] { (Branch: ECP5 - Testes)
[Pipeline] { (Branch: TangNano - Testes)
[Pipeline] { (Branch: Nexys 4 - Testes)
[Pipeline] stage
[Pipeline] { (ECP5 - Testes)
[Pipeline] stage
[Pipeline] { (TangNano - Testes)
[Pipeline] stage
[Pipeline] { (Nexys 4 - Testes)
[Pipeline] script
[Pipeline] {
[Pipeline] script
[Pipeline] {
[Pipeline] script
[Pipeline] {
[Pipeline] echo
Rodando teste na ECP5
[Pipeline] lock
Trying to acquire lock on [Resource: ecp5]
Resource [ecp5] did not exist. Created.
Lock acquired on [Resource: ecp5]
[Pipeline] {
[Pipeline] echo
Rodando teste na tang nano
[Pipeline] lock
Trying to acquire lock on [Resource: tangnano20k]
Resource [tangnano20k] did not exist. Created.
Lock acquired on [Resource: tangnano20k]
[Pipeline] {
[Pipeline] echo
Rodando teste na Nexys 4
[Pipeline] lock
Trying to acquire lock on [Resource: nexys4]
Resource [nexys4] did not exist. Created.
Lock acquired on [Resource: nexys4]
[Pipeline] {
[Pipeline] echo
FPGA ECP5 Broqueada
[Pipeline] sh
[Pipeline] echo
FPGA TangNano Broqueada
+ echo testando na ecp5
testando na ecp5
[Pipeline] sh
[Pipeline] echo
FPGA Nexys 4 Broqueada
+ echo testando na tang nano
testando na tang nano
[Pipeline] sh
[Pipeline] }
+ echo testando na tang nano
testando na tang nano
Lock released on resource [Resource: ecp5]
[Pipeline] }
Lock released on resource [Resource: tangnano20k]
[Pipeline] // lock
[Pipeline] // lock
[Pipeline] echo
ECP5 liberada
[Pipeline] }
[Pipeline] echo
TangNano liberada
[Pipeline] }
[Pipeline] }
Lock released on resource [Resource: nexys4]
[Pipeline] // script
[Pipeline] // script
[Pipeline] // lock
[Pipeline] }
[Pipeline] }
[Pipeline] echo
TangNano liberada
[Pipeline] }
[Pipeline] // stage
[Pipeline] // stage
[Pipeline] // script
[Pipeline] }
[Pipeline] }
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // node
[Pipeline] End of Pipeline
Finished: SUCCESS
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