Console Output
+ /eda/oss-cad-suite/bin/nextpnr-ecp5 --json ./build/out.json --write ./build/out_pnr.json --45k --lpf Risco-5/fpga/ecp5/pinout.lpf --textcfg ./build/out.config --package CABGA381 --speed 6 --lpf-allow-unconstrained
Info: constraining clock net 'clk' to 25.00 MHz
Info: Logic utilisation before packing:
Info: Total LUT4s: 2976/43848 6%
Info: logic LUTs: 2336/43848 5%
Info: carry LUTs: 328/43848 0%
Info: RAM LUTs: 208/ 5481 3%
Info: RAMW LUTs: 104/10962 0%
Info: Total DFFs: 603/43848 1%
Info: Packing IOs..
Info: $gpios[5]$iobuf_i: gpios_$_TBUF__Y.Y
Info: pin 'gpios[5]$tr_io' constrained to Bel 'X9/Y71/PIOB'.
Info: $gpios[4]$iobuf_i: gpios_$_TBUF__Y_1.Y
Info: pin 'gpios[4]$tr_io' constrained to Bel 'X4/Y71/PIOB'.
Info: $gpios[3]$iobuf_i: gpios_$_TBUF__Y_2.Y
Info: pin 'gpios[3]$tr_io' constrained to Bel 'X0/Y65/PIOB'.
Info: $gpios[2]$iobuf_i: gpios_$_TBUF__Y_3.Y
Info: pin 'gpios[2]$tr_io' constrained to Bel 'X9/Y71/PIOA'.
Info: $gpios[1]$iobuf_i: gpios_$_TBUF__Y_4.Y
Info: pin 'gpios[1]$tr_io' constrained to Bel 'X6/Y71/PIOA'.
Info: $gpios[0]$iobuf_i: gpios_$_TBUF__Y_5.Y
Info: pin 'gpios[0]$tr_io' constrained to Bel 'X4/Y71/PIOA'.
Info: pin 'tx$tr_io' constrained to Bel 'X90/Y20/PIOC'.
Info: pin 'rx$tr_io' constrained to Bel 'X90/Y20/PIOA'.
Info: pin 'reset$tr_io' constrained to Bel 'X0/Y29/PIOA'.
Info: pin 'led[7]$tr_io' constrained to Bel 'X90/Y20/PIOD'.
Info: pin 'led[6]$tr_io' constrained to Bel 'X0/Y44/PIOD'.
Info: pin 'led[5]$tr_io' constrained to Bel 'X0/Y59/PIOA'.
Info: pin 'led[4]$tr_io' constrained to Bel 'X15/Y71/PIOB'.
Info: pin 'led[3]$tr_io' constrained to Bel 'X90/Y29/PIOC'.
Info: pin 'led[2]$tr_io' constrained to Bel 'X90/Y44/PIOB'.
Info: pin 'led[1]$tr_io' constrained to Bel 'X0/Y44/PIOC'.
Info: pin 'led[0]$tr_io' constrained to Bel 'X0/Y59/PIOC'.
Info: pin 'clk$tr_io' constrained to Bel 'X0/Y68/PIOC'.
Info: Packing constants..
Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info: 338 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info: Promoting globals...
Info: promoting clock net clk$TRELLIS_IO_IN to global network
Info: Checksum: 0xc6e142a3
Info: Device utilisation:
Info: TRELLIS_IO: 18/ 245 7%
Info: DCCA: 1/ 56 1%
Info: DP16KD: 0/ 108 0%
Info: MULT18X18D: 0/ 72 0%
Info: ALU54B: 0/ 36 0%
Info: EHXPLLL: 0/ 4 0%
Info: EXTREFB: 0/ 2 0%
Info: DCUA: 0/ 2 0%
Info: PCSCLKDIV: 0/ 2 0%
Info: IOLOGIC: 0/ 160 0%
Info: SIOLOGIC: 0/ 85 0%
Info: GSR: 0/ 1 0%
Info: JTAGG: 0/ 1 0%
Info: OSCG: 0/ 1 0%
Info: SEDGA: 0/ 1 0%
Info: DTR: 0/ 1 0%
Info: USRMCLK: 0/ 1 0%
Info: CLKDIVF: 0/ 4 0%
Info: ECLKSYNCB: 0/ 10 0%
Info: DLLDELD: 0/ 8 0%
Info: DDRDLL: 0/ 4 0%
Info: DQSBUFM: 0/ 10 0%
Info: TRELLIS_ECLKBUF: 0/ 8 0%
Info: ECLKBRIDGECS: 0/ 2 0%
Info: DCSC: 0/ 2 0%
Info: TRELLIS_FF: 603/ 43848 1%
Info: TRELLIS_COMB: 3064/ 43848 6%
Info: TRELLIS_RAMW: 52/ 5481 0%
Info: Placed 18 cells based on constraints.
Info: Creating initial analytic placement for 1544 cells, random placement wirelen = 139708.
Info: at initial placer iter 0, wirelen = 1872
Info: at initial placer iter 1, wirelen = 1477
Info: at initial placer iter 2, wirelen = 1511
Info: at initial placer iter 3, wirelen = 1473
Info: Running main analytical placer, max placement attempts per cell = 1746580.
Info: at iteration #1, type ALL: wirelen solved = 1463, spread = 19509, legal = 19759; time = 0.10s
Info: at iteration #2, type ALL: wirelen solved = 2731, spread = 16377, legal = 16630; time = 0.10s
Info: at iteration #3, type ALL: wirelen solved = 3414, spread = 15384, legal = 15675; time = 0.09s
Info: at iteration #4, type ALL: wirelen solved = 3968, spread = 14698, legal = 15228; time = 0.06s
Info: at iteration #5, type ALL: wirelen solved = 4755, spread = 13794, legal = 14147; time = 0.06s
Info: at iteration #6, type ALL: wirelen solved = 5054, spread = 13906, legal = 14438; time = 0.06s
Info: at iteration #7, type ALL: wirelen solved = 5802, spread = 13623, legal = 14058; time = 0.06s
Info: at iteration #8, type ALL: wirelen solved = 6277, spread = 13239, legal = 13656; time = 0.06s
Info: at iteration #9, type ALL: wirelen solved = 6511, spread = 13468, legal = 13770; time = 0.06s
Info: at iteration #10, type ALL: wirelen solved = 7155, spread = 13345, legal = 13665; time = 0.06s
Info: at iteration #11, type ALL: wirelen solved = 7311, spread = 13636, legal = 13994; time = 0.06s
Info: at iteration #12, type ALL: wirelen solved = 7619, spread = 13787, legal = 14080; time = 0.06s
Info: at iteration #13, type ALL: wirelen solved = 7970, spread = 12771, legal = 13221; time = 0.06s
Info: at iteration #14, type ALL: wirelen solved = 7747, spread = 12611, legal = 13118; time = 0.06s
Info: at iteration #15, type ALL: wirelen solved = 7837, spread = 12512, legal = 13128; time = 0.06s
Info: at iteration #16, type ALL: wirelen solved = 8080, spread = 12907, legal = 13339; time = 0.06s
Info: at iteration #17, type ALL: wirelen solved = 8489, spread = 13348, legal = 13646; time = 0.06s
Info: at iteration #18, type ALL: wirelen solved = 8852, spread = 13650, legal = 13982; time = 0.06s
Info: at iteration #19, type ALL: wirelen solved = 9194, spread = 14300, legal = 14630; time = 0.06s
Info: HeAP Placer Time: 2.15s
Info: of which solving equations: 1.30s
Info: of which spreading cells: 0.18s
Info: of which strict legalisation: 0.06s
Info: Running simulated annealing placer for refinement.
Info: at iteration #1: temp = 0.000000, timing cost = 2420, wirelen = 13118
Info: at iteration #5: temp = 0.000000, timing cost = 2126, wirelen = 11316
Info: at iteration #10: temp = 0.000000, timing cost = 2154, wirelen = 10938
Info: at iteration #15: temp = 0.000000, timing cost = 2173, wirelen = 10710
Info: at iteration #20: temp = 0.000000, timing cost = 2031, wirelen = 10632
Info: at iteration #20: temp = 0.000000, timing cost = 2026, wirelen = 10640
Info: SA placement time 5.47s
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 46.63 MHz (PASS at 25.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 7.91 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 10.12 ns
Info: Slack histogram:
Info: legend: * represents 8 endpoint(s)
Info: + represents [1,8) endpoint(s)
Info: [ 18556, 19591) |**+
Info: [ 19591, 20626) |*+
Info: [ 20626, 21661) |
Info: [ 21661, 22696) |+
Info: [ 22696, 23731) |**+
Info: [ 23731, 24766) |**+
Info: [ 24766, 25801) |**+
Info: [ 25801, 26836) |+
Info: [ 26836, 27871) |*****+
Info: [ 27871, 28906) |*********************+
Info: [ 28906, 29941) |************************************************************
Info: [ 29941, 30976) |**************+
Info: [ 30976, 32011) |*********+
Info: [ 32011, 33046) |********+
Info: [ 33046, 34081) |******************+
Info: [ 34081, 35116) |*******************+
Info: [ 35116, 36151) |*************************************************+
Info: [ 36151, 37186) |*****************************************+
Info: [ 37186, 38221) |************************************+
Info: [ 38221, 39256) |****************+
Info: Checksum: 0x78216731
Info: Routing globals...
Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
Info: Routing..
Info: Setting up routing queue.
Info: Routing 13102 arcs.
Info: | (re-)routed arcs | delta | remaining| time spent |
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
Info: 1000 | 361 638 | 361 638 | 12626| 0.38 0.38|
Info: 2000 | 681 1318 | 320 680 | 12026| 0.25 0.63|
Info: 3000 | 1123 1876 | 442 558 | 11599| 0.25 0.88|
Info: 4000 | 1535 2464 | 412 588 | 11088| 0.28 1.15|
Info: 5000 | 1996 3003 | 461 539 | 10631| 0.28 1.43|
Info: 6000 | 2391 3608 | 395 605 | 10133| 0.27 1.70|
Info: 7000 | 2777 4222 | 386 614 | 9566| 0.26 1.96|
Info: 8000 | 3171 4828 | 394 606 | 9111| 0.28 2.24|
Info: 9000 | 3595 5404 | 424 576 | 8611| 0.31 2.55|
Info: 10000 | 3986 6013 | 391 609 | 8112| 0.28 2.83|
Info: 11000 | 4414 6585 | 428 572 | 7686| 0.29 3.13|
Info: 12000 | 4878 7121 | 464 536 | 7330| 0.30 3.43|
Info: 13000 | 5326 7673 | 448 552 | 6975| 0.30 3.72|
Info: 14000 | 5818 8181 | 492 508 | 6587| 0.28 4.00|
Info: 15000 | 6204 8753 | 386 572 | 6052| 0.26 4.27|
Info: 16000 | 6525 9247 | 321 494 | 5422| 0.17 4.44|
Info: 17000 | 6721 9831 | 196 584 | 4661| 0.15 4.59|
Info: 18000 | 7015 10473 | 294 642 | 4013| 0.22 4.81|
Info: 19000 | 7095 11365 | 80 892 | 3113| 0.20 5.01|
Info: 20000 | 7194 12216 | 99 851 | 2229| 0.21 5.21|
Info: 21000 | 7286 13081 | 92 865 | 1339| 0.22 5.44|
Info: 22000 | 7358 13920 | 72 839 | 434| 0.20 5.63|
Info: 22433 | 7358 14115 | 0 195 | 0| 0.08 5.71|
Info: Routing complete.
Info: Router1 time 5.71s
Info: Checksum: 0xf7bfca53
Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
Info: curr total
Info: 0.5 0.5 Source SOC.Core.instruction_register_TRELLIS_FF_Q_28.Q
Info: 1.1 1.7 Net SOC.Core.instruction_register[2] (6,29) -> (5,30)
Info: Sink SOC.Core.Control_Unit.func7_lsb_bit_LUT4_A_3_D_LUT4_Z.B
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 1.9 Source SOC.Core.Control_Unit.func7_lsb_bit_LUT4_A_3_D_LUT4_Z.F
Info: 0.7 2.6 Net SOC.Core.Control_Unit.func7_lsb_bit_LUT4_A_3_D[4] (5,30) -> (6,30)
Info: Sink SOC.Core.Control_Unit.func7_lsb_bit_LUT4_A_3_D_L6MUX21_SD_D1_PFUMX_Z_ALUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 2.8 Source SOC.Core.Control_Unit.func7_lsb_bit_LUT4_A_3_D_L6MUX21_SD_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: 0.0 2.8 Net SOC.Core.Control_Unit.func7_lsb_bit_LUT4_A_3_D_L6MUX21_SD_Z (6,30) -> (6,30)
Info: Sink SOC.Core.Control_Unit.func7_lsb_bit_LUT4_A_3_D_L6MUX21_SD_D0_PFUMX_Z_ALUT_LUT4_Z.FXB
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:157.70-157.72
Info: 0.2 3.1 Source SOC.Core.Control_Unit.func7_lsb_bit_LUT4_A_3_D_L6MUX21_SD_D0_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: 1.7 4.7 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_1_C_LUT4_Z_D_CCU2C_S1_B1_LUT4_D_Z_LUT4_Z_1_C[2] (6,30) -> (13,41)
Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_1_C_LUT4_Z_D_CCU2C_S1_B1_LUT4_D_Z_LUT4_Z_D_LUT4_C_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_B_3_Z_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 5.0 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_1_C_LUT4_Z_D_CCU2C_S1_B1_LUT4_D_Z_LUT4_Z_D_LUT4_C_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_B_3_Z_LUT4_Z.F
Info: 1.5 6.5 Net SOC.Core.Alu.ALU_out_S_L6MUX21_Z_1_SD_PFUMX_Z_C0_PFUMX_Z_C0[3] (13,41) -> (12,36)
Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_A_LUT4_Z_D_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.B
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.4 6.9 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_A_LUT4_Z_D_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: 0.0 6.9 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_A_LUT4_Z_D_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (12,36) -> (12,36)
Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_A_LUT4_Z_D_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: 0.0 6.9 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_A_LUT4_Z_D_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: 0.0 6.9 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_A_LUT4_Z_D_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (12,36) -> (12,36)
Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_A_LUT4_Z_D_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/src/core/alu.v:35.26-35.45
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 7.0 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_A_LUT4_Z_D_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: 0.0 7.0 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_A_LUT4_Z_D_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (12,36) -> (12,36)
Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_A_LUT4_Z_D_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: 0.0 7.0 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_A_LUT4_Z_D_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: 0.0 7.0 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_A_LUT4_Z_D_CCU2C_S1_CIN_CCU2C_COUT_CIN (12,36) -> (12,36)
Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_A_LUT4_Z_D_CCU2C_S1_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/src/core/alu.v:35.26-35.45
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 7.0 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_A_LUT4_Z_D_CCU2C_S1_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: 0.0 7.0 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_A_LUT4_Z_D_CCU2C_S1_CIN_CCU2C_COUT$CCU2_FCI_INT (12,36) -> (12,36)
Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_A_LUT4_Z_D_CCU2C_S1_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: 0.0 7.0 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_A_LUT4_Z_D_CCU2C_S1_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: 0.0 7.0 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_A_LUT4_Z_D_CCU2C_S1_CIN (12,36) -> (13,36)
Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_A_LUT4_Z_D_CCU2C_S1$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/src/core/alu.v:35.26-35.45
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 7.1 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_A_LUT4_Z_D_CCU2C_S1$CCU2_COMB0.FCO
Info: 0.0 7.1 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_A_LUT4_Z_D_CCU2C_S1$CCU2_FCI_INT (13,36) -> (13,36)
Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_A_LUT4_Z_D_CCU2C_S1$CCU2_COMB1.FCI
Info: 0.0 7.1 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_A_LUT4_Z_D_CCU2C_S1$CCU2_COMB1.FCO
Info: 0.0 7.1 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_A_LUT4_Z_D_CCU2C_S1_COUT (13,36) -> (13,36)
Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_A_LUT4_Z_D_CCU2C_S1_COUT_CCU2C_CIN$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/src/core/alu.v:35.26-35.45
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.4 7.6 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_A_LUT4_Z_D_CCU2C_S1_COUT_CCU2C_CIN$CCU2_COMB0.F
Info: 1.3 8.8 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_A_LUT4_Z_D_CCU2C_S1_COUT_CCU2C_CIN_S0[5] (13,36) -> (12,31)
Info: Sink SOC.Core.Alu.ALU_out_S_L6MUX21_Z_6_SD_L6MUX21_Z_2_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 9.1 Source SOC.Core.Alu.ALU_out_S_L6MUX21_Z_6_SD_L6MUX21_Z_2_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: 0.0 9.1 Net SOC.Core.Alu.ALU_out_S_L6MUX21_Z_6_SD_L6MUX21_Z_2_D1 (12,31) -> (12,31)
Info: Sink SOC.Core.Alu.ALU_out_S_L6MUX21_Z_6_SD_L6MUX21_Z_2_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.FXB
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:157.70-157.72
Info: 0.2 9.3 Source SOC.Core.Alu.ALU_out_S_L6MUX21_Z_6_SD_L6MUX21_Z_2_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: 1.5 10.9 Net SOC.Core.Alu.ALU_out_S_L6MUX21_Z_6_SD[6] (12,31) -> (12,43)
Info: Sink SOC.Core.Alu.ALU_out_S_L6MUX21_Z_6_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 11.1 Source SOC.Core.Alu.ALU_out_S_L6MUX21_Z_6_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: 1.0 12.1 Net SOC.Core.alu_out[8] (12,43) -> (12,37)
Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_1_D_LUT4_A_Z_LUT4_Z.D
Info: Defined in:
Info: Risco-5/src/core/core.v:60.31-60.38
Info: 0.2 12.4 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_1_D_LUT4_A_Z_LUT4_Z.F
Info: 0.5 12.8 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_1_D_LUT4_A_Z[2] (12,37) -> (15,37)
Info: Sink SOC.Core.Pc.load_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.C
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 13.1 Source SOC.Core.Pc.load_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.F
Info: 0.0 13.1 Net SOC.Core.Pc.load_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT (15,37) -> (15,37)
Info: Sink SOC.Core.Pc.load_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.F1
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:157.46-157.48
Info: 0.2 13.2 Source SOC.Core.Pc.load_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: 0.0 13.2 Net SOC.Core.Pc.load_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D1 (15,37) -> (15,37)
Info: Sink SOC.Core.Pc.load_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.FXB
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:157.62-157.64
Info: 0.2 13.5 Source SOC.Core.Pc.load_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: 0.0 13.5 Net SOC.Core.Pc.load_LUT4_Z_A_L6MUX21_Z_D1 (15,37) -> (15,37)
Info: Sink SOC.Core.Pc.load_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.FXB
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:157.70-157.72
Info: 0.2 13.7 Source SOC.Core.Pc.load_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: 0.8 14.5 Net SOC.Core.Pc.load_LUT4_Z_A[3] (15,37) -> (16,37)
Info: Sink SOC.Core.Pc.load_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 14.7 Source SOC.Core.Pc.load_LUT4_Z.F
Info: 1.6 16.3 Net SOC.Core.pc_load (16,37) -> (8,32)
Info: Sink SOC.Core.Pc.Output_TRELLIS_FF_Q_21.CE
Info: Defined in:
Info: Risco-5/src/core/core.v:51.32-51.39
Info: 0.0 16.3 Setup SOC.Core.Pc.Output_TRELLIS_FF_Q_21.CE
Info: 4.7 ns logic, 11.6 ns routing
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
Info: curr total
Info: 0.0 0.0 Source gpios[0]$tr_io.O
Info: 2.3 2.3 Net gpios[0]$TRELLIS_IO_IN (4,71) -> (4,49)
Info: Sink SOC.GPIOS.Gpios[0].data_in_LUT4_C.A
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 2.5 Source SOC.GPIOS.Gpios[0].data_in_LUT4_C.F
Info: 1.3 3.8 Net SOC.GPIOS.Gpios[0].data_in_LUT4_C_Z[3] (4,49) -> (6,42)
Info: Sink SOC.Core.read_data_LUT4_Z_D_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 4.0 Source SOC.Core.read_data_LUT4_Z_D_LUT4_Z.F
Info: 0.6 4.7 Net SOC.Core.read_data_LUT4_Z_D[2] (6,42) -> (6,42)
Info: Sink SOC.Core.read_data_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 4.9 Source SOC.Core.read_data_LUT4_Z.F
Info: 1.4 6.3 Net SOC.read_data[0] (6,42) -> (5,30)
Info: Sink SOC.Core.instruction_register_TRELLIS_FF_Q_30.M
Info: Defined in:
Info: Risco-5/src/peripheral/soc.v:24.34-24.43
Info: 0.0 6.3 Setup SOC.Core.instruction_register_TRELLIS_FF_Q_30.M
Info: 0.7 ns logic, 5.6 ns routing
Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
Info: curr total
Info: 0.5 0.5 Source SOC.Leds.data_TRELLIS_FF_Q_24.Q
Info: 4.4 4.9 Net SOC.Core.read_data_LUT4_Z_6_C[0] (9,28) -> (84,27)
Info: Sink led_LUT4_Z.D
Info: Defined in:
Info: Risco-5/src/peripheral/leds.v:19.12-19.16
Info: 0.2 5.1 Source led_LUT4_Z.F
Info: 1.2 6.3 Net led[7]$TRELLIS_IO_OUT (84,27) -> (90,20)
Info: Sink led[7]$tr_io.I
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:6.22-6.25
Info: 0.8 ns logic, 5.6 ns routing
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 61.24 MHz (PASS at 25.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 6.29 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 6.35 ns
Info: Slack histogram:
Info: legend: * represents 8 endpoint(s)
Info: + represents [1,8) endpoint(s)
Info: [ 23671, 24441) |**+
Info: [ 24441, 25211) |+
Info: [ 25211, 25981) |
Info: [ 25981, 26751) |+
Info: [ 26751, 27521) |*+
Info: [ 27521, 28291) |****+
Info: [ 28291, 29061) |*+
Info: [ 29061, 29831) |*+
Info: [ 29831, 30601) |***********+
Info: [ 30601, 31371) |*****************************************+
Info: [ 31371, 32141) |*********************************************+
Info: [ 32141, 32911) |*************+
Info: [ 32911, 33681) |*************+
Info: [ 33681, 34451) |**********************+
Info: [ 34451, 35221) |**********+
Info: [ 35221, 35991) |***************+
Info: [ 35991, 36761) |*********************+
Info: [ 36761, 37531) |************************************************************
Info: [ 37531, 38301) |*****************************************+
Info: [ 38301, 39071) |*********************+
Info: Program finished normally.
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