Console Output
+ /eda/oss-cad-suite/bin/nextpnr-ecp5 --json ./build/out.json --write ./build/out_pnr.json --45k --lpf Risco-5/fpga/ecp5/pinout.lpf --textcfg ./build/out.config --package CABGA381 --speed 6 --lpf-allow-unconstrained
Info: constraining clock net 'clk' to 25.00 MHz
Info: Logic utilisation before packing:
Info: Total LUT4s: 4951/43848 11%
Info: logic LUTs: 3853/43848 8%
Info: carry LUTs: 690/43848 1%
Info: RAM LUTs: 272/ 5481 4%
Info: RAMW LUTs: 136/10962 1%
Info: Total DFFs: 1216/43848 2%
Info: Packing IOs..
Info: $gpios[5]$iobuf_i: gpios_$_TBUF__Y.Y
Info: pin 'gpios[5]$tr_io' constrained to Bel 'X9/Y71/PIOB'.
Info: $gpios[4]$iobuf_i: gpios_$_TBUF__Y_1.Y
Info: pin 'gpios[4]$tr_io' constrained to Bel 'X4/Y71/PIOB'.
Info: $gpios[3]$iobuf_i: gpios_$_TBUF__Y_2.Y
Info: pin 'gpios[3]$tr_io' constrained to Bel 'X0/Y65/PIOB'.
Info: $gpios[2]$iobuf_i: gpios_$_TBUF__Y_3.Y
Info: pin 'gpios[2]$tr_io' constrained to Bel 'X9/Y71/PIOA'.
Info: $gpios[1]$iobuf_i: gpios_$_TBUF__Y_4.Y
Info: pin 'gpios[1]$tr_io' constrained to Bel 'X6/Y71/PIOA'.
Info: $gpios[0]$iobuf_i: gpios_$_TBUF__Y_5.Y
Info: pin 'gpios[0]$tr_io' constrained to Bel 'X4/Y71/PIOA'.
Info: pin 'tx$tr_io' constrained to Bel 'X90/Y20/PIOC'.
Info: pin 'rx$tr_io' constrained to Bel 'X90/Y20/PIOA'.
Info: pin 'reset$tr_io' constrained to Bel 'X0/Y29/PIOA'.
Info: pin 'led[7]$tr_io' constrained to Bel 'X90/Y20/PIOD'.
Info: pin 'led[6]$tr_io' constrained to Bel 'X0/Y44/PIOD'.
Info: pin 'led[5]$tr_io' constrained to Bel 'X0/Y59/PIOA'.
Info: pin 'led[4]$tr_io' constrained to Bel 'X15/Y71/PIOB'.
Info: pin 'led[3]$tr_io' constrained to Bel 'X90/Y29/PIOC'.
Info: pin 'led[2]$tr_io' constrained to Bel 'X90/Y44/PIOB'.
Info: pin 'led[1]$tr_io' constrained to Bel 'X0/Y44/PIOC'.
Info: pin 'led[0]$tr_io' constrained to Bel 'X0/Y59/PIOC'.
Info: pin 'clk$tr_io' constrained to Bel 'X0/Y68/PIOC'.
Info: Packing constants..
Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info: 613 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info: Promoting globals...
Info: promoting clock net clk$TRELLIS_IO_IN to global network
Info: Checksum: 0x9cd20c2a
Info: Device utilisation:
Info: TRELLIS_IO: 18/ 245 7%
Info: DCCA: 1/ 56 1%
Info: DP16KD: 0/ 108 0%
Info: MULT18X18D: 4/ 72 5%
Info: ALU54B: 0/ 36 0%
Info: EHXPLLL: 0/ 4 0%
Info: EXTREFB: 0/ 2 0%
Info: DCUA: 0/ 2 0%
Info: PCSCLKDIV: 0/ 2 0%
Info: IOLOGIC: 0/ 160 0%
Info: SIOLOGIC: 0/ 85 0%
Info: GSR: 0/ 1 0%
Info: JTAGG: 0/ 1 0%
Info: OSCG: 0/ 1 0%
Info: SEDGA: 0/ 1 0%
Info: DTR: 0/ 1 0%
Info: USRMCLK: 0/ 1 0%
Info: CLKDIVF: 0/ 4 0%
Info: ECLKSYNCB: 0/ 10 0%
Info: DLLDELD: 0/ 8 0%
Info: DDRDLL: 0/ 4 0%
Info: DQSBUFM: 0/ 10 0%
Info: TRELLIS_ECLKBUF: 0/ 8 0%
Info: ECLKBRIDGECS: 0/ 2 0%
Info: DCSC: 0/ 2 0%
Info: TRELLIS_FF: 1216/ 43848 2%
Info: TRELLIS_COMB: 5075/ 43848 11%
Info: TRELLIS_RAMW: 68/ 5481 1%
Info: Placed 18 cells based on constraints.
Info: Creating initial analytic placement for 2786 cells, random placement wirelen = 243224.
Info: at initial placer iter 0, wirelen = 2741
Info: at initial placer iter 1, wirelen = 2207
Info: at initial placer iter 2, wirelen = 2149
Info: at initial placer iter 3, wirelen = 2225
Info: Running main analytical placer, max placement attempts per cell = 5091240.
Info: at iteration #1, type ALL: wirelen solved = 2250, spread = 36854, legal = 40973; time = 0.16s
Info: at iteration #2, type ALL: wirelen solved = 4489, spread = 31050, legal = 33356; time = 0.19s
Info: at iteration #3, type ALL: wirelen solved = 6026, spread = 29241, legal = 32485; time = 0.19s
Info: at iteration #4, type ALL: wirelen solved = 6922, spread = 27282, legal = 30366; time = 0.19s
Info: at iteration #5, type ALL: wirelen solved = 8021, spread = 26402, legal = 28773; time = 0.18s
Info: at iteration #6, type ALL: wirelen solved = 9466, spread = 25732, legal = 28187; time = 0.18s
Info: at iteration #7, type ALL: wirelen solved = 11137, spread = 24574, legal = 27123; time = 0.18s
Info: at iteration #8, type ALL: wirelen solved = 12265, spread = 26286, legal = 28679; time = 0.17s
Info: at iteration #9, type ALL: wirelen solved = 13045, spread = 25658, legal = 27706; time = 0.18s
Info: at iteration #10, type ALL: wirelen solved = 13676, spread = 26092, legal = 27707; time = 0.18s
Info: at iteration #11, type ALL: wirelen solved = 14363, spread = 25636, legal = 26781; time = 0.18s
Info: at iteration #12, type ALL: wirelen solved = 15223, spread = 24927, legal = 25735; time = 0.18s
Info: at iteration #13, type ALL: wirelen solved = 15803, spread = 24620, legal = 25524; time = 0.18s
Info: at iteration #14, type ALL: wirelen solved = 15740, spread = 22871, legal = 24210; time = 0.17s
Info: at iteration #15, type ALL: wirelen solved = 15784, spread = 23709, legal = 24679; time = 0.14s
Info: at iteration #16, type ALL: wirelen solved = 16415, spread = 23525, legal = 24948; time = 0.17s
Info: at iteration #17, type ALL: wirelen solved = 16482, spread = 23628, legal = 25076; time = 0.17s
Info: at iteration #18, type ALL: wirelen solved = 17134, spread = 22851, legal = 24272; time = 0.17s
Info: at iteration #19, type ALL: wirelen solved = 17130, spread = 24199, legal = 25573; time = 0.12s
Info: HeAP Placer Time: 4.78s
Info: of which solving equations: 3.01s
Info: of which spreading cells: 0.36s
Info: of which strict legalisation: 0.16s
Info: Running simulated annealing placer for refinement.
Info: at iteration #1: temp = 0.000000, timing cost = 4636, wirelen = 24210
Info: at iteration #5: temp = 0.000000, timing cost = 4382, wirelen = 21207
Info: at iteration #10: temp = 0.000000, timing cost = 4297, wirelen = 20415
Info: at iteration #15: temp = 0.000000, timing cost = 3959, wirelen = 20103
Info: at iteration #20: temp = 0.000000, timing cost = 4002, wirelen = 19957
Info: at iteration #20: temp = 0.000000, timing cost = 3995, wirelen = 19960
Info: SA placement time 12.46s
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 43.87 MHz (PASS at 25.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 7.19 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 9.72 ns
Info: Slack histogram:
Info: legend: * represents 9 endpoint(s)
Info: + represents [1,9) endpoint(s)
Info: [ 17207, 18309) |*+
Info: [ 18309, 19411) |*+
Info: [ 19411, 20513) |+
Info: [ 20513, 21615) |**+
Info: [ 21615, 22717) |******+
Info: [ 22717, 23819) |****+
Info: [ 23819, 24921) |******************************+
Info: [ 24921, 26023) |****************************************************+
Info: [ 26023, 27125) |************************************************+
Info: [ 27125, 28227) |******************+
Info: [ 28227, 29329) |*************+
Info: [ 29329, 30431) |****************+
Info: [ 30431, 31533) |********+
Info: [ 31533, 32635) |*********+
Info: [ 32635, 33737) |********************+
Info: [ 33737, 34839) |************************************************+
Info: [ 34839, 35941) |**************************************************+
Info: [ 35941, 37043) |************************************************************
Info: [ 37043, 38145) |******************************************+
Info: [ 38145, 39247) |***********************************+
Info: Checksum: 0x9b49a7e6
Info: Routing globals...
Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
Info: Routing..
Info: Setting up routing queue.
Info: Routing 22349 arcs.
Info: | (re-)routed arcs | delta | remaining| time spent |
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
Info: 1000 | 484 515 | 484 515 | 21927| 0.56 0.56|
Info: 2000 | 898 1101 | 414 586 | 21459| 0.28 0.84|
Info: 3000 | 1363 1636 | 465 535 | 21003| 0.25 1.09|
Info: 4000 | 1765 2234 | 402 598 | 20746| 0.29 1.38|
Info: 5000 | 2243 2756 | 478 522 | 20397| 0.35 1.73|
Info: 6000 | 2715 3284 | 472 528 | 20069| 0.27 2.00|
Info: 7000 | 3091 3908 | 376 624 | 19759| 0.24 2.24|
Info: 8000 | 3566 4433 | 475 525 | 19322| 0.29 2.52|
Info: 9000 | 4005 4994 | 439 561 | 18891| 0.28 2.80|
Info: 10000 | 4399 5600 | 394 606 | 18600| 0.28 3.08|
Info: 11000 | 4773 6226 | 374 626 | 18231| 0.26 3.34|
Info: 12000 | 5131 6868 | 358 642 | 17829| 0.31 3.65|
Info: 13000 | 5405 7594 | 274 726 | 17613| 0.24 3.90|
Info: 14000 | 5673 8326 | 268 732 | 17096| 0.28 4.18|
Info: 15000 | 5994 9005 | 321 679 | 16629| 0.37 4.55|
Info: 16000 | 6327 9672 | 333 667 | 16181| 0.33 4.88|
Info: 17000 | 6734 10265 | 407 593 | 15915| 0.35 5.23|
Info: 18000 | 7061 10938 | 327 673 | 15482| 0.33 5.56|
Info: 19000 | 7536 11463 | 475 525 | 15069| 0.39 5.95|
Info: 20000 | 7871 12128 | 335 665 | 14814| 0.34 6.30|
Info: 21000 | 8271 12728 | 400 600 | 14593| 0.34 6.63|
Info: 22000 | 8685 13314 | 414 586 | 14143| 0.33 6.97|
Info: 23000 | 9074 13925 | 389 611 | 13613| 0.32 7.28|
Info: 24000 | 9497 14502 | 423 577 | 13260| 0.32 7.60|
Info: 25000 | 9972 15027 | 475 525 | 12937| 0.33 7.93|
Info: 26000 | 10406 15593 | 434 566 | 12522| 0.34 8.26|
Info: 27000 | 10825 16174 | 419 581 | 12170| 0.35 8.62|
Info: 28000 | 11226 16773 | 401 599 | 12159| 0.36 8.97|
Info: 29000 | 11601 17398 | 375 625 | 11994| 0.33 9.30|
Info: 30000 | 12157 17842 | 556 444 | 11671| 0.34 9.64|
Info: 31000 | 12673 18326 | 516 484 | 11352| 0.35 9.98|
Info: 32000 | 13091 18908 | 418 582 | 11025| 0.35 10.33|
Info: 33000 | 13626 19373 | 535 465 | 10659| 0.39 10.72|
Info: 34000 | 13996 20003 | 370 630 | 10320| 0.37 11.08|
Info: 35000 | 14244 20615 | 248 612 | 9619| 0.24 11.33|
Info: 36000 | 14418 21203 | 174 588 | 8845| 0.23 11.55|
Info: 37000 | 14617 21807 | 199 604 | 8073| 0.18 11.73|
Info: 38000 | 14931 22396 | 314 589 | 7447| 0.25 11.98|
Info: 39000 | 15201 23088 | 270 692 | 6843| 0.31 12.29|
Info: 40000 | 15313 23916 | 112 828 | 6025| 0.24 12.53|
Info: 41000 | 15419 24723 | 106 807 | 5146| 0.24 12.76|
Info: 42000 | 15541 25562 | 122 839 | 4271| 0.32 13.08|
Info: 43000 | 15661 26332 | 120 770 | 3395| 0.29 13.37|
Info: 44000 | 15801 27114 | 140 782 | 2585| 0.26 13.63|
Info: 45000 | 15893 27961 | 92 847 | 1704| 0.31 13.93|
Info: 46000 | 15972 28863 | 79 902 | 804| 0.27 14.20|
Info: 46817 | 15986 29263 | 14 400 | 0| 0.14 14.33|
Info: Routing complete.
Info: Router1 time 14.33s
Info: Checksum: 0xff21d021
Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
Info: curr total
Info: 0.5 0.5 Source SOC.Core.instruction_register_TRELLIS_FF_Q_22.Q
Info: 1.4 1.9 Net SOC.Core.instruction_register[8] (11,35) -> (10,33)
Info: Sink SOC.Core.RegisterBank.registers.0.8$DPRAM_COMB1.B
Info: Defined in:
Info: Risco-5/src/core/core.v:63.12-63.32
Info: 0.2 2.1 Source SOC.Core.RegisterBank.registers.0.8$DPRAM_COMB1.F
Info: 0.9 3.0 Net SOC.Core.RegisterBank.registers.0.0_DO_2[0] (10,33) -> (12,33)
Info: Sink SOC.Core.RegisterBank.registers.0.0_DO_2_LUT4_B.B
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 3.2 Source SOC.Core.RegisterBank.registers.0.0_DO_2_LUT4_B.F
Info: 0.9 4.1 Net SOC.Core.RegisterBank.registers.0.0_DO_2_LUT4_B_Z[2] (12,33) -> (14,35)
Info: Sink SOC.Core.RegisterBank.registers.0.0_DO_2_LUT4_B_Z_LUT4_C.C
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 4.4 Source SOC.Core.RegisterBank.registers.0.0_DO_2_LUT4_B_Z_LUT4_C.F
Info: 1.2 5.5 Net SOC.Core.RegisterBank.registers.0.0_DO_2_LUT4_B_Z_LUT4_C_Z[3] (14,35) -> (21,35)
Info: Sink SOC.Core.RegisterBank.registers.0.0_DO_2_LUT4_B_Z_LUT4_C_Z_LUT4_D.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.4 5.9 Source SOC.Core.RegisterBank.registers.0.0_DO_2_LUT4_B_Z_LUT4_C_Z_LUT4_D.OFX
Info: 1.5 7.4 Net SOC.Core.Alu.ALU_out_S_L6MUX21_Z_19_SD_PFUMX_Z_BLUT_LUT4_Z_D[0] (21,35) -> (16,38)
Info: Sink SOC.Core.RegisterBank.registers.0.1_DO_1_LUT4_A_Z_PFUMX_C0_Z_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.B
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.4 7.8 Source SOC.Core.RegisterBank.registers.0.1_DO_1_LUT4_A_Z_PFUMX_C0_Z_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: 0.0 7.8 Net SOC.Core.RegisterBank.registers.0.1_DO_1_LUT4_A_Z_PFUMX_C0_Z_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (16,38) -> (16,38)
Info: Sink SOC.Core.RegisterBank.registers.0.1_DO_1_LUT4_A_Z_PFUMX_C0_Z_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/src/core/alu.v:35.26-35.45
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.4 8.3 Source SOC.Core.RegisterBank.registers.0.1_DO_1_LUT4_A_Z_PFUMX_C0_Z_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.F
Info: 0.7 9.0 Net SOC.Core.RegisterBank.registers.0.1_DO_1_LUT4_A_Z_PFUMX_C0_Z_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0[4] (16,38) -> (16,37)
Info: Sink SOC.Core.RegisterBank.registers.0.1_DO_1_LUT4_A_Z_PFUMX_C0_Z_CCU2C_B0_1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_PFUMX_Z_BLUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 9.3 Source SOC.Core.RegisterBank.registers.0.1_DO_1_LUT4_A_Z_PFUMX_C0_Z_CCU2C_B0_1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: 0.9 10.2 Net SOC.Core.RegisterBank.registers.0.1_DO_1_LUT4_A_Z_PFUMX_C0_Z_CCU2C_B0_1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0[5] (16,37) -> (16,33)
Info: Sink SOC.Core.Alu.ALU_out_S_L6MUX21_Z_9_SD_L6MUX21_Z_2_D1_PFUMX_Z_ALUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 10.5 Source SOC.Core.Alu.ALU_out_S_L6MUX21_Z_9_SD_L6MUX21_Z_2_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: 1.3 11.7 Net SOC.Core.Alu.ALU_out_S_L6MUX21_Z_9_SD[6] (16,33) -> (23,30)
Info: Sink SOC.Core.Alu.ALU_out_S_L6MUX21_Z_9_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 12.0 Source SOC.Core.Alu.ALU_out_S_L6MUX21_Z_9_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: 1.4 13.4 Net SOC.Core.alu_out[2] (23,30) -> (21,41)
Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_2_D_LUT4_A_Z_L6MUX21_Z_SD_LUT4_Z.D
Info: Defined in:
Info: Risco-5/src/core/core.v:60.31-60.38
Info: 0.2 13.6 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_2_D_LUT4_A_Z_L6MUX21_Z_SD_LUT4_Z.F
Info: 0.4 14.0 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_2_D_LUT4_A_Z_L6MUX21_Z_SD[4] (21,41) -> (21,41)
Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_2_D_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 14.3 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_2_D_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: 0.0 14.3 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_2_D_LUT4_A_Z_L6MUX21_Z_D1 (21,41) -> (21,41)
Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_2_D_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.FXB
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:141.38-141.40
Info: 0.2 14.5 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_2_D_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: 0.7 15.2 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_2_D_LUT4_A_Z[4] (21,41) -> (18,41)
Info: Sink SOC.Core.Pc.load_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 15.5 Source SOC.Core.Pc.load_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: 0.0 15.5 Net SOC.Core.Pc.load_L6MUX21_Z_D1 (18,41) -> (18,41)
Info: Sink SOC.Core.Pc.load_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.FXB
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:141.38-141.40
Info: 0.2 15.7 Source SOC.Core.Pc.load_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: 1.7 17.4 Net SOC.Core.pc_load (18,41) -> (10,30)
Info: Sink SOC.Core.Pc.Output_TRELLIS_FF_Q_16.CE
Info: Defined in:
Info: Risco-5/src/core/core.v:51.32-51.39
Info: 0.0 17.4 Setup SOC.Core.Pc.Output_TRELLIS_FF_Q_16.CE
Info: 4.5 ns logic, 12.9 ns routing
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
Info: curr total
Info: 0.0 0.0 Source gpios[5]$tr_io.O
Info: 2.1 2.1 Net gpios[5]$TRELLIS_IO_IN (9,71) -> (8,60)
Info: Sink SOC.GPIOS.Gpios[5].data_in_LUT4_C.A
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:7.16-7.21
Info: 0.2 2.3 Source SOC.GPIOS.Gpios[5].data_in_LUT4_C.F
Info: 1.5 3.8 Net SOC.GPIOS.Gpios[5].data_in_LUT4_C_Z[3] (8,60) -> (7,42)
Info: Sink SOC.Core.read_data_LUT4_Z_5_D_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 4.0 Source SOC.Core.read_data_LUT4_Z_5_D_LUT4_Z.F
Info: 0.6 4.6 Net SOC.Core.read_data_LUT4_Z_5_D[2] (7,42) -> (7,42)
Info: Sink SOC.Core.read_data_LUT4_Z_5.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 4.8 Source SOC.Core.read_data_LUT4_Z_5.F
Info: 1.1 5.9 Net SOC.read_data[5] (7,42) -> (9,39)
Info: Sink SOC.Core.instruction_register_TRELLIS_FF_Q_25.M
Info: Defined in:
Info: Risco-5/src/peripheral/soc.v:24.34-24.43
Info: 0.0 5.9 Setup SOC.Core.instruction_register_TRELLIS_FF_Q_25.M
Info: 0.7 ns logic, 5.2 ns routing
Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
Info: curr total
Info: 0.5 0.5 Source SOC.Leds.data_TRELLIS_FF_Q_24.Q
Info: 3.9 4.4 Net SOC.Core.read_data_LUT4_Z_6_C[0] (25,35) -> (78,26)
Info: Sink led_LUT4_Z.D
Info: Defined in:
Info: Risco-5/src/peripheral/leds.v:19.12-19.16
Info: 0.2 4.7 Source led_LUT4_Z.F
Info: 1.8 6.5 Net led[7]$TRELLIS_IO_OUT (78,26) -> (90,20)
Info: Sink led[7]$tr_io.I
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:6.22-6.25
Info: 0.8 ns logic, 5.7 ns routing
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 57.52 MHz (PASS at 25.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 5.91 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 6.49 ns
Info: Slack histogram:
Info: legend: * represents 10 endpoint(s)
Info: + represents [1,10) endpoint(s)
Info: [ 22615, 23438) |**+
Info: [ 23438, 24261) |+
Info: [ 24261, 25084) |****+
Info: [ 25084, 25907) |*****+
Info: [ 25907, 26730) |***********+
Info: [ 26730, 27553) |*************+
Info: [ 27553, 28376) |********************************************+
Info: [ 28376, 29199) |*************************************************+
Info: [ 29199, 30022) |**********************+
Info: [ 30022, 30845) |***********+
Info: [ 30845, 31668) |***********+
Info: [ 31668, 32491) |**************+
Info: [ 32491, 33314) |****************+
Info: [ 33314, 34137) |***************+
Info: [ 34137, 34960) |*****************+
Info: [ 34960, 35783) |*********************+
Info: [ 35783, 36606) |******************************************************+
Info: [ 36606, 37429) |************************************************************
Info: [ 37429, 38252) |***********************************************+
Info: [ 38252, 39075) |******************************+
Info: Program finished normally.
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