![[Jenkins]](/jenkins/static/b6fe011e/images/svgs/logo.svg){kind=logo}
| Step | Arguments | Status | ||
|---|---|---|---|---|
| Start of Pipeline - (1 min 43 sec in block) | ||||
| node - (1 min 42 sec in block) | ||||
| node block - (1 min 42 sec in block) | ||||
| stage - (2 sec in block) | Git Clone | |||
| stage block (Git Clone) - (1.8 sec in block) | ||||
| sh - (0.37 sec in self) | rm -Rf Risco-5/ build/ | |||
| sh - (0.92 sec in self) | git clone https://github.com/JN513/Risco-5 | |||
| sh - (0.35 sec in self) | cd Risco-5 | |||
| stage - (2.4 sec in block) | IVerilog | |||
| stage block (IVerilog) - (2.1 sec in block) | ||||
| sh - (0.43 sec in self) | mkdir -p build | |||
| sh - (0.39 sec in self) | cp Risco-5/software/memory/add.hex Risco-5/software/memory/generic.hex | |||
| sh - (0.41 sec in self) | /eda/oss-cad-suite/bin/iverilog -o build/soc_test.o -s soc_tb Risco-5/src/core/*.v Risco-5/src/peripheral/*.v Risco-5/tests/soc_test.v | |||
| sh - (0.39 sec in self) | /eda/oss-cad-suite/bin/vvp build/soc_test.o | |||
| sh - (0.34 sec in self) | rm -f Risco5/software/memory/generic.hex | |||
| stage - (16 sec in block) | Síntese | |||
| stage block (Síntese) - (16 sec in block) | ||||
| parallel - (16 sec in block) | ||||
| parallel block (Branch: Yosys) - (34 ms in block) | ||||
| stage - (15 sec in block) | Yosys | |||
| stage block (Yosys) - (15 sec in block) | ||||
| sh - (15 sec in self) | /eda/oss-cad-suite/bin/yosys -p " read_verilog Risco-5/fpga/ecp5/*.v; read_verilog Risco-5/debug/clk_divider.v; read_verilog Risco-5/src/core/*.v; read_verilog Risco-5/src/peripheral/*.v; synth_ecp5 -json ./build/out.json -abc9 " | |||
| parallel block (Branch: Gowin) - (1.3 sec in block) | ||||
| stage - (0.91 sec in block) | Gowin | |||
| stage block (Gowin) - (0.72 sec in block) | ||||
| sh - (0.45 sec in self) | echo "ola" | |||
| stage - (1 min 15 sec in block) | NextPNR | |||
| stage block (NextPNR) - (1 min 15 sec in block) | ||||
| sh - (1 min 14 sec in self) | /eda/oss-cad-suite/bin/nextpnr-ecp5 --json ./build/out.json --write ./build/out_pnr.json --45k --lpf Risco-5/fpga/ecp5/pinout.lpf --textcfg ./build/out.config --package CABGA381 --speed 6 --ignore-loops --lpf-allow-unconstrained | |||
| stage - (1.3 sec in block) | ECPPACK | |||
| stage block (ECPPACK) - (1 sec in block) | ||||
| sh - (0.87 sec in self) | /eda/oss-cad-suite/bin/ecppack --compress --input ./build/out.config --bit ./build/out.bit | |||
| stage - (4.2 sec in block) | openFPGAloader | |||
| stage block (openFPGAloader) - (4 sec in block) | ||||
| sh - (3.8 sec in self) | /eda/oss-cad-suite/bin/openFPGALoader -b colorlight-i9 ./build/out.bit |