Console Output

+ iverilog -o simulation.out -s core src/core/alu.v src/core/alu_control.v src/core/control_unit.v src/core/core.v src/core/csr_unit.v src/core/immediate_generator.v src/core/mdu.v src/core/mux.v src/core/pc.v src/core/registers.v
error: Unable to find the root module "core" in the Verilog source.
     : Perhaps ``-s core'' is incorrect?
1 error(s) during elaboration.