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Start of Pipeline - (11 min in block)
node - (11 min in block)
node block - (11 min in block)
stage - (3 sec in block)Git Clone and Cleanup
stage block (Git Clone and Cleanup) - (2.4 sec in block)
sh - (0.65 sec in self)rm -rf Risco-5
sh - (1.3 sec in self)git clone --recursive https://github.com/JN513/Risco-5.git Risco-5
stage - (1.9 sec in block)Iverilog Simulation
stage block (Iverilog Simulation) - (1.3 sec in block)
dir - (0.95 sec in block)Risco-5
dir block - (0.61 sec in block)
sh - (0.41 sec in self)iverilog -o simulation.out -s soc_tb src/core/alu.v src/core/alu_control.v src/core/control_unit.v src/core/core.v src/core/csr_unit.v src/core/immediate_generator.v src/core/mdu.v src/core/mux.v src/core/pc.v src/core/registers.v tests/soc_test.v src/peripheral/bus.v src/peripheral/fifo.v src/peripheral/gpios.v src/peripheral/gpio.v src/peripheral/leds.v src/peripheral/memory.v src/peripheral/pwm.v src/peripheral/soc.v src/peripheral/uart_rx.v src/peripheral/uart_tx.v src/peripheral/uart.v
stage - (11 min in block)FPGA Synthesis
stage block (FPGA Synthesis) - (11 min in block)
parallel - (11 min in block)
parallel block (Branch: colorlight_i9) - (56 ms in block)
stage - (7 min 0 sec in block)colorlight_i9
stage block (colorlight_i9) - (6 min 59 sec in block)
lock - (6 min 58 sec in block)colorlight_i9
lock block - (6 min 58 sec in block)
echo - (0.26 sec in self)FPGA colorlight_i9 bloqueada para síntese.
dir - (6 min 57 sec in block)Risco-5
dir block - (6 min 57 sec in block)
sh - (6 min 56 sec in self)python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p Risco-5 -b colorlight_i9
parallel block (Branch: digilent_nexys4_ddr) - (11 min in block)
stage - (11 min in block)digilent_nexys4_ddr
stage block (digilent_nexys4_ddr) - (11 min in block)
lock - (11 min in block)digilent_nexys4_ddr
lock block - (10 min in block)
echo - (0.51 sec in self)FPGA digilent_nexys4_ddr bloqueada para síntese.
dir - (10 min in block)Risco-5
dir block - (10 min in block)
sh - (10 min in self)python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p Risco-5 -b digilent_nexys4_ddr
stage - (3.1 sec in block)Run Tests
stage block (Run Tests) - (2.6 sec in block)
parallel - (2.2 sec in block)
parallel block (Branch: colorlight_i9 Tests) - (56 ms in block)
stage - (1.1 sec in block)colorlight_i9 Tests
stage block (colorlight_i9 Tests) - (0.6 sec in block)
echo - (0.13 sec in self)Executando testes para FPGA colorlight_i9.
parallel block (Branch: digilent_nexys4_ddr Tests) - (1.7 sec in block)
stage - (1 sec in block)digilent_nexys4_ddr Tests
stage block (digilent_nexys4_ddr Tests) - (0.63 sec in block)
echo - (0.13 sec in self)Executando testes para FPGA digilent_nexys4_ddr.
stage - (1.7 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (1.4 sec in block)
dir - (0.97 sec in block)Risco-5
dir block - (0.69 sec in block)
sh - (0.46 sec in self)rm -rf *