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Start of Pipeline - (11 min in block)
node - (11 min in block)
node block - (11 min in block)
stage - (2.9 sec in block)Git Clone
stage block (Git Clone) - (2.4 sec in block)
sh - (0.48 sec in self)rm -rf Risco-5
sh - (1.7 sec in self)git clone --recursive https://github.com/JN513/Risco-5.git Risco-5
stage - (11 min in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (11 min in block)
parallel - (11 min in block)
parallel block (Branch: colorlight_i9) - (67 ms in block)
stage - (7 min 18 sec in block)colorlight_i9
stage block (colorlight_i9) - (7 min 17 sec in block)
stage - (6 min 53 sec in block)Síntese e PnR
stage block (Síntese e PnR) - (6 min 53 sec in block)
dir - (6 min 52 sec in block)Risco-5
dir block - (6 min 52 sec in block)
echo - (0.16 sec in self)Iniciando síntese para FPGA colorlight_i9.
sh - (6 min 51 sec in self)python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p Risco-5 -b colorlight_i9
stage - (20 sec in block)Flash colorlight_i9
stage block (Flash colorlight_i9) - (20 sec in block)
lock - (20 sec in block)colorlight_i9
lock block - (19 sec in block)
echo - (0.22 sec in self)FPGA colorlight_i9 bloqueada para flash.
dir - (18 sec in block)Risco-5
dir block - (18 sec in block)
sh - (18 sec in self)python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p Risco-5 -b colorlight_i9 -l
stage - (2.4 sec in block)Teste colorlight_i9
stage block (Teste colorlight_i9) - (2.1 sec in block)
lock - (1.7 sec in block)colorlight_i9
lock block - (1.1 sec in block)
echo - (0.22 sec in self)Testando FPGA colorlight_i9.
dir - (0.44 sec in block)Risco-5
dir block - (0.15 sec in block)
parallel block (Branch: digilent_nexys4_ddr) - (11 min in block)
stage - (11 min in block)digilent_nexys4_ddr
stage block (digilent_nexys4_ddr) - (11 min in block)
stage - (10 min in block)Síntese e PnR
stage block (Síntese e PnR) - (10 min in block)
dir - (10 min in block)Risco-5
dir block - (10 min in block)
echo - (0.16 sec in self)Iniciando síntese para FPGA digilent_nexys4_ddr.
sh - (10 min in self)python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p Risco-5 -b digilent_nexys4_ddr
stage - (8.2 sec in block)Flash digilent_nexys4_ddr
stage block (Flash digilent_nexys4_ddr) - (7.7 sec in block)
lock - (7.3 sec in block)digilent_nexys4_ddr
lock block - (6.7 sec in block)
echo - (0.25 sec in self)FPGA digilent_nexys4_ddr bloqueada para flash.
dir - (6.1 sec in block)Risco-5
dir block - (5.8 sec in block)
sh - (5.6 sec in self)python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p Risco-5 -b digilent_nexys4_ddr -l
stage - (2.3 sec in block)Teste digilent_nexys4_ddr
stage block (Teste digilent_nexys4_ddr) - (2.1 sec in block)
lock - (1.6 sec in block)digilent_nexys4_ddr
lock block - (1 sec in block)
echo - (0.22 sec in self)Testando FPGA digilent_nexys4_ddr.
dir - (0.41 sec in block)Risco-5
dir block - (0.15 sec in block)
stage - (1.6 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (1.3 sec in block)
dir - (0.86 sec in block)Risco-5
dir block - (0.62 sec in block)
sh - (0.4 sec in self)rm -rf *