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Full LogTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTest
Optimizing lut $abc$96743$lut$aiger96742$13262.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$13278.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$13309.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$13379.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$13395.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$13411.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$13439.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$13446.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$13479.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$13495.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$13517.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$13581.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$13642.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$13658.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$13674.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$13702.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$13709.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$13742.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$13758.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$13780.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$13865.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$13881.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$13912.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$13928.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$13944.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$13960.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$13979.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$13995.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$14011.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$14027.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$14040.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$14053.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$14120.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$14184.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$14246.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$14262.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$14278.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$14294.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$14313.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$14346.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$14362.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$14387.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$14453.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$14466.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$14517.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$14586.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$14602.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$14609.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$14619.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$14653.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$14669.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$14703.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$14724.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$14797.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$14858.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$14874.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$14959.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$14996.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$15127.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$15143.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$15159.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$15175.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$15194.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$15210.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$15226.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$15242.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$15267.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$15331.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$15347.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$15363.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$15379.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$15431.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$15447.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$15475.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$15539.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$15546.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$96743$lut$aiger96742$15553.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$15571.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$15584.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96743$lut$aiger96742$15600.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$96743$lut$aiger96742$15607.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$15623.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$15636.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96743$lut$aiger96742$15652.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96743$lut$aiger96742$15687.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$15753.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$15829.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$15845.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$15876.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$15886.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$15906.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96743$lut$aiger96742$15928.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$15945.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$15961.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$15974.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96743$lut$aiger96742$15990.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96743$lut$aiger96742$16007.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$96743$lut$aiger96742$16023.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$16092.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$16157.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$16178.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96743$lut$aiger96742$16187.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$16200.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96743$lut$aiger96742$16223.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$16236.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96743$lut$aiger96742$16258.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$16274.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$16285.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$96743$lut$aiger96742$16298.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$16372.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$16385.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$16395.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$16402.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$16415.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96743$lut$aiger96742$16438.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$16451.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96743$lut$aiger96742$16473.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$16489.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$16500.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$96743$lut$aiger96742$16528.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$16544.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$16590.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$16606.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$16669.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$16685.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$16715.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$16728.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96743$lut$aiger96742$16744.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96743$lut$aiger96742$16766.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$16777.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$96743$lut$aiger96742$16789.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$16805.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$16821.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$16834.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96743$lut$aiger96742$16859.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$16925.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$16987.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$16994.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96743$lut$aiger96742$17020.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$17033.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96743$lut$aiger96742$17061.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$17093.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$17106.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96743$lut$aiger96742$17151.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$17167.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$17197.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$17260.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$17323.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96743$lut$aiger96742$17361.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$17374.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96743$lut$aiger96742$17393.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96743$lut$aiger96742$17409.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96743$lut$aiger96742$17434.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$17446.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96743$lut$aiger96742$17491.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$17507.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$17549.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$17581.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$17594.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96743$lut$aiger96742$17613.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96743$lut$aiger96742$17635.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$17648.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96743$lut$aiger96742$17669.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$17691.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$17819.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96743$lut$aiger96742$17841.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$17857.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$17870.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96743$lut$aiger96742$17895.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$17911.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$17924.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96743$lut$aiger96742$17945.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$17969.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$18032.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$18099.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96743$lut$aiger96742$18121.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$18137.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$18150.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96743$lut$aiger96742$18175.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$18191.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$18204.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96743$lut$aiger96742$18225.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$18247.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$18314.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$18330.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$18343.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96743$lut$aiger96742$18359.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96743$lut$aiger96742$18376.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$96743$lut$aiger96742$18382.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96743$lut$aiger96742$18420.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$18433.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96743$lut$aiger96742$18477.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$18493.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$18506.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$18513.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$5935.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$6203.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$6219.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$6252.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$6331.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$6347.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$6377.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$6456.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$6472.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$10003.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$6605.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$6670.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$6759.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$6769.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96929.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $abc$96743$lut$aiger96742$6769.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$6793.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$6793.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$6831.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$6859.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$6859.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$6881.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$6885.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96743$lut$aiger96742$6893.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96743$lut$aiger96742$6909.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$6909.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96925.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $abc$96743$lut$aiger96742$6930.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$6930.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96920.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $abc$96743$lut$aiger96742$6951.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$6951.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$6971.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96921.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $abc$96743$lut$aiger96742$7005.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$7005.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96944.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $abc$96743$lut$aiger96742$7027.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96940.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $abc$96743$lut$aiger96742$7048.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$7069.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96932.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $abc$96743$lut$aiger96742$7092.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$7115.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$7160.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$7160.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$7181.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$7181.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$7202.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$7202.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$7234.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$7234.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$7255.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$7255.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$7276.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$7300.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$7300.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$7320.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$7320.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$7341.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$7341.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$7359.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$7373.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96743$lut$aiger96742$7377.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$7388.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96955.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$7388.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96956.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $abc$96743$lut$aiger96742$7457.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$7483.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$7490.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$7509.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$7513.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96743$lut$aiger96742$7519.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$96743$lut$aiger96742$7483.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$7540.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96946.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $abc$96743$lut$aiger96742$7931.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$7577.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$7577.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$7616.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$7650.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96923.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
Optimizing lut $abc$96743$lut$aiger96742$7687.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$7768.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$7810.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$7845.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$8183.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$7891.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$7901.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$7911.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$7921.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$7931.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$7921.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$7509.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$7968.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$7978.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$7990.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$7990.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$8005.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96743$lut$aiger96742$8018.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$8023.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$8033.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$8043.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$8049.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$8060.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$8070.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$8080.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$8090.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$8108.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$8118.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$8128.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$8138.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$8170.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$96743$lut$aiger96742$8183.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$8190.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$8194.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$8201.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$8208.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$8218.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$8232.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$8242.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$8270.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$8280.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$8290.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$8310.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$8320.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$8329.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$8344.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$8354.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$8365.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96743$lut$aiger96742$8373.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$96743$lut$aiger96742$8388.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$8398.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$8414.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$96743$lut$aiger96742$8423.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$96743$lut$aiger96742$8429.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$96743$lut$aiger96742$8435.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$8442.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$8452.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$8462.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$8472.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$8489.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$8501.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$8511.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$8531.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$96743$lut$aiger96742$8542.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$8552.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$8594.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$96743$lut$aiger96742$8606.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$8606.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$8632.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$8647.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96743$lut$aiger96742$8655.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$96743$lut$aiger96742$8662.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$8676.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$8694.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96743$lut$aiger96742$8702.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$96743$lut$aiger96742$8720.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96743$lut$aiger96742$8489.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$8751.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$8775.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$96743$lut$aiger96742$8784.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$96743$lut$aiger96742$8790.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$96743$lut$aiger96742$8799.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$8807.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$96743$lut$aiger96742$8816.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$96743$lut$aiger96742$8816.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$8462.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$8842.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$8852.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$8862.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$8882.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96743$lut$aiger96742$8890.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$8900.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$8910.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$8920.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$8957.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$96743$lut$aiger96742$8398.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$9027.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96743$lut$aiger96742$9035.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$96743$lut$aiger96742$9044.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$96743$lut$aiger96742$9057.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$9087.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$96743$lut$aiger96742$9006.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$9110.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$9133.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$9159.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$96743$lut$aiger96742$9168.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$96743$lut$aiger96742$9174.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$9180.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96743$lut$aiger96742$9194.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$9200.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96743$lut$aiger96742$9223.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$9231.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$8388.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$9265.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96743$lut$aiger96742$9274.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96743$lut$aiger96742$9281.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$96743$lut$aiger96742$9285.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$9329.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$9341.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$9347.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96743$lut$aiger96742$9355.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$96743$lut$aiger96742$9363.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$9388.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$9399.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$9406.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$8472.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$9445.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$9487.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96743$lut$aiger96742$9498.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$9504.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$9510.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96743$lut$aiger96742$9518.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$96743$lut$aiger96742$9527.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$9542.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$9552.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$9558.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96743$lut$aiger96742$9566.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$96743$lut$aiger96742$9575.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$9624.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96743$lut$aiger96742$9637.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$9532.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$9653.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$9658.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$9664.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$9673.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96743$lut$aiger96742$9705.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$9728.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96743$lut$aiger96742$9760.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$9778.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96743$lut$aiger96742$9792.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$96743$lut$aiger96742$9829.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96743$lut$aiger96742$9837.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$96743$lut$aiger96742$9849.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$9870.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$9952.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$9985.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$15669.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96753.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96749.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96748.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96746.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96748.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96759.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$9194.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$9174.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96799.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96813.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$96743$lut$aiger96742$8190.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96818.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96743$lut$aiger96742$9363.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$9341.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$96743$lut$aiger96742$9504.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96889.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96746.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96896.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96897.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96900.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96904.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96905.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96743$lut$aiger96742$7901.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96908.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96909.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96912.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
Optimizing lut $abc$96743$lut$aiger96742$7911.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96916.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96937.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96941.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96945.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96946.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96947.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Removed 0 unused cells and 11004 unused wires.
21.45. Executing AUTONAME pass.
Renamed 385185 objects in module top (277 iterations).
<suppressed ~13757 debug messages>
21.46. Executing HIERARCHY pass (managing design hierarchy).
21.46.1. Analyzing design hierarchy..
Top module: \top
21.46.2. Analyzing design hierarchy..
Top module: \top
Removed 0 unused modules.
21.47. Printing statistics.
=== top ===
Number of wires: 5730
Number of wire bits: 15992
Number of public wires: 5730
Number of public wire bits: 15992
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 8730
$_TBUF_ 5
CCU2C 165
L6MUX21 407
LUT4 5287
PFUMX 1052
TRELLIS_DPR16X4 512
TRELLIS_FF 1302
21.48. Executing CHECK pass (checking for obvious problems).
Checking module top...
Found and reported 0 problems.
21.49. Executing JSON backend.
Warnings: 258 unique messages, 259 total
End of script. Logfile hash: 40fbb01a00, CPU: user 8.61s system 0.11s, MEM: 221.86 MB peak
Yosys 0.36+8 (git sha1 fb4cbfa73, clang 10.0.0-4ubuntu1 -fPIC -Os)
Time spent: 41% 1x abc9_exe (6 sec), 12% 11x techmap (1 sec), ...
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (NextPNR)
[Pipeline] sh
+ /eda/oss-cad-suite/bin/nextpnr-ecp5 --json ./build/out.json --write ./build/out_pnr.json --45k --lpf Risco-5/fpga/ecp5/pinout.lpf --textcfg ./build/out.config --package CABGA381 --speed 6 --ignore-loops --lpf-allow-unconstrained
Info: constraining clock net 'clk' to 25.00 MHz
Warning: IO 'gpios[4]' is unconstrained in LPF and will be automatically placed
Warning: IO 'gpios[3]' is unconstrained in LPF and will be automatically placed
Warning: IO 'gpios[2]' is unconstrained in LPF and will be automatically placed
Warning: IO 'gpios[1]' is unconstrained in LPF and will be automatically placed
Warning: IO 'gpios[0]' is unconstrained in LPF and will be automatically placed
Info: Logic utilisation before packing:
Info: Total LUT4s: 8689/43848 19%
Info: logic LUTs: 5287/43848 12%
Info: carry LUTs: 330/43848 0%
Info: RAM LUTs: 2048/ 5481 37%
Info: RAMW LUTs: 1024/10962 9%
Info: Total DFFs: 1302/43848 2%
Info: Packing IOs..
Info: $gpios[4]$iobuf_i: gpios_$_TBUF__Y.Y
Info: $gpios[3]$iobuf_i: gpios_$_TBUF__Y_1.Y
Info: $gpios[2]$iobuf_i: gpios_$_TBUF__Y_2.Y
Info: $gpios[1]$iobuf_i: gpios_$_TBUF__Y_3.Y
Info: $gpios[0]$iobuf_i: gpios_$_TBUF__Y_4.Y
Info: pin 'tx$tr_io' constrained to Bel 'X90/Y20/PIOC'.
Info: pin 'rx$tr_io' constrained to Bel 'X90/Y20/PIOA'.
Info: pin 'reset$tr_io' constrained to Bel 'X0/Y29/PIOA'.
Info: pin 'led[7]$tr_io' constrained to Bel 'X90/Y20/PIOD'.
Info: pin 'led[6]$tr_io' constrained to Bel 'X0/Y44/PIOD'.
Info: pin 'led[5]$tr_io' constrained to Bel 'X0/Y59/PIOA'.
Info: pin 'led[4]$tr_io' constrained to Bel 'X15/Y71/PIOB'.
Info: pin 'led[3]$tr_io' constrained to Bel 'X90/Y29/PIOC'.
Info: pin 'led[2]$tr_io' constrained to Bel 'X90/Y44/PIOB'.
Info: pin 'led[1]$tr_io' constrained to Bel 'X0/Y44/PIOC'.
Info: pin 'led[0]$tr_io' constrained to Bel 'X0/Y59/PIOC'.
Info: pin 'clk$tr_io' constrained to Bel 'X0/Y68/PIOC'.
Info: Packing constants..
Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info: 298 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info: Promoting globals...
Info: promoting clock net clk_o to global network
Info: promoting clock net clk$TRELLIS_IO_IN to global network
Info: Checksum: 0xcf017e8b
Info: Device utilisation:
Info: TRELLIS_IO: 17/ 245 6%
Info: DCCA: 2/ 56 3%
Info: DP16KD: 0/ 108 0%
Info: MULT18X18D: 0/ 72 0%
Info: ALU54B: 0/ 36 0%
Info: EHXPLLL: 0/ 4 0%
Info: EXTREFB: 0/ 2 0%
Info: DCUA: 0/ 2 0%
Info: PCSCLKDIV: 0/ 2 0%
Info: IOLOGIC: 0/ 160 0%
Info: SIOLOGIC: 0/ 85 0%
Info: GSR: 0/ 1 0%
Info: JTAGG: 0/ 1 0%
Info: OSCG: 0/ 1 0%
Info: SEDGA: 0/ 1 0%
Info: DTR: 0/ 1 0%
Info: USRMCLK: 0/ 1 0%
Info: CLKDIVF: 0/ 4 0%
Info: ECLKSYNCB: 0/ 10 0%
Info: DLLDELD: 0/ 8 0%
Info: DDRDLL: 0/ 4 0%
Info: DQSBUFM: 0/ 10 0%
Info: TRELLIS_ECLKBUF: 0/ 8 0%
Info: ECLKBRIDGECS: 0/ 2 0%
Info: DCSC: 0/ 2 0%
Info: TRELLIS_FF: 1302/43848 2%
Info: TRELLIS_COMB: 8752/43848 19%
Info: TRELLIS_RAMW: 512/ 5481 9%
Info: Placed 12 cells based on constraints.
Info: Creating initial analytic placement for 5365 cells, random placement wirelen = 447552.
Info: at initial placer iter 0, wirelen = 2449
Info: at initial placer iter 1, wirelen = 2489
Info: at initial placer iter 2, wirelen = 1965
Info: at initial placer iter 3, wirelen = 2357
Info: Running main analytical placer, max placement attempts per cell = 14005278.
Info: at iteration #1, type ALL: wirelen solved = 2085, spread = 65436, legal = 66229; time = 0.26s
Info: at iteration #2, type ALL: wirelen solved = 6997, spread = 44414, legal = 45567; time = 0.26s
Info: at iteration #3, type ALL: wirelen solved = 11712, spread = 42262, legal = 43587; time = 0.26s
Info: at iteration #4, type ALL: wirelen solved = 15117, spread = 44584, legal = 45425; time = 0.25s
Info: at iteration #5, type ALL: wirelen solved = 18077, spread = 42326, legal = 43150; time = 0.25s
Info: at iteration #6, type ALL: wirelen solved = 19030, spread = 42412, legal = 43555; time = 0.24s
Info: at iteration #7, type ALL: wirelen solved = 20185, spread = 37819, legal = 39424; time = 0.24s
Info: at iteration #8, type ALL: wirelen solved = 20032, spread = 39799, legal = 40749; time = 0.24s
Info: at iteration #9, type ALL: wirelen solved = 21754, spread = 38085, legal = 39166; time = 0.24s
Info: at iteration #10, type ALL: wirelen solved = 22415, spread = 37200, legal = 38295; time = 0.24s
Info: at iteration #11, type ALL: wirelen solved = 22642, spread = 39189, legal = 39958; time = 0.24s
Info: at iteration #12, type ALL: wirelen solved = 23578, spread = 36552, legal = 37644; time = 0.24s
Info: at iteration #13, type ALL: wirelen solved = 22758, spread = 36817, legal = 37906; time = 0.23s
Info: at iteration #14, type ALL: wirelen solved = 23153, spread = 36896, legal = 37959; time = 0.24s
Info: at iteration #15, type ALL: wirelen solved = 23882, spread = 37013, legal = 38017; time = 0.26s
Info: at iteration #16, type ALL: wirelen solved = 25264, spread = 36423, legal = 37389; time = 0.23s
Info: at iteration #17, type ALL: wirelen solved = 25419, spread = 36286, legal = 37407; time = 0.23s
Info: at iteration #18, type ALL: wirelen solved = 25159, spread = 35327, legal = 36588; time = 0.23s
Info: at iteration #19, type ALL: wirelen solved = 24823, spread = 35816, legal = 36688; time = 0.23s
Info: at iteration #20, type ALL: wirelen solved = 25525, spread = 34377, legal = 35616; time = 0.23s
Info: at iteration #21, type ALL: wirelen solved = 24876, spread = 35098, legal = 36287; time = 0.23s
Info: at iteration #22, type ALL: wirelen solved = 25421, spread = 36401, legal = 37399; time = 0.23s
Info: at iteration #23, type ALL: wirelen solved = 26180, spread = 35377, legal = 36482; time = 0.23s
Info: at iteration #24, type ALL: wirelen solved = 25922, spread = 35438, legal = 36616; time = 0.23s
Info: at iteration #25, type ALL: wirelen solved = 25764, spread = 34857, legal = 36085; time = 0.23s
Info: HeAP Placer Time: 9.28s
Info: of which solving equations: 5.44s
Info: of which spreading cells: 0.83s
Info: of which strict legalisation: 0.25s
Info: Running simulated annealing placer for refinement.
Info: at iteration #1: temp = 0.000000, timing cost = 9119, wirelen = 35616
Info: at iteration #5: temp = 0.000000, timing cost = 12729, wirelen = 31186
Info: at iteration #10: temp = 0.000000, timing cost = 13901, wirelen = 29881
Info: at iteration #15: temp = 0.000000, timing cost = 12787, wirelen = 29374
Info: at iteration #20: temp = 0.000000, timing cost = 13004, wirelen = 29157
Info: at iteration #24: temp = 0.000000, timing cost = 12985, wirelen = 29058
Info: SA placement time 22.75s
Info: Max frequency for clock '$glbnet$clk_o': 29.56 MHz (PASS at 12.00 MHz)
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 146.33 MHz (PASS at 25.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 6.90 ns
Info: Max delay <async> -> posedge $glbnet$clk_o : 13.72 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 15.64 ns
Info: Max delay posedge $glbnet$clk_o -> <async> : 12.16 ns
Info: Slack histogram:
Info: legend: * represents 105 endpoint(s)
Info: + represents [1,105) endpoint(s)
Info: [ 33166, 35637) |+
Info: [ 35637, 38108) |+
Info: [ 38108, 40579) |+
Info: [ 40579, 43050) |
Info: [ 43050, 45521) |
Info: [ 45521, 47992) |
Info: [ 47992, 50463) |+
Info: [ 50463, 52934) |+
Info: [ 52934, 55405) |+
Info: [ 55405, 57876) |*****+
Info: [ 57876, 60347) |*************+
Info: [ 60347, 62818) |************************************************************
Info: [ 62818, 65289) |************************************+
Info: [ 65289, 67760) |***+
Info: [ 67760, 70231) |*+
Info: [ 70231, 72702) |******+
Info: [ 72702, 75173) |****+
Info: [ 75173, 77644) |********+
Info: [ 77644, 80115) |*+
Info: [ 80115, 82586) |+
Info: Checksum: 0xff348508
Info: Routing globals...
Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
Info: routing clock net $glbnet$clk_o using global 1
Info: Routing..
Info: Setting up routing queue.
Info: Routing 42482 arcs.
Info: | (re-)routed arcs | delta | remaining| time spent |
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
Info: 1000 | 283 716 | 283 716 | 41934| 0.74 0.74|
Info: 2000 | 456 1543 | 173 827 | 41548| 0.16 0.91|
Info: 3000 | 644 2355 | 188 812 | 41142| 0.17 1.08|
Info: 4000 | 819 3180 | 175 825 | 40748| 0.16 1.24|
Info: 5000 | 1037 3962 | 218 782 | 40280| 0.16 1.40|
Info: 6000 | 1174 4825 | 137 863 | 40023| 0.15 1.55|
Info: 7000 | 1348 5651 | 174 826 | 39601| 0.17 1.73|
Info: 8000 | 1515 6484 | 167 833 | 39238| 0.19 1.91|
Info: 9000 | 1696 7303 | 181 819 | 39405| 0.19 2.10|
Info: 10000 | 1810 8189 | 114 886 | 39182| 0.18 2.28|
Info: 11000 | 1891 9108 | 81 919 | 39382| 0.19 2.46|
Info: 12000 | 2023 9976 | 132 868 | 39726| 0.18 2.64|
Info: 13000 | 2177 10822 | 154 846 | 39397| 0.18 2.81|
Info: 14000 | 2282 11717 | 105 895 | 39390| 0.17 2.99|
Info: 15000 | 2452 12547 | 170 830 | 38978| 0.19 3.18|
Info: 16000 | 2659 13340 | 207 793 | 38642| 0.17 3.35|
Info: 17000 | 2865 14134 | 206 794 | 38516| 0.17 3.52|
Info: 18000 | 3016 14983 | 151 849 | 38739| 0.16 3.68|
Info: 19000 | 3171 15828 | 155 845 | 38597| 0.16 3.84|
Info: 20000 | 3265 16734 | 94 906 | 38376| 0.16 4.00|
Info: 21000 | 3432 17567 | 167 833 | 38083| 0.17 4.17|
Info: 22000 | 3582 18417 | 150 850 | 37975| 0.16 4.33|
Info: 23000 | 3759 19240 | 177 823 | 37442| 0.18 4.50|
Info: 24000 | 3849 20150 | 90 910 | 38326| 0.18 4.68|
Info: 25000 | 3915 21084 | 66 934 | 38265| 0.17 4.85|
Info: 26000 | 4064 21935 | 149 851 | 38229| 0.18 5.04|
Info: 27000 | 4169 22830 | 105 895 | 37514| 0.17 5.21|
Info: 28000 | 4351 23648 | 182 818 | 37025| 0.18 5.38|
Info: 29000 | 4545 24454 | 194 806 | 36453| 0.19 5.57|
Info: 30000 | 4707 25292 | 162 838 | 36662| 0.19 5.76|
Info: 31000 | 4882 26117 | 175 825 | 36259| 0.18 5.93|
Info: 32000 | 5103 26896 | 221 779 | 35843| 0.18 6.11|
Info: 33000 | 5262 27737 | 159 841 | 35700| 0.18 6.29|
Info: 34000 | 5442 28557 | 180 820 | 35339| 0.17 6.45|
Info: 35000 | 5637 29362 | 195 805 | 35173| 0.20 6.66|
Info: 36000 | 5837 30162 | 200 800 | 35158| 0.20 6.85|
Info: 37000 | 6021 30978 | 184 816 | 34834| 0.20 7.06|
Info: 38000 | 6204 31795 | 183 817 | 34904| 0.18 7.24|
Info: 39000 | 6352 32647 | 148 852 | 34781| 0.18 7.43|
Info: 40000 | 6555 33444 | 203 797 | 34415| 0.18 7.61|
Info: 41000 | 6778 34221 | 223 777 | 34038| 0.19 7.80|
Info: 42000 | 6981 35018 | 203 797 | 33364| 0.18 7.98|
Info: 43000 | 7187 35812 | 206 794 | 32895| 0.17 8.15|
Info: 44000 | 7445 36554 | 258 742 | 32484| 0.21 8.36|
Info: 45000 | 7684 37315 | 239 761 | 32217| 0.20 8.56|
Info: 46000 | 7958 38041 | 274 726 | 31920| 0.19 8.75|
Info: 47000 | 8178 38821 | 220 780 | 31386| 0.21 8.95|
Info: 48000 | 8359 39640 | 181 819 | 31247| 0.19 9.14|
Info: 49000 | 8586 40413 | 227 773 | 31065| 0.20 9.34|
Info: 50000 | 8810 41189 | 224 776 | 30590| 0.19 9.53|
Info: 51000 | 9045 41954 | 235 765 | 30178| 0.19 9.72|
Info: 52000 | 9259 42740 | 214 786 | 29845| 0.20 9.92|
Info: 53000 | 9473 43526 | 214 786 | 29474| 0.20 10.12|
Info: 54000 | 9749 44250 | 276 724 | 29054| 0.22 10.34|
Info: 55000 | 9968 45031 | 219 781 | 28775| 0.21 10.55|
Info: 56000 | 10194 45805 | 226 774 | 28507| 0.22 10.77|
Info: 57000 | 10509 46490 | 315 685 | 28318| 0.22 10.99|
Info: 58000 | 10762 47237 | 253 747 | 27919| 0.20 11.19|
Info: 59000 | 11007 47992 | 245 755 | 27818| 0.22 11.41|
Info: 60000 | 11296 48703 | 289 711 | 27739| 0.22 11.63|
Info: 61000 | 11471 49528 | 175 825 | 27292| 0.21 11.84|
Info: 62000 | 11702 50297 | 231 769 | 26965| 0.25 12.08|
Info: 63000 | 11990 51009 | 288 712 | 26488| 0.22 12.30|
Info: 64000 | 12219 51780 | 229 771 | 26180| 0.22 12.52|
Info: 65000 | 12523 52476 | 304 696 | 25830| 0.24 12.76|
Info: 66000 | 12861 53138 | 338 662 | 25519| 0.26 13.02|
Info: 67000 | 13172 53827 | 311 689 | 25093| 0.24 13.26|
Info: 68000 | 13489 54510 | 317 683 | 24701| 0.22 13.48|
Info: 69000 | 13787 55212 | 298 702 | 24250| 0.22 13.70|
Info: 70000 | 14063 55936 | 276 724 | 24232| 0.19 13.89|
Info: 71000 | 14355 56644 | 292 708 | 23898| 0.26 14.15|
Info: 72000 | 14643 57356 | 288 712 | 23753| 0.25 14.40|
Info: 73000 | 14943 58056 | 300 700 | 23427| 0.27 14.67|
Info: 74000 | 15349 58650 | 406 594 | 23191| 0.31 14.98|
Info: 75000 | 15544 59455 | 195 805 | 23864| 0.22 15.20|
Info: 76000 | 15620 60379 | 76 924 | 23206| 0.18 15.37|
Info: 77000 | 15988 61011 | 368 632 | 22946| 0.25 15.62|
Info: 78000 | 16309 61690 | 321 679 | 22621| 0.23 15.85|
Info: 79000 | 16594 62405 | 285 715 | 22297| 0.24 16.09|
Info: 80000 | 16908 63091 | 314 686 | 22197| 0.23 16.33|
Info: 81000 | 17238 63761 | 330 670 | 21835| 0.23 16.56|
Info: 82000 | 17571 64428 | 333 667 | 21559| 0.24 16.79|
Info: 83000 | 17895 65104 | 324 676 | 21404| 0.25 17.04|
Info: 84000 | 18206 65793 | 311 689 | 21667| 0.23 17.27|
Info: 85000 | 18492 66507 | 286 714 | 21088| 0.25 17.52|
Info: 86000 | 18842 67157 | 350 650 | 21286| 0.23 17.74|
Info: 87000 | 19050 67949 | 208 792 | 21611| 0.24 17.98|
Info: 88000 | 19191 68808 | 141 859 | 21233| 0.21 18.19|
Info: 89000 | 19498 69501 | 307 693 | 20919| 0.26 18.45|
Info: 90000 | 19822 70177 | 324 676 | 20758| 0.24 18.69|
Info: 91000 | 20174 70825 | 352 648 | 20476| 0.26 18.95|
Info: 92000 | 20521 71478 | 347 653 | 20316| 0.29 19.23|
Info: 93000 | 20923 72076 | 402 598 | 20231| 0.25 19.48|
Info: 94000 | 21212 72787 | 289 711 | 20067| 0.25 19.74|
Info: 95000 | 21618 73381 | 406 594 | 19851| 0.27 20.01|
Info: 96000 | 22036 73963 | 418 582 | 19642| 0.24 20.24|
Info: 97000 | 22489 74510 | 453 547 | 19325| 0.26 20.50|
Info: 98000 | 22984 75015 | 495 505 | 19110| 0.25 20.75|
Info: 99000 | 23335 75664 | 351 649 | 19019| 0.25 21.00|
Info: 100000 | 23812 76187 | 477 523 | 18830| 0.26 21.27|
Info: 101000 | 24235 76764 | 423 577 | 18669| 0.27 21.54|
Info: 102000 | 24548 77451 | 313 687 | 18591| 0.24 21.78|
Info: 103000 | 24773 78226 | 225 775 | 18511| 0.22 22.00|
Info: 104000 | 25203 78796 | 430 570 | 18271| 0.27 22.27|
Info: 105000 | 25621 79378 | 418 582 | 17969| 0.27 22.54|
Info: 106000 | 26174 79825 | 553 447 | 17741| 0.27 22.81|
Info: 107000 | 26581 80418 | 407 593 | 17609| 0.25 23.06|
Info: 108000 | 27162 80837 | 581 419 | 17411| 0.25 23.31|
Info: 109000 | 27737 81262 | 575 425 | 17271| 0.27 23.58|
Info: 110000 | 28356 81643 | 619 381 | 17071| 0.26 23.84|
Info: 111000 | 29016 81983 | 660 340 | 16846| 0.25 24.09|
Info: 112000 | 29584 82415 | 568 432 | 16627| 0.28 24.37|
Info: 113000 | 30180 82819 | 596 404 | 16491| 0.26 24.63|
Info: 114000 | 30766 83233 | 586 414 | 16416| 0.26 24.89|
Info: 115000 | 31197 83802 | 431 569 | 16335| 0.28 25.17|
Info: 116000 | 31592 84407 | 395 605 | 16176| 0.25 25.42|
Info: 117000 | 31979 85020 | 387 613 | 16203| 0.27 25.69|
Info: 118000 | 32379 85620 | 400 600 | 16017| 0.28 25.96|
Info: 119000 | 32833 86166 | 454 546 | 16036| 0.26 26.22|
Info: 120000 | 33256 86743 | 423 577 | 15842| 0.30 26.52|
Info: 121000 | 33824 87175 | 568 432 | 15624| 0.26 26.78|
Info: 122000 | 34335 87664 | 511 489 | 15432| 0.26 27.05|
Info: 123000 | 34778 88197 | 443 533 | 15238| 0.29 27.34|
Info: 124000 | 35134 88824 | 356 627 | 16642| 0.26 27.60|
Info: 125000 | 35218 89740 | 84 916 | 15818| 0.21 27.81|
Info: 126000 | 35379 90579 | 161 839 | 15272| 0.23 28.04|
Info: 127000 | 35666 91292 | 287 713 | 16341| 0.27 28.31|
Info: 128000 | 35837 92121 | 171 829 | 15812| 0.24 28.55|
Info: 129000 | 36048 92910 | 211 789 | 15156| 0.24 28.79|
Info: 130000 | 36618 93282 | 570 372 | 14893| 0.24 29.03|
Info: 131000 | 37210 93658 | 592 376 | 14788| 0.28 29.31|
Info: 132000 | 37467 94365 | 257 707 | 14828| 0.29 29.61|
Info: 133000 | 37905 94909 | 438 544 | 14449| 0.26 29.86|
Info: 134000 | 38507 95238 | 602 329 | 14173| 0.24 30.11|
Info: 135000 | 39111 95572 | 604 334 | 13894| 0.26 30.37|
Info: 136000 | 39761 95861 | 650 289 | 13631| 0.25 30.62|
Info: 137000 | 40343 96248 | 582 387 | 13456| 0.31 30.93|
Info: 138000 | 40860 96677 | 517 429 | 13195| 0.28 31.21|
Info: 139000 | 41371 97102 | 511 425 | 12883| 0.28 31.49|
Info: 140000 | 41814 97617 | 443 515 | 12652| 0.26 31.74|
Info: 141000 | 42307 98067 | 493 450 | 12303| 0.31 32.06|
Info: 142000 | 42655 98633 | 348 566 | 11824| 0.21 32.27|
Info: 143000 | 42928 99255 | 273 622 | 11174| 0.21 32.47|
Info: 144000 | 43048 100119 | 120 864 | 10303| 0.13 32.60|
Info: 145000 | 43160 100997 | 112 878 | 9460| 0.14 32.74|
Info: 146000 | 43250 101904 | 90 907 | 8614| 0.17 32.91|
Info: 147000 | 43291 102859 | 41 955 | 7659| 0.09 33.00|
Info: 148000 | 43427 103718 | 136 859 | 6951| 0.18 33.18|
Info: 149000 | 43702 104442 | 275 724 | 6606| 0.30 33.48|
Info: 150000 | 44086 105058 | 384 616 | 6564| 0.30 33.77|
Info: 151000 | 44392 105752 | 306 694 | 6112| 0.25 34.02|
Info: 152000 | 44517 106621 | 125 869 | 5288| 0.17 34.19|
Info: 153000 | 44654 107461 | 137 840 | 4444| 0.15 34.34|
Info: 154000 | 44919 108191 | 265 730 | 3874| 0.25 34.59|
Info: 155000 | 45349 108761 | 430 570 | 3860| 0.38 34.97|
Info: 156000 | 45712 109394 | 363 633 | 3433| 0.35 35.32|
Info: 157000 | 46147 109940 | 435 546 | 3098| 0.35 35.66|
Info: 158000 | 46601 110481 | 454 541 | 3004| 0.43 36.10|
Info: 159000 | 46981 111097 | 380 616 | 2613| 0.29 36.39|
Info: 160000 | 47437 111638 | 456 541 | 2207| 0.29 36.68|
Info: 161000 | 47927 112140 | 490 502 | 1977| 0.41 37.09|
Info: 162000 | 48362 112705 | 435 565 | 1846| 0.47 37.56|
Info: 163000 | 48808 113255 | 446 550 | 1461| 0.34 37.90|
Info: 164000 | 49287 113776 | 479 521 | 1203| 0.41 38.30|
Info: 165000 | 49758 114304 | 471 528 | 871| 0.37 38.68|
Info: 166000 | 50299 114754 | 541 450 | 617| 0.37 39.05|
Info: 167000 | 50632 115200 | 333 446 | 156| 0.26 39.31|
Info: 167272 | 50710 115317 | 78 117 | 0| 0.16 39.47|
Info: Routing complete.
Info: Router1 time 39.47s
Info: Checksum: 0xb137b3bd
Info: Critical path report for clock '$glbnet$clk_o' (posedge -> posedge):
Info: curr total
Info: 0.5 0.5 Source SOC.Core.Control_Unit.state_TRELLIS_FF_Q_1.Q
Info: 1.5 2.0 Net SOC.Core.Control_Unit.nextstate_LUT4_Z_2_B_LUT4_Z_A[0] (33,26) -> (34,18)
Info: Sink SOC.Memory.address_LUT4_Z_C_LUT4_Z_D_LUT4_Z.B
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:42.3-49.2
Info: Risco-5/src/core/core.v:97.14-113.2
Info: Risco-5/src/core/control_unit.v:46.11-46.16
Info: Risco-5/src/peripheral/soc.v:28.3-36.2
Info: 0.2 2.3 Source SOC.Memory.address_LUT4_Z_C_LUT4_Z_D_LUT4_Z.F
Info: 1.4 3.7 Net SOC.Memory.address_LUT4_Z_C_LUT4_Z_D[2] (34,18) -> (28,5)
Info: Sink SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 4.0 Source SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_LUT4_Z.F
Info: 1.5 5.4 Net SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0 (28,5) -> (31,8)
Info: Sink SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.B
Info: 0.4 5.9 Source SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info: 0.0 5.9 Net SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (31,8) -> (31,8)
Info: Sink SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info: 0.0 5.9 Source SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info: 0.0 5.9 Net SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_COUT (31,8) -> (31,8)
Info: Sink SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:42.3-49.2
Info: Risco-5/src/peripheral/bus.v:54.5-54.37
Info: Risco-5/src/peripheral/soc.v:51.5-81.2
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 5.9 Source SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info: 0.0 5.9 Net SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (31,8) -> (31,8)
Info: Sink SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info: 0.0 5.9 Source SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info: 0.0 5.9 Net SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_COUT (31,8) -> (31,8)
Info: Sink SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:42.3-49.2
Info: Risco-5/src/peripheral/bus.v:54.5-54.37
Info: Risco-5/src/peripheral/soc.v:51.5-81.2
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 6.0 Source SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info: 0.0 6.0 Net SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (31,8) -> (31,8)
Info: Sink SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info: 0.0 6.0 Source SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info: 0.0 6.0 Net SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_COUT (31,8) -> (32,8)
Info: Sink SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:42.3-49.2
Info: Risco-5/src/peripheral/bus.v:54.5-54.37
Info: Risco-5/src/peripheral/soc.v:51.5-81.2
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 6.1 Source SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info: 0.0 6.1 Net SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (32,8) -> (32,8)
Info: Sink SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info: 0.0 6.1 Source SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info: 0.0 6.1 Net SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_COUT (32,8) -> (32,8)
Info: Sink SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:42.3-49.2
Info: Risco-5/src/peripheral/bus.v:54.5-54.37
Info: Risco-5/src/peripheral/soc.v:51.5-81.2
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 6.2 Source SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info: 0.0 6.2 Net SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (32,8) -> (32,8)
Info: Sink SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info: 0.0 6.2 Source SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info: 0.0 6.2 Net SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_COUT (32,8) -> (32,8)
Info: Sink SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:42.3-49.2
Info: Risco-5/src/peripheral/bus.v:54.5-54.37
Info: Risco-5/src/peripheral/soc.v:51.5-81.2
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 6.2 Source SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info: 0.0 6.2 Net SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (32,8) -> (32,8)
Info: Sink SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info: 0.0 6.2 Source SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info: 0.0 6.2 Net SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_COUT (32,8) -> (32,8)
Info: Sink SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:42.3-49.2
Info: Risco-5/src/peripheral/bus.v:54.5-54.37
Info: Risco-5/src/peripheral/soc.v:51.5-81.2
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 6.3 Source SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info: 0.0 6.3 Net SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (32,8) -> (32,8)
Info: Sink SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info: 0.0 6.3 Source SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info: 0.0 6.3 Net SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_COUT (32,8) -> (33,8)
Info: Sink SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:42.3-49.2
Info: Risco-5/src/peripheral/bus.v:54.5-54.37
Info: Risco-5/src/peripheral/soc.v:51.5-81.2
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 6.4 Source SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info: 0.0 6.4 Net SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (33,8) -> (33,8)
Info: Sink SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info: 0.0 6.4 Source SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info: 0.0 6.4 Net SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_COUT (33,8) -> (33,8)
Info: Sink SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:42.3-49.2
Info: Risco-5/src/peripheral/bus.v:54.5-54.37
Info: Risco-5/src/peripheral/soc.v:51.5-81.2
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 6.4 Source SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info: 0.0 6.4 Net SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (33,8) -> (33,8)
Info: Sink SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info: 0.0 6.4 Source SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info: 0.0 6.4 Net SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_COUT (33,8) -> (33,8)
Info: Sink SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:42.3-49.2
Info: Risco-5/src/peripheral/bus.v:54.5-54.37
Info: Risco-5/src/peripheral/soc.v:51.5-81.2
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 6.5 Source SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info: 0.0 6.5 Net SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (33,8) -> (33,8)
Info: Sink SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info: 0.0 6.5 Source SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info: 0.0 6.5 Net $nextpnr_CCU2C_1$CIN (33,8) -> (33,8)
Info: Sink $nextpnr_CCU2C_1$CCU2_COMB0.FCI
Info: 0.4 7.0 Source $nextpnr_CCU2C_1$CCU2_COMB0.F
Info: 2.9 9.9 Net SOC.Memory.address_LUT4_Z_1_C[1] (33,8) -> (11,29)
Info: Sink SOC.Memory.address_LUT4_Z_1.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 10.1 Source SOC.Memory.address_LUT4_Z_1.F
Info: 2.1 12.2 Net SOC.slave_address[4] (11,29) -> (13,40)
Info: Sink SOC.Memory.memory.0.216$DPRAM_COMB1.C
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:42.3-49.2
Info: Risco-5/src/peripheral/soc.v:21.5-21.18
Info: 0.2 12.5 Source SOC.Memory.memory.0.216$DPRAM_COMB1.F
Info: 0.9 13.4 Net SOC.Memory.memory.0.216_DO_2[3] (13,40) -> (13,38)
Info: Sink SOC.Memory.memory.0.208_DO_1_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 13.6 Source SOC.Memory.memory.0.208_DO_1_LUT4_Z.F
Info: 0.7 14.4 Net SOC.Memory.memory.0.208_DO_1[4] (13,38) -> (13,37)
Info: Sink SOC.Memory.memory.0.200_DO_2_LUT4_C_Z_PFUMX_Z_BLUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 14.6 Source SOC.Memory.memory.0.200_DO_2_LUT4_C_Z_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: 0.7 15.3 Net SOC.Memory.memory.0.200_DO_2_LUT4_C_Z[3] (13,37) -> (14,36)
Info: Sink SOC.Memory.memory.0.200_DO_2_LUT4_C_Z_LUT4_B.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 15.5 Source SOC.Memory.memory.0.200_DO_2_LUT4_C_Z_LUT4_B.F
Info: 0.5 16.0 Net SOC.Memory.memory.0.264_DO_2_PFUMX_C0_Z[3] (14,36) -> (14,35)
Info: Sink SOC.Memory.memory.0.0_DO_2_LUT4_C_Z_LUT4_A_Z_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 16.3 Source SOC.Memory.memory.0.0_DO_2_LUT4_C_Z_LUT4_A_Z_LUT4_Z.F
Info: 0.9 17.2 Net SOC.Memory.memory.0.0_DO_2_LUT4_C_Z_LUT4_A_Z[3] (14,35) -> (18,35)
Info: Sink SOC.Core.read_data_LUT4_Z_1_D_LUT4_Z_D_LUT4_Z_B_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 17.4 Source SOC.Core.read_data_LUT4_Z_1_D_LUT4_Z_D_LUT4_Z_B_LUT4_Z.F
Info: 0.4 17.8 Net SOC.Core.read_data_LUT4_Z_1_D_LUT4_Z_D_LUT4_Z_B[2] (18,35) -> (18,35)
Info: Sink SOC.Core.read_data_LUT4_Z_1_D_LUT4_Z_D_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 18.1 Source SOC.Core.read_data_LUT4_Z_1_D_LUT4_Z_D_LUT4_Z.F
Info: 1.1 19.2 Net SOC.Core.read_data_LUT4_Z_1_D_LUT4_Z_D[3] (18,35) -> (18,29)
Info: Sink SOC.Core.read_data_LUT4_Z_1_D_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 19.4 Source SOC.Core.read_data_LUT4_Z_1_D_LUT4_Z.F
Info: 1.3 20.7 Net SOC.Core.read_data_LUT4_Z_1_D[3] (18,29) -> (16,24)
Info: Sink SOC.Core.read_data_LUT4_Z_1.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 20.9 Source SOC.Core.read_data_LUT4_Z_1.F
Info: 1.1 22.0 Net SOC.read_data[1] (16,24) -> (26,24)
Info: Sink SOC.Core.instruction_register_TRELLIS_FF_Q_30.M
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:42.3-49.2
Info: Risco-5/src/peripheral/soc.v:20.34-20.43
Info: 0.0 22.0 Setup SOC.Core.instruction_register_TRELLIS_FF_Q_30.M
Info: 4.9 ns logic, 17.1 ns routing
Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
Info: curr total
Info: 0.5 0.5 Source ClkDivider.clk_counter_TRELLIS_FF_Q_27.Q
Info: 1.2 1.7 Net ClkDivider.clk_counter[4] (3,3) -> (4,2)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.B
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:15.3-23.2
Info: Risco-5/debug/clk_divider.v:14.26-14.37
Info: 0.4 2.1 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: 0.0 2.1 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (4,2) -> (4,2)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: 0.0 2.1 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: 0.0 2.1 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (4,2) -> (4,2)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:15.3-23.2
Info: Risco-5/debug/clk_divider.v:40.12-40.38
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 2.2 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: 0.0 2.2 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (4,2) -> (4,2)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: 0.0 2.2 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: 0.0 2.2 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (4,2) -> (4,2)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:15.3-23.2
Info: Risco-5/debug/clk_divider.v:40.12-40.38
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 2.3 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: 0.0 2.3 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (4,2) -> (4,2)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: 0.0 2.3 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: 0.0 2.3 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (4,2) -> (5,2)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:15.3-23.2
Info: Risco-5/debug/clk_divider.v:40.12-40.38
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 2.3 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: 0.0 2.3 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (5,2) -> (5,2)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: 0.0 2.3 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: 0.0 2.3 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (5,2) -> (5,2)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:15.3-23.2
Info: Risco-5/debug/clk_divider.v:40.12-40.38
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 2.4 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: 0.0 2.4 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (5,2) -> (5,2)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: 0.0 2.4 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: 0.0 2.4 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (5,2) -> (5,2)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:15.3-23.2
Info: Risco-5/debug/clk_divider.v:40.12-40.38
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 2.5 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: 0.0 2.5 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (5,2) -> (5,2)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: 0.0 2.5 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: 0.0 2.5 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (5,2) -> (5,2)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:15.3-23.2
Info: Risco-5/debug/clk_divider.v:40.12-40.38
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 2.5 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: 0.0 2.5 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (5,2) -> (5,2)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: 0.0 2.5 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: 0.0 2.5 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (5,2) -> (6,2)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:15.3-23.2
Info: Risco-5/debug/clk_divider.v:40.12-40.38
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 2.6 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: 0.0 2.6 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (6,2) -> (6,2)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: 0.0 2.6 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: 0.0 2.6 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (6,2) -> (6,2)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:15.3-23.2
Info: Risco-5/debug/clk_divider.v:40.12-40.38
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 2.7 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: 0.0 2.7 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (6,2) -> (6,2)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: 0.0 2.7 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: 0.0 2.7 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (6,2) -> (6,2)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:15.3-23.2
Info: Risco-5/debug/clk_divider.v:40.12-40.38
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 2.8 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: 0.0 2.8 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (6,2) -> (6,2)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: 0.0 2.8 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: 0.0 2.8 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (6,2) -> (6,2)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:15.3-23.2
Info: Risco-5/debug/clk_divider.v:40.12-40.38
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 2.8 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: 0.0 2.8 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (6,2) -> (6,2)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: 0.0 2.8 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: 0.0 2.8 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (6,2) -> (7,2)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:15.3-23.2
Info: Risco-5/debug/clk_divider.v:40.12-40.38
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 2.9 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: 0.0 2.9 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (7,2) -> (7,2)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: 0.0 2.9 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: 0.0 2.9 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN (7,2) -> (7,2)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:15.3-23.2
Info: Risco-5/debug/clk_divider.v:40.12-40.38
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 3.0 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: 0.0 3.0 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (7,2) -> (7,2)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: 0.0 3.0 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: 0.0 3.0 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN (7,2) -> (7,2)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:15.3-23.2
Info: Risco-5/debug/clk_divider.v:40.12-40.38
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 3.0 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT$CCU2_COMB0.FCO
Info: 0.0 3.0 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT$CCU2_FCI_INT (7,2) -> (7,2)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT$CCU2_COMB1.FCI
Info: 0.0 3.0 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT$CCU2_COMB1.FCO
Info: 0.0 3.0 Net $nextpnr_CCU2C_7$CIN (7,2) -> (7,2)
Info: Sink $nextpnr_CCU2C_7$CCU2_COMB0.FCI
Info: 0.4 3.5 Source $nextpnr_CCU2C_7$CCU2_COMB0.F
Info: 0.5 4.0 Net reset_LUT4_B_C_LUT4_Z_D (7,2) -> (7,4)
Info: Sink reset_LUT4_B_C_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 4.2 Source reset_LUT4_B_C_LUT4_Z.F
Info: 0.7 4.9 Net reset_LUT4_B_C[1] (7,4) -> (5,4)
Info: Sink reset_LUT4_B.C
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 5.1 Source reset_LUT4_B.F
Info: 0.7 5.8 Net reset_LUT4_B_Z (5,4) -> (6,3)
Info: Sink ClkDivider.clk_counter_TRELLIS_FF_Q_9.LSR
Info: 0.4 6.2 Setup ClkDivider.clk_counter_TRELLIS_FF_Q_9.LSR
Info: 3.2 ns logic, 3.0 ns routing
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
Info: curr total
Info: 0.0 0.0 Source reset$tr_io.O
Info: 3.3 3.3 Net reset$TRELLIS_IO_IN (0,29) -> (5,4)
Info: Sink reset_LUT4_B.B
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 3.5 Source reset_LUT4_B.F
Info: 0.7 4.2 Net reset_LUT4_B_Z (5,4) -> (6,3)
Info: Sink ClkDivider.clk_counter_TRELLIS_FF_Q_9.LSR
Info: 0.4 4.6 Setup ClkDivider.clk_counter_TRELLIS_FF_Q_9.LSR
Info: 0.7 ns logic, 4.0 ns routing
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk_o':
Info: curr total
Info: 0.0 0.0 Source gpios[0]$tr_io.O
Info: 4.1 4.1 Net gpios[0]$TRELLIS_IO_IN (90,35) -> (23,32)
Info: Sink SOC.GPIOS.Gpios[0].direction_LUT4_C.A
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:7.16-7.21
Info: 0.2 4.3 Source SOC.GPIOS.Gpios[0].direction_LUT4_C.F
Info: 0.0 4.3 Net SOC.GPIOS.Gpios[0].direction_LUT4_C_Z (23,32) -> (23,32)
Info: Sink SOC.GPIOS.Gpios[0].direction_LUT4_C_1.F1
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:133.22-133.24
Info: 0.2 4.5 Source SOC.GPIOS.Gpios[0].direction_LUT4_C_1.OFX
Info: 0.9 5.4 Net SOC.GPIOS.Gpios[0].direction_LUT4_C_Z_PFUMX_ALUT_Z[1] (23,32) -> (23,32)
Info: Sink SOC.Core.read_data_LUT4_Z.B
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 5.6 Source SOC.Core.read_data_LUT4_Z.F
Info: 1.3 6.9 Net SOC.read_data[0] (23,32) -> (26,24)
Info: Sink SOC.Core.instruction_register_TRELLIS_FF_Q_31.M
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:42.3-49.2
Info: Risco-5/src/peripheral/soc.v:20.34-20.43
Info: 0.0 6.9 Setup SOC.Core.instruction_register_TRELLIS_FF_Q_31.M
Info: 0.6 ns logic, 6.3 ns routing
Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
Info: curr total
Info: 0.5 0.5 Source ClkDivider.clk_o_auto_TRELLIS_FF_Q.Q
Info: 4.2 4.7 Net clk_o (6,4) -> (63,17)
Info: Sink led_LUT4_Z_3.D
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:10.6-10.11
Info: 0.2 5.0 Source led_LUT4_Z_3.F
Info: 2.0 7.0 Net led[7]$TRELLIS_IO_OUT (63,17) -> (90,20)
Info: Sink led[7]$tr_io.I
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:6.22-6.25
Info: 0.8 ns logic, 6.2 ns routing
Info: Critical path report for cross-domain path 'posedge $glbnet$clk_o' -> '<async>':
Info: curr total
Info: 0.5 0.5 Source SOC.GPIOS.Gpios[0].direction_TRELLIS_FF_Q.Q
Info: 2.7 3.2 Net SOC.GPIOS.gpio_direction[0] (32,29) -> (68,35)
Info: Sink gpios_$_TBUF__Y_4_E_LUT4_Z.D
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:42.3-49.2
Info: Risco-5/src/peripheral/gpios.v:14.19-14.33
Info: Risco-5/src/peripheral/soc.v:111.3-120.2
Info: 0.2 3.4 Source gpios_$_TBUF__Y_4_E_LUT4_Z.F
Info: 1.0 4.5 Net gpios_$_TBUF__Y_4_E (68,35) -> (74,35)
Info: Sink gpios[0]$tr_io$invert_T.A
Info: 0.2 4.7 Source gpios[0]$tr_io$invert_T.F
Info: 1.6 6.2 Net gpios[0]$tr_io$invert_T$conn$Z (74,35) -> (90,35)
Info: Sink gpios[0]$tr_io.T
Info: 1.0 ns logic, 5.3 ns routing
Info: Max frequency for clock '$glbnet$clk_o': 45.48 MHz (PASS at 12.00 MHz)
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 161.50 MHz (PASS at 25.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 4.62 ns
Info: Max delay <async> -> posedge $glbnet$clk_o : 6.90 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 6.99 ns
Info: Max delay posedge $glbnet$clk_o -> <async> : 6.25 ns
Info: Slack histogram:
Info: legend: * represents 158 endpoint(s)
Info: + represents [1,158) endpoint(s)
Info: [ 33808, 36229) |+
Info: [ 36229, 38650) |+
Info: [ 38650, 41071) |+
Info: [ 41071, 43492) |
Info: [ 43492, 45913) |
Info: [ 45913, 48334) |
Info: [ 48334, 50755) |
Info: [ 50755, 53176) |
Info: [ 53176, 55597) |
Info: [ 55597, 58018) |
Info: [ 58018, 60439) |
Info: [ 60439, 62860) |+
Info: [ 62860, 65281) |+
Info: [ 65281, 67702) |**+
Info: [ 67702, 70123) |****************+
Info: [ 70123, 72544) |************************************************************
Info: [ 72544, 74965) |+
Info: [ 74965, 77386) |******+
Info: [ 77386, 79807) |*******+
Info: [ 79807, 82228) |+
5 warnings, 0 errors
Info: Program finished normally.
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (ECPPACK)
[Pipeline] sh
+ /eda/oss-cad-suite/bin/ecppack --compress --input ./build/out.config --bit ./build/out.bit
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (FPGA Flash)
[Pipeline] parallel
[Pipeline] { (Branch: openFPGAloader ECP5)
[Pipeline] { (Branch: openFPGAloader Tangnano 20k)
[Pipeline] stage
[Pipeline] { (openFPGAloader ECP5)
[Pipeline] stage
[Pipeline] { (openFPGAloader Tangnano 20k)
[Pipeline] script
[Pipeline] {
[Pipeline] script
[Pipeline] {
[Pipeline] lock
Trying to acquire lock on [ecp5]
Resource [ecp5] did not exist. Created.
Lock acquired on [ecp5]
[Pipeline] {
[Pipeline] lock
Trying to acquire lock on [tangnano20k]
Resource [tangnano20k] did not exist. Created.
Lock acquired on [tangnano20k]
[Pipeline] {
[Pipeline] echo
FPGA ECP5 Broqueada
[Pipeline] sh
[Pipeline] echo
FPGA TangNano Broqueada
[Pipeline] sh
+ /eda/oss-cad-suite/bin/openFPGALoader -b colorlight-i9 ./build/out.bit
Found 1 compatible device:
0x0d28 0x0204 0x3 DAPLink CMSIS-DAP
Open file: DONE
Parse file: DONE
Enable configuration: DONE
SRAM erase: DONE
+ echo gravando na tang nano
gravando na tang nano
[Pipeline] }
Lock released on resource [tangnano20k]
[Pipeline] // lock
[Pipeline] }
[Pipeline] // script
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Loading: [===== ] 9.54%
Loading: [========== ] 19.07%
Loading: [=============== ] 28.61%
Loading: [==================== ] 38.14%
Loading: [======================== ] 47.68%
Loading: [============================= ] 57.21%
Loading: [================================== ] 66.75%
Loading: [======================================= ] 76.29%
Loading: [=========================================== ] 85.82%
Loading: [================================================ ] 95.36%
Loading: [==================================================] 100.00%
Done
Disable configuration: DONE
[Pipeline] }
Lock released on resource [ecp5]
[Pipeline] // lock
[Pipeline] }
[Pipeline] // script
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Testes)
[Pipeline] parallel
[Pipeline] { (Branch: ECP5 - Testes)
[Pipeline] { (Branch: TangNano - Testes)
[Pipeline] stage
[Pipeline] { (ECP5 - Testes)
[Pipeline] stage
[Pipeline] { (TangNano - Testes)
[Pipeline] script
[Pipeline] {
[Pipeline] script
[Pipeline] {
[Pipeline] echo
Rodando teste na ECP5
[Pipeline] lock
Trying to acquire lock on [ecp5]
Resource [ecp5] did not exist. Created.
Lock acquired on [ecp5]
[Pipeline] {
[Pipeline] echo
Rodando teste na tang nano
[Pipeline] lock
Trying to acquire lock on [tangnano20k]
Resource [tangnano20k] did not exist. Created.
Lock acquired on [tangnano20k]
[Pipeline] {
[Pipeline] echo
FPGA ECP5 Broqueada
[Pipeline] sh
[Pipeline] echo
FPGA TangNano Broqueada
[Pipeline] sh
+ echo testando na ecp5
testando na ecp5
[Pipeline] }
Lock released on resource [ecp5]
+ echo testando na tang nano
testando na tang nano
[Pipeline] // lock
[Pipeline] echo
ECP5 liberada
[Pipeline] }
[Pipeline] }
Lock released on resource [tangnano20k]
[Pipeline] // script
[Pipeline] // lock
[Pipeline] }
[Pipeline] echo
TangNano liberada
[Pipeline] }
[Pipeline] // stage
[Pipeline] // script
[Pipeline] }
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // node
[Pipeline] End of Pipeline
Finished: SUCCESS
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