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Start of Pipeline - (35 sec in block)
node - (35 sec in block)
node block - (34 sec in block)
stage - (2.1 sec in block)Git Clone
stage block (Git Clone) - (1.8 sec in block)
sh - (0.39 sec in self)rm -Rf Risco-5/ build/
sh - (0.91 sec in self)git clone https://github.com/JN513/Risco-5
sh - (0.35 sec in self)cd Risco-5
stage - (2.3 sec in block)IVerilog
stage block (IVerilog) - (2 sec in block)
sh - (0.39 sec in self)mkdir -p build
sh - (0.4 sec in self)cp Risco-5/software/memory/add.hex Risco-5/software/memory/generic.hex
sh - (0.39 sec in self) /eda/oss-cad-suite/bin/iverilog -o build/soc_test.o -s soc_tb Risco-5/src/core/*.v Risco-5/src/peripheral/*.v Risco-5/tests/soc_test.v
sh - (0.39 sec in self)/eda/oss-cad-suite/bin/vvp build/soc_test.o
sh - (0.36 sec in self)rm -f Risco5/software/memory/generic.hex
stage - (25 sec in block)Síntese
stage block (Síntese) - (24 sec in block)
parallel - (24 sec in block)
parallel block (Branch: OSS-Cad-Suite) - (34 ms in block)
stage - (23 sec in block)OSS-Cad-Suite
stage block (OSS-Cad-Suite) - (23 sec in block)
stage - (15 sec in block)Yosys
stage block (Yosys) - (15 sec in block)
sh - (15 sec in self) /eda/oss-cad-suite/bin/yosys -p " read_verilog Risco-5/fpga/ecp5/*.v; read_verilog Risco-5/debug/clk_divider.v; read_verilog Risco-5/src/core/*.v; read_verilog Risco-5/src/peripheral/*.v; synth_ecp5 -json ./build/out.json -abc9 "
stage - (6.7 sec in block)NextPNR
stage block (NextPNR) - (6.3 sec in block)
sh - (6.1 sec in self) /eda/oss-cad-suite/bin/nextpnr-ecp5 --json ./build/out.json --write ./build/out_pnr.json --45k --lpf Risco-5/fpga/ecp5/pinout.lpf --textcfg ./build/out.config --package CABGA381 --speed 6 --ignore-loops --lpf-allow-unconstrained
stage - (0.35 sec in block)ECPPACK
stage block (ECPPACK) - (0.13 sec in block)
parallel block (Branch: Gowin) - (22 sec in block)
stage - (21 sec in block)Gowin
stage block (Gowin) - (21 sec in block)
sh - (21 sec in self) /eda/gowin/IDE/bin/gw_sh Risco-5/fpga/tangnano20k/run.tcl
stage - (2.1 sec in block)FPGA Flash
stage block (FPGA Flash) - (1.8 sec in block)
parallel - (1.5 sec in block)
parallel block (Branch: openFPGAloader ECP5) - (23 ms in block)
stage - (0.62 sec in block)openFPGAloader ECP5
stage block (openFPGAloader ECP5) - (0.32 sec in block)
parallel block (Branch: openFPGAloader Tangnano 20k) - (1.1 sec in block)
stage - (0.65 sec in block)openFPGAloader Tangnano 20k
stage block (openFPGAloader Tangnano 20k) - (0.3 sec in block)
stage - (2.4 sec in block)Testes
stage block (Testes) - (1.9 sec in block)
parallel - (1.6 sec in block)
parallel block (Branch: ECP5 - Testes) - (34 ms in block)
stage - (0.67 sec in block)ECP5 - Testes
stage block (ECP5 - Testes) - (0.31 sec in block)
parallel block (Branch: TangNano - Testes) - (1.1 sec in block)
stage - (0.68 sec in block)TangNano - Testes
stage block (TangNano - Testes) - (0.31 sec in block)