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Start of Pipeline - (4 min 29 sec in block)
node - (4 min 28 sec in block)
node block - (4 min 28 sec in block)
stage - (2.4 sec in block)Git Clone
stage block (Git Clone) - (2 sec in block)
sh - (0.47 sec in self)rm -rf Risco-5
sh - (1.2 sec in self)git clone --recursive https://github.com/JN513/Risco-5.git Risco-5
stage - (1.7 sec in block)Simulation
stage block (Simulation) - (1.3 sec in block)
dir - (0.92 sec in block)Risco-5
dir block - (0.64 sec in block)
sh - (0.42 sec in self)/eda/oss-cad-suite/bin/iverilog -o simulation.out -g2005 -s soc_tb -I src/core/ -I src/peripheral/ src/core/alu.v src/core/alu_control.v src/core/control_unit.v src/core/core.v src/core/csr_unit.v src/core/immediate_generator.v src/core/mdu.v src/core/mux.v src/core/pc.v src/core/registers.v tests/soc_test.v src/peripheral/bus.v src/peripheral/fifo.v src/peripheral/gpios.v src/peripheral/gpio.v src/peripheral/leds.v src/peripheral/memory.v src/peripheral/pwm.v src/peripheral/soc.v src/peripheral/uart_rx.v src/peripheral/uart_tx.v src/peripheral/uart.v
stage - (4 min 22 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (4 min 21 sec in block)
parallel - (4 min 21 sec in block)
parallel block (Branch: colorlight_i9) - (58 ms in block)
stage - (3 min 44 sec in block)colorlight_i9
stage block (colorlight_i9) - (3 min 43 sec in block)
lock - (3 min 43 sec in block)colorlight_i9
lock block - (3 min 42 sec in block)
stage - (3 min 38 sec in block)Síntese e PnR
stage block (Síntese e PnR) - (3 min 38 sec in block)
dir - (3 min 37 sec in block)Risco-5
dir block - (3 min 37 sec in block)
echo - (0.17 sec in self)Iniciando síntese para FPGA colorlight_i9.
sh - (3 min 36 sec in self)python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p Risco-5 -b colorlight_i9
stage - (2.2 sec in block)Flash colorlight_i9
stage block (Flash colorlight_i9) - (1.6 sec in block)
dir - (1.1 sec in block)Risco-5
dir block - (0.83 sec in block)
echo - (0.16 sec in self)FPGA colorlight_i9 bloqueada para flash.
sh - (0.45 sec in self)python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p Risco-5 -b colorlight_i9 -l
stage - (0.71 sec in block)Teste colorlight_i9
stage block (Teste colorlight_i9) - (0.38 sec in block)
getContext - (0.16 sec in self)
parallel block (Branch: digilent_nexys4_ddr) - (4 min 20 sec in block)
stage - (4 min 19 sec in block)digilent_nexys4_ddr
stage block (digilent_nexys4_ddr) - (4 min 19 sec in block)
lock - (4 min 18 sec in block)digilent_nexys4_ddr
lock block - (4 min 17 sec in block)
stage - (4 min 8 sec in block)Síntese e PnR
stage block (Síntese e PnR) - (4 min 8 sec in block)
dir - (4 min 7 sec in block)Risco-5
dir block - (4 min 7 sec in block)
echo - (0.15 sec in self)Iniciando síntese para FPGA digilent_nexys4_ddr.
sh - (4 min 6 sec in self)python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p Risco-5 -b digilent_nexys4_ddr
stage - (7 sec in block)Flash digilent_nexys4_ddr
stage block (Flash digilent_nexys4_ddr) - (6.6 sec in block)
dir - (6.2 sec in block)Risco-5
dir block - (6 sec in block)
echo - (0.17 sec in self)FPGA digilent_nexys4_ddr bloqueada para flash.
sh - (5.6 sec in self)python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p Risco-5 -b digilent_nexys4_ddr -l
stage - (1.1 sec in block)Teste digilent_nexys4_ddr
stage block (Teste digilent_nexys4_ddr) - (0.94 sec in block)
echo - (0.23 sec in self)Testando FPGA digilent_nexys4_ddr.
dir - (0.38 sec in block)Risco-5
dir block - (0.14 sec in block)
stage - (0.77 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (0.53 sec in block)
junit - (0.27 sec in self)**/test-reports/*.xml