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Optimizing lut $abc$96765$lut$aiger96764$13925.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$13951.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$13964.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$14027.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$14043.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$14085.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$14092.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$14156.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$14172.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$14211.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$14227.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$14243.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$14259.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$14278.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$14294.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$14301.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$14311.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$14327.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$14352.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$14423.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$14484.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$14500.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$14516.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$14532.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$14551.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$14584.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$14600.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$14625.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$14689.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$14756.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$14772.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$14788.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$14804.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$14823.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$14839.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$14846.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$14856.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$14872.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$14895.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$14961.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$15028.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$15044.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$15051.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$15061.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$15095.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$15111.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$15127.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$15143.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$15166.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$15228.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$15244.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$15278.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$15321.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$15328.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$15344.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$15366.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$15439.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$15452.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$15504.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$15568.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$15584.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$15597.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96765$lut$aiger96764$15613.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96765$lut$aiger96764$15630.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$96765$lut$aiger96764$15642.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$15655.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$15665.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$15672.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$15691.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$15716.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$15782.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$15795.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$15805.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$15812.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$15825.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96765$lut$aiger96764$15853.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$15885.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$15898.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96765$lut$aiger96764$15923.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$15988.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$16071.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$16087.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$16120.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$16130.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$16150.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96765$lut$aiger96764$16172.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$16189.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$16205.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$16218.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96765$lut$aiger96764$16234.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96765$lut$aiger96764$16251.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$96765$lut$aiger96764$16282.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$16313.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$16330.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$16393.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$16403.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$16426.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$16439.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96765$lut$aiger96764$16462.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$16478.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$16491.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96765$lut$aiger96764$16507.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96765$lut$aiger96764$16524.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$96765$lut$aiger96764$16546.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$16556.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$16579.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$16592.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96765$lut$aiger96764$16620.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$16652.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$16665.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96765$lut$aiger96764$16690.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$16751.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$16819.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$16883.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$16949.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$16962.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$16972.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$16979.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$16992.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96765$lut$aiger96764$17015.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$17028.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96765$lut$aiger96764$17044.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96765$lut$aiger96764$17066.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$17077.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$96765$lut$aiger96764$17096.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$17158.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$17231.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$17244.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$17258.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96765$lut$aiger96764$17280.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$17297.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$17313.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$17326.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96765$lut$aiger96764$17342.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96765$lut$aiger96764$17359.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$96765$lut$aiger96764$17372.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$17438.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$17451.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$17503.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$17513.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$17536.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$17549.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96765$lut$aiger96764$17571.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96765$lut$aiger96764$17609.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$17622.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96765$lut$aiger96764$17666.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$17682.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$17765.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$17778.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$17788.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$17808.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96765$lut$aiger96764$17830.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$17846.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96765$lut$aiger96764$17868.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$17884.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$17897.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96765$lut$aiger96764$17926.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$17996.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$18006.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$18026.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96765$lut$aiger96764$18048.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$18065.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$18081.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$18094.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96765$lut$aiger96764$18110.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96765$lut$aiger96764$18127.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$96765$lut$aiger96764$18154.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$18205.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$18269.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$18279.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96765$lut$aiger96764$18292.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$18299.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$18312.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96765$lut$aiger96764$18340.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$18372.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$18385.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96765$lut$aiger96764$7449.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$5975.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$6015.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$6049.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$6068.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$6188.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$6267.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$6283.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$6331.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$6347.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$6377.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$6456.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$6472.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$6605.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$6670.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$6759.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$10000.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$96765$lut$aiger96764$6823.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$6823.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$6829.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$6803.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$96765$lut$aiger96764$6857.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$6857.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$6871.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$6886.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$6916.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$6920.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96765$lut$aiger96764$6934.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$6934.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$6942.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96765$lut$aiger96764$6956.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96765$lut$aiger96764$6971.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$6975.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96765$lut$aiger96764$6991.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$6991.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$6998.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96765$lut$aiger96764$6998.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$96765$lut$aiger96764$7017.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$96765$lut$aiger96764$7056.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$7061.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96765$lut$aiger96764$7061.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
Optimizing lut $abc$96765$lut$aiger96764$7071.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$7071.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96943.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96947.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $abc$96765$lut$aiger96764$7092.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$7112.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$7112.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96964.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96963.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$96765$lut$aiger96764$7187.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$96765$lut$aiger96764$7199.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$7199.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$7207.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$7218.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$7223.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$7237.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$96765$lut$aiger96764$7255.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$7270.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$7285.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$7300.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$7386.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$7328.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$96765$lut$aiger96764$7352.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$7367.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$7367.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$7386.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96978.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$7404.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$96765$lut$aiger96764$7404.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
Optimizing lut $abc$96765$lut$aiger96764$7421.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$7421.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$7436.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$7436.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$7449.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$7459.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
Optimizing lut $abc$96765$lut$aiger96764$7476.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$7554.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$7619.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$7619.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$7680.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$8289.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$96765$lut$aiger96764$7707.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$7711.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$7715.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$7721.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$7721.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$7772.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$96765$lut$aiger96764$7779.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$7786.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$7793.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$7800.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$7816.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$7823.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$7830.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$7837.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$7870.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$7877.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$7877.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$7887.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$7894.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$7908.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$7915.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$7922.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$7944.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$7954.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$7970.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$7980.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$7985.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$7994.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96765$lut$aiger96764$8005.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$96765$lut$aiger96764$8028.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$8035.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$8042.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$8049.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$8065.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$8072.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$8088.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$8095.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$8095.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$8105.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$8112.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$8125.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$8132.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$8148.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$8153.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$8157.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$8169.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$8180.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96765$lut$aiger96764$8193.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$8206.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$8216.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$8226.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$8236.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$8256.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96922.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $abc$96765$lut$aiger96764$8272.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$8289.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96765$lut$aiger96764$8125.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$8315.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$8321.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96765$lut$aiger96764$8335.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$8356.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$8065.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$8403.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$8415.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$8422.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$8422.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$8432.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$8439.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$8453.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$8464.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$8477.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$8484.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$8491.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$8498.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$8533.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96765$lut$aiger96764$8541.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$96765$lut$aiger96764$8550.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$96765$lut$aiger96764$8584.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$8599.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96765$lut$aiger96764$8617.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$96765$lut$aiger96764$7850.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$8678.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96765$lut$aiger96764$8689.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$96765$lut$aiger96764$8695.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$8730.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96765$lut$aiger96764$8730.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$96765$lut$aiger96764$8742.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96765$lut$aiger96764$8748.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$8112.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$8770.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$7837.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$8821.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$8828.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$8838.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$8884.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96765$lut$aiger96764$8891.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96765$lut$aiger96764$8907.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96765$lut$aiger96764$8931.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$96765$lut$aiger96764$8931.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$8941.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$8951.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$8969.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$96765$lut$aiger96764$8975.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$9023.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$9029.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$9041.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$9061.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96765$lut$aiger96764$9075.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$9090.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96936.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $abc$96765$lut$aiger96764$9096.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96765$lut$aiger96764$9104.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$96765$lut$aiger96764$9157.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$96765$lut$aiger96764$9090.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$9181.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$9185.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96934.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $abc$96765$lut$aiger96764$9211.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96765$lut$aiger96764$9219.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$96765$lut$aiger96764$9239.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$8226.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$9269.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$96765$lut$aiger96764$9308.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$9317.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$9409.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96765$lut$aiger96764$9417.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$96765$lut$aiger96764$9431.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$9438.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$9451.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$9488.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$9431.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$8821.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$9526.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$96765$lut$aiger96764$9559.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$9601.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$9640.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$9649.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$9676.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$9694.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96953.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $abc$96765$lut$aiger96764$9711.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96765$lut$aiger96764$9721.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$9747.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$9829.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$9862.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$9880.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$9898.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$9956.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$9974.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96787.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96769.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96781.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96780.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96777.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96779.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96778.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96775.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96785.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96805.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96898.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96771.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96782.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96783.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96768.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96769.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96772.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96775.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96765$lut$aiger96764$9373.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96779.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96782.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96783.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96784.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96786.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96787.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96790.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$16318.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96844.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96911.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96768.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
Optimizing lut $abc$96765$lut$aiger96764$8453.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$8477.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$8484.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96944.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$96765$lut$aiger96764$8491.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96948.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96765$lut$aiger96764$7300.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$7255.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$7270.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96959.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96960.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96963.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96968.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96969.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96970.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$96765$lut$aiger96764$7352.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$96765$lut$aiger96764$7328.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
Optimizing lut $abc$96765$lut$aiger96764$7223.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Removed 0 unused cells and 11058 unused wires.
21.45. Executing AUTONAME pass.
Renamed 397600 objects in module top (280 iterations).
<suppressed ~13379 debug messages>
21.46. Executing HIERARCHY pass (managing design hierarchy).
21.46.1. Analyzing design hierarchy..
Top module: \top
21.46.2. Analyzing design hierarchy..
Top module: \top
Removed 0 unused modules.
21.47. Printing statistics.
=== top ===
Number of wires: 5533
Number of wire bits: 15840
Number of public wires: 5533
Number of public wire bits: 15840
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 8549
$_TBUF_ 5
CCU2C 165
L6MUX21 356
LUT4 5206
PFUMX 1003
TRELLIS_DPR16X4 512
TRELLIS_FF 1302
21.48. Executing CHECK pass (checking for obvious problems).
Checking module top...
Found and reported 0 problems.
21.49. Executing JSON backend.
Warnings: 258 unique messages, 259 total
End of script. Logfile hash: 5120a89526, CPU: user 8.70s system 0.12s, MEM: 228.24 MB peak
Yosys 0.36+8 (git sha1 fb4cbfa73, clang 10.0.0-4ubuntu1 -fPIC -Os)
Time spent: 38% 1x abc9_exe (5 sec), 13% 11x techmap (1 sec), ...
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (NextPNR)
[Pipeline] sh
+ /eda/oss-cad-suite/bin/nextpnr-ecp5 --json ./build/out.json --write ./build/out_pnr.json --45k --lpf Risco-5/fpga/ecp5/pinout.lpf --textcfg ./build/out.config --package CABGA381 --speed 6 --ignore-loops --lpf-allow-unconstrained
Info: constraining clock net 'clk' to 25.00 MHz
Warning: IO 'gpios[4]' is unconstrained in LPF and will be automatically placed
Warning: IO 'gpios[3]' is unconstrained in LPF and will be automatically placed
Warning: IO 'gpios[2]' is unconstrained in LPF and will be automatically placed
Warning: IO 'gpios[1]' is unconstrained in LPF and will be automatically placed
Warning: IO 'gpios[0]' is unconstrained in LPF and will be automatically placed
Info: Logic utilisation before packing:
Info: Total LUT4s: 8608/43848 19%
Info: logic LUTs: 5206/43848 11%
Info: carry LUTs: 330/43848 0%
Info: RAM LUTs: 2048/ 5481 37%
Info: RAMW LUTs: 1024/10962 9%
Info: Total DFFs: 1302/43848 2%
Info: Packing IOs..
Info: $gpios[4]$iobuf_i: gpios_$_TBUF__Y.Y
Info: $gpios[3]$iobuf_i: gpios_$_TBUF__Y_1.Y
Info: $gpios[2]$iobuf_i: gpios_$_TBUF__Y_2.Y
Info: $gpios[1]$iobuf_i: gpios_$_TBUF__Y_3.Y
Info: $gpios[0]$iobuf_i: gpios_$_TBUF__Y_4.Y
Info: pin 'tx$tr_io' constrained to Bel 'X90/Y20/PIOC'.
Info: pin 'rx$tr_io' constrained to Bel 'X90/Y20/PIOA'.
Info: pin 'reset$tr_io' constrained to Bel 'X0/Y29/PIOA'.
Info: pin 'led[7]$tr_io' constrained to Bel 'X90/Y20/PIOD'.
Info: pin 'led[6]$tr_io' constrained to Bel 'X0/Y44/PIOD'.
Info: pin 'led[5]$tr_io' constrained to Bel 'X0/Y59/PIOA'.
Info: pin 'led[4]$tr_io' constrained to Bel 'X15/Y71/PIOB'.
Info: pin 'led[3]$tr_io' constrained to Bel 'X90/Y29/PIOC'.
Info: pin 'led[2]$tr_io' constrained to Bel 'X90/Y44/PIOB'.
Info: pin 'led[1]$tr_io' constrained to Bel 'X0/Y44/PIOC'.
Info: pin 'led[0]$tr_io' constrained to Bel 'X0/Y59/PIOC'.
Info: pin 'clk$tr_io' constrained to Bel 'X0/Y68/PIOC'.
Info: Packing constants..
Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info: 287 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info: Promoting globals...
Info: promoting clock net clk_o to global network
Info: promoting clock net clk$TRELLIS_IO_IN to global network
Info: Checksum: 0xf8f9e0f3
Info: Device utilisation:
Info: TRELLIS_IO: 17/ 245 6%
Info: DCCA: 2/ 56 3%
Info: DP16KD: 0/ 108 0%
Info: MULT18X18D: 0/ 72 0%
Info: ALU54B: 0/ 36 0%
Info: EHXPLLL: 0/ 4 0%
Info: EXTREFB: 0/ 2 0%
Info: DCUA: 0/ 2 0%
Info: PCSCLKDIV: 0/ 2 0%
Info: IOLOGIC: 0/ 160 0%
Info: SIOLOGIC: 0/ 85 0%
Info: GSR: 0/ 1 0%
Info: JTAGG: 0/ 1 0%
Info: OSCG: 0/ 1 0%
Info: SEDGA: 0/ 1 0%
Info: DTR: 0/ 1 0%
Info: USRMCLK: 0/ 1 0%
Info: CLKDIVF: 0/ 4 0%
Info: ECLKSYNCB: 0/ 10 0%
Info: DLLDELD: 0/ 8 0%
Info: DDRDLL: 0/ 4 0%
Info: DQSBUFM: 0/ 10 0%
Info: TRELLIS_ECLKBUF: 0/ 8 0%
Info: ECLKBRIDGECS: 0/ 2 0%
Info: DCSC: 0/ 2 0%
Info: TRELLIS_FF: 1302/43848 2%
Info: TRELLIS_COMB: 8671/43848 19%
Info: TRELLIS_RAMW: 512/ 5481 9%
Info: Placed 12 cells based on constraints.
Info: Creating initial analytic placement for 5395 cells, random placement wirelen = 447040.
Info: at initial placer iter 0, wirelen = 2325
Info: at initial placer iter 1, wirelen = 2478
Info: at initial placer iter 2, wirelen = 2277
Info: at initial placer iter 3, wirelen = 2094
Info: Running main analytical placer, max placement attempts per cell = 13791752.
Info: at iteration #1, type ALL: wirelen solved = 2455, spread = 60821, legal = 61818; time = 0.27s
Info: at iteration #2, type ALL: wirelen solved = 8721, spread = 46544, legal = 47485; time = 0.26s
Info: at iteration #3, type ALL: wirelen solved = 13469, spread = 43302, legal = 44134; time = 0.26s
Info: at iteration #4, type ALL: wirelen solved = 16810, spread = 39951, legal = 41148; time = 0.25s
Info: at iteration #5, type ALL: wirelen solved = 17465, spread = 41190, legal = 42203; time = 0.25s
Info: at iteration #6, type ALL: wirelen solved = 19848, spread = 42906, legal = 43583; time = 0.24s
Info: at iteration #7, type ALL: wirelen solved = 22350, spread = 44186, legal = 44794; time = 0.24s
Info: at iteration #8, type ALL: wirelen solved = 23277, spread = 44295, legal = 44722; time = 0.24s
Info: at iteration #9, type ALL: wirelen solved = 23778, spread = 43370, legal = 43945; time = 0.24s
Info: HeAP Placer Time: 4.02s
Info: of which solving equations: 2.59s
Info: of which spreading cells: 0.31s
Info: of which strict legalisation: 0.08s
Info: Running simulated annealing placer for refinement.
Info: at iteration #1: temp = 0.000000, timing cost = 17119, wirelen = 41148
Info: at iteration #5: temp = 0.000000, timing cost = 13127, wirelen = 33555
Info: at iteration #10: temp = 0.000000, timing cost = 13475, wirelen = 31617
Info: at iteration #15: temp = 0.000000, timing cost = 8396, wirelen = 30838
Info: at iteration #20: temp = 0.000000, timing cost = 11447, wirelen = 30077
Info: at iteration #25: temp = 0.000000, timing cost = 12317, wirelen = 29834
Info: at iteration #30: temp = 0.000000, timing cost = 12578, wirelen = 29709
Info: at iteration #35: temp = 0.000000, timing cost = 12576, wirelen = 29660
Info: at iteration #37: temp = 0.000000, timing cost = 12414, wirelen = 29662
Info: SA placement time 35.76s
Info: Max frequency for clock '$glbnet$clk_o': 29.99 MHz (PASS at 12.00 MHz)
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 153.30 MHz (PASS at 25.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 10.50 ns
Info: Max delay <async> -> posedge $glbnet$clk_o : 12.64 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 12.40 ns
Info: Max delay posedge $glbnet$clk_o -> <async> : 15.40 ns
Info: Slack histogram:
Info: legend: * represents 98 endpoint(s)
Info: + represents [1,98) endpoint(s)
Info: [ 33477, 35932) |+
Info: [ 35932, 38387) |+
Info: [ 38387, 40842) |+
Info: [ 40842, 43297) |
Info: [ 43297, 45752) |
Info: [ 45752, 48207) |
Info: [ 48207, 50662) |+
Info: [ 50662, 53117) |+
Info: [ 53117, 55572) |+
Info: [ 55572, 58027) |+
Info: [ 58027, 60482) |********+
Info: [ 60482, 62937) |*************************************************+
Info: [ 62937, 65392) |************************************************************
Info: [ 65392, 67847) |*******+
Info: [ 67847, 70302) |*+
Info: [ 70302, 72757) |****+
Info: [ 72757, 75212) |*********+
Info: [ 75212, 77667) |*******+
Info: [ 77667, 80122) |*+
Info: [ 80122, 82577) |+
Info: Checksum: 0x553c49bd
Info: Routing globals...
Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
Info: routing clock net $glbnet$clk_o using global 1
Info: Routing..
Info: Setting up routing queue.
Info: Routing 42018 arcs.
Info: | (re-)routed arcs | delta | remaining| time spent |
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
Info: 1000 | 303 696 | 303 696 | 41609| 0.71 0.71|
Info: 2000 | 497 1502 | 194 806 | 41172| 0.15 0.86|
Info: 3000 | 673 2326 | 176 824 | 40931| 0.15 1.01|
Info: 4000 | 875 3124 | 202 798 | 40664| 0.17 1.17|
Info: 5000 | 1056 3943 | 181 819 | 40478| 0.15 1.33|
Info: 6000 | 1180 4819 | 124 876 | 40307| 0.14 1.47|
Info: 7000 | 1320 5679 | 140 860 | 39952| 0.15 1.63|
Info: 8000 | 1509 6490 | 189 811 | 39792| 0.17 1.79|
Info: 9000 | 1654 7345 | 145 855 | 39540| 0.15 1.94|
Info: 10000 | 1803 8196 | 149 851 | 39372| 0.16 2.11|
Info: 11000 | 2042 8957 | 239 761 | 39521| 0.20 2.30|
Info: 12000 | 2189 9810 | 147 853 | 39365| 0.18 2.48|
Info: 13000 | 2325 10674 | 136 864 | 39052| 0.15 2.63|
Info: 14000 | 2492 11507 | 167 833 | 38733| 0.16 2.80|
Info: 15000 | 2649 12350 | 157 843 | 38317| 0.15 2.95|
Info: 16000 | 2867 13132 | 218 782 | 37911| 0.16 3.11|
Info: 17000 | 3040 13959 | 173 827 | 37758| 0.16 3.27|
Info: 18000 | 3155 14844 | 115 885 | 37594| 0.16 3.42|
Info: 19000 | 3301 15698 | 146 854 | 37143| 0.16 3.59|
Info: 20000 | 3489 16510 | 188 812 | 36813| 0.16 3.75|
Info: 21000 | 3693 17306 | 204 796 | 36560| 0.16 3.91|
Info: 22000 | 3806 18193 | 113 887 | 36358| 0.15 4.06|
Info: 23000 | 4041 18958 | 235 765 | 35983| 0.18 4.24|
Info: 24000 | 4266 19733 | 225 775 | 35583| 0.17 4.41|
Info: 25000 | 4346 20653 | 80 920 | 35785| 0.17 4.57|
Info: 26000 | 4439 21560 | 93 907 | 35276| 0.15 4.72|
Info: 27000 | 4682 22317 | 243 757 | 34851| 0.20 4.92|
Info: 28000 | 4859 23140 | 177 823 | 34458| 0.17 5.09|
Info: 29000 | 4988 24011 | 129 871 | 34324| 0.16 5.26|
Info: 30000 | 5198 24801 | 210 790 | 33998| 0.19 5.45|
Info: 31000 | 5418 25581 | 220 780 | 34012| 0.18 5.63|
Info: 32000 | 5584 26415 | 166 834 | 33526| 0.17 5.80|
Info: 33000 | 5791 27208 | 207 793 | 33141| 0.18 5.98|
Info: 34000 | 5933 28066 | 142 858 | 33027| 0.17 6.15|
Info: 35000 | 6039 28960 | 106 894 | 32916| 0.16 6.31|
Info: 36000 | 6284 29715 | 245 755 | 32632| 0.18 6.49|
Info: 37000 | 6463 30536 | 179 821 | 32484| 0.18 6.67|
Info: 38000 | 6672 31327 | 209 791 | 32167| 0.18 6.85|
Info: 39000 | 6934 32065 | 262 738 | 31823| 0.19 7.04|
Info: 40000 | 7222 32777 | 288 712 | 31578| 0.18 7.23|
Info: 41000 | 7478 33521 | 256 744 | 31200| 0.20 7.43|
Info: 42000 | 7760 34239 | 282 718 | 31039| 0.20 7.62|
Info: 43000 | 8034 34965 | 274 726 | 30812| 0.20 7.82|
Info: 44000 | 8317 35682 | 283 717 | 30467| 0.23 8.05|
Info: 45000 | 8569 36430 | 252 748 | 30258| 0.19 8.24|
Info: 46000 | 8711 37288 | 142 858 | 30296| 0.17 8.42|
Info: 47000 | 8887 38112 | 176 824 | 30131| 0.18 8.59|
Info: 48000 | 9028 38971 | 141 859 | 30417| 0.19 8.78|
Info: 49000 | 9173 39826 | 145 855 | 30049| 0.18 8.96|
Info: 50000 | 9382 40617 | 209 791 | 29895| 0.19 9.15|
Info: 51000 | 9577 41422 | 195 805 | 29505| 0.20 9.35|
Info: 52000 | 9795 42204 | 218 782 | 29418| 0.21 9.56|
Info: 53000 | 10039 42960 | 244 756 | 28915| 0.21 9.77|
Info: 54000 | 10315 43684 | 276 724 | 28598| 0.18 9.95|
Info: 55000 | 10542 44457 | 227 773 | 28454| 0.21 10.17|
Info: 56000 | 10666 45333 | 124 876 | 28462| 0.18 10.35|
Info: 57000 | 10899 46100 | 233 767 | 28018| 0.21 10.56|
Info: 58000 | 11178 46821 | 279 721 | 27774| 0.23 10.79|
Info: 59000 | 11445 47554 | 267 733 | 27478| 0.22 11.01|
Info: 60000 | 11631 48368 | 186 814 | 27323| 0.20 11.21|
Info: 61000 | 11852 49147 | 221 779 | 26910| 0.19 11.40|
Info: 62000 | 12036 49963 | 184 816 | 26786| 0.22 11.61|
Info: 63000 | 12134 50865 | 98 902 | 27080| 0.19 11.81|
Info: 64000 | 12334 51665 | 200 800 | 26693| 0.25 12.06|
Info: 65000 | 12598 52401 | 264 736 | 26462| 0.22 12.27|
Info: 66000 | 12760 53239 | 162 838 | 26611| 0.19 12.46|
Info: 67000 | 12957 54042 | 197 803 | 26139| 0.20 12.66|
Info: 68000 | 13231 54768 | 274 726 | 25833| 0.21 12.87|
Info: 69000 | 13519 55480 | 288 712 | 25386| 0.21 13.08|
Info: 70000 | 13706 56293 | 187 813 | 25812| 0.21 13.29|
Info: 71000 | 13832 57167 | 126 874 | 25292| 0.18 13.48|
Info: 72000 | 14122 57877 | 290 710 | 25080| 0.21 13.69|
Info: 73000 | 14396 58603 | 274 726 | 24678| 0.24 13.93|
Info: 74000 | 14669 59330 | 273 727 | 24556| 0.24 14.17|
Info: 75000 | 14965 60034 | 296 704 | 24467| 0.23 14.40|
Info: 76000 | 15264 60735 | 299 701 | 24233| 0.24 14.64|
Info: 77000 | 15570 61429 | 306 694 | 23997| 0.24 14.88|
Info: 78000 | 15735 62264 | 165 835 | 23821| 0.21 15.09|
Info: 79000 | 16055 62944 | 320 680 | 23532| 0.23 15.32|
Info: 80000 | 16388 63611 | 333 667 | 23214| 0.23 15.55|
Info: 81000 | 16722 64277 | 334 666 | 22905| 0.25 15.80|
Info: 82000 | 17068 64931 | 346 654 | 22715| 0.24 16.03|
Info: 83000 | 17461 65538 | 393 607 | 22467| 0.25 16.28|
Info: 84000 | 17789 66210 | 328 672 | 22315| 0.24 16.53|
Info: 85000 | 18110 66889 | 321 679 | 22128| 0.25 16.77|
Info: 86000 | 18509 67490 | 399 601 | 21846| 0.25 17.03|
Info: 87000 | 18884 68115 | 375 625 | 21637| 0.26 17.29|
Info: 88000 | 19271 68728 | 387 613 | 21352| 0.25 17.54|
Info: 89000 | 19483 69516 | 212 788 | 22024| 0.23 17.78|
Info: 90000 | 19510 70489 | 27 973 | 22214| 0.19 17.96|
Info: 91000 | 19522 71477 | 12 988 | 22501| 0.18 18.14|
Info: 92000 | 19536 72463 | 14 986 | 22455| 0.18 18.32|
Info: 93000 | 19544 73455 | 8 992 | 22358| 0.17 18.49|
Info: 94000 | 19584 74415 | 40 960 | 21739| 0.18 18.67|
Info: 95000 | 19762 75237 | 178 822 | 21379| 0.22 18.89|
Info: 96000 | 20058 75941 | 296 704 | 21047| 0.24 19.14|
Info: 97000 | 20382 76617 | 324 676 | 20984| 0.25 19.39|
Info: 98000 | 20700 77299 | 318 682 | 20985| 0.25 19.64|
Info: 99000 | 21035 77964 | 335 665 | 20676| 0.26 19.90|
Info: 100000 | 21337 78662 | 302 698 | 20865| 0.25 20.15|
Info: 101000 | 21521 79478 | 184 816 | 20902| 0.22 20.36|
Info: 102000 | 21651 80348 | 130 870 | 21870| 0.20 20.57|
Info: 103000 | 21744 81255 | 93 907 | 21078| 0.21 20.78|
Info: 104000 | 21936 82063 | 192 808 | 22821| 0.23 21.01|
Info: 105000 | 21979 83020 | 43 957 | 21938| 0.20 21.20|
Info: 106000 | 22005 83994 | 26 974 | 20961| 0.18 21.38|
Info: 107000 | 22245 84754 | 240 760 | 20842| 0.24 21.63|
Info: 108000 | 22447 85552 | 202 798 | 21037| 0.24 21.87|
Info: 109000 | 22522 86477 | 75 925 | 20609| 0.19 22.06|
Info: 110000 | 22847 87152 | 325 675 | 20407| 0.24 22.30|
Info: 111000 | 23067 87932 | 220 780 | 20656| 0.24 22.53|
Info: 112000 | 23342 88657 | 275 725 | 20195| 0.24 22.78|
Info: 113000 | 23714 89285 | 372 628 | 20105| 0.25 23.03|
Info: 114000 | 24155 89844 | 441 559 | 19835| 0.27 23.30|
Info: 115000 | 24559 90440 | 404 596 | 19654| 0.27 23.57|
Info: 116000 | 24957 91042 | 398 602 | 19417| 0.25 23.81|
Info: 117000 | 25363 91636 | 406 594 | 19212| 0.27 24.08|
Info: 118000 | 25829 92170 | 466 534 | 18940| 0.25 24.33|
Info: 119000 | 26253 92746 | 424 576 | 18695| 0.26 24.59|
Info: 120000 | 26667 93332 | 414 586 | 18516| 0.29 24.88|
Info: 121000 | 27014 93985 | 347 653 | 18383| 0.26 25.13|
Info: 122000 | 27408 94591 | 394 606 | 18150| 0.27 25.41|
Info: 123000 | 27926 95073 | 518 482 | 17948| 0.28 25.68|
Info: 124000 | 28358 95641 | 432 568 | 17870| 0.27 25.96|
Info: 125000 | 28792 96207 | 434 566 | 17705| 0.30 26.26|
Info: 126000 | 29298 96701 | 506 494 | 17549| 0.28 26.54|
Info: 127000 | 29889 97110 | 591 409 | 17376| 0.26 26.80|
Info: 128000 | 30356 97643 | 467 533 | 17283| 0.29 27.09|
Info: 129000 | 30979 98020 | 623 377 | 17098| 0.25 27.34|
Info: 130000 | 31534 98465 | 555 445 | 16903| 0.26 27.61|
Info: 131000 | 32106 98893 | 572 428 | 16684| 0.28 27.89|
Info: 132000 | 32478 99521 | 372 628 | 16637| 0.24 28.14|
Info: 133000 | 32992 100007 | 514 486 | 16405| 0.25 28.38|
Info: 134000 | 33559 100440 | 567 433 | 16122| 0.26 28.64|
Info: 135000 | 34037 100962 | 478 522 | 16090| 0.29 28.93|
Info: 136000 | 34467 101532 | 430 570 | 15934| 0.29 29.22|
Info: 137000 | 35021 101978 | 554 446 | 15662| 0.27 29.49|
Info: 138000 | 35481 102518 | 460 540 | 15409| 0.26 29.75|
Info: 139000 | 35900 103070 | 419 552 | 15223| 0.31 30.06|
Info: 140000 | 36314 103656 | 414 586 | 15182| 0.30 30.36|
Info: 141000 | 36873 104059 | 559 403 | 14917| 0.29 30.64|
Info: 142000 | 37176 104729 | 303 670 | 14916| 0.19 30.84|
Info: 143000 | 37408 105491 | 232 762 | 14841| 0.22 31.06|
Info: 144000 | 37891 105971 | 483 480 | 14602| 0.30 31.35|
Info: 145000 | 38491 106307 | 600 336 | 14373| 0.24 31.60|
Info: 146000 | 39060 106697 | 569 390 | 14092| 0.26 31.86|
Info: 147000 | 39555 107132 | 495 435 | 13859| 0.23 32.09|
Info: 148000 | 40081 107555 | 526 423 | 13539| 0.26 32.35|
Info: 149000 | 40610 107972 | 529 417 | 13239| 0.25 32.60|
Info: 150000 | 41092 108391 | 482 419 | 12868| 0.24 32.84|
Info: 151000 | 41645 108790 | 553 399 | 12640| 0.25 33.09|
Info: 152000 | 41946 109459 | 301 669 | 12619| 0.23 33.32|
Info: 153000 | 42442 109945 | 496 486 | 12360| 0.27 33.59|
Info: 154000 | 42928 110398 | 486 453 | 11991| 0.32 33.91|
Info: 155000 | 43353 110926 | 425 528 | 11740| 0.28 34.19|
Info: 156000 | 43705 111541 | 352 615 | 11299| 0.29 34.48|
Info: 157000 | 43879 112356 | 174 815 | 10584| 0.16 34.64|
Info: 158000 | 43949 113280 | 70 924 | 9695| 0.13 34.77|
Info: 159000 | 44012 114211 | 63 931 | 8800| 0.11 34.88|
Info: 160000 | 44040 115173 | 28 962 | 7828| 0.09 34.97|
Info: 161000 | 44118 116089 | 78 916 | 6932| 0.13 35.10|
Info: 162000 | 44185 117002 | 67 913 | 6023| 0.12 35.22|
Info: 163000 | 44301 117881 | 116 879 | 5164| 0.15 35.37|
Info: 164000 | 44440 118728 | 139 847 | 4322| 0.16 35.53|
Info: 165000 | 44718 119445 | 278 717 | 3745| 0.29 35.82|
Info: 166000 | 45193 119965 | 475 520 | 3780| 0.42 36.23|
Info: 167000 | 45616 120539 | 423 574 | 3492| 0.41 36.65|
Info: 168000 | 45986 121159 | 370 620 | 3094| 0.32 36.96|
Info: 169000 | 46409 121732 | 423 573 | 2727| 0.34 37.30|
Info: 170000 | 46868 122263 | 459 531 | 2343| 0.32 37.62|
Info: 171000 | 47327 122795 | 459 532 | 2151| 0.36 37.97|
Info: 172000 | 47772 123343 | 445 548 | 1865| 0.37 38.35|
Info: 173000 | 48191 123922 | 419 579 | 1474| 0.36 38.71|
Info: 174000 | 48693 124418 | 502 496 | 1129| 0.39 39.10|
Info: 175000 | 49224 124887 | 531 469 | 802| 0.40 39.49|
Info: 176000 | 49778 125324 | 554 437 | 573| 0.38 39.87|
Info: 176623 | 49825 125602 | 47 278 | 0| 0.17 40.05|
Info: Routing complete.
Info: Router1 time 40.05s
Info: Checksum: 0xd6c2e009
Info: Critical path report for clock '$glbnet$clk_o' (posedge -> posedge):
Info: curr total
Info: 0.5 0.5 Source SOC.Core.Control_Unit.state_TRELLIS_FF_Q_3.Q
Info: 1.1 1.6 Net SOC.Core.Control_Unit.nextstate_LUT4_Z_3_B[0] (64,16) -> (65,15)
Info: Sink SOC.Memory.address_LUT4_Z_C_LUT4_Z_D_LUT4_Z.D
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:42.3-49.2
Info: Risco-5/src/core/core.v:97.14-114.2
Info: Risco-5/src/core/control_unit.v:47.11-47.16
Info: Risco-5/src/peripheral/soc.v:28.3-36.2
Info: 0.2 1.8 Source SOC.Memory.address_LUT4_Z_C_LUT4_Z_D_LUT4_Z.F
Info: 1.7 3.5 Net SOC.Memory.address_LUT4_Z_C_LUT4_Z_D[2] (65,15) -> (60,6)
Info: Sink SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 3.7 Source SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_LUT4_Z.F
Info: 2.1 5.9 Net SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0 (60,6) -> (69,17)
Info: Sink SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB0.B
Info: 0.4 6.3 Source SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB0.FCO
Info: 0.0 6.3 Net SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_FCI_INT (69,17) -> (69,17)
Info: Sink SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB1.FCI
Info: 0.0 6.3 Source SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB1.FCO
Info: 0.0 6.3 Net SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0_COUT (69,17) -> (69,17)
Info: Sink SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:42.3-49.2
Info: Risco-5/src/peripheral/bus.v:54.5-54.37
Info: Risco-5/src/peripheral/soc.v:51.5-81.2
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 6.4 Source SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB0.FCO
Info: 0.0 6.4 Net SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_FCI_INT (69,17) -> (69,17)
Info: Sink SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB1.FCI
Info: 0.0 6.4 Source SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB1.FCO
Info: 0.0 6.4 Net SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0_COUT (69,17) -> (69,17)
Info: Sink SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:42.3-49.2
Info: Risco-5/src/peripheral/bus.v:54.5-54.37
Info: Risco-5/src/peripheral/soc.v:51.5-81.2
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 6.5 Source SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB0.FCO
Info: 0.0 6.5 Net SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_FCI_INT (69,17) -> (69,17)
Info: Sink SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB1.FCI
Info: 0.0 6.5 Source SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB1.FCO
Info: 0.0 6.5 Net SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0_COUT (69,17) -> (70,17)
Info: Sink SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:42.3-49.2
Info: Risco-5/src/peripheral/bus.v:54.5-54.37
Info: Risco-5/src/peripheral/soc.v:51.5-81.2
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 6.5 Source SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB0.FCO
Info: 0.0 6.5 Net SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_FCI_INT (70,17) -> (70,17)
Info: Sink SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB1.FCI
Info: 0.0 6.5 Source SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB1.FCO
Info: 0.0 6.5 Net SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0_COUT (70,17) -> (70,17)
Info: Sink SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:42.3-49.2
Info: Risco-5/src/peripheral/bus.v:54.5-54.37
Info: Risco-5/src/peripheral/soc.v:51.5-81.2
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 6.6 Source SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB0.FCO
Info: 0.0 6.6 Net SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_FCI_INT (70,17) -> (70,17)
Info: Sink SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB1.FCI
Info: 0.0 6.6 Source SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB1.FCO
Info: 0.0 6.6 Net SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0_COUT (70,17) -> (70,17)
Info: Sink SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:42.3-49.2
Info: Risco-5/src/peripheral/bus.v:54.5-54.37
Info: Risco-5/src/peripheral/soc.v:51.5-81.2
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 6.7 Source SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB0.FCO
Info: 0.0 6.7 Net SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_FCI_INT (70,17) -> (70,17)
Info: Sink SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB1.FCI
Info: 0.0 6.7 Source SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB1.FCO
Info: 0.0 6.7 Net SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0_COUT (70,17) -> (70,17)
Info: Sink SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:42.3-49.2
Info: Risco-5/src/peripheral/bus.v:54.5-54.37
Info: Risco-5/src/peripheral/soc.v:51.5-81.2
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 6.7 Source SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB0.FCO
Info: 0.0 6.7 Net SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_FCI_INT (70,17) -> (70,17)
Info: Sink SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB1.FCI
Info: 0.0 6.7 Source SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB1.FCO
Info: 0.0 6.7 Net SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0_COUT (70,17) -> (71,17)
Info: Sink SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:42.3-49.2
Info: Risco-5/src/peripheral/bus.v:54.5-54.37
Info: Risco-5/src/peripheral/soc.v:51.5-81.2
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 6.8 Source SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB0.FCO
Info: 0.0 6.8 Net SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_FCI_INT (71,17) -> (71,17)
Info: Sink SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB1.FCI
Info: 0.0 6.8 Source SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB1.FCO
Info: 0.0 6.8 Net SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0_COUT (71,17) -> (71,17)
Info: Sink SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:42.3-49.2
Info: Risco-5/src/peripheral/bus.v:54.5-54.37
Info: Risco-5/src/peripheral/soc.v:51.5-81.2
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 6.9 Source SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB0.FCO
Info: 0.0 6.9 Net SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_FCI_INT (71,17) -> (71,17)
Info: Sink SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB1.FCI
Info: 0.0 6.9 Source SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB1.FCO
Info: 0.0 6.9 Net SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0_COUT (71,17) -> (71,17)
Info: Sink SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:42.3-49.2
Info: Risco-5/src/peripheral/bus.v:54.5-54.37
Info: Risco-5/src/peripheral/soc.v:51.5-81.2
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 7.0 Source SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB0.FCO
Info: 0.0 7.0 Net SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_FCI_INT (71,17) -> (71,17)
Info: Sink SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB1.FCI
Info: 0.0 7.0 Source SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB1.FCO
Info: 0.0 7.0 Net $nextpnr_CCU2C_5$CIN (71,17) -> (71,17)
Info: Sink $nextpnr_CCU2C_5$CCU2_COMB0.FCI
Info: 0.4 7.4 Source $nextpnr_CCU2C_5$CCU2_COMB0.F
Info: 2.7 10.1 Net SOC.Memory.address_LUT4_Z_1_C[1] (71,17) -> (44,25)
Info: Sink SOC.Memory.address_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 10.3 Source SOC.Memory.address_LUT4_Z.F
Info: 2.1 12.4 Net SOC.slave_address[5] (44,25) -> (59,19)
Info: Sink SOC.Memory.memory.0.208$DPRAM_COMB2.A
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:42.3-49.2
Info: Risco-5/src/peripheral/soc.v:21.5-21.18
Info: 0.2 12.7 Source SOC.Memory.memory.0.208$DPRAM_COMB2.F
Info: 0.9 13.6 Net SOC.Memory.memory.0.208_DO_1[3] (59,19) -> (58,20)
Info: Sink SOC.Memory.memory.0.240_DO_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 13.9 Source SOC.Memory.memory.0.240_DO_LUT4_Z.F
Info: 0.7 14.5 Net SOC.Memory.memory.0.240_DO[4] (58,20) -> (58,21)
Info: Sink SOC.Memory.memory.0.200_DO_1_LUT4_C_Z_PFUMX_Z_BLUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 14.8 Source SOC.Memory.memory.0.200_DO_1_LUT4_C_Z_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: 1.1 15.9 Net SOC.Memory.memory.0.200_DO_1_LUT4_C_Z[3] (58,21) -> (57,20)
Info: Sink SOC.Memory.memory.0.200_DO_1_LUT4_C_Z_LUT4_B.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 16.1 Source SOC.Memory.memory.0.200_DO_1_LUT4_C_Z_LUT4_B.F
Info: 1.1 17.2 Net SOC.Memory.memory.0.32_DO_LUT4_C_Z_LUT4_A_Z[2] (57,20) -> (56,24)
Info: Sink SOC.Core.read_data_LUT4_Z_2_D_LUT4_Z_D_LUT4_Z_A_LUT4_Z_1.C
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 17.4 Source SOC.Core.read_data_LUT4_Z_2_D_LUT4_Z_D_LUT4_Z_A_LUT4_Z_1.F
Info: 1.3 18.7 Net SOC.Core.read_data_LUT4_Z_2_D_LUT4_Z_D_LUT4_Z_A[3] (56,24) -> (63,21)
Info: Sink SOC.Core.read_data_LUT4_Z_2_D_LUT4_Z_D_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 18.9 Source SOC.Core.read_data_LUT4_Z_2_D_LUT4_Z_D_LUT4_Z.F
Info: 0.8 19.7 Net SOC.Core.read_data_LUT4_Z_2_D_LUT4_Z_D[3] (63,21) -> (66,19)
Info: Sink SOC.Core.read_data_LUT4_Z_2_D_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 20.0 Source SOC.Core.read_data_LUT4_Z_2_D_LUT4_Z.F
Info: 0.8 20.7 Net SOC.Core.read_data_LUT4_Z_2_D[3] (66,19) -> (66,15)
Info: Sink SOC.Core.read_data_LUT4_Z_2.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 21.0 Source SOC.Core.read_data_LUT4_Z_2.F
Info: 1.2 22.2 Net SOC.read_data[2] (66,15) -> (62,16)
Info: Sink SOC.Core.instruction_register_TRELLIS_FF_Q_29.M
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:42.3-49.2
Info: Risco-5/src/peripheral/soc.v:20.34-20.43
Info: 0.0 22.2 Setup SOC.Core.instruction_register_TRELLIS_FF_Q_29.M
Info: 4.7 ns logic, 17.5 ns routing
Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
Info: curr total
Info: 0.5 0.5 Source ClkDivider.clk_counter_TRELLIS_FF_Q_27.Q
Info: 1.1 1.6 Net ClkDivider.clk_counter[4] (32,4) -> (32,5)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.B
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:15.3-23.2
Info: Risco-5/debug/clk_divider.v:14.26-14.37
Info: 0.4 2.1 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: 0.0 2.1 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (32,5) -> (32,5)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: 0.0 2.1 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: 0.0 2.1 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (32,5) -> (32,5)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:15.3-23.2
Info: Risco-5/debug/clk_divider.v:40.12-40.38
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 2.1 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: 0.0 2.1 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (32,5) -> (32,5)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: 0.0 2.1 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: 0.0 2.1 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (32,5) -> (32,5)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:15.3-23.2
Info: Risco-5/debug/clk_divider.v:40.12-40.38
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 2.2 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: 0.0 2.2 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (32,5) -> (32,5)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: 0.0 2.2 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: 0.0 2.2 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (32,5) -> (33,5)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:15.3-23.2
Info: Risco-5/debug/clk_divider.v:40.12-40.38
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 2.3 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: 0.0 2.3 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (33,5) -> (33,5)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: 0.0 2.3 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: 0.0 2.3 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (33,5) -> (33,5)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:15.3-23.2
Info: Risco-5/debug/clk_divider.v:40.12-40.38
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 2.3 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: 0.0 2.3 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (33,5) -> (33,5)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: 0.0 2.3 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: 0.0 2.3 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (33,5) -> (33,5)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:15.3-23.2
Info: Risco-5/debug/clk_divider.v:40.12-40.38
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 2.4 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: 0.0 2.4 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (33,5) -> (33,5)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: 0.0 2.4 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: 0.0 2.4 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (33,5) -> (33,5)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:15.3-23.2
Info: Risco-5/debug/clk_divider.v:40.12-40.38
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 2.5 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: 0.0 2.5 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (33,5) -> (33,5)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: 0.0 2.5 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: 0.0 2.5 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (33,5) -> (34,5)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:15.3-23.2
Info: Risco-5/debug/clk_divider.v:40.12-40.38
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 2.6 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: 0.0 2.6 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (34,5) -> (34,5)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: 0.0 2.6 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: 0.0 2.6 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (34,5) -> (34,5)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:15.3-23.2
Info: Risco-5/debug/clk_divider.v:40.12-40.38
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 2.6 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: 0.0 2.6 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (34,5) -> (34,5)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: 0.0 2.6 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: 0.0 2.6 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (34,5) -> (34,5)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:15.3-23.2
Info: Risco-5/debug/clk_divider.v:40.12-40.38
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 2.7 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: 0.0 2.7 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (34,5) -> (34,5)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: 0.0 2.7 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: 0.0 2.7 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (34,5) -> (34,5)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:15.3-23.2
Info: Risco-5/debug/clk_divider.v:40.12-40.38
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 2.8 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: 0.0 2.8 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (34,5) -> (34,5)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: 0.0 2.8 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: 0.0 2.8 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (34,5) -> (35,5)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:15.3-23.2
Info: Risco-5/debug/clk_divider.v:40.12-40.38
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 2.8 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: 0.0 2.8 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (35,5) -> (35,5)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: 0.0 2.8 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: 0.0 2.8 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN (35,5) -> (35,5)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:15.3-23.2
Info: Risco-5/debug/clk_divider.v:40.12-40.38
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 2.9 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: 0.0 2.9 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (35,5) -> (35,5)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: 0.0 2.9 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: 0.0 2.9 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN (35,5) -> (35,5)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:15.3-23.2
Info: Risco-5/debug/clk_divider.v:40.12-40.38
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 3.0 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT$CCU2_COMB0.FCO
Info: 0.0 3.0 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT$CCU2_FCI_INT (35,5) -> (35,5)
Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT$CCU2_COMB1.FCI
Info: 0.0 3.0 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT$CCU2_COMB1.FCO
Info: 0.0 3.0 Net $nextpnr_CCU2C_1$CIN (35,5) -> (35,5)
Info: Sink $nextpnr_CCU2C_1$CCU2_COMB0.FCI
Info: 0.4 3.4 Source $nextpnr_CCU2C_1$CCU2_COMB0.F
Info: 0.5 3.9 Net reset_LUT4_B_C_LUT4_Z_D (35,5) -> (35,3)
Info: Sink reset_LUT4_B_C_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 4.2 Source reset_LUT4_B_C_LUT4_Z.F
Info: 0.4 4.6 Net reset_LUT4_B_C[1] (35,3) -> (34,3)
Info: Sink reset_LUT4_B.C
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 4.8 Source reset_LUT4_B.F
Info: 0.6 5.5 Net reset_LUT4_B_Z (34,3) -> (35,4)
Info: Sink ClkDivider.clk_counter_TRELLIS_FF_Q_9.LSR
Info: 0.4 5.9 Setup ClkDivider.clk_counter_TRELLIS_FF_Q_9.LSR
Info: 3.2 ns logic, 2.7 ns routing
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
Info: curr total
Info: 0.0 0.0 Source reset$tr_io.O
Info: 3.6 3.6 Net reset$TRELLIS_IO_IN (0,29) -> (34,3)
Info: Sink reset_LUT4_B.B
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 3.9 Source reset_LUT4_B.F
Info: 0.6 4.5 Net reset_LUT4_B_Z (34,3) -> (35,4)
Info: Sink ClkDivider.clk_counter_TRELLIS_FF_Q_9.LSR
Info: 0.4 4.9 Setup ClkDivider.clk_counter_TRELLIS_FF_Q_9.LSR
Info: 0.7 ns logic, 4.3 ns routing
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk_o':
Info: curr total
Info: 0.0 0.0 Source gpios[4]$tr_io.O
Info: 2.8 2.8 Net gpios[4]$TRELLIS_IO_IN (0,29) -> (38,29)
Info: Sink SOC.GPIOS.Gpios[4].direction_LUT4_C.A
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:7.16-7.21
Info: 0.2 3.0 Source SOC.GPIOS.Gpios[4].direction_LUT4_C.F
Info: 0.0 3.0 Net SOC.GPIOS.Gpios[4].direction_LUT4_C_Z (38,29) -> (38,29)
Info: Sink SOC.GPIOS.Gpios[4].direction_LUT4_C_Z_PFUMX_ALUT_BLUT_LUT4_Z.F1
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:133.22-133.24
Info: 0.2 3.2 Source SOC.GPIOS.Gpios[4].direction_LUT4_C_Z_PFUMX_ALUT_BLUT_LUT4_Z.OFX
Info: 0.9 4.1 Net SOC.GPIOS.Gpios[4].direction_LUT4_C_Z_PFUMX_ALUT_Z[1] (38,29) -> (39,28)
Info: Sink SOC.Core.read_data_LUT4_Z_4.B
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 4.3 Source SOC.Core.read_data_LUT4_Z_4.F
Info: 2.4 6.7 Net SOC.read_data[4] (39,28) -> (59,17)
Info: Sink SOC.Core.instruction_register_TRELLIS_FF_Q_27.M
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:42.3-49.2
Info: Risco-5/src/peripheral/soc.v:20.34-20.43
Info: 0.0 6.7 Setup SOC.Core.instruction_register_TRELLIS_FF_Q_27.M
Info: 0.6 ns logic, 6.1 ns routing
Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
Info: curr total
Info: 0.5 0.5 Source ClkDivider.clk_o_auto_TRELLIS_FF_Q.Q
Info: 3.7 4.2 Net clk_o (33,3) -> (82,18)
Info: Sink led_LUT4_Z_4.D
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:10.6-10.11
Info: 0.2 4.5 Source led_LUT4_Z_4.F
Info: 1.3 5.7 Net led[7]$TRELLIS_IO_OUT (82,18) -> (90,20)
Info: Sink led[7]$tr_io.I
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:6.22-6.25
Info: 0.8 ns logic, 5.0 ns routing
Info: Critical path report for cross-domain path 'posedge $glbnet$clk_o' -> '<async>':
Info: curr total
Info: 0.5 0.5 Source SOC.Leds.data_TRELLIS_FF_Q_31.Q
Info: 2.9 3.4 Net SOC.Leds.data[0] (70,30) -> (59,57)
Info: Sink led_LUT4_Z_1.D
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:42.3-49.2
Info: Risco-5/src/peripheral/leds.v:15.12-15.16
Info: Risco-5/src/peripheral/soc.v:83.6-92.2
Info: 0.2 3.7 Source led_LUT4_Z_1.F
Info: 3.9 7.6 Net led[0]$TRELLIS_IO_OUT (59,57) -> (0,59)
Info: Sink led[0]$tr_io.I
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:6.22-6.25
Info: 0.8 ns logic, 6.8 ns routing
Info: Max frequency for clock '$glbnet$clk_o': 45.11 MHz (PASS at 12.00 MHz)
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 169.35 MHz (PASS at 25.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 4.92 ns
Info: Max delay <async> -> posedge $glbnet$clk_o : 6.73 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 5.73 ns
Info: Max delay posedge $glbnet$clk_o -> <async> : 7.56 ns
Info: Slack histogram:
Info: legend: * represents 162 endpoint(s)
Info: + represents [1,162) endpoint(s)
Info: [ 34095, 36502) |+
Info: [ 36502, 38909) |+
Info: [ 38909, 41316) |
Info: [ 41316, 43723) |
Info: [ 43723, 46130) |
Info: [ 46130, 48537) |
Info: [ 48537, 50944) |
Info: [ 50944, 53351) |
Info: [ 53351, 55758) |
Info: [ 55758, 58165) |
Info: [ 58165, 60572) |
Info: [ 60572, 62979) |+
Info: [ 62979, 65386) |+
Info: [ 65386, 67793) |+
Info: [ 67793, 70200) |***************+
Info: [ 70200, 72607) |************************************************************
Info: [ 72607, 75014) |+
Info: [ 75014, 77421) |*******+
Info: [ 77421, 79828) |******+
Info: [ 79828, 82235) |+
5 warnings, 0 errors
Info: Program finished normally.
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (ECPPACK)
[Pipeline] sh
+ /eda/oss-cad-suite/bin/ecppack --compress --input ./build/out.config --bit ./build/out.bit
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (FPGA Flash)
[Pipeline] parallel
[Pipeline] { (Branch: openFPGAloader ECP5)
[Pipeline] { (Branch: openFPGAloader Tangnano 20k)
[Pipeline] stage
[Pipeline] { (openFPGAloader ECP5)
[Pipeline] stage
[Pipeline] { (openFPGAloader Tangnano 20k)
[Pipeline] script
[Pipeline] {
[Pipeline] script
[Pipeline] {
[Pipeline] lock
Trying to acquire lock on [ecp5]
Resource [ecp5] did not exist. Created.
Lock acquired on [ecp5]
[Pipeline] {
[Pipeline] lock
Trying to acquire lock on [tangnano20k]
Resource [tangnano20k] did not exist. Created.
Lock acquired on [tangnano20k]
[Pipeline] {
[Pipeline] echo
FPGA ECP5 Broqueada
[Pipeline] sh
[Pipeline] echo
FPGA TangNano Broqueada
[Pipeline] sh
+ /eda/oss-cad-suite/bin/openFPGALoader -b colorlight-i9 ./build/out.bit
Found 1 compatible device:
0x0d28 0x0204 0x3 DAPLink CMSIS-DAP
Open file: DONE
Parse file: DONE
Enable configuration: DONE
SRAM erase: DONE
+ echo gravando na tang nano
gravando na tang nano
[Pipeline] }
Lock released on resource [tangnano20k]
[Pipeline] // lock
[Pipeline] }
[Pipeline] // script
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Loading: [===== ] 9.57%
Loading: [========== ] 19.15%
Loading: [=============== ] 28.72%
Loading: [==================== ] 38.30%
Loading: [======================== ] 47.87%
Loading: [============================= ] 57.45%
Loading: [================================== ] 67.02%
Loading: [======================================= ] 76.60%
Loading: [============================================ ] 86.17%
Loading: [================================================ ] 95.75%
Loading: [==================================================] 100.00%
Done
Disable configuration: DONE
[Pipeline] }
Lock released on resource [ecp5]
[Pipeline] // lock
[Pipeline] }
[Pipeline] // script
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Testes)
[Pipeline] parallel
[Pipeline] { (Branch: ECP5 - Testes)
[Pipeline] { (Branch: TangNano - Testes)
[Pipeline] stage
[Pipeline] { (ECP5 - Testes)
[Pipeline] stage
[Pipeline] { (TangNano - Testes)
[Pipeline] script
[Pipeline] {
[Pipeline] script
[Pipeline] {
[Pipeline] echo
Rodando teste na ECP5
[Pipeline] lock
Trying to acquire lock on [ecp5]
Resource [ecp5] did not exist. Created.
Lock acquired on [ecp5]
[Pipeline] {
[Pipeline] echo
Rodando teste na tang nano
[Pipeline] lock
Trying to acquire lock on [tangnano20k]
Resource [tangnano20k] did not exist. Created.
Lock acquired on [tangnano20k]
[Pipeline] {
[Pipeline] echo
FPGA ECP5 Broqueada
[Pipeline] sh
[Pipeline] echo
FPGA TangNano Broqueada
[Pipeline] sh
+ echo testando na ecp5
testando na ecp5
[Pipeline] }
Lock released on resource [ecp5]
+ echo testando na tang nano
testando na tang nano
[Pipeline] // lock
[Pipeline] echo
ECP5 liberada
[Pipeline] }
[Pipeline] }
Lock released on resource [tangnano20k]
[Pipeline] // script
[Pipeline] // lock
[Pipeline] }
[Pipeline] echo
TangNano liberada
[Pipeline] }
[Pipeline] // stage
[Pipeline] // script
[Pipeline] }
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // node
[Pipeline] End of Pipeline
Finished: SUCCESS
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