Console Output

Started by timer
[Pipeline] Start of Pipeline
[Pipeline] node
Running on Jenkins in /var/lib/jenkins/workspace/Risco 5
[Pipeline] {
[Pipeline] stage
[Pipeline] { (Git Clone)
[Pipeline] sh
+ rm -Rf Risco-5/ build/
[Pipeline] sh
+ git clone https://github.com/JN513/Risco-5
Cloning into 'Risco-5'...
[Pipeline] sh
+ cd Risco-5
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (IVerilog)
[Pipeline] sh
+ mkdir -p build
[Pipeline] sh
+ cp Risco-5/software/memory/add.hex Risco-5/software/memory/generic.hex
[Pipeline] sh
+ /eda/oss-cad-suite/bin/iverilog -o build/soc_test.o -s soc_tb Risco-5/src/core/alu.v Risco-5/src/core/alu_control.v Risco-5/src/core/control_unit.v Risco-5/src/core/core.v Risco-5/src/core/immediate_generator.v Risco-5/src/core/mux.v Risco-5/src/core/pc.v Risco-5/src/core/registers.v Risco-5/src/peripheral/bus.v Risco-5/src/peripheral/gpio.v Risco-5/src/peripheral/gpios.v Risco-5/src/peripheral/leds.v Risco-5/src/peripheral/memory.v Risco-5/src/peripheral/soc.v Risco-5/src/peripheral/uart.v Risco-5/src/peripheral/uart_rx.v Risco-5/src/peripheral/uart_tx.v Risco-5/tests/soc_test.v
[Pipeline] sh
+ /eda/oss-cad-suite/bin/vvp build/soc_test.o
ERROR: Risco-5/src/peripheral/memory.v:27: $readmemh: Unable to open software/memory/generic.hex for reading.
VCD info: dumpfile build/soc.vcd opened for output.
Risco-5/tests/soc_test.v:32: $finish called at 566 (1s)
[Pipeline] sh
+ rm -f Risco-5/software/memory/generic.hex
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Síntese)
[Pipeline] parallel
[Pipeline] { (Branch: OSS-Cad-Suite)
[Pipeline] { (Branch: Gowin)
[Pipeline] stage
[Pipeline] { (OSS-Cad-Suite)
[Pipeline] stage
[Pipeline] { (Gowin)
[Pipeline] stage
[Pipeline] { (Yosys)
[Pipeline] sh
[Pipeline] sh
+ rm -rf Risco-5/impl/pnr
[Pipeline] sh
+ /eda/oss-cad-suite/bin/yosys -p                                          read_verilog Risco-5/fpga/ecp5/main.v;                                         read_verilog Risco-5/debug/clk_divider.v;                                         read_verilog Risco-5/debug/reset.v;                                         read_verilog Risco-5/src/core/*.v;                                         read_verilog Risco-5/src/peripheral/*.v;                                         synth_ecp5 -json ./build/out.json -abc9                                     

 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/

 Yosys 0.36+8 (git sha1 fb4cbfa73, clang 10.0.0-4ubuntu1 -fPIC -Os)


-- Running command `                                         read_verilog Risco-5/fpga/ecp5/main.v;                                         read_verilog Risco-5/debug/clk_divider.v;                                         read_verilog Risco-5/debug/reset.v;                                         read_verilog Risco-5/src/core/*.v;                                         read_verilog Risco-5/src/peripheral/*.v;                                         synth_ecp5 -json ./build/out.json -abc9                                     ' --

1. Executing Verilog-2005 frontend: Risco-5/fpga/ecp5/main.v
Parsing Verilog input from `Risco-5/fpga/ecp5/main.v' to AST representation.
Generating RTLIL representation for module `\top'.
Successfully finished Verilog frontend.

2. Executing Verilog-2005 frontend: Risco-5/debug/clk_divider.v
Parsing Verilog input from `Risco-5/debug/clk_divider.v' to AST representation.
Generating RTLIL representation for module `\ClkDivider'.
Successfully finished Verilog frontend.

3. Executing Verilog-2005 frontend: Risco-5/debug/reset.v
Parsing Verilog input from `Risco-5/debug/reset.v' to AST representation.
Generating RTLIL representation for module `\ResetBootSystem'.
Successfully finished Verilog frontend.

4. Executing Verilog-2005 frontend: Risco-5/src/core/alu.v
Parsing Verilog input from `Risco-5/src/core/alu.v' to AST representation.
Generating RTLIL representation for module `\ALU'.
Successfully finished Verilog frontend.

5. Executing Verilog-2005 frontend: Risco-5/src/core/alu_control.v
Parsing Verilog input from `Risco-5/src/core/alu_control.v' to AST representation.
Generating RTLIL representation for module `\ALU_Control'.
Successfully finished Verilog frontend.

6. Executing Verilog-2005 frontend: Risco-5/src/core/control_unit.v
Parsing Verilog input from `Risco-5/src/core/control_unit.v' to AST representation.
Generating RTLIL representation for module `\Control_Unit'.
Successfully finished Verilog frontend.

7. Executing Verilog-2005 frontend: Risco-5/src/core/core.v
Parsing Verilog input from `Risco-5/src/core/core.v' to AST representation.
Generating RTLIL representation for module `\Core'.
Risco-5/src/core/core.v:76: Warning: Identifier `\pc_source' is implicitly declared.
Successfully finished Verilog frontend.

8. Executing Verilog-2005 frontend: Risco-5/src/core/immediate_generator.v
Parsing Verilog input from `Risco-5/src/core/immediate_generator.v' to AST representation.
Generating RTLIL representation for module `\Immediate_Generator'.
Successfully finished Verilog frontend.

9. Executing Verilog-2005 frontend: Risco-5/src/core/mux.v
Parsing Verilog input from `Risco-5/src/core/mux.v' to AST representation.
Generating RTLIL representation for module `\MUX'.
Successfully finished Verilog frontend.

10. Executing Verilog-2005 frontend: Risco-5/src/core/pc.v
Parsing Verilog input from `Risco-5/src/core/pc.v' to AST representation.
Generating RTLIL representation for module `\PC'.
Successfully finished Verilog frontend.

11. Executing Verilog-2005 frontend: Risco-5/src/core/registers.v
Parsing Verilog input from `Risco-5/src/core/registers.v' to AST representation.
Generating RTLIL representation for module `\Registers'.
Successfully finished Verilog frontend.

12. Executing Verilog-2005 frontend: Risco-5/src/peripheral/bus.v
Parsing Verilog input from `Risco-5/src/peripheral/bus.v' to AST representation.
Generating RTLIL representation for module `\BUS'.
Successfully finished Verilog frontend.

13. Executing Verilog-2005 frontend: Risco-5/src/peripheral/gpio.v
Parsing Verilog input from `Risco-5/src/peripheral/gpio.v' to AST representation.
Warning: Yosys has only limited support for tri-state logic at the moment. (Risco-5/src/peripheral/gpio.v:9)
Generating RTLIL representation for module `\GPIO'.
Successfully finished Verilog frontend.

14. Executing Verilog-2005 frontend: Risco-5/src/peripheral/gpios.v
Parsing Verilog input from `Risco-5/src/peripheral/gpios.v' to AST representation.
Generating RTLIL representation for module `\GPIOS'.
Successfully finished Verilog frontend.

15. Executing Verilog-2005 frontend: Risco-5/src/peripheral/leds.v
Parsing Verilog input from `Risco-5/src/peripheral/leds.v' to AST representation.
Generating RTLIL representation for module `\LEDs'.
Successfully finished Verilog frontend.

16. Executing Verilog-2005 frontend: Risco-5/src/peripheral/memory.v
Parsing Verilog input from `Risco-5/src/peripheral/memory.v' to AST representation.
Generating RTLIL representation for module `\Memory'.
Successfully finished Verilog frontend.

17. Executing Verilog-2005 frontend: Risco-5/src/peripheral/soc.v
Parsing Verilog input from `Risco-5/src/peripheral/soc.v' to AST representation.
Generating RTLIL representation for module `\Risco_5_SOC'.
Successfully finished Verilog frontend.

18. Executing Verilog-2005 frontend: Risco-5/src/peripheral/uart.v
Parsing Verilog input from `Risco-5/src/peripheral/uart.v' to AST representation.
Generating RTLIL representation for module `\UART'.
Successfully finished Verilog frontend.

19. Executing Verilog-2005 frontend: Risco-5/src/peripheral/uart_rx.v
Parsing Verilog input from `Risco-5/src/peripheral/uart_rx.v' to AST representation.
Generating RTLIL representation for module `\uart_tool_rx'.
Successfully finished Verilog frontend.

20. Executing Verilog-2005 frontend: Risco-5/src/peripheral/uart_tx.v
Parsing Verilog input from `Risco-5/src/peripheral/uart_tx.v' to AST representation.
Generating RTLIL representation for module `\uart_tool_tx'.
Successfully finished Verilog frontend.

21. Executing SYNTH_ECP5 pass.

21.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v' to AST representation.
Generating RTLIL representation for module `\LUT4'.
Generating RTLIL representation for module `\$__ABC9_LUT5'.
Generating RTLIL representation for module `\$__ABC9_LUT6'.
Generating RTLIL representation for module `\$__ABC9_LUT7'.
Generating RTLIL representation for module `\L6MUX21'.
Generating RTLIL representation for module `\CCU2C'.
Generating RTLIL representation for module `\TRELLIS_RAM16X2'.
Generating RTLIL representation for module `\PFUMX'.
Generating RTLIL representation for module `\TRELLIS_DPR16X4'.
Generating RTLIL representation for module `\DPR16X4C'.
Generating RTLIL representation for module `\LUT2'.
Generating RTLIL representation for module `\TRELLIS_FF'.
Generating RTLIL representation for module `\TRELLIS_IO'.
Generating RTLIL representation for module `\INV'.
Generating RTLIL representation for module `\TRELLIS_COMB'.
Generating RTLIL representation for module `\DP16KD'.
Generating RTLIL representation for module `\FD1P3AX'.
Generating RTLIL representation for module `\FD1P3AY'.
Generating RTLIL representation for module `\FD1P3BX'.
Generating RTLIL representation for module `\FD1P3DX'.
Generating RTLIL representation for module `\FD1P3IX'.
Generating RTLIL representation for module `\FD1P3JX'.
Generating RTLIL representation for module `\FD1S3AX'.
Generating RTLIL representation for module `\FD1S3AY'.
Generating RTLIL representation for module `\FD1S3BX'.
Generating RTLIL representation for module `\FD1S3DX'.
Generating RTLIL representation for module `\FD1S3IX'.
Generating RTLIL representation for module `\FD1S3JX'.
Generating RTLIL representation for module `\IFS1P3BX'.
Generating RTLIL representation for module `\IFS1P3DX'.
Generating RTLIL representation for module `\IFS1P3IX'.
Generating RTLIL representation for module `\IFS1P3JX'.
Generating RTLIL representation for module `\OFS1P3BX'.
Generating RTLIL representation for module `\OFS1P3DX'.
Generating RTLIL representation for module `\OFS1P3IX'.
Generating RTLIL representation for module `\OFS1P3JX'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\IBPU'.
Generating RTLIL representation for module `\IBPD'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\OBZPU'.
Generating RTLIL representation for module `\OBZPD'.
Generating RTLIL representation for module `\OBCO'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\BBPU'.
Generating RTLIL representation for module `\BBPD'.
Generating RTLIL representation for module `\ILVDS'.
Generating RTLIL representation for module `\OLVDS'.
Successfully finished Verilog frontend.

21.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_bb.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_bb.v' to AST representation.
Generating RTLIL representation for module `\MULT18X18D'.
Generating RTLIL representation for module `\ALU54B'.
Generating RTLIL representation for module `\EHXPLLL'.
Generating RTLIL representation for module `\DTR'.
Generating RTLIL representation for module `\OSCG'.
Generating RTLIL representation for module `\USRMCLK'.
Generating RTLIL representation for module `\JTAGG'.
Generating RTLIL representation for module `\DELAYF'.
Generating RTLIL representation for module `\DELAYG'.
Generating RTLIL representation for module `\IDDRX1F'.
Generating RTLIL representation for module `\IDDRX2F'.
Generating RTLIL representation for module `\IDDR71B'.
Generating RTLIL representation for module `\IDDRX2DQA'.
Generating RTLIL representation for module `\ODDRX1F'.
Generating RTLIL representation for module `\ODDRX2F'.
Generating RTLIL representation for module `\ODDR71B'.
Generating RTLIL representation for module `\OSHX2A'.
Generating RTLIL representation for module `\ODDRX2DQA'.
Generating RTLIL representation for module `\ODDRX2DQSB'.
Generating RTLIL representation for module `\TSHX2DQA'.
Generating RTLIL representation for module `\TSHX2DQSA'.
Generating RTLIL representation for module `\DQSBUFM'.
Generating RTLIL representation for module `\DDRDLLA'.
Generating RTLIL representation for module `\DLLDELD'.
Generating RTLIL representation for module `\CLKDIVF'.
Generating RTLIL representation for module `\ECLKSYNCB'.
Generating RTLIL representation for module `\ECLKBRIDGECS'.
Generating RTLIL representation for module `\DCCA'.
Generating RTLIL representation for module `\DCSC'.
Generating RTLIL representation for module `\DCUA'.
Generating RTLIL representation for module `\EXTREFB'.
Generating RTLIL representation for module `\PCSCLKDIV'.
Generating RTLIL representation for module `\PUR'.
Generating RTLIL representation for module `\GSR'.
Generating RTLIL representation for module `\SGSR'.
Generating RTLIL representation for module `\PDPW16KD'.
Successfully finished Verilog frontend.

21.3. Executing HIERARCHY pass (managing design hierarchy).

21.3.1. Finding top of design hierarchy..
root of   0 design levels: uart_tool_tx        
root of   0 design levels: uart_tool_rx        
root of   1 design levels: UART                
root of   2 design levels: Risco_5_SOC         
root of   0 design levels: Memory              
root of   0 design levels: LEDs                
root of   1 design levels: GPIOS               
root of   0 design levels: GPIO                
root of   0 design levels: BUS                 
root of   0 design levels: Registers           
root of   0 design levels: PC                  
root of   0 design levels: MUX                 
root of   0 design levels: Immediate_Generator 
root of   1 design levels: Core                
root of   0 design levels: Control_Unit        
root of   0 design levels: ALU_Control         
root of   0 design levels: ALU                 
root of   0 design levels: ResetBootSystem     
root of   0 design levels: ClkDivider          
root of   3 design levels: top                 
Automatically selected top as design top module.

21.3.2. Analyzing design hierarchy..
Top module:  \top
Used module:     \Risco_5_SOC
Used module:         \GPIOS
Used module:             \GPIO
Used module:         \UART
Used module:             \uart_tool_tx
Used module:             \uart_tool_rx
Used module:         \LEDs
Used module:         \BUS
Used module:         \Memory
Used module:         \Core
Used module:             \Immediate_Generator
Used module:             \ALU
Used module:             \ALU_Control
Used module:             \Control_Unit
Used module:             \Registers
Used module:             \MUX
Used module:             \PC
Used module:     \ResetBootSystem
Used module:     \ClkDivider
Parameter \CLOCK_FREQ = 25000000
Parameter \BIT_RATE = 9600
Parameter \MEMORY_SIZE = 4096
Parameter \MEMORY_FILE = 248'00101110001011100010111100101110001011100010111101110011011011110110011001110100011101110110000101110010011001010010111101101101011001010110110101101111011100100111100100101111011011000110111101101111011100000011001100101110011010000110010101111000
Parameter \GPIO_WIDHT = 6

21.3.3. Executing AST frontend in derive mode using pre-parsed AST for module `\Risco_5_SOC'.
Parameter \CLOCK_FREQ = 25000000
Parameter \BIT_RATE = 9600
Parameter \MEMORY_SIZE = 4096
Parameter \MEMORY_FILE = 248'00101110001011100010111100101110001011100010111101110011011011110110011001110100011101110110000101110010011001010010111101101101011001010110110101101111011100100111100100101111011011000110111101101111011100000011001100101110011010000110010101111000
Parameter \GPIO_WIDHT = 6
Generating RTLIL representation for module `$paramod$3184ad0c07f8e5ef1997e235d9a61459f8c3c9b2\Risco_5_SOC'.
Parameter \CYCLES = 20

21.3.4. Executing AST frontend in derive mode using pre-parsed AST for module `\ResetBootSystem'.
Parameter \CYCLES = 20
Generating RTLIL representation for module `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100'.
Parameter \COUNTER_BITS = 32

21.3.5. Executing AST frontend in derive mode using pre-parsed AST for module `\ClkDivider'.
Parameter \COUNTER_BITS = 32
Generating RTLIL representation for module `$paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000'.
Parameter \WIDHT = 5

21.3.6. Executing AST frontend in derive mode using pre-parsed AST for module `\GPIOS'.
Parameter \WIDHT = 5
Generating RTLIL representation for module `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000101'.
Parameter \CLOCK_FREQ = 25000000
Parameter \BIT_RATE = 9600

21.3.7. Executing AST frontend in derive mode using pre-parsed AST for module `\UART'.
Parameter \CLOCK_FREQ = 25000000
Parameter \BIT_RATE = 9600
Generating RTLIL representation for module `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART'.
Parameter \MEMORY_FILE = { }
Parameter \MEMORY_SIZE = 4096

21.3.8. Executing AST frontend in derive mode using pre-parsed AST for module `\Memory'.
Parameter \MEMORY_FILE = { }
Parameter \MEMORY_SIZE = 4096
Generating RTLIL representation for module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'.
Parameter \BOOT_ADDRESS = 0

21.3.9. Executing AST frontend in derive mode using pre-parsed AST for module `\Core'.
Parameter \BOOT_ADDRESS = 0
Generating RTLIL representation for module `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000'.
Risco-5/src/core/core.v:76: Warning: Identifier `\pc_source' is implicitly declared.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8

21.3.10. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tool_tx'.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8
Generating RTLIL representation for module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx'.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8

21.3.11. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tool_rx'.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8
Generating RTLIL representation for module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx'.

21.3.12. Analyzing design hierarchy..
Top module:  \top
Used module:     $paramod$3184ad0c07f8e5ef1997e235d9a61459f8c3c9b2\Risco_5_SOC
Used module:         \GPIOS
Used module:             \GPIO
Used module:         \UART
Used module:             $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx
Used module:             $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx
Used module:         \LEDs
Used module:         \BUS
Used module:         \Memory
Used module:         \Core
Used module:             \Immediate_Generator
Used module:             \ALU
Used module:             \ALU_Control
Used module:             \Control_Unit
Used module:             \Registers
Used module:             \MUX
Used module:             \PC
Used module:     $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100
Used module:     $paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000
Parameter \WIDHT = 6

21.3.13. Executing AST frontend in derive mode using pre-parsed AST for module `\GPIOS'.
Parameter \WIDHT = 6
Generating RTLIL representation for module `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110'.
Parameter \CLOCK_FREQ = 25000000
Parameter \BIT_RATE = 9600
Found cached RTLIL representation for module `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART'.
Parameter \MEMORY_FILE = 248'00101110001011100010111100101110001011100010111101110011011011110110011001110100011101110110000101110010011001010010111101101101011001010110110101101111011100100111100100101111011011000110111101101111011100000011001100101110011010000110010101111000
Parameter \MEMORY_SIZE = 4096

21.3.14. Executing AST frontend in derive mode using pre-parsed AST for module `\Memory'.
Parameter \MEMORY_FILE = 248'00101110001011100010111100101110001011100010111101110011011011110110011001110100011101110110000101110010011001010010111101101101011001010110110101101111011100100111100100101111011011000110111101101111011100000011001100101110011010000110010101111000
Parameter \MEMORY_SIZE = 4096
Generating RTLIL representation for module `$paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory'.
Parameter \BOOT_ADDRESS = 0
Found cached RTLIL representation for module `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000'.

21.3.15. Analyzing design hierarchy..
Top module:  \top
Used module:     $paramod$3184ad0c07f8e5ef1997e235d9a61459f8c3c9b2\Risco_5_SOC
Used module:         $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110
Used module:             \GPIO
Used module:         $paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART
Used module:             \uart_tool_tx
Used module:             \uart_tool_rx
Used module:         \LEDs
Used module:         \BUS
Used module:         $paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory
Used module:         $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000
Used module:             \Immediate_Generator
Used module:             \ALU
Used module:             \ALU_Control
Used module:             \Control_Unit
Used module:             \Registers
Used module:             \MUX
Used module:             \PC
Used module:     $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100
Used module:     $paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8
Found cached RTLIL representation for module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx'.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8
Found cached RTLIL representation for module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx'.

21.3.16. Analyzing design hierarchy..
Top module:  \top
Used module:     $paramod$3184ad0c07f8e5ef1997e235d9a61459f8c3c9b2\Risco_5_SOC
Used module:         $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110
Used module:             \GPIO
Used module:         $paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART
Used module:             $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx
Used module:             $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx
Used module:         \LEDs
Used module:         \BUS
Used module:         $paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory
Used module:         $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000
Used module:             \Immediate_Generator
Used module:             \ALU
Used module:             \ALU_Control
Used module:             \Control_Unit
Used module:             \Registers
Used module:             \MUX
Used module:             \PC
Used module:     $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100
Used module:     $paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000

21.3.17. Analyzing design hierarchy..
Top module:  \top
Used module:     $paramod$3184ad0c07f8e5ef1997e235d9a61459f8c3c9b2\Risco_5_SOC
Used module:         $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110
Used module:             \GPIO
Used module:         $paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART
Used module:             $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx
Used module:             $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx
Used module:         \LEDs
Used module:         \BUS
Used module:         $paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory
Used module:         $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000
Used module:             \Immediate_Generator
Used module:             \ALU
Used module:             \ALU_Control
Used module:             \Control_Unit
Used module:             \Registers
Used module:             \MUX
Used module:             \PC
Used module:     $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100
Used module:     $paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000
Removing unused module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'.
Removing unused module `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000101'.
Removing unused module `\uart_tool_tx'.
Removing unused module `\uart_tool_rx'.
Removing unused module `\UART'.
Removing unused module `\Risco_5_SOC'.
Removing unused module `\Memory'.
Removing unused module `\GPIOS'.
Removing unused module `\Core'.
Removing unused module `\ResetBootSystem'.
Removing unused module `\ClkDivider'.
Removed 11 unused modules.

21.4. Executing PROC pass (convert processes to netlists).

21.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$399'.
Found and cleaned up 1 empty switch in `$paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory.$proc$Risco-5/src/peripheral/memory.v:0$676'.
Removing empty process `$paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory.$proc$Risco-5/src/peripheral/memory.v:0$676'.
Cleaned up 2 empty switches.

21.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$506 in module TRELLIS_FF.
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$458 in module DPR16X4C.
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$400 in module TRELLIS_DPR16X4.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:197$655 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:186$653 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.
Marked 2 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:171$645 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:160$642 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.
Marked 2 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:148$636 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.
Marked 3 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:133$631 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:116$626 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:97$617 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.
Marked 4 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:173$604 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:162$602 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.
Marked 2 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:147$594 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.
Marked 4 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:130$580 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.
Marked 3 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:115$574 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:98$569 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/core.v:137$559 in module $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/memory.v:31$667 in module $paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/leds.v:23$163 in module LEDs.
Marked 2 switch rules as full_case in process $proc$Risco-5/src/peripheral/gpios.v:29$661 in module $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.
Marked 2 switch rules as full_case in process $proc$Risco-5/src/core/registers.v:155$69 in module Registers.
Removed 2 dead cases from process $proc$Risco-5/src/core/registers.v:81$68 in module Registers.
Marked 2 switch rules as full_case in process $proc$Risco-5/src/core/registers.v:81$68 in module Registers.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/pc.v:19$64 in module PC.
Removed 1 dead cases from process $proc$Risco-5/src/core/mux.v:10$63 in module MUX.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/mux.v:10$63 in module MUX.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/immediate_generator.v:7$60 in module Immediate_Generator.
Marked 3 switch rules as full_case in process $proc$Risco-5/debug/clk_divider.v:25$520 in module $paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/control_unit.v:119$52 in module Control_Unit.
Marked 4 switch rules as full_case in process $proc$Risco-5/src/core/control_unit.v:76$50 in module Control_Unit.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/control_unit.v:68$49 in module Control_Unit.
Removed 1 dead cases from process $proc$Risco-5/src/core/alu_control.v:9$45 in module ALU_Control.
Marked 4 switch rules as full_case in process $proc$Risco-5/src/core/alu_control.v:9$45 in module ALU_Control.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/alu.v:11$30 in module ALU.
Marked 5 switch rules as full_case in process $proc$Risco-5/debug/reset.v:24$509 in module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.
Removed a total of 4 dead cases.

21.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 8 redundant assignments.
Promoted 137 assignments to connections.

21.4.4. Executing PROC_INIT pass (extract init attributes).
Found init rule in `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$507'.
  Set init value: \Q = 1'0
Found init rule in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:132$657'.
  Set init value: \i = 0
Found init rule in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:114$610'.
  Set init value: \i = 0
Found init rule in `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:0$562'.
  Set init value: \instruction_register = 0
  Set init value: \memory_register = 0
  Set init value: \alu_out_register = 0
  Set init value: \register_data_1 = 0
  Set init value: \register_data_2 = 0
Found init rule in `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART.$proc$Risco-5/src/peripheral/uart.v:0$543'.
  Set init value: \uart_tx_en = 1'0
  Set init value: \uart_tx_data = 8'00000000
Found init rule in `\LEDs.$proc$Risco-5/src/peripheral/leds.v:0$166'.
  Set init value: \data = 33'000000000000000000000000000000000
Found init rule in `\Registers.$proc$Risco-5/src/core/registers.v:0$72'.
  Set init value: \register0 = 0
  Set init value: \register1 = 0
  Set init value: \register2 = 0
  Set init value: \register3 = 0
  Set init value: \register4 = 0
  Set init value: \register5 = 0
  Set init value: \register6 = 0
  Set init value: \register7 = 0
  Set init value: \register8 = 0
  Set init value: \register9 = 0
  Set init value: \register10 = 0
  Set init value: \register11 = 0
  Set init value: \register12 = 0
  Set init value: \register13 = 0
  Set init value: \register14 = 0
  Set init value: \register15 = 0
  Set init value: \register16 = 0
  Set init value: \register17 = 0
  Set init value: \register18 = 0
  Set init value: \register19 = 0
  Set init value: \register20 = 0
  Set init value: \register21 = 0
  Set init value: \register22 = 0
  Set init value: \register23 = 0
  Set init value: \register24 = 0
  Set init value: \register25 = 0
  Set init value: \register26 = 0
  Set init value: \register27 = 0
  Set init value: \register28 = 0
  Set init value: \register29 = 0
  Set init value: \register30 = 0
  Set init value: \register31 = 0
Found init rule in `\PC.$proc$Risco-5/src/core/pc.v:0$67'.
  Set init value: \PC_Register = 0
Found init rule in `$paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.$proc$Risco-5/debug/clk_divider.v:0$532'.
  Set init value: \clk_o_pulse = 1'0
  Set init value: \clk_o_auto = 1'0
  Set init value: \clk_counter = 0
Found init rule in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:0$53'.
  Set init value: \state = 4'0000
  Set init value: \is_immediate = 1'0
  Set init value: \pc_write_cond = 1'0
  Set init value: \pc_write = 1'0
  Set init value: \lorD = 1'0
  Set init value: \memory_read = 1'0
  Set init value: \memory_write = 1'0
  Set init value: \memory_to_reg = 1'0
  Set init value: \ir_write = 1'0
  Set init value: \pc_source = 1'0
  Set init value: \aluop = 2'00
  Set init value: \alu_src_a = 2'00
  Set init value: \alu_src_b = 2'00
  Set init value: \reg_write = 1'0
  Set init value: \nextstate = 4'0000
Found init rule in `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:0$515'.
  Set init value: \reset_o = 1'0
  Set init value: \state = 2'01
  Set init value: \counter = 6'000000

21.4.5. Executing PROC_ARST pass (detect async resets in processes).

21.4.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 1 switch.
<suppressed ~75 debug messages>

21.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$507'.
Creating decoders for process `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$506'.
     1/1: $0\Q[0:0]
Creating decoders for process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$481'.
Creating decoders for process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$458'.
     1/3: $1$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$457_EN[3:0]$464
     2/3: $1$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$457_DATA[3:0]$463
     3/3: $1$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$457_ADDR[3:0]$462
Creating decoders for process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$424'.
Creating decoders for process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$400'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$398_EN[3:0]$406
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$398_DATA[3:0]$405
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$398_ADDR[3:0]$404
Creating decoders for process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$399'.
Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:132$657'.
Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:197$655'.
     1/2: $0\rxd_reg_0[0:0]
     2/2: $0\rxd_reg[0:0]
Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:186$653'.
     1/1: $0\fsm_state[2:0]
Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:171$645'.
     1/1: $0\cycle_counter[12:0]
Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:160$642'.
     1/1: $0\bit_sample[0:0]
Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:148$636'.
     1/1: $0\bit_counter[3:0]
Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:133$631'.
     1/11: $3\i[31:0]
     2/11: $0\recieved_data[7:0] [1]
     3/11: $0\recieved_data[7:0] [0]
     4/11: $0\recieved_data[7:0] [2]
     5/11: $0\recieved_data[7:0] [3]
     6/11: $0\recieved_data[7:0] [4]
     7/11: $0\recieved_data[7:0] [5]
     8/11: $0\recieved_data[7:0] [6]
     9/11: $0\recieved_data[7:0] [7]
    10/11: $1\i[31:0]
    11/11: $2\i[31:0]
Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:116$626'.
     1/1: $1\n_fsm_state[2:0]
Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:97$617'.
     1/1: $0\uart_rx_data[7:0]
Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:114$610'.
Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:173$604'.
     1/1: $0\txd_reg[0:0]
Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:162$602'.
     1/1: $0\fsm_state[2:0]
Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:147$594'.
     1/1: $0\cycle_counter[12:0]
Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:130$580'.
     1/1: $0\bit_counter[3:0]
Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:115$574'.
     1/11: $3\i[31:0]
     2/11: $0\data_to_send[7:0] [1]
     3/11: $0\data_to_send[7:0] [0]
     4/11: $0\data_to_send[7:0] [2]
     5/11: $0\data_to_send[7:0] [3]
     6/11: $0\data_to_send[7:0] [4]
     7/11: $0\data_to_send[7:0] [5]
     8/11: $0\data_to_send[7:0] [6]
     9/11: $0\data_to_send[7:0] [7]
    10/11: $1\i[31:0]
    11/11: $2\i[31:0]
Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:98$569'.
     1/1: $1\n_fsm_state[2:0]
Creating decoders for process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:0$562'.
Creating decoders for process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:137$559'.
     1/5: $0\alu_out_register[31:0]
     2/5: $0\register_data_2[31:0]
     3/5: $0\register_data_1[31:0]
     4/5: $0\memory_register[31:0]
     5/5: $0\instruction_register[31:0]
Creating decoders for process `$paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory.$proc$Risco-5/src/peripheral/memory.v:31$667'.
     1/3: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:33$663_EN[31:0]$674
     2/3: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:33$663_DATA[31:0]$673
     3/3: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:33$663_ADDR[31:0]$672
Creating decoders for process `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART.$proc$Risco-5/src/peripheral/uart.v:0$543'.
Creating decoders for process `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART.$proc$Risco-5/src/peripheral/uart.v:31$540'.
Creating decoders for process `\LEDs.$proc$Risco-5/src/peripheral/leds.v:0$166'.
Creating decoders for process `\LEDs.$proc$Risco-5/src/peripheral/leds.v:23$163'.
     1/1: $0\data[32:0]
Creating decoders for process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:29$661'.
     1/2: $0\gpio_value[5:0]
     2/2: $0\gpio_direction[5:0]
Creating decoders for process `\Registers.$proc$Risco-5/src/core/registers.v:0$72'.
Creating decoders for process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
     1/32: $0\register31[31:0]
     2/32: $0\register30[31:0]
     3/32: $0\register29[31:0]
     4/32: $0\register28[31:0]
     5/32: $0\register27[31:0]
     6/32: $0\register26[31:0]
     7/32: $0\register25[31:0]
     8/32: $0\register24[31:0]
     9/32: $0\register23[31:0]
    10/32: $0\register22[31:0]
    11/32: $0\register21[31:0]
    12/32: $0\register20[31:0]
    13/32: $0\register19[31:0]
    14/32: $0\register18[31:0]
    15/32: $0\register17[31:0]
    16/32: $0\register16[31:0]
    17/32: $0\register15[31:0]
    18/32: $0\register14[31:0]
    19/32: $0\register13[31:0]
    20/32: $0\register12[31:0]
    21/32: $0\register11[31:0]
    22/32: $0\register10[31:0]
    23/32: $0\register9[31:0]
    24/32: $0\register8[31:0]
    25/32: $0\register7[31:0]
    26/32: $0\register6[31:0]
    27/32: $0\register5[31:0]
    28/32: $0\register4[31:0]
    29/32: $0\register3[31:0]
    30/32: $0\register2[31:0]
    31/32: $0\register1[31:0]
    32/32: $0\register0[31:0]
Creating decoders for process `\Registers.$proc$Risco-5/src/core/registers.v:81$68'.
     1/2: $1\readData2[31:0]
     2/2: $1\readData1[31:0]
Creating decoders for process `\PC.$proc$Risco-5/src/core/pc.v:0$67'.
Creating decoders for process `\PC.$proc$Risco-5/src/core/pc.v:19$64'.
     1/1: $1\PC_Register[31:0]
Creating decoders for process `\MUX.$proc$Risco-5/src/core/mux.v:10$63'.
     1/1: $1\S[31:0]
Creating decoders for process `\Immediate_Generator.$proc$Risco-5/src/core/immediate_generator.v:7$60'.
     1/1: $1\immediate[31:0]
Creating decoders for process `$paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.$proc$Risco-5/debug/clk_divider.v:0$532'.
Creating decoders for process `$paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.$proc$Risco-5/debug/clk_divider.v:46$530'.
Creating decoders for process `$paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.$proc$Risco-5/debug/clk_divider.v:25$520'.
     1/2: $0\clk_counter[31:0]
     2/2: $0\clk_o_auto[0:0]
Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:0$53'.
Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:119$52'.
     1/1: { $1\pc_write[0:0] $1\alu_src_b[1:0] $1\ir_write[0:0] $1\memory_read[0:0] $1\reg_write[0:0] $1\alu_src_a[1:0] $1\aluop[1:0] $1\pc_source[0:0] $1\memory_to_reg[0:0] $1\memory_write[0:0] $1\lorD[0:0] $1\pc_write_cond[0:0] $1\is_immediate[0:0] }
Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:76$50'.
     1/4: $4\nextstate[3:0]
     2/4: $3\nextstate[3:0]
     3/4: $2\nextstate[3:0]
     4/4: $1\nextstate[3:0]
Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:68$49'.
     1/1: $0\state[3:0]
Creating decoders for process `\ALU_Control.$proc$Risco-5/src/core/alu_control.v:9$45'.
     1/4: $4\aluop_out[3:0]
     2/4: $3\aluop_out[3:0]
     3/4: $2\aluop_out[3:0]
     4/4: $1\aluop_out[3:0]
Creating decoders for process `\ALU.$proc$Risco-5/src/core/alu.v:11$30'.
     1/1: $1\ALU_out_S[31:0]
Creating decoders for process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:0$515'.
Creating decoders for process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$509'.
     1/3: $0\counter[5:0]
     2/3: $0\state[1:0]
     3/3: $0\reset_o[0:0]

21.4.8. Executing PROC_DLATCH pass (convert process syncs to latches).
No latch inferred for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.\n_fsm_state' from process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:116$626'.
No latch inferred for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.\n_fsm_state' from process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:98$569'.
No latch inferred for signal `\Registers.\readData1' from process `\Registers.$proc$Risco-5/src/core/registers.v:81$68'.
No latch inferred for signal `\Registers.\readData2' from process `\Registers.$proc$Risco-5/src/core/registers.v:81$68'.
No latch inferred for signal `\MUX.\S' from process `\MUX.$proc$Risco-5/src/core/mux.v:10$63'.
No latch inferred for signal `\Immediate_Generator.\immediate' from process `\Immediate_Generator.$proc$Risco-5/src/core/immediate_generator.v:7$60'.
No latch inferred for signal `\Control_Unit.\is_immediate' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:119$52'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\is_immediate` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:119$52`.
No latch inferred for signal `\Control_Unit.\pc_write_cond' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:119$52'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\pc_write_cond` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:119$52`.
No latch inferred for signal `\Control_Unit.\pc_write' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:119$52'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\pc_write` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:119$52`.
No latch inferred for signal `\Control_Unit.\lorD' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:119$52'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\lorD` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:119$52`.
No latch inferred for signal `\Control_Unit.\memory_read' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:119$52'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_read` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:119$52`.
No latch inferred for signal `\Control_Unit.\memory_write' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:119$52'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_write` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:119$52`.
No latch inferred for signal `\Control_Unit.\memory_to_reg' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:119$52'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_to_reg` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:119$52`.
No latch inferred for signal `\Control_Unit.\ir_write' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:119$52'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\ir_write` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:119$52`.
No latch inferred for signal `\Control_Unit.\pc_source' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:119$52'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\pc_source` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:119$52`.
No latch inferred for signal `\Control_Unit.\aluop' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:119$52'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\aluop [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:119$52`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\aluop [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:119$52`.
No latch inferred for signal `\Control_Unit.\alu_src_a' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:119$52'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_a [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:119$52`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_a [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:119$52`.
No latch inferred for signal `\Control_Unit.\alu_src_b' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:119$52'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_b [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:119$52`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_b [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:119$52`.
No latch inferred for signal `\Control_Unit.\reg_write' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:119$52'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\reg_write` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:119$52`.
No latch inferred for signal `\Control_Unit.\nextstate' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:76$50'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:76$50`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:76$50`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [2]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:76$50`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [3]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:76$50`.
Latch inferred for signal `\ALU_Control.\aluop_out' from process `\ALU_Control.$proc$Risco-5/src/core/alu_control.v:9$45': $auto$proc_dlatch.cc:427:proc_dlatch$2049
No latch inferred for signal `\ALU.\ALU_out_S' from process `\ALU.$proc$Risco-5/src/core/alu.v:11$30'.

21.4.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `\TRELLIS_FF.\Q' using process `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$506'.
  created $dff cell `$procdff$2072' with positive edge clock.
Creating register for signal `\DPR16X4C.\i' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$481'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$442_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$481'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$443_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$481'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$444_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$481'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$445_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$481'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$446_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$481'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$447_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$481'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$448_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$481'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$449_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$481'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$450_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$481'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$451_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$481'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$452_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$481'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$453_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$481'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$454_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$481'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$455_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$481'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$456_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$481'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$457_ADDR' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$458'.
  created $dff cell `$procdff$2073' with positive edge clock.
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$457_DATA' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$458'.
  created $dff cell `$procdff$2074' with positive edge clock.
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$457_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$458'.
  created $dff cell `$procdff$2075' with positive edge clock.
Creating register for signal `\TRELLIS_DPR16X4.\i' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$424'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$382_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$424'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$383_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$424'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$384_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$424'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$385_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$424'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$386_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$424'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$387_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$424'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$388_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$424'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$389_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$424'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$390_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$424'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$391_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$424'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$392_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$424'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$393_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$424'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$394_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$424'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$395_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$424'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$396_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$424'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$397_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$424'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$398_ADDR' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$400'.
  created $dff cell `$procdff$2076' with positive edge clock.
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$398_DATA' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$400'.
  created $dff cell `$procdff$2077' with positive edge clock.
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$398_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$400'.
  created $dff cell `$procdff$2078' with positive edge clock.
Creating register for signal `\TRELLIS_DPR16X4.\muxwre' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$399'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.\rxd_reg' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:197$655'.
  created $dff cell `$procdff$2079' with positive edge clock.
Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.\rxd_reg_0' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:197$655'.
  created $dff cell `$procdff$2080' with positive edge clock.
Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.\fsm_state' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:186$653'.
  created $dff cell `$procdff$2081' with positive edge clock.
Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.\cycle_counter' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:171$645'.
  created $dff cell `$procdff$2082' with positive edge clock.
Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.\bit_sample' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:160$642'.
  created $dff cell `$procdff$2083' with positive edge clock.
Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.\bit_counter' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:148$636'.
  created $dff cell `$procdff$2084' with positive edge clock.
Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.\i' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:133$631'.
  created $dff cell `$procdff$2085' with positive edge clock.
Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.\recieved_data' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:133$631'.
  created $dff cell `$procdff$2086' with positive edge clock.
Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.\uart_rx_data' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:97$617'.
  created $dff cell `$procdff$2087' with positive edge clock.
Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.\txd_reg' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:173$604'.
  created $dff cell `$procdff$2088' with positive edge clock.
Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.\fsm_state' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:162$602'.
  created $dff cell `$procdff$2089' with positive edge clock.
Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.\cycle_counter' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:147$594'.
  created $dff cell `$procdff$2090' with positive edge clock.
Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.\bit_counter' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:130$580'.
  created $dff cell `$procdff$2091' with positive edge clock.
Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.\i' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:115$574'.
  created $dff cell `$procdff$2092' with positive edge clock.
Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.\data_to_send' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:115$574'.
  created $dff cell `$procdff$2093' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\instruction_register' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:137$559'.
  created $dff cell `$procdff$2094' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\memory_register' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:137$559'.
  created $dff cell `$procdff$2095' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\alu_out_register' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:137$559'.
  created $dff cell `$procdff$2096' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\register_data_1' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:137$559'.
  created $dff cell `$procdff$2097' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\register_data_2' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:137$559'.
  created $dff cell `$procdff$2098' with positive edge clock.
Creating register for signal `$paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:33$663_ADDR' using process `$paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory.$proc$Risco-5/src/peripheral/memory.v:31$667'.
  created $dff cell `$procdff$2099' with positive edge clock.
Creating register for signal `$paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:33$663_DATA' using process `$paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory.$proc$Risco-5/src/peripheral/memory.v:31$667'.
  created $dff cell `$procdff$2100' with positive edge clock.
Creating register for signal `$paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:33$663_EN' using process `$paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory.$proc$Risco-5/src/peripheral/memory.v:31$667'.
  created $dff cell `$procdff$2101' with positive edge clock.
Creating register for signal `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART.\uart_tx_en' using process `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART.$proc$Risco-5/src/peripheral/uart.v:31$540'.
  created $dff cell `$procdff$2102' with positive edge clock.
Creating register for signal `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART.\uart_tx_data' using process `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART.$proc$Risco-5/src/peripheral/uart.v:31$540'.
  created $dff cell `$procdff$2103' with positive edge clock.
Creating register for signal `\LEDs.\data' using process `\LEDs.$proc$Risco-5/src/peripheral/leds.v:23$163'.
  created $dff cell `$procdff$2104' with positive edge clock.
Creating register for signal `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.\gpio_direction' using process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:29$661'.
  created $dff cell `$procdff$2105' with positive edge clock.
Creating register for signal `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.\gpio_value' using process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:29$661'.
  created $dff cell `$procdff$2106' with positive edge clock.
Creating register for signal `\Registers.\register0' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2107' with positive edge clock.
Creating register for signal `\Registers.\register1' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2108' with positive edge clock.
Creating register for signal `\Registers.\register2' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2109' with positive edge clock.
Creating register for signal `\Registers.\register3' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2110' with positive edge clock.
Creating register for signal `\Registers.\register4' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2111' with positive edge clock.
Creating register for signal `\Registers.\register5' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2112' with positive edge clock.
Creating register for signal `\Registers.\register6' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2113' with positive edge clock.
Creating register for signal `\Registers.\register7' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2114' with positive edge clock.
Creating register for signal `\Registers.\register8' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2115' with positive edge clock.
Creating register for signal `\Registers.\register9' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2116' with positive edge clock.
Creating register for signal `\Registers.\register10' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2117' with positive edge clock.
Creating register for signal `\Registers.\register11' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2118' with positive edge clock.
Creating register for signal `\Registers.\register12' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2119' with positive edge clock.
Creating register for signal `\Registers.\register13' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2120' with positive edge clock.
Creating register for signal `\Registers.\register14' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2121' with positive edge clock.
Creating register for signal `\Registers.\register15' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2122' with positive edge clock.
Creating register for signal `\Registers.\register16' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2123' with positive edge clock.
Creating register for signal `\Registers.\register17' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2124' with positive edge clock.
Creating register for signal `\Registers.\register18' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2125' with positive edge clock.
Creating register for signal `\Registers.\register19' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2126' with positive edge clock.
Creating register for signal `\Registers.\register20' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2127' with positive edge clock.
Creating register for signal `\Registers.\register21' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2128' with positive edge clock.
Creating register for signal `\Registers.\register22' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2129' with positive edge clock.
Creating register for signal `\Registers.\register23' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2130' with positive edge clock.
Creating register for signal `\Registers.\register24' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2131' with positive edge clock.
Creating register for signal `\Registers.\register25' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2132' with positive edge clock.
Creating register for signal `\Registers.\register26' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2133' with positive edge clock.
Creating register for signal `\Registers.\register27' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2134' with positive edge clock.
Creating register for signal `\Registers.\register28' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2135' with positive edge clock.
Creating register for signal `\Registers.\register29' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2136' with positive edge clock.
Creating register for signal `\Registers.\register30' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2137' with positive edge clock.
Creating register for signal `\Registers.\register31' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2138' with positive edge clock.
Creating register for signal `\PC.\PC_Register' using process `\PC.$proc$Risco-5/src/core/pc.v:19$64'.
  created $dff cell `$procdff$2139' with positive edge clock.
Creating register for signal `$paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.\clk_o_pulse' using process `$paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.$proc$Risco-5/debug/clk_divider.v:46$530'.
  created $dff cell `$procdff$2140' with positive edge clock.
Creating register for signal `$paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.\clk_o_auto' using process `$paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.$proc$Risco-5/debug/clk_divider.v:25$520'.
  created $dff cell `$procdff$2141' with positive edge clock.
Creating register for signal `$paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.\clk_counter' using process `$paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.$proc$Risco-5/debug/clk_divider.v:25$520'.
  created $dff cell `$procdff$2142' with positive edge clock.
Creating register for signal `\Control_Unit.\state' using process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:68$49'.
  created $dff cell `$procdff$2143' with positive edge clock.
Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\reset_o' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$509'.
  created $dff cell `$procdff$2144' with positive edge clock.
Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\state' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$509'.
  created $dff cell `$procdff$2145' with positive edge clock.
Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\counter' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$509'.
  created $dff cell `$procdff$2146' with positive edge clock.

21.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

21.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$507'.
Found and cleaned up 2 empty switches in `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$506'.
Removing empty process `TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$506'.
Removing empty process `DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$481'.
Found and cleaned up 1 empty switch in `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$458'.
Removing empty process `TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$424'.
Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$400'.
Removing empty process `TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$399'.
Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:132$657'.
Found and cleaned up 2 empty switches in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:197$655'.
Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:197$655'.
Found and cleaned up 1 empty switch in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:186$653'.
Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:186$653'.
Found and cleaned up 3 empty switches in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:171$645'.
Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:171$645'.
Found and cleaned up 2 empty switches in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:160$642'.
Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:160$642'.
Found and cleaned up 3 empty switches in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:148$636'.
Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:148$636'.
Found and cleaned up 3 empty switches in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:133$631'.
Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:133$631'.
Found and cleaned up 1 empty switch in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:116$626'.
Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:116$626'.
Found and cleaned up 2 empty switches in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:97$617'.
Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:97$617'.
Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:114$610'.
Found and cleaned up 5 empty switches in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:173$604'.
Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:173$604'.
Found and cleaned up 1 empty switch in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:162$602'.
Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:162$602'.
Found and cleaned up 3 empty switches in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:147$594'.
Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:147$594'.
Found and cleaned up 5 empty switches in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:130$580'.
Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:130$580'.
Found and cleaned up 3 empty switches in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:115$574'.
Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:115$574'.
Found and cleaned up 1 empty switch in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:98$569'.
Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:98$569'.
Removing empty process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:0$562'.
Found and cleaned up 2 empty switches in `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:137$559'.
Removing empty process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:137$559'.
Found and cleaned up 1 empty switch in `$paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory.$proc$Risco-5/src/peripheral/memory.v:31$667'.
Removing empty process `$paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory.$proc$Risco-5/src/peripheral/memory.v:31$667'.
Removing empty process `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART.$proc$Risco-5/src/peripheral/uart.v:0$543'.
Removing empty process `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART.$proc$Risco-5/src/peripheral/uart.v:31$540'.
Removing empty process `LEDs.$proc$Risco-5/src/peripheral/leds.v:0$166'.
Found and cleaned up 2 empty switches in `\LEDs.$proc$Risco-5/src/peripheral/leds.v:23$163'.
Removing empty process `LEDs.$proc$Risco-5/src/peripheral/leds.v:23$163'.
Found and cleaned up 3 empty switches in `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:29$661'.
Removing empty process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:29$661'.
Removing empty process `Registers.$proc$Risco-5/src/core/registers.v:0$72'.
Found and cleaned up 3 empty switches in `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
Removing empty process `Registers.$proc$Risco-5/src/core/registers.v:155$69'.
Found and cleaned up 2 empty switches in `\Registers.$proc$Risco-5/src/core/registers.v:81$68'.
Removing empty process `Registers.$proc$Risco-5/src/core/registers.v:81$68'.
Removing empty process `PC.$proc$Risco-5/src/core/pc.v:0$67'.
Found and cleaned up 2 empty switches in `\PC.$proc$Risco-5/src/core/pc.v:19$64'.
Removing empty process `PC.$proc$Risco-5/src/core/pc.v:19$64'.
Found and cleaned up 1 empty switch in `\MUX.$proc$Risco-5/src/core/mux.v:10$63'.
Removing empty process `MUX.$proc$Risco-5/src/core/mux.v:10$63'.
Found and cleaned up 1 empty switch in `\Immediate_Generator.$proc$Risco-5/src/core/immediate_generator.v:7$60'.
Removing empty process `Immediate_Generator.$proc$Risco-5/src/core/immediate_generator.v:7$60'.
Removing empty process `$paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.$proc$Risco-5/debug/clk_divider.v:0$532'.
Removing empty process `$paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.$proc$Risco-5/debug/clk_divider.v:46$530'.
Found and cleaned up 4 empty switches in `$paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.$proc$Risco-5/debug/clk_divider.v:25$520'.
Removing empty process `$paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.$proc$Risco-5/debug/clk_divider.v:25$520'.
Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:0$53'.
Found and cleaned up 1 empty switch in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:119$52'.
Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:119$52'.
Found and cleaned up 4 empty switches in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:76$50'.
Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:76$50'.
Found and cleaned up 1 empty switch in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:68$49'.
Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:68$49'.
Found and cleaned up 4 empty switches in `\ALU_Control.$proc$Risco-5/src/core/alu_control.v:9$45'.
Removing empty process `ALU_Control.$proc$Risco-5/src/core/alu_control.v:9$45'.
Found and cleaned up 1 empty switch in `\ALU.$proc$Risco-5/src/core/alu.v:11$30'.
Removing empty process `ALU.$proc$Risco-5/src/core/alu.v:11$30'.
Removing empty process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:0$515'.
Found and cleaned up 5 empty switches in `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$509'.
Removing empty process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$509'.
Cleaned up 76 empty switches.

21.4.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.
<suppressed ~21 debug messages>
Optimizing module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.
<suppressed ~19 debug messages>
Optimizing module $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.
<suppressed ~2 debug messages>
Optimizing module $paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory.
<suppressed ~2 debug messages>
Optimizing module $paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART.
<suppressed ~1 debug messages>
Optimizing module LEDs.
<suppressed ~3 debug messages>
Optimizing module $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.
<suppressed ~4 debug messages>
Optimizing module GPIO.
<suppressed ~3 debug messages>
Optimizing module BUS.
Optimizing module Registers.
<suppressed ~4 debug messages>
Optimizing module PC.
<suppressed ~2 debug messages>
Optimizing module MUX.
<suppressed ~1 debug messages>
Optimizing module Immediate_Generator.
Optimizing module $paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.
<suppressed ~5 debug messages>
Optimizing module Control_Unit.
<suppressed ~2 debug messages>
Optimizing module ALU_Control.
<suppressed ~14 debug messages>
Optimizing module ALU.
<suppressed ~1 debug messages>
Optimizing module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.
<suppressed ~7 debug messages>
Optimizing module $paramod$3184ad0c07f8e5ef1997e235d9a61459f8c3c9b2\Risco_5_SOC.
Optimizing module top.

21.5. Executing FLATTEN pass (flatten design).
Deleting now unused module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.
Deleting now unused module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.
Deleting now unused module $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.
Deleting now unused module $paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory.
Deleting now unused module $paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART.
Deleting now unused module LEDs.
Deleting now unused module $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.
Deleting now unused module GPIO.
Deleting now unused module BUS.
Deleting now unused module Registers.
Deleting now unused module PC.
Deleting now unused module MUX.
Deleting now unused module Immediate_Generator.
Deleting now unused module $paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.
Deleting now unused module Control_Unit.
Deleting now unused module ALU_Control.
Deleting now unused module ALU.
Deleting now unused module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.
Deleting now unused module $paramod$3184ad0c07f8e5ef1997e235d9a61459f8c3c9b2\Risco_5_SOC.
<suppressed ~28 debug messages>

21.6. Executing TRIBUF pass.

21.7. Executing DEMINOUT pass (demote inout ports to input or output).

21.8. Executing OPT_EXPR pass (perform const folding).
+ mkdir -p Risco-5/impl/pnr
[Pipeline] }
Optimizing module top.
<suppressed ~52 debug messages>

21.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 54 unused cells and 591 unused wires.
<suppressed ~78 debug messages>

21.10. Executing CHECK pass (checking for obvious problems).
Checking module top...
Warning: Wire top.\SOC.Core.PCSourceMUX.C [31] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [30] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [29] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [28] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [27] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [26] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [25] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [24] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [23] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [22] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [21] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [20] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [19] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [18] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [17] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [16] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [15] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [14] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [13] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [12] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [11] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [10] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [9] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [8] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [7] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [6] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [5] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [4] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [3] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [2] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [1] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [0] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [31] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [30] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [29] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [28] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [27] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [26] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [25] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [24] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [23] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [22] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [21] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [20] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [19] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [18] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [17] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [16] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [15] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [14] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [13] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [12] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [11] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [10] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [9] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [8] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [7] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [6] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [5] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [4] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [3] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [2] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [1] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [0] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [31] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [30] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [29] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [28] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [27] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [26] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [25] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [24] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [23] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [22] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [21] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [20] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [19] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [18] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [17] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [16] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [15] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [14] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [13] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [12] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [11] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [10] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [9] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [8] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [7] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [6] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [5] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [4] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [3] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [2] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [1] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [0] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [31] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [30] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [29] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [28] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [27] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [26] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [25] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [24] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [23] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [22] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [21] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [20] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [19] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [18] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [17] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [16] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [15] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [14] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [13] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [12] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [11] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [10] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [9] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [8] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [7] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [6] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [5] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [4] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [3] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [2] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [1] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [0] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [31] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [30] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [29] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [28] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [27] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [26] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [25] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [24] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [23] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [22] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [21] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [20] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [19] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [18] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [17] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [16] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [15] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [14] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [13] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [12] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [11] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [10] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [9] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [8] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [7] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [6] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [5] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [4] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [3] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [2] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [1] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [0] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [31] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [30] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [29] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [28] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [27] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [26] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [25] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [24] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [23] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [22] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [21] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [20] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [19] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [18] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [17] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [16] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [15] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [14] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [13] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [12] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [11] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [10] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [9] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [8] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [7] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [6] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [5] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [4] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [3] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [2] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [1] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [0] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [31] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [30] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [29] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [28] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [27] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [26] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [25] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [24] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [23] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [22] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [21] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [20] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [19] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [18] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [17] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [16] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [15] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [14] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [13] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [12] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [11] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [10] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [9] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [8] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [7] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [6] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [5] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [4] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [3] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [2] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [1] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [0] is used but has no driver.
Found and reported 224 problems.

21.11. Executing OPT pass (performing simple optimizations).

21.11.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~9 debug messages>

21.11.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~348 debug messages>
Removed a total of 116 cells.

21.11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$1892.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$1917.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$1937.
    dead port 1/5 on $pmux $flatten\SOC.\Core.\MemoryAddressMUX.$procmux$1840.
    dead port 2/5 on $pmux $flatten\SOC.\Core.\MemoryAddressMUX.$procmux$1840.
    dead port 1/5 on $pmux $flatten\SOC.\Core.\MemoryDataMUX.$procmux$1840.
    dead port 2/5 on $pmux $flatten\SOC.\Core.\MemoryDataMUX.$procmux$1840.
    dead port 1/5 on $pmux $flatten\SOC.\Core.\PCSourceMUX.$procmux$1840.
    dead port 2/5 on $pmux $flatten\SOC.\Core.\PCSourceMUX.$procmux$1840.
Removed 9 multiplexer ports.
<suppressed ~97 debug messages>

21.11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\ALU_Control.$procmux$1971: { $flatten\SOC.\Core.\ALU_Control.$procmux$1978_CMP $auto$opt_reduce.cc:134:opt_pmux$2161 $flatten\SOC.\Core.\ALU_Control.$procmux$1975_CMP $flatten\SOC.\Core.\ALU_Control.$procmux$1974_CMP $flatten\SOC.\Core.\ALU_Control.$procmux$1973_CMP $flatten\SOC.\Core.\ALU_Control.$procmux$1972_CMP }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\ALU_Control.$procmux$1985: { $auto$opt_reduce.cc:134:opt_pmux$2165 $auto$opt_reduce.cc:134:opt_pmux$2163 $flatten\SOC.\Core.\ALU_Control.$procmux$1978_CMP }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\ALU_Control.$procmux$1994: { $flatten\SOC.\Core.\ALU_Control.$procmux$1996_CMP $flatten\SOC.\Core.\ALU_Control.$procmux$1995_CMP }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$1908: { $auto$opt_reduce.cc:134:opt_pmux$2167 $flatten\SOC.\Core.\Control_Unit.$procmux$1914_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1913_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1912_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1911_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1910_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1909_CMP }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$1940: { $flatten\SOC.\Core.\Control_Unit.$procmux$1938_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1950_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1918_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1893_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1947_CMP $auto$opt_reduce.cc:134:opt_pmux$2169 }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Immediate_Generator.$procmux$1846: { $flatten\SOC.\Core.\Control_Unit.$procmux$1911_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1912_CMP $auto$opt_reduce.cc:134:opt_pmux$2173 $flatten\SOC.\Core.\Control_Unit.$eq$Risco-5/src/core/control_unit.v:99$51_Y $auto$opt_reduce.cc:134:opt_pmux$2171 $flatten\SOC.\Core.\Control_Unit.$procmux$1915_CMP }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\RegisterBank.$procmux$1732: $auto$opt_reduce.cc:134:opt_pmux$2175
    Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$989:
      Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$663_EN[31:0]$670
      New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$663_EN[31:0]$670 [0]
      New connections: $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$663_EN[31:0]$670 [31:1] = { $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$663_EN[31:0]$670 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$663_EN[31:0]$670 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$663_EN[31:0]$670 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$663_EN[31:0]$670 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$663_EN[31:0]$670 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$663_EN[31:0]$670 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$663_EN[31:0]$670 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$663_EN[31:0]$670 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$663_EN[31:0]$670 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$663_EN[31:0]$670 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$663_EN[31:0]$670 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$663_EN[31:0]$670 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$663_EN[31:0]$670 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$663_EN[31:0]$670 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$663_EN[31:0]$670 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$663_EN[31:0]$670 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$663_EN[31:0]$670 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$663_EN[31:0]$670 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$663_EN[31:0]$670 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$663_EN[31:0]$670 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$663_EN[31:0]$670 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$663_EN[31:0]$670 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$663_EN[31:0]$670 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$663_EN[31:0]$670 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$663_EN[31:0]$670 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$663_EN[31:0]$670 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$663_EN[31:0]$670 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$663_EN[31:0]$670 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$663_EN[31:0]$670 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$663_EN[31:0]$670 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$663_EN[31:0]$670 [0] }
  Optimizing cells in module \top.
Performed a total of 10 changes.

21.11.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

21.11.6. Executing OPT_DFF pass (perform DFF optimizations).

21.11.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 1 unused cells and 137 unused wires.
<suppressed ~8 debug messages>

21.11.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

21.11.9. Rerunning OPT passes. (Maybe there is more to do..)

21.11.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~97 debug messages>

21.11.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

21.11.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

21.11.13. Executing OPT_DFF pass (perform DFF optimizations).

21.11.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

21.11.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

21.11.16. Finished OPT passes. (There is nothing left to do.)

21.12. Executing FSM pass (extract and optimize FSM).

21.12.1. Executing FSM_DETECT pass (finding FSMs in design).
Not marking top.ResetBootSystem.state as FSM state register:
    Register has an initialization value.
    Circuit seems to be self-resetting.
Not marking top.SOC.Core.Control_Unit.state as FSM state register:
    Users of register don't seem to benefit from recoding.
    Register has an initialization value.
Not marking top.SOC.Core.RegisterBank.register0 as FSM state register:
    Users of register don't seem to benefit from recoding.
    Register has an initialization value.
Found FSM state register top.SOC.Uart.i_uart_rx.fsm_state.
Found FSM state register top.SOC.Uart.i_uart_tx.fsm_state.

21.12.2. Executing FSM_EXTRACT pass (extracting FSM from design).
Extracting FSM `\SOC.Uart.i_uart_rx.fsm_state' from module `\top'.
  found $dff cell for state register: $flatten\SOC.\Uart.\i_uart_rx.$procdff$2081
  root of input selection tree: $flatten\SOC.\Uart.\i_uart_rx.$0\fsm_state[2:0]
  found reset state: 3'000 (guessed from mux tree)
  found ctrl input: \ResetBootSystem.reset_o
  found ctrl input: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:100$619_Y
  found ctrl input: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:138$634_Y
  found ctrl input: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:176$647_Y
  found ctrl input: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:136$633_Y
  found state code: 3'000
  found ctrl input: \SOC.Uart.i_uart_rx.next_bit
  found state code: 3'011
  found ctrl input: \SOC.Uart.i_uart_rx.payload_done
  found state code: 3'010
  found state code: 3'001
  found ctrl input: \SOC.Uart.i_uart_rx.rxd_reg
  found ctrl output: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:176$647_Y
  found ctrl output: $flatten\SOC.\Uart.\i_uart_rx.$ne$Risco-5/src/peripheral/uart_rx.v:151$638_Y
  found ctrl output: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:138$634_Y
  found ctrl output: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:136$633_Y
  found ctrl output: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:100$619_Y
  ctrl inputs: { \SOC.Uart.i_uart_rx.rxd_reg \SOC.Uart.i_uart_rx.next_bit \SOC.Uart.i_uart_rx.payload_done \ResetBootSystem.reset_o }
  ctrl outputs: { $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:100$619_Y $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:136$633_Y $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:138$634_Y $flatten\SOC.\Uart.\i_uart_rx.$ne$Risco-5/src/peripheral/uart_rx.v:151$638_Y $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:176$647_Y $flatten\SOC.\Uart.\i_uart_rx.$0\fsm_state[2:0] }
  transition:      3'000 4'0--0 ->      3'001 8'01010001
  transition:      3'000 4'1--0 ->      3'000 8'01010000
  transition:      3'000 4'---1 ->      3'000 8'01010000
  transition:      3'010 4'--00 ->      3'010 8'00100010
  transition:      3'010 4'--10 ->      3'011 8'00100011
  transition:      3'010 4'---1 ->      3'000 8'00100000
  transition:      3'001 4'-0-0 ->      3'001 8'00011001
  transition:      3'001 4'-1-0 ->      3'010 8'00011010
  transition:      3'001 4'---1 ->      3'000 8'00011000
  transition:      3'011 4'-0-0 ->      3'011 8'10010011
  transition:      3'011 4'-1-0 ->      3'000 8'10010000
  transition:      3'011 4'---1 ->      3'000 8'10010000
Extracting FSM `\SOC.Uart.i_uart_tx.fsm_state' from module `\top'.
  found $dff cell for state register: $flatten\SOC.\Uart.\i_uart_tx.$procdff$2089
  root of input selection tree: $flatten\SOC.\Uart.\i_uart_tx.$0\fsm_state[2:0]
  found reset state: 3'000 (guessed from mux tree)
  found ctrl input: \ResetBootSystem.reset_o
  found ctrl input: $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:137$588_Y
  found ctrl input: $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:120$578_Y
  found ctrl input: $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:152$596_Y
  found ctrl input: $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:118$576_Y
  found state code: 3'000
  found ctrl input: \SOC.Uart.i_uart_tx.stop_done
  found state code: 3'011
  found ctrl input: \SOC.Uart.i_uart_tx.payload_done
  found state code: 3'010
  found ctrl input: \SOC.Uart.i_uart_tx.next_bit
  found state code: 3'001
  found ctrl input: \SOC.Uart.uart_tx_en
  found ctrl output: $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:152$596_Y
  found ctrl output: $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:137$588_Y
  found ctrl output: $flatten\SOC.\Uart.\i_uart_tx.$ne$Risco-5/src/peripheral/uart_tx.v:133$583_Y
  found ctrl output: $flatten\SOC.\Uart.\i_uart_tx.$ne$Risco-5/src/peripheral/uart_tx.v:133$582_Y
  found ctrl output: $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:120$578_Y
  found ctrl output: $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:118$576_Y
  ctrl inputs: { \SOC.Uart.i_uart_tx.next_bit \SOC.Uart.i_uart_tx.payload_done \SOC.Uart.i_uart_tx.stop_done \SOC.Uart.uart_tx_en \ResetBootSystem.reset_o }
  ctrl outputs: { $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:118$576_Y $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:120$578_Y $flatten\SOC.\Uart.\i_uart_tx.$ne$Risco-5/src/peripheral/uart_tx.v:133$582_Y $flatten\SOC.\Uart.\i_uart_tx.$ne$Risco-5/src/peripheral/uart_tx.v:133$583_Y $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:137$588_Y $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:152$596_Y $flatten\SOC.\Uart.\i_uart_tx.$0\fsm_state[2:0] }
  transition:      3'000 5'---00 ->      3'000 9'101100000
  transition:      3'000 5'---10 ->      3'001 9'101100001
  transition:      3'000 5'----1 ->      3'000 9'101100000
  transition:      3'010 5'-0--0 ->      3'010 9'010100010
  transition:      3'010 5'-1--0 ->      3'011 9'010100011
  transition:      3'010 5'----1 ->      3'000 9'010100000
  transition:      3'001 5'0---0 ->      3'001 9'001101001
  transition:      3'001 5'1---0 ->      3'010 9'001101010
  transition:      3'001 5'----1 ->      3'000 9'001101000
  transition:      3'011 5'--0-0 ->      3'011 9'001010011
  transition:      3'011 5'--1-0 ->      3'000 9'001010000
  transition:      3'011 5'----1 ->      3'000 9'001010000

21.12.3. Executing FSM_OPT pass (simple optimizations of FSMs).
Optimizing FSM `$fsm$\SOC.Uart.i_uart_tx.fsm_state$2183' from module `\top'.
Optimizing FSM `$fsm$\SOC.Uart.i_uart_rx.fsm_state$2176' from module `\top'.

21.12.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 20 unused cells and 20 unused wires.
<suppressed ~22 debug messages>

21.12.5. Executing FSM_OPT pass (simple optimizations of FSMs).
Optimizing FSM `$fsm$\SOC.Uart.i_uart_rx.fsm_state$2176' from module `\top'.
  Removing unused output signal $flatten\SOC.\Uart.\i_uart_rx.$0\fsm_state[2:0] [0].
  Removing unused output signal $flatten\SOC.\Uart.\i_uart_rx.$0\fsm_state[2:0] [1].
  Removing unused output signal $flatten\SOC.\Uart.\i_uart_rx.$0\fsm_state[2:0] [2].
Optimizing FSM `$fsm$\SOC.Uart.i_uart_tx.fsm_state$2183' from module `\top'.
  Removing unused output signal $flatten\SOC.\Uart.\i_uart_tx.$0\fsm_state[2:0] [0].
  Removing unused output signal $flatten\SOC.\Uart.\i_uart_tx.$0\fsm_state[2:0] [1].
  Removing unused output signal $flatten\SOC.\Uart.\i_uart_tx.$0\fsm_state[2:0] [2].

21.12.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
Recoding FSM `$fsm$\SOC.Uart.i_uart_rx.fsm_state$2176' from module `\top' using `auto' encoding:
  mapping auto encoding to `one-hot` for this FSM.
  000 -> ---1
  010 -> --1-
  001 -> -1--
  011 -> 1---
Recoding FSM `$fsm$\SOC.Uart.i_uart_tx.fsm_state$2183' from module `\top' using `auto' encoding:
  mapping auto encoding to `one-hot` for this FSM.
  000 -> ---1
  010 -> --1-
  001 -> -1--
  011 -> 1---

21.12.7. Executing FSM_INFO pass (dumping all available information on FSM cells).

FSM `$fsm$\SOC.Uart.i_uart_rx.fsm_state$2176' from module `top':
-------------------------------------

  Information on FSM $fsm$\SOC.Uart.i_uart_rx.fsm_state$2176 (\SOC.Uart.i_uart_rx.fsm_state):

  Number of input signals:    4
  Number of output signals:   5
  Number of state bits:       4

  Input signals:
    0: \ResetBootSystem.reset_o
    1: \SOC.Uart.i_uart_rx.payload_done
    2: \SOC.Uart.i_uart_rx.next_bit
    3: \SOC.Uart.i_uart_rx.rxd_reg

  Output signals:
    0: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:176$647_Y
    1: $flatten\SOC.\Uart.\i_uart_rx.$ne$Risco-5/src/peripheral/uart_rx.v:151$638_Y
    2: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:138$634_Y
    3: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:136$633_Y
    4: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:100$619_Y

  State encoding:
    0:     4'---1  <RESET STATE>
    1:     4'--1-
    2:     4'-1--
    3:     4'1---

  Transition Table (state_in, ctrl_in, state_out, ctrl_out):
      0:     0 4'1--0   ->     0 5'01010
      1:     0 4'---1   ->     0 5'01010
      2:     0 4'0--0   ->     2 5'01010
      3:     1 4'---1   ->     0 5'00100
      4:     1 4'--00   ->     1 5'00100
      5:     1 4'--10   ->     3 5'00100
      6:     2 4'---1   ->     0 5'00011
      7:     2 4'-1-0   ->     1 5'00011
      8:     2 4'-0-0   ->     2 5'00011
      9:     3 4'-1-0   ->     0 5'10010
     10:     3 4'---1   ->     0 5'10010
     11:     3 4'-0-0   ->     3 5'10010

-------------------------------------

FSM `$fsm$\SOC.Uart.i_uart_tx.fsm_state$2183' from module `top':
-------------------------------------

  Information on FSM $fsm$\SOC.Uart.i_uart_tx.fsm_state$2183 (\SOC.Uart.i_uart_tx.fsm_state):

  Number of input signals:    5
  Number of output signals:   6
  Number of state bits:       4

  Input signals:
    0: \ResetBootSystem.reset_o
    1: \SOC.Uart.uart_tx_en
    2: \SOC.Uart.i_uart_tx.stop_done
    3: \SOC.Uart.i_uart_tx.payload_done
    4: \SOC.Uart.i_uart_tx.next_bit

  Output signals:
    0: $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:152$596_Y
    1: $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:137$588_Y
    2: $flatten\SOC.\Uart.\i_uart_tx.$ne$Risco-5/src/peripheral/uart_tx.v:133$583_Y
    3: $flatten\SOC.\Uart.\i_uart_tx.$ne$Risco-5/src/peripheral/uart_tx.v:133$582_Y
    4: $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:120$578_Y
    5: $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:118$576_Y

  State encoding:
    0:     4'---1  <RESET STATE>
    1:     4'--1-
    2:     4'-1--
    3:     4'1---

  Transition Table (state_in, ctrl_in, state_out, ctrl_out):
      0:     0 5'---00   ->     0 6'101100
      1:     0 5'----1   ->     0 6'101100
      2:     0 5'---10   ->     2 6'101100
      3:     1 5'----1   ->     0 6'010100
      4:     1 5'-0--0   ->     1 6'010100
      5:     1 5'-1--0   ->     3 6'010100
      6:     2 5'----1   ->     0 6'001101
      7:     2 5'1---0   ->     1 6'001101
      8:     2 5'0---0   ->     2 6'001101
      9:     3 5'--1-0   ->     0 6'001010
     10:     3 5'----1   ->     0 6'001010
     11:     3 5'--0-0   ->     3 6'001010

-------------------------------------

21.12.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
Mapping FSM `$fsm$\SOC.Uart.i_uart_rx.fsm_state$2176' from module `\top'.
Mapping FSM `$fsm$\SOC.Uart.i_uart_tx.fsm_state$2183' from module `\top'.

21.13. Executing OPT pass (performing simple optimizations).

21.13.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~10 debug messages>

21.13.2. Executing OPT_MERGE pass (detect identical cells).
[Pipeline] // stage
[Pipeline] }
Finding identical cells in module `\top'.
<suppressed ~6 debug messages>
Removed a total of 2 cells.

21.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~95 debug messages>

21.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

21.13.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

21.13.6. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$2093 ($dff) from module top (D = { $flatten\SOC.\Uart.\i_uart_tx.$procmux$951_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$945_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$936_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$927_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$918_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$909_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$891_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$900_Y }, Q = \SOC.Uart.i_uart_tx.data_to_send, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$2278 ($sdff) from module top (D = \SOC.Uart.uart_tx_data [7], Q = \SOC.Uart.i_uart_tx.data_to_send [7]).
Adding EN signal on $auto$ff.cc:266:slice$2278 ($sdff) from module top (D = { $flatten\SOC.\Uart.\i_uart_tx.$procmux$945_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$936_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$927_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$918_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$909_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$891_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$900_Y }, Q = \SOC.Uart.i_uart_tx.data_to_send [6:0]).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$2091 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$867_Y, Q = \SOC.Uart.i_uart_tx.bit_counter, rval = 4'0000).
Adding EN signal on $auto$ff.cc:266:slice$2283 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$867_Y, Q = \SOC.Uart.i_uart_tx.bit_counter).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$2090 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$856_Y, Q = \SOC.Uart.i_uart_tx.cycle_counter, rval = 13'0000000000000).
Adding EN signal on $auto$ff.cc:266:slice$2289 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:155$601_Y, Q = \SOC.Uart.i_uart_tx.cycle_counter).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$2088 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$845_Y, Q = \SOC.Uart.i_uart_tx.txd_reg, rval = 1'1).
Adding EN signal on $auto$ff.cc:266:slice$2293 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$845_Y, Q = \SOC.Uart.i_uart_tx.txd_reg).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$2087 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$procmux$834_Y, Q = \SOC.Uart.i_uart_rx.uart_rx_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$2299 ($sdff) from module top (D = \SOC.Uart.i_uart_rx.recieved_data, Q = \SOC.Uart.i_uart_rx.uart_rx_data).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$2086 ($dff) from module top (D = { $flatten\SOC.\Uart.\i_uart_rx.$procmux$811_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$802_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$793_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$784_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$775_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$766_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$748_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$757_Y }, Q = \SOC.Uart.i_uart_rx.recieved_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$2301 ($sdff) from module top (D = { \SOC.Uart.i_uart_rx.bit_sample \SOC.Uart.i_uart_rx.recieved_data [7:1] }, Q = \SOC.Uart.i_uart_rx.recieved_data).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$2084 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$procmux$730_Y, Q = \SOC.Uart.i_uart_rx.bit_counter, rval = 4'0000).
Adding EN signal on $auto$ff.cc:266:slice$2305 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:154$641_Y, Q = \SOC.Uart.i_uart_rx.bit_counter).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$2083 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$procmux$725_Y, Q = \SOC.Uart.i_uart_rx.bit_sample, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$2309 ($sdff) from module top (D = \SOC.Uart.i_uart_rx.rxd_reg, Q = \SOC.Uart.i_uart_rx.bit_sample).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$2082 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$procmux$717_Y, Q = \SOC.Uart.i_uart_rx.cycle_counter, rval = 13'0000000000000).
Adding EN signal on $auto$ff.cc:266:slice$2311 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:179$652_Y, Q = \SOC.Uart.i_uart_rx.cycle_counter).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$2080 ($dff) from module top (D = \rx, Q = \SOC.Uart.i_uart_rx.rxd_reg_0, rval = 1'1).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$2079 ($dff) from module top (D = \SOC.Uart.i_uart_rx.rxd_reg_0, Q = \SOC.Uart.i_uart_rx.rxd_reg, rval = 1'1).
Adding SRST signal on $flatten\SOC.\Uart.$procdff$2103 ($dff) from module top (D = \SOC.Bus.write_data [7:0], Q = \SOC.Uart.uart_tx_data, rval = 8'00000000).
Adding SRST signal on $flatten\SOC.\Uart.$procdff$2102 ($dff) from module top (D = \SOC.Bus.write, Q = \SOC.Uart.uart_tx_en, rval = 1'0).
Adding SRST signal on $flatten\SOC.\Leds.$procdff$2104 ($dff) from module top (D = $flatten\SOC.\Leds.$procmux$997_Y, Q = \SOC.Leds.data, rval = 33'000000000000000000000000000000000).
Adding EN signal on $auto$ff.cc:266:slice$2319 ($sdff) from module top (D = { 1'0 \SOC.Leds.write_data }, Q = \SOC.Leds.data).
Adding SRST signal on $flatten\SOC.\GPIOS.$procdff$2106 ($dff) from module top (D = $flatten\SOC.\GPIOS.$procmux$1005_Y, Q = \SOC.GPIOS.gpio_value, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$2321 ($sdff) from module top (D = \SOC.GPIOS.write_data [5:0], Q = \SOC.GPIOS.gpio_value).
Adding SRST signal on $flatten\SOC.\GPIOS.$procdff$2105 ($dff) from module top (D = $flatten\SOC.\GPIOS.$procmux$1013_Y, Q = \SOC.GPIOS.gpio_direction, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$2325 ($sdff) from module top (D = \SOC.GPIOS.write_data [5:0], Q = \SOC.GPIOS.gpio_direction).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2138 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register31).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2137 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register30).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2136 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register29).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2135 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register28).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2134 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register27).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2133 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register26).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2132 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register25).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2131 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register24).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2130 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register23).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2129 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register22).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2128 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register21).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2127 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register20).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2126 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register19).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2125 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register18).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2124 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register17).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2123 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register16).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2122 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register15).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2121 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register14).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2120 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register13).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2119 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register12).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2118 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register11).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2117 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register10).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2116 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register9).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2115 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register8).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2114 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register7).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2113 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register6).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2112 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register5).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2111 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register4).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2110 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register3).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2109 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register2).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2108 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register1).
Adding SRST signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2107 ($dff) from module top (D = $flatten\SOC.\Core.\RegisterBank.$procmux$1764_Y, Q = \SOC.Core.RegisterBank.register0, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$2486 ($sdff) from module top (D = 0, Q = \SOC.Core.RegisterBank.register0).
Adding SRST signal on $flatten\SOC.\Core.\Pc.$procdff$2139 ($dff) from module top (D = $flatten\SOC.\Core.\Pc.$procmux$1835_Y, Q = \SOC.Core.Pc.PC_Register, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$2492 ($sdff) from module top (D = \SOC.Core.Pc.Input, Q = \SOC.Core.Pc.PC_Register).
Adding SRST signal on $flatten\SOC.\Core.\Control_Unit.$procdff$2143 ($dff) from module top (D = \SOC.Core.Control_Unit.nextstate, Q = \SOC.Core.Control_Unit.state, rval = 4'0000).
Adding SRST signal on $flatten\SOC.\Core.$procdff$2098 ($dff) from module top (D = \SOC.Bus.write_data, Q = \SOC.Core.register_data_2, rval = 0).
Adding SRST signal on $flatten\SOC.\Core.$procdff$2097 ($dff) from module top (D = \SOC.Core.register_data_1_out, Q = \SOC.Core.register_data_1, rval = 0).
Adding SRST signal on $flatten\SOC.\Core.$procdff$2096 ($dff) from module top (D = \SOC.Core.Alu.ALU_out_S, Q = \SOC.Core.alu_out_register, rval = 0).
Adding SRST signal on $flatten\SOC.\Core.$procdff$2095 ($dff) from module top (D = \SOC.Core.read_data, Q = \SOC.Core.memory_register, rval = 0).
Adding SRST signal on $flatten\SOC.\Core.$procdff$2094 ($dff) from module top (D = $flatten\SOC.\Core.$procmux$983_Y, Q = \SOC.Core.instruction_register, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$2499 ($sdff) from module top (D = \SOC.Core.read_data, Q = \SOC.Core.instruction_register).
Adding EN signal on $flatten\ResetBootSystem.$procdff$2146 ($dff) from module top (D = $flatten\ResetBootSystem.$0\counter[5:0], Q = \ResetBootSystem.counter).
Adding EN signal on $flatten\ResetBootSystem.$procdff$2145 ($dff) from module top (D = $flatten\ResetBootSystem.$0\state[1:0], Q = \ResetBootSystem.state).
Adding EN signal on $flatten\ResetBootSystem.$procdff$2144 ($dff) from module top (D = $flatten\ResetBootSystem.$0\reset_o[0:0], Q = \ResetBootSystem.reset_o).
Adding SRST signal on $flatten\ClkDivider.$procdff$2142 ($dff) from module top (D = $flatten\ClkDivider.$add$Risco-5/debug/clk_divider.v:32$523_Y, Q = \ClkDivider.clk_counter, rval = 0).
Adding SRST signal on $flatten\ClkDivider.$procdff$2141 ($dff) from module top (D = $flatten\ClkDivider.$procmux$1871_Y, Q = \ClkDivider.clk_o_auto, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$2527 ($sdff) from module top (D = $flatten\ClkDivider.$procmux$1871_Y, Q = \ClkDivider.clk_o_auto).
Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$2487 ($sdffe) from module top.
Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$2487 ($sdffe) from module top.
Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$2487 ($sdffe) from module top.
Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$2487 ($sdffe) from module top.
Setting constant 0-bit at position 4 on $auto$ff.cc:266:slice$2487 ($sdffe) from module top.
Setting constant 0-bit at position 5 on $auto$ff.cc:266:slice$2487 ($sdffe) from module top.
Setting constant 0-bit at position 6 on $auto$ff.cc:266:slice$2487 ($sdffe) from module top.
Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$2487 ($sdffe) from module top.
Setting constant 0-bit at position 8 on $auto$ff.cc:266:slice$2487 ($sdffe) from module top.
Setting constant 0-bit at position 9 on $auto$ff.cc:266:slice$2487 ($sdffe) from module top.
Setting constant 0-bit at position 10 on $auto$ff.cc:266:slice$2487 ($sdffe) from module top.
Setting constant 0-bit at position 11 on $auto$ff.cc:266:slice$2487 ($sdffe) from module top.
Setting constant 0-bit at position 12 on $auto$ff.cc:266:slice$2487 ($sdffe) from module top.
Setting constant 0-bit at position 13 on $auto$ff.cc:266:slice$2487 ($sdffe) from module top.
Setting constant 0-bit at position 14 on $auto$ff.cc:266:slice$2487 ($sdffe) from module top.
Setting constant 0-bit at position 15 on $auto$ff.cc:266:slice$2487 ($sdffe) from module top.
Setting constant 0-bit at position 16 on $auto$ff.cc:266:slice$2487 ($sdffe) from module top.
Setting constant 0-bit at position 17 on $auto$ff.cc:266:slice$2487 ($sdffe) from module top.
Setting constant 0-bit at position 18 on $auto$ff.cc:266:slice$2487 ($sdffe) from module top.
Setting constant 0-bit at position 19 on $auto$ff.cc:266:slice$2487 ($sdffe) from module top.
Setting constant 0-bit at position 20 on $auto$ff.cc:266:slice$2487 ($sdffe) from module top.
Setting constant 0-bit at position 21 on $auto$ff.cc:266:slice$2487 ($sdffe) from module top.
Setting constant 0-bit at position 22 on $auto$ff.cc:266:slice$2487 ($sdffe) from module top.
Setting constant 0-bit at position 23 on $auto$ff.cc:266:slice$2487 ($sdffe) from module top.
Setting constant 0-bit at position 24 on $auto$ff.cc:266:slice$2487 ($sdffe) from module top.
Setting constant 0-bit at position 25 on $auto$ff.cc:266:slice$2487 ($sdffe) from module top.
Setting constant 0-bit at position 26 on $auto$ff.cc:266:slice$2487 ($sdffe) from module top.
Setting constant 0-bit at position 27 on $auto$ff.cc:266:slice$2487 ($sdffe) from module top.
Setting constant 0-bit at position 28 on $auto$ff.cc:266:slice$2487 ($sdffe) from module top.
Setting constant 0-bit at position 29 on $auto$ff.cc:266:slice$2487 ($sdffe) from module top.
Setting constant 0-bit at position 30 on $auto$ff.cc:266:slice$2487 ($sdffe) from module top.
Setting constant 0-bit at position 31 on $auto$ff.cc:266:slice$2487 ($sdffe) from module top.
Setting constant 0-bit at position 32 on $auto$ff.cc:266:slice$2320 ($sdffe) from module top.

21.13.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 174 unused cells and 182 unused wires.
<suppressed ~181 debug messages>

21.13.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~6 debug messages>

21.13.9. Rerunning OPT passes. (Maybe there is more to do..)

21.13.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~38 debug messages>

21.13.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
    New input vector for $reduce_or cell $auto$opt_dff.cc:254:combine_resets$2307: { \SOC.Uart.i_uart_rx.fsm_state [3:2] \SOC.Uart.i_uart_rx.fsm_state [0] \ResetBootSystem.reset_o }
  Optimizing cells in module \top.
Performed a total of 1 changes.

21.13.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~93 debug messages>
Removed a total of 31 cells.

21.13.13. Executing OPT_DFF pass (perform DFF optimizations).

21.13.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 1 unused cells and 32 unused wires.
<suppressed ~2 debug messages>

21.13.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

21.13.16. Rerunning OPT passes. (Maybe there is more to do..)

21.13.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~38 debug messages>

21.13.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

21.13.19. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

21.13.20. Executing OPT_DFF pass (perform DFF optimizations).

21.13.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

21.13.22. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

21.13.23. Finished OPT passes. (There is nothing left to do.)

21.14. Executing WREDUCE pass (reducing word size of cells).
Removed top 28 address bits (of 32) from memory init port top.$flatten\SOC.\Core.\Control_Unit.$auto$mem.cc:328:emit$680 ($flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678).
Removed top 22 address bits (of 32) from memory init port top.$flatten\SOC.\Memory.$auto$proc_memwr.cc:45:proc_memwr$2147 (SOC.Memory.memory).
Removed top 22 address bits (of 32) from memory init port top.$flatten\SOC.\Memory.$meminit$\memory$Risco-5/src/peripheral/memory.v:0$675 (SOC.Memory.memory).
Removed top 22 address bits (of 32) from memory read port top.$flatten\SOC.\Memory.$memrd$\memory$Risco-5/src/peripheral/memory.v:17$665 (SOC.Memory.memory).
Removed top 9 bits (of 32) from port B of cell top.$flatten\ClkDivider.$ge$Risco-5/debug/clk_divider.v:40$529 ($ge).
Removed top 31 bits (of 32) from port B of cell top.$flatten\ClkDivider.$add$Risco-5/debug/clk_divider.v:37$527 ($add).
Removed top 10 bits (of 32) from port B of cell top.$flatten\ClkDivider.$eq$Risco-5/debug/clk_divider.v:33$525 ($eq).
Removed top 1 bits (of 2) from port B of cell top.$flatten\ResetBootSystem.$procmux$2023_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\ResetBootSystem.$eq$Risco-5/debug/reset.v:38$513 ($eq).
Removed top 31 bits (of 32) from port B of cell top.$flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$512 ($add).
Removed top 26 bits (of 32) from port Y of cell top.$flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$512 ($add).
Removed top 27 bits (of 32) from port B of cell top.$flatten\ResetBootSystem.$lt$Risco-5/debug/reset.v:36$511 ($lt).
Removed top 26 bits (of 32) from mux cell top.$flatten\SOC.\GPIOS.$ternary$Risco-5/src/peripheral/gpios.v:20$660 ($mux).
Removed top 24 bits (of 32) from mux cell top.$flatten\SOC.\Uart.$ternary$Risco-5/src/peripheral/uart.v:24$539 ($mux).
Removed top 2 bits (of 13) from port B of cell top.$flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:111$622 ($eq).
Removed top 1 bits (of 13) from port B of cell top.$flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:109$620 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:135$586 ($eq).
Removed top 30 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:103$573 ($mux).
Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:102$572 ($mux).
Removed top 30 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:101$571 ($mux).
Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:100$570 ($mux).
Removed top 3 bits (of 4) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:94$566 ($eq).
Removed top 1 bits (of 13) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:92$564 ($eq).
Removed top 1 bits (of 33) from mux cell top.$flatten\SOC.\Leds.$ternary$Risco-5/src/peripheral/leds.v:21$162 ($mux).
Removed top 2 bits (of 8) from port Y of cell top.$flatten\SOC.\Leds.$not$Risco-5/src/peripheral/leds.v:31$165 ($not).
Removed top 2 bits (of 8) from port A of cell top.$flatten\SOC.\Leds.$not$Risco-5/src/peripheral/leds.v:31$165 ($not).
Removed top 20 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:54$74 ($le).
Removed top 19 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:55$77 ($ge).
Removed top 19 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:56$78 ($le).
Removed top 19 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:57$81 ($ge).
Removed top 19 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:58$82 ($le).
Removed top 19 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:59$85 ($ge).
Removed top 19 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:60$86 ($le).
Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$2512 ($ne).
Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$2507 ($ne).
Removed top 24 bits (of 32) from mux cell top.$flatten\SOC.\Bus.$ternary$Risco-5/src/peripheral/bus.v:91$146 ($mux).
Removed top 22 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$995 ($mux).
Removed top 5 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$eq$Risco-5/src/core/control_unit.v:99$51 ($eq).
Removed top 29 bits (of 32) from port B of cell top.$flatten\SOC.\Core.\Immediate_Generator.$sub$Risco-5/src/core/immediate_generator.v:10$61 ($sub).
Removed top 1 bits (of 2) from port B of cell top.$flatten\SOC.\Core.\AluInputAMUX.$procmux$1843_CMP0 ($eq).
Removed top 1 bits (of 2) from port B of cell top.$flatten\SOC.\Core.\AluInputBMUX.$procmux$1843_CMP0 ($eq).
Removed top 4 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1833_CMP0 ($eq).
Removed top 3 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1832_CMP0 ($eq).
Removed top 3 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1831_CMP0 ($eq).
Removed top 2 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1830_CMP0 ($eq).
Removed top 2 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1829_CMP0 ($eq).
Removed top 2 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1828_CMP0 ($eq).
Removed top 2 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1827_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1826_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1825_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1824_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1823_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1822_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1821_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1820_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1819_CMP0 ($eq).
Removed top 4 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1800_CMP0 ($eq).
Removed top 3 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1799_CMP0 ($eq).
Removed top 3 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1798_CMP0 ($eq).
Removed top 2 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1797_CMP0 ($eq).
Removed top 2 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1796_CMP0 ($eq).
Removed top 2 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1795_CMP0 ($eq).
Removed top 2 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1794_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1793_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1792_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1791_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1790_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1789_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1788_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1787_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1786_CMP0 ($eq).
Removed top 4 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1725_CMP0 ($eq).
Removed top 3 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1687_CMP0 ($eq).
Removed top 3 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1650_CMP0 ($eq).
Removed top 2 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1614_CMP0 ($eq).
Removed top 2 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1579_CMP0 ($eq).
Removed top 2 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1545_CMP0 ($eq).
Removed top 2 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1512_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1480_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1449_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1419_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1390_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1362_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1335_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1309_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1284_CMP0 ($eq).
Removed top 2 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1947_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1946_CMP0 ($eq).
Removed top 3 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1918_CMP0 ($eq).
Removed top 1 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1915_CMP0 ($eq).
Removed top 1 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1914_CMP0 ($eq).
Removed top 2 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1913_CMP0 ($eq).
Removed top 2 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1910_CMP0 ($eq).
Removed top 1 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1909_CMP0 ($eq).
Removed top 2 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1893_CMP0 ($eq).
Removed top 1 bits (of 4) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1890 ($mux).
Removed top 1 bits (of 2) from port B of cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$1996_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$1978_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$1977_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$1976_CMP0 ($eq).
Removed top 1 bits (of 4) from mux cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$1964 ($mux).
Removed top 1 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\ALU_Control.$eq$Risco-5/src/core/alu_control.v:35$47 ($eq).
Removed top 3 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Alu.$procmux$2009_CMP0 ($eq).
Removed top 2 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Alu.$procmux$2008_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Alu.$procmux$2007_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Alu.$procmux$2006_CMP0 ($eq).
Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Core.\Alu.$ternary$Risco-5/src/core/alu.v:34$44 ($mux).
Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Core.\Alu.$ternary$Risco-5/src/core/alu.v:22$36 ($mux).
Removed top 29 bits (of 32) from port B of cell top.$flatten\SOC.\Core.\Immediate_Generator.$sub$Risco-5/src/core/immediate_generator.v:12$62 ($sub).
Removed top 31 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:53$73 ($ge).
Removed top 20 bits (of 32) from mux cell top.$flatten\SOC.\Bus.$ternary$Risco-5/src/peripheral/bus.v:80$124 ($mux).
Removed top 26 bits (of 32) from wire top.$flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$512_Y.
Removed top 24 bits (of 32) from wire top.$flatten\SOC.\Bus.$ternary$Risco-5/src/peripheral/bus.v:91$146_Y.
Removed top 1 bits (of 4) from wire top.$flatten\SOC.\Core.\ALU_Control.$4\aluop_out[3:0].
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Core.\Alu.$eq$Risco-5/src/core/alu.v:32$42_Y.
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Core.\Alu.$ternary$Risco-5/src/core/alu.v:22$36_Y.
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Core.\Alu.$ternary$Risco-5/src/core/alu.v:34$44_Y.
Removed top 1 bits (of 4) from wire top.$flatten\SOC.\Core.\Control_Unit.$4\nextstate[3:0].
Removed top 22 bits (of 32) from wire top.$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$663_ADDR[31:0]$668.
Removed top 2 bits (of 32) from wire top.$flatten\SOC.\Memory.$memrd$\memory$Risco-5/src/peripheral/memory.v:17$665_DATA.
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:100$570_Y.
Removed top 30 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:101$571_Y.
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:102$572_Y.
Removed top 30 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:103$573_Y.
Removed top 2 bits (of 8) from wire top.leds.

21.15. Executing PEEPOPT pass (run peephole optimizers).

21.16. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 15 unused wires.
<suppressed ~1 debug messages>

21.17. Executing SHARE pass (SAT-based resource sharing).
Found 3 cells in module top that may be considered for resource sharing.
  Analyzing resource sharing options for $flatten\SOC.\Memory.$memrd$\memory$Risco-5/src/peripheral/memory.v:17$665 ($memrd):
    Found 1 activation_patterns using ctrl signal { $flatten\SOC.\Bus.$logic_and$Risco-5/src/peripheral/bus.v:53$75_Y \SOC.Bus.slave_0_read }.
    No candidates found.
  Analyzing resource sharing options for $flatten\SOC.\Core.\Alu.$shr$Risco-5/src/core/alu.v:28$40 ($shr):
    Found 1 activation_patterns using ctrl signal $flatten\SOC.\Core.\Alu.$procmux$2003_CMP.
    No candidates found.
  Analyzing resource sharing options for $flatten\SOC.\Core.\Alu.$shl$Risco-5/src/core/alu.v:26$39 ($shl):
    Found 1 activation_patterns using ctrl signal $flatten\SOC.\Core.\Alu.$procmux$2004_CMP.
    No candidates found.

21.18. Executing TECHMAP pass (map to technology primitives).

21.18.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/cmp2lut.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/cmp2lut.v' to AST representation.
Generating RTLIL representation for module `\_90_lut_cmp_'.
Successfully finished Verilog frontend.

21.18.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~322 debug messages>

21.19. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

21.20. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

21.21. Executing TECHMAP pass (map to technology primitives).

21.21.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v' to AST representation.
Generating RTLIL representation for module `\_80_mul'.
Generating RTLIL representation for module `\_90_soft_mul'.
Successfully finished Verilog frontend.

21.21.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/dsp_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/dsp_map.v' to AST representation.
Generating RTLIL representation for module `\$__MUL18X18'.
Successfully finished Verilog frontend.

21.21.3. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~5 debug messages>

21.22. Executing ALUMACC pass (create $alu and $macc cells).
Extracting $alu and $macc cells in module top:
  creating $macc model for $flatten\ClkDivider.$add$Risco-5/debug/clk_divider.v:37$527 ($add).
  creating $macc model for $flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$512 ($add).
  creating $macc model for $flatten\SOC.\Core.\Alu.$add$Risco-5/src/core/alu.v:18$33 ($add).
  creating $macc model for $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:20$34 ($sub).
  creating $macc model for $flatten\SOC.\Core.\Immediate_Generator.$sub$Risco-5/src/core/immediate_generator.v:10$61 ($sub).
  creating $macc model for $flatten\SOC.\Core.\Immediate_Generator.$sub$Risco-5/src/core/immediate_generator.v:12$62 ($sub).
  creating $macc model for $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:154$641 ($add).
  creating $macc model for $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:179$652 ($add).
  creating $macc model for $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:138$590 ($add).
  creating $macc model for $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:155$601 ($add).
  creating $alu model for $macc $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:155$601.
  creating $alu model for $macc $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:138$590.
  creating $alu model for $macc $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:179$652.
  creating $alu model for $macc $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:154$641.
  creating $alu model for $macc $flatten\SOC.\Core.\Immediate_Generator.$sub$Risco-5/src/core/immediate_generator.v:12$62.
  creating $alu model for $macc $flatten\SOC.\Core.\Immediate_Generator.$sub$Risco-5/src/core/immediate_generator.v:10$61.
  creating $alu model for $macc $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:20$34.
  creating $alu model for $macc $flatten\SOC.\Core.\Alu.$add$Risco-5/src/core/alu.v:18$33.
  creating $alu model for $macc $flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$512.
  creating $alu model for $macc $flatten\ClkDivider.$add$Risco-5/debug/clk_divider.v:37$527.
  creating $alu model for $flatten\ClkDivider.$ge$Risco-5/debug/clk_divider.v:40$529 ($ge): new $alu
  creating $alu model for $flatten\ResetBootSystem.$lt$Risco-5/debug/reset.v:36$511 ($lt): new $alu
  creating $alu model for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:53$73 ($ge): new $alu
  creating $alu model for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:55$77 ($ge): new $alu
  creating $alu model for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:57$81 ($ge): new $alu
  creating $alu model for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:59$85 ($ge): new $alu
  creating $alu model for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:54$74 ($le): new $alu
  creating $alu model for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:56$78 ($le): new $alu
  creating $alu model for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:58$82 ($le): new $alu
  creating $alu model for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:60$86 ($le): new $alu
  creating $alu model for $flatten\SOC.\Core.\Alu.$ge$Risco-5/src/core/alu.v:34$43 ($ge): merged with $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:20$34.
  creating $alu model for $flatten\SOC.\Core.\Alu.$lt$Risco-5/src/core/alu.v:22$35 ($lt): merged with $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:20$34.
  creating $alu model for $flatten\ResetBootSystem.$eq$Risco-5/debug/reset.v:38$513 ($eq): merged with $flatten\ResetBootSystem.$lt$Risco-5/debug/reset.v:36$511.
  creating $alu model for $flatten\SOC.\Core.\Alu.$eq$Risco-5/src/core/alu.v:32$42 ($eq): merged with $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:20$34.
  creating $alu cell for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:60$86: $auto$alumacc.cc:485:replace_alu$2557
  creating $alu cell for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:58$82: $auto$alumacc.cc:485:replace_alu$2570
  creating $alu cell for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:56$78: $auto$alumacc.cc:485:replace_alu$2583
  creating $alu cell for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:54$74: $auto$alumacc.cc:485:replace_alu$2596
  creating $alu cell for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:59$85: $auto$alumacc.cc:485:replace_alu$2609
  creating $alu cell for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:57$81: $auto$alumacc.cc:485:replace_alu$2618
  creating $alu cell for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:55$77: $auto$alumacc.cc:485:replace_alu$2627
  creating $alu cell for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:53$73: $auto$alumacc.cc:485:replace_alu$2636
  creating $alu cell for $flatten\ResetBootSystem.$lt$Risco-5/debug/reset.v:36$511, $flatten\ResetBootSystem.$eq$Risco-5/debug/reset.v:38$513: $auto$alumacc.cc:485:replace_alu$2645
  creating $alu cell for $flatten\ClkDivider.$ge$Risco-5/debug/clk_divider.v:40$529: $auto$alumacc.cc:485:replace_alu$2656
  creating $alu cell for $flatten\ClkDivider.$add$Risco-5/debug/clk_divider.v:37$527: $auto$alumacc.cc:485:replace_alu$2665
  creating $alu cell for $flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$512: $auto$alumacc.cc:485:replace_alu$2668
  creating $alu cell for $flatten\SOC.\Core.\Alu.$add$Risco-5/src/core/alu.v:18$33: $auto$alumacc.cc:485:replace_alu$2671
  creating $alu cell for $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:20$34, $flatten\SOC.\Core.\Alu.$ge$Risco-5/src/core/alu.v:34$43, $flatten\SOC.\Core.\Alu.$lt$Risco-5/src/core/alu.v:22$35, $flatten\SOC.\Core.\Alu.$eq$Risco-5/src/core/alu.v:32$42: $auto$alumacc.cc:485:replace_alu$2674
  creating $alu cell for $flatten\SOC.\Core.\Immediate_Generator.$sub$Risco-5/src/core/immediate_generator.v:10$61: $auto$alumacc.cc:485:replace_alu$2687
  creating $alu cell for $flatten\SOC.\Core.\Immediate_Generator.$sub$Risco-5/src/core/immediate_generator.v:12$62: $auto$alumacc.cc:485:replace_alu$2690
  creating $alu cell for $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:154$641: $auto$alumacc.cc:485:replace_alu$2693
  creating $alu cell for $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:179$652: $auto$alumacc.cc:485:replace_alu$2696
  creating $alu cell for $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:138$590: $auto$alumacc.cc:485:replace_alu$2699
  creating $alu cell for $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:155$601: $auto$alumacc.cc:485:replace_alu$2702
  created 20 $alu and 0 $macc cells.

21.23. Executing OPT pass (performing simple optimizations).

21.23.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~3 debug messages>

21.23.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

21.23.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~38 debug messages>

21.23.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
    New input vector for $reduce_or cell $auto$opt_dff.cc:254:combine_resets$2526: { $auto$rtlil.cc:2461:Not$2660 $auto$rtlil.cc:2464:ReduceAnd$2662 \reset }
  Optimizing cells in module \top.
Performed a total of 1 changes.

21.23.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

21.23.6. Executing OPT_DFF pass (perform DFF optimizations).

21.23.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 1 unused cells and 15 unused wires.
<suppressed ~2 debug messages>

21.23.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

21.23.9. Rerunning OPT passes. (Maybe there is more to do..)

21.23.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~38 debug messages>

21.23.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

21.23.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

21.23.13. Executing OPT_DFF pass (perform DFF optimizations).

21.23.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

21.23.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

21.23.16. Finished OPT passes. (There is nothing left to do.)

21.24. Executing MEMORY pass.

21.24.1. Executing OPT_MEM pass (optimize memories).
Performed a total of 0 transformations.

21.24.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).
Performed a total of 0 transformations.

21.24.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).
  Analyzing top.SOC.Memory.memory write port 0.

21.24.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs).

21.24.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd).
Checking read port `$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678'[0] in module `\top': no output FF found.
Checking read port `\SOC.Memory.memory'[0] in module `\top': no output FF found.
Checking read port address `$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678'[0] in module `\top': address FF has fully-defined init value, not supported.
Checking read port address `\SOC.Memory.memory'[0] in module `\top': no address FF found.

21.24.6. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

21.24.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).

21.24.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).
Performed a total of 0 transformations.

21.24.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

21.24.10. Executing MEMORY_COLLECT pass (generating $mem cells).

21.25. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

21.26. Executing MEMORY_LIBMAP pass (mapping memories to cells).
using FF mapping for memory top.$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678
mapping memory top.SOC.Memory.memory via $__TRELLIS_DPR16X4_
<suppressed ~88 debug messages>

21.27. Executing TECHMAP pass (map to technology primitives).

21.27.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/lutrams_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/lutrams_map.v' to AST representation.
Generating RTLIL representation for module `\$__TRELLIS_DPR16X4_'.
Successfully finished Verilog frontend.

21.27.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/brams_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/brams_map.v' to AST representation.
Generating RTLIL representation for module `\$__ECP5_DP16KD_'.
Generating RTLIL representation for module `\$__ECP5_PDPW16KD_'.
Successfully finished Verilog frontend.

21.27.3. Continuing TECHMAP pass.
Using template $paramod$b089c18cc881634130ec6d4716ef25d78c9d48c9\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$04778961cc1285a5efea28f98f28381eb2862208\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$731f2d82778baee6f78f5f3e0670a3ade61ac0d6\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$48358c22c7a8e5b48ddefb8e14a8bb1f81de841f\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$5276274b86ff102139fbc8ae2dfc335d77b58a6a\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$0eb199c7b2cea9c358f23ffe94c4548bdd802747\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$fb6ed8f936d3525780a052d218072c625795bc14\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$c75b2ca41d3ff8a2b5ad26d6a6ec321bb6e56448\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$315d0c5245324146665fc1ab307bed98cfcb6adf\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
No more expansions possible.
<suppressed ~634 debug messages>

21.28. Executing OPT pass (performing simple optimizations).

21.28.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~71 debug messages>

21.28.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~12 debug messages>
Removed a total of 4 cells.

21.28.3. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $auto$ff.cc:266:slice$2501 ($dffe) from module top (D = $flatten\ResetBootSystem.$procmux$2020_Y, Q = \ResetBootSystem.counter, rval = 6'000000).

21.28.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 26 unused cells and 3638 unused wires.
<suppressed ~27 debug messages>

21.28.5. Rerunning OPT passes. (Removed registers in this run.)

21.28.6. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~2 debug messages>

21.28.7. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

21.28.8. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $auto$ff.cc:266:slice$3978 ($sdffce) from module top (D = $auto$wreduce.cc:461:run$2532 [5:0], Q = \ResetBootSystem.counter, rval = 6'000000).

21.28.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 2 unused cells and 3 unused wires.
<suppressed ~3 debug messages>

21.28.10. Rerunning OPT passes. (Removed registers in this run.)

21.28.11. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

21.28.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

21.28.13. Executing OPT_DFF pass (perform DFF optimizations).

21.28.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

21.28.15. Finished fast OPT passes.

21.29. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).
Mapping memory $flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678 in module \top:
  created 16 $dff cells and 0 static cells of width 16.
  read interface: 0 $dff and 15 $mux cells.
  write interface: 0 write mux blocks.

21.30. Executing OPT pass (performing simple optimizations).

21.30.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

21.30.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

21.30.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~34 debug messages>

21.30.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
    Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][3][6]$4023:
      Old ports: A=16'0100000000000000, B=16'0100001000000000, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][2][3]$a$4003
      New ports: A=1'0, B=1'1, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][2][3]$a$4003 [9]
      New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][2][3]$a$4003 [15:10] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][2][3]$a$4003 [8:0] } = 15'010000000000000
    Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][3][5]$4020:
      Old ports: A=16'0000000101100010, B=16'1010000000100001, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][2][2]$b$4001
      New ports: A=2'10, B=2'01, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][2][2]$b$4001 [1:0]
      New connections: $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][2][2]$b$4001 [15:2] = { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][2][2]$b$4001 [0] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][2][2]$b$4001 [0] 4'0000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][2][2]$b$4001 [1] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][2][2]$b$4001 [1] 4'1000 }
    Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][3][4]$4017:
      Old ports: A=16'0100000110000001, B=16'1010000000100000, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][2][2]$a$4000
      New ports: A=2'01, B=2'10, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][2][2]$a$4000 [5] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][2][2]$a$4000 [0] }
      New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][2][2]$a$4000 [15:6] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][2][2]$a$4000 [4:1] } = { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][2][2]$a$4000 [5] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][2][2]$a$4000 [0] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][2][2]$a$4000 [5] 4'0000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][2][2]$a$4000 [0] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][2][2]$a$4000 [0] 5'00000 }
    Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][3][3]$4014:
      Old ports: A=16'0000000110000000, B=16'0000010000000000, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][2][1]$b$3998
      New ports: A=2'01, B=2'10, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][2][1]$b$3998 [10] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][2][1]$b$3998 [7] }
      New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][2][1]$b$3998 [15:11] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][2][1]$b$3998 [9:8] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][2][1]$b$3998 [6:0] } = { 6'000000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][2][1]$b$3998 [7] 7'0000000 }
    Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][3][2]$4011:
      Old ports: A=16'0000010000010000, B=16'0000000000001100, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][2][1]$a$3997
      New ports: A=2'10, B=2'01, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][2][1]$a$3997 [4] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][2][1]$a$3997 [2] }
      New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][2][1]$a$3997 [15:5] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][2][1]$a$3997 [3] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][2][1]$a$3997 [1:0] } = { 5'00000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][2][1]$a$3997 [4] 5'00000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][2][1]$a$3997 [2] 2'00 }
    Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][3][1]$4008:
      Old ports: A=16'0100000100000000, B=16'0000100000000100, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][2][0]$b$3995
      New ports: A=2'10, B=2'01, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][2][0]$b$3995 [8] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][2][0]$b$3995 [2] }
      New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][2][0]$b$3995 [15:9] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][2][0]$b$3995 [7:3] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][2][0]$b$3995 [1:0] } = { 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][2][0]$b$3995 [8] 2'00 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][2][0]$b$3995 [2] 9'000000000 }
    Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][3][0]$4005:
      Old ports: A=16'1011100000000000, B=16'0100000000000000, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][2][0]$a$3994
      New ports: A=2'01, B=2'10, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][2][0]$a$3994 [14] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][2][0]$a$3994 [11] }
      New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][2][0]$a$3994 [15] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][2][0]$a$3994 [13:12] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][2][0]$a$3994 [10:0] } = { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][2][0]$a$3994 [11] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][2][0]$a$3994 [11] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][2][0]$a$3994 [11] 11'00000000000 }
    New ctrl vector for $pmux cell $flatten\ResetBootSystem.$procmux$2029: { $flatten\ResetBootSystem.$procmux$2024_CMP $flatten\ResetBootSystem.$procmux$2023_CMP }
    Consolidated identical input bits for $mux cell $flatten\ResetBootSystem.$procmux$2032:
      Old ports: A=2'00, B=2'10, Y=$flatten\ResetBootSystem.$procmux$2032_Y
      New ports: A=1'0, B=1'1, Y=$flatten\ResetBootSystem.$procmux$2032_Y [1]
      New connections: $flatten\ResetBootSystem.$procmux$2032_Y [0] = 1'0
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\ALU_Control.$procmux$1964:
      Old ports: A=3'010, B=3'110, Y=$auto$wreduce.cc:461:run$2534 [2:0]
      New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:461:run$2534 [2]
      New connections: $auto$wreduce.cc:461:run$2534 [1:0] = 2'10
    Consolidated identical input bits for $pmux cell $flatten\SOC.\Core.\ALU_Control.$procmux$1985:
      Old ports: A=4'0110, B=12'101101111110, Y=$flatten\SOC.\Core.\ALU_Control.$2\aluop_out[3:0]
      New ports: A=3'010, B=9'101011110, Y={ $flatten\SOC.\Core.\ALU_Control.$2\aluop_out[3:0] [3:2] $flatten\SOC.\Core.\ALU_Control.$2\aluop_out[3:0] [0] }
      New connections: $flatten\SOC.\Core.\ALU_Control.$2\aluop_out[3:0] [1] = 1'1
    Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][3][7]$4026:
      Old ports: A=16'0100000100000000, B=16'0000000000000000, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][2][3]$b$4004
      New ports: A=1'1, B=1'0, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][2][3]$b$4004 [8]
      New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][2][3]$b$4004 [15:9] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][2][3]$b$4004 [7:0] } = { 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][2][3]$b$4004 [8] 13'0000000000000 }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$1890:
      Old ports: A=3'101, B=3'011, Y=$auto$wreduce.cc:461:run$2538 [2:0]
      New ports: A=2'10, B=2'01, Y=$auto$wreduce.cc:461:run$2538 [2:1]
      New connections: $auto$wreduce.cc:461:run$2538 [0] = 1'1
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$1935:
      Old ports: A=4'0001, B=4'1110, Y=$flatten\SOC.\Core.\Control_Unit.$2\nextstate[3:0]
      New ports: A=2'01, B=2'10, Y=$flatten\SOC.\Core.\Control_Unit.$2\nextstate[3:0] [1:0]
      New connections: $flatten\SOC.\Core.\Control_Unit.$2\nextstate[3:0] [3:2] = { $flatten\SOC.\Core.\Control_Unit.$2\nextstate[3:0] [1] $flatten\SOC.\Core.\Control_Unit.$2\nextstate[3:0] [1] }
    Consolidated identical input bits for $pmux cell $flatten\SOC.\Uart.\i_uart_tx.$procmux$966:
      Old ports: A=3'000, B={ 2'00 \SOC.Uart.uart_tx_en 1'0 $auto$wreduce.cc:461:run$2542 [1:0] 2'01 \SOC.Uart.i_uart_tx.payload_done 1'0 $auto$wreduce.cc:461:run$2544 [1:0] }, Y=\SOC.Uart.i_uart_tx.n_fsm_state
      New ports: A=2'00, B={ 1'0 \SOC.Uart.uart_tx_en $auto$wreduce.cc:461:run$2542 [1:0] 1'1 \SOC.Uart.i_uart_tx.payload_done $auto$wreduce.cc:461:run$2544 [1:0] }, Y=\SOC.Uart.i_uart_tx.n_fsm_state [1:0]
      New connections: \SOC.Uart.i_uart_tx.n_fsm_state [2] = 1'0
    Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:103$573:
      Old ports: A=2'11, B=2'00, Y=$auto$wreduce.cc:461:run$2544 [1:0]
      New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$2544 [0]
      New connections: $auto$wreduce.cc:461:run$2544 [1] = $auto$wreduce.cc:461:run$2544 [0]
  Optimizing cells in module \top.
    Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][2][3]$4002:
      Old ports: A=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][2][3]$a$4003, B=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][2][3]$b$4004, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][1][1]$b$3992
      New ports: A={ 1'1 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][2][3]$a$4003 [9] 1'0 }, B={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][2][3]$b$4004 [8] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][2][3]$b$4004 [8] }, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][1][1]$b$3992 [14] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][1][1]$b$3992 [9:8] }
      New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][1][1]$b$3992 [15] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][1][1]$b$3992 [13:10] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][1][1]$b$3992 [7:0] } = 13'0000000000000
    Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][2][2]$3999:
      Old ports: A=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][2][2]$a$4000, B=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][2][2]$b$4001, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][1][1]$a$3991
      New ports: A={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][2][2]$a$4000 [5] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][2][2]$a$4000 [0] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][2][2]$a$4000 [0] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][2][2]$a$4000 [5] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][2][2]$a$4000 [0] }, B={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][2][2]$b$4001 [0] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][2][2]$b$4001 [1] 2'01 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][2][2]$b$4001 [1:0] }, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][1][1]$a$3991 [13] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][1][1]$a$3991 [8:7] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][1][1]$a$3991 [5] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][1][1]$a$3991 [1:0] }
      New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][1][1]$a$3991 [15:14] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][1][1]$a$3991 [12:9] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][1][1]$a$3991 [6] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][1][1]$a$3991 [4:2] } = { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][1][1]$a$3991 [13] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][1][1]$a$3991 [7] 4'0000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][1][1]$a$3991 [1] 3'000 }
    Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][2][1]$3996:
      Old ports: A=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][2][1]$a$3997, B=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][2][1]$b$3998, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][1][0]$b$3989
      New ports: A={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][2][1]$a$3997 [4] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][2][1]$a$3997 [4] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][2][1]$a$3997 [2] }, B={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][2][1]$b$3998 [10] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][2][1]$b$3998 [7] 2'00 }, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][1][0]$b$3989 [10] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][1][0]$b$3989 [7] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][1][0]$b$3989 [4] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][1][0]$b$3989 [2] }
      New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][1][0]$b$3989 [15:11] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][1][0]$b$3989 [9:8] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][1][0]$b$3989 [6:5] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][1][0]$b$3989 [3] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][1][0]$b$3989 [1:0] } = { 6'000000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][1][0]$b$3989 [7] 2'00 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][1][0]$b$3989 [2] 2'00 }
    Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][2][0]$3993:
      Old ports: A=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][2][0]$a$3994, B=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][2][0]$b$3995, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][1][0]$a$3988
      New ports: A={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][2][0]$a$3994 [14] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][2][0]$a$3994 [11] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][2][0]$a$3994 [11] 2'00 }, B={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][2][0]$b$3995 [8] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][2][0]$b$3995 [2] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][2][0]$b$3995 [8] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][2][0]$b$3995 [2] }, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][1][0]$a$3988 [14] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][1][0]$a$3988 [12:11] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][1][0]$a$3988 [8] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][1][0]$a$3988 [2] }
      New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][1][0]$a$3988 [15] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][1][0]$a$3988 [13] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][1][0]$a$3988 [10:9] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][1][0]$a$3988 [7:3] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][1][0]$a$3988 [1:0] } = { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][1][0]$a$3988 [12] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][1][0]$a$3988 [12] 9'000000000 }
    Consolidated identical input bits for $mux cell $flatten\ResetBootSystem.$procmux$2038:
      Old ports: A=2'00, B=$flatten\ResetBootSystem.$procmux$2032_Y, Y=$flatten\ResetBootSystem.$procmux$2038_Y
      New ports: A=1'0, B=$flatten\ResetBootSystem.$procmux$2032_Y [1], Y=$flatten\ResetBootSystem.$procmux$2038_Y [1]
      New connections: $flatten\ResetBootSystem.$procmux$2038_Y [0] = 1'0
  Optimizing cells in module \top.
    Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][1][1]$3990:
      Old ports: A=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][1][1]$a$3991, B=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][1][1]$b$3992, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][0][0]$b$3986
      New ports: A={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][1][1]$a$3991 [7] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][1][1]$a$3991 [13] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][1][1]$a$3991 [8:7] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][1][1]$a$3991 [5] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][1][1]$a$3991 [1:0] }, B={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][1][1]$b$3992 [14] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][1][1]$b$3992 [9:8] 4'0000 }, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][0][0]$b$3986 [14:13] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][0][0]$b$3986 [9:7] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][0][0]$b$3986 [5] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][0][0]$b$3986 [1:0] }
      New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][0][0]$b$3986 [15] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][0][0]$b$3986 [12:10] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][0][0]$b$3986 [6] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][0][0]$b$3986 [4:2] } = { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][0][0]$b$3986 [13] 3'000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][0][0]$b$3986 [1] 3'000 }
    Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][1][0]$3987:
      Old ports: A=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][1][0]$a$3988, B=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][1][0]$b$3989, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][0][0]$a$3985
      New ports: A={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][1][0]$a$3988 [14] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][1][0]$a$3988 [12:11] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][1][0]$a$3988 [8] 3'000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][1][0]$a$3988 [2] }, B={ 3'000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][1][0]$b$3989 [10] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][1][0]$b$3989 [7] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][1][0]$b$3989 [7] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][1][0]$b$3989 [4] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][1][0]$b$3989 [2] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][1][0]$b$3989 [2] }, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][0][0]$a$3985 [14] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][0][0]$a$3985 [12:10] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][0][0]$a$3985 [8:7] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][0][0]$a$3985 [4:2] }
      New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][0][0]$a$3985 [15] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][0][0]$a$3985 [13] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][0][0]$a$3985 [9] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][0][0]$a$3985 [6:5] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][0][0]$a$3985 [1:0] } = { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][0][0]$a$3985 [12] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][0][0]$a$3985 [12] 5'00000 }
  Optimizing cells in module \top.
    Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][0][0]$3984:
      Old ports: A=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][0][0]$a$3985, B=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][0][0]$b$3986, Y={ \SOC.Core.pc_write \SOC.Core.AluInputBMUX.option \SOC.Core.Control_Unit.ir_write \SOC.Bus.read \SOC.Core.Control_Unit.reg_write \SOC.Core.AluInputAMUX.option \SOC.Core.ALU_Control.aluop_in \SOC.Core.PCSourceMUX.option [0] \SOC.Core.MemoryDataMUX.option [0] \SOC.Bus.write \SOC.Core.MemoryAddressMUX.option [0] \SOC.Core.pc_write_cond \SOC.Core.ALU_Control.is_immediate }
      New ports: A={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][0][0]$a$3985 [14] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][0][0]$a$3985 [12] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][0][0]$a$3985 [12:10] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][0][0]$a$3985 [8:7] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][0][0]$a$3985 [4:2] 2'00 }, B={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][0][0]$b$3986 [14:13] 3'000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][0][0]$b$3986 [9:7] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][0][0]$b$3986 [5] 3'000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$678$rdmux[0][0][0]$b$3986 [1:0] }, Y={ \SOC.Core.AluInputBMUX.option \SOC.Core.Control_Unit.ir_write \SOC.Bus.read \SOC.Core.Control_Unit.reg_write \SOC.Core.AluInputAMUX.option \SOC.Core.ALU_Control.aluop_in [1] \SOC.Core.PCSourceMUX.option [0] \SOC.Core.MemoryDataMUX.option [0] \SOC.Bus.write \SOC.Core.MemoryAddressMUX.option [0] \SOC.Core.pc_write_cond \SOC.Core.ALU_Control.is_immediate }
      New connections: { \SOC.Core.pc_write \SOC.Core.ALU_Control.aluop_in [0] } = { \SOC.Core.AluInputBMUX.option [0] \SOC.Core.pc_write_cond }
  Optimizing cells in module \top.
Performed a total of 24 changes.

21.30.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~12 debug messages>
Removed a total of 4 cells.

21.30.6. Executing OPT_DFF pass (perform DFF optimizations).

21.30.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 20 unused wires.
<suppressed ~1 debug messages>

21.30.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

21.30.9. Rerunning OPT passes. (Maybe there is more to do..)

21.30.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~36 debug messages>

21.30.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

21.30.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

21.30.13. Executing OPT_DFF pass (perform DFF optimizations).

21.30.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

21.30.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

21.30.16. Finished OPT passes. (There is nothing left to do.)

21.31. Executing TECHMAP pass (map to technology primitives).

21.31.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/techmap.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

21.31.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v' to AST representation.
Generating RTLIL representation for module `\_80_ecp5_alu'.
Successfully finished Verilog frontend.

21.31.3. Continuing TECHMAP pass.
Using extmapper simplemap for cells of type $not.
Using extmapper simplemap for cells of type $mux.
Using extmapper simplemap for cells of type $reduce_or.
Using extmapper simplemap for cells of type $eq.
Using extmapper simplemap for cells of type $and.
Using extmapper simplemap for cells of type $sdffce.
Using template $paramod$6a42b6fefed750f8a1c58eab59479d960557103c\_80_ecp5_alu for cells of type $alu.
Using template $paramod$32efbfac1c4dc57230cf86180788fdfd12e3b511\_80_ecp5_alu for cells of type $alu.
Using extmapper simplemap for cells of type $reduce_and.
Using extmapper simplemap for cells of type $logic_not.
Using extmapper simplemap for cells of type $sdffe.
Using extmapper simplemap for cells of type $or.
Using extmapper simplemap for cells of type $dffe.
Using extmapper simplemap for cells of type $sdff.
Using template $paramod$521ce43182eecb9f60c72393a788160d2c356bf5\_90_pmux for cells of type $pmux.
Using extmapper simplemap for cells of type $reduce_bool.
Using template $paramod$b469e176aa82369781227d524b4fecc3cede3e1d\_80_ecp5_alu for cells of type $alu.
Using template $paramod$8fabc56b80a569262acfc42757a02ca0b8e91278\_90_pmux for cells of type $pmux.
Using template $paramod$861f5302217787cd55fd1a501bc728125f176580\_80_ecp5_alu for cells of type $alu.
Using template $paramod$c96def1cdcef2eee3c62e5dfb7ba2dd09c9f74dd\_90_pmux for cells of type $pmux.
Using template $paramod$54d740639e1393b22262823179ff783ea9f17a35\_90_pmux for cells of type $pmux.
Using template $paramod$fbc7873bff55778c0b3173955b7e4bce1d9d6834\_80_ecp5_alu for cells of type $alu.
Using template $paramod$3111a1a8e90c88cc8c163ba5aed0203d96ddc46d\_80_ecp5_alu for cells of type $alu.
Using extmapper simplemap for cells of type $dff.
Using extmapper simplemap for cells of type $bmux.
Using template $paramod$eaeb96106163dbf82031649d189817109fe07c69\_90_demux for cells of type $demux.
Using extmapper simplemap for cells of type $tribuf.
Using template $paramod$32a7b7b86c07519b7537abc18e96f0331f97914d\_90_alu for cells of type $alu.
Using extmapper simplemap for cells of type $logic_or.
Using template $paramod$215440792383f7884e57d9c95f84e9552d0bf4ac\_80_ecp5_alu for cells of type $alu.
Using extmapper simplemap for cells of type $logic_and.
Using template $paramod$068ad458e7761d78e5eed8238508872e7b0aef95\_90_pmux for cells of type $pmux.
Using template $paramod$41ef080258eed1ff8fcfbb7776f540ab469a3d7b\_80_ecp5_alu for cells of type $alu.
Using template $paramod$c4ef20b21801b37ea2d65c32a05dfe56e84a870d\_80_ecp5_alu for cells of type $alu.
Using extmapper simplemap for cells of type $ne.
Using template $paramod$c83925f608704c3fa34790ddcfce9302bdcd7533\_90_pmux for cells of type $pmux.
Using template $paramod$33afdd83bf3811dac2de7a968d39eea5718691bc\_90_pmux for cells of type $pmux.
Using template $paramod$a13703aa027da371a1931fc542d213d7de559b19\_90_pmux for cells of type $pmux.
Using template $paramod$85df5dc01c7df96a7d8e5f1fdf76ce9ac452af63\_90_pmux for cells of type $pmux.
Using template $paramod$bf2533632d512eac76dd186c0da49367e29b8e98\_90_pmux for cells of type $pmux.
Using extmapper simplemap for cells of type $dlatch.
Using template $paramod$constmap:b9a86d073741c2a0f7bb241e73c2dd11747f3288$paramod$56955d0f36f77738c952d3505dc563df3ee11b94\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shr.
Using template $paramod$constmap:b9a86d073741c2a0f7bb241e73c2dd11747f3288$paramod$dce7c1188cb25d2520d170426d59301c3b73f9e7\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl.
Using template $paramod$a5f0941832cc861549e29ccafffe20bfdf2e5528\_90_pmux for cells of type $pmux.
Using extmapper simplemap for cells of type $xor.
Using template $paramod$e04283ca12514baf3d204c6994bec8f178dd89f8\_80_ecp5_alu for cells of type $alu.
Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000000100 for cells of type $lcu.
Using extmapper simplemap for cells of type $pos.
Using template $paramod$46c272b461898a6a76adeeeedb0917ce1a81b478\_90_demux for cells of type $demux.
Using template $paramod$63301a5e78ceb1f2c17a4ac1894f292ed5701c1f\_90_demux for cells of type $demux.
Using template $paramod$5d1d2614b24accd0f9d06c4779fd9ef771faf494\_90_demux for cells of type $demux.
No more expansions possible.
<suppressed ~3681 debug messages>

21.32. Executing OPT pass (performing simple optimizations).

21.32.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~6170 debug messages>

21.32.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~3882 debug messages>
Removed a total of 1294 cells.

21.32.3. Executing OPT_DFF pass (perform DFF optimizations).

21.32.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 340 unused cells and 3625 unused wires.
<suppressed ~341 debug messages>

21.32.5. Finished fast OPT passes.

21.33. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

21.34. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).

21.35. Executing TECHMAP pass (map to technology primitives).

21.35.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v' to AST representation.
Generating RTLIL representation for module `\$_DFF_N_'.
Generating RTLIL representation for module `\$_DFF_P_'.
Generating RTLIL representation for module `\$_DFFE_NN_'.
Generating RTLIL representation for module `\$_DFFE_PN_'.
Generating RTLIL representation for module `\$_DFFE_NP_'.
Generating RTLIL representation for module `\$_DFFE_PP_'.
Generating RTLIL representation for module `\$_DFF_NP0_'.
Generating RTLIL representation for module `\$_DFF_NP1_'.
Generating RTLIL representation for module `\$_DFF_PP0_'.
Generating RTLIL representation for module `\$_DFF_PP1_'.
Generating RTLIL representation for module `\$_SDFF_NP0_'.
Generating RTLIL representation for module `\$_SDFF_NP1_'.
Generating RTLIL representation for module `\$_SDFF_PP0_'.
Generating RTLIL representation for module `\$_SDFF_PP1_'.
Generating RTLIL representation for module `\$_DFFE_NP0P_'.
Generating RTLIL representation for module `\$_DFFE_NP1P_'.
Generating RTLIL representation for module `\$_DFFE_PP0P_'.
Generating RTLIL representation for module `\$_DFFE_PP1P_'.
Generating RTLIL representation for module `\$_DFFE_NP0N_'.
Generating RTLIL representation for module `\$_DFFE_NP1N_'.
Generating RTLIL representation for module `\$_DFFE_PP0N_'.
Generating RTLIL representation for module `\$_DFFE_PP1N_'.
Generating RTLIL representation for module `\$_SDFFE_NP0P_'.
Generating RTLIL representation for module `\$_SDFFE_NP1P_'.
Generating RTLIL representation for module `\$_SDFFE_PP0P_'.
Generating RTLIL representation for module `\$_SDFFE_PP1P_'.
Generating RTLIL representation for module `\$_SDFFE_NP0N_'.
Generating RTLIL representation for module `\$_SDFFE_NP1N_'.
Generating RTLIL representation for module `\$_SDFFE_PP0N_'.
Generating RTLIL representation for module `\$_SDFFE_PP1N_'.
Generating RTLIL representation for module `\$_ALDFF_NP_'.
Generating RTLIL representation for module `\$_ALDFF_PP_'.
Generating RTLIL representation for module `\$_ALDFFE_NPN_'.
Generating RTLIL representation for module `\$_ALDFFE_NPP_'.
Generating RTLIL representation for module `\$_ALDFFE_PPN_'.
Generating RTLIL representation for module `\$_ALDFFE_PPP_'.
Generating RTLIL representation for module `\FD1P3AX'.
Generating RTLIL representation for module `\FD1P3AY'.
Generating RTLIL representation for module `\FD1P3BX'.
Generating RTLIL representation for module `\FD1P3DX'.
Generating RTLIL representation for module `\FD1P3IX'.
Generating RTLIL representation for module `\FD1P3JX'.
Generating RTLIL representation for module `\FD1S3AX'.
Generating RTLIL representation for module `\FD1S3AY'.
Generating RTLIL representation for module `\FD1S3BX'.
Generating RTLIL representation for module `\FD1S3DX'.
Generating RTLIL representation for module `\FD1S3IX'.
Generating RTLIL representation for module `\FD1S3JX'.
Generating RTLIL representation for module `\IFS1P3BX'.
Generating RTLIL representation for module `\IFS1P3DX'.
Generating RTLIL representation for module `\IFS1P3IX'.
Generating RTLIL representation for module `\IFS1P3JX'.
Generating RTLIL representation for module `\OFS1P3BX'.
Generating RTLIL representation for module `\OFS1P3DX'.
Generating RTLIL representation for module `\OFS1P3IX'.
Generating RTLIL representation for module `\OFS1P3JX'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\IBPU'.
Generating RTLIL representation for module `\IBPD'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\OBZPU'.
Generating RTLIL representation for module `\OBZPD'.
Generating RTLIL representation for module `\OBCO'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\BBPU'.
Generating RTLIL representation for module `\BBPD'.
Generating RTLIL representation for module `\ILVDS'.
Generating RTLIL representation for module `\OLVDS'.
Successfully finished Verilog frontend.

21.35.2. Continuing TECHMAP pass.
Using template \$_SDFF_PP0_ for cells of type $_SDFF_PP0_.
Using template \$_SDFFE_PP0P_ for cells of type $_SDFFE_PP0P_.
Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'0 for cells of type $_DFFE_PP_.
Using template \$_SDFF_PP1_ for cells of type $_SDFF_PP1_.
Using template \$_SDFFE_PP0N_ for cells of type $_SDFFE_PP0N_.
Using template $paramod\$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_.
Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'1 for cells of type $_DFFE_PP_.
Using template \$_SDFFE_PP1P_ for cells of type $_SDFFE_PP1P_.
No more expansions possible.
<suppressed ~1457 debug messages>

21.36. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~29 debug messages>

21.37. Executing SIMPLEMAP pass (map simple cells to gate primitives).

21.38. Executing LATTICE_GSR pass (implement FF init values).
Handling GSR in top.

21.39. Executing ATTRMVCP pass (move or copy attributes).

21.40. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 6932 unused wires.
<suppressed ~1 debug messages>

21.41. Executing TECHMAP pass (map to technology primitives).

21.41.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/latches_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/latches_map.v' to AST representation.
Generating RTLIL representation for module `\$_DLATCH_N_'.
Generating RTLIL representation for module `\$_DLATCH_P_'.
Successfully finished Verilog frontend.

21.41.2. Continuing TECHMAP pass.

21.41.3. Executing SIMPLEMAP pass (map simple cells to gate primitives).
Mapping \$_DLATCH_N_.$ternary$/eda/oss-cad-suite/lib/../share/yosys/ecp5/latches_map.v:4$28319 ($mux).
Mapping \$_DLATCH_N_.$logic_not$/eda/oss-cad-suite/lib/../share/yosys/ecp5/latches_map.v:4$28318 ($logic_not).
<suppressed ~4 debug messages>

21.41.4. Executing OPT pass (performing simple optimizations).

21.41.4.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module \$_DLATCH_N_.
<suppressed ~1 debug messages>

21.41.4.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\$_DLATCH_N_'.
Removed a total of 0 cells.

21.41.4.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \$_DLATCH_N_..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

21.41.4.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \$_DLATCH_N_.
Performed a total of 0 changes.

21.41.4.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\$_DLATCH_N_'.
Removed a total of 0 cells.

21.41.4.6. Executing OPT_DFF pass (perform DFF optimizations).

21.41.4.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \$_DLATCH_N_..
Removed 1 unused cells and 2 unused wires.
<suppressed ~2 debug messages>

21.41.4.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module \$_DLATCH_N_.

21.41.4.9. Rerunning OPT passes. (Maybe there is more to do..)

21.41.4.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \$_DLATCH_N_..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

21.41.4.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \$_DLATCH_N_.
Performed a total of 0 changes.

21.41.4.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\$_DLATCH_N_'.
Removed a total of 0 cells.

21.41.4.13. Executing OPT_DFF pass (perform DFF optimizations).

21.41.4.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \$_DLATCH_N_..

21.41.4.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module \$_DLATCH_N_.

21.41.4.16. Finished OPT passes. (There is nothing left to do.)
Using template \$_DLATCH_N_ for cells of type $_DLATCH_N_.
No more expansions possible.
<suppressed ~4 debug messages>

21.42. Executing ABC9 pass.

21.42.1. Executing ABC9_OPS pass (helper functions for ABC9).

21.42.2. Executing ABC9_OPS pass (helper functions for ABC9).

21.42.3. Executing PROC pass (convert processes to netlists).

21.42.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$28423'.
Cleaned up 1 empty switch.

21.42.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28424 in module $paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

21.42.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

21.42.3.4. Executing PROC_INIT pass (extract init attributes).

21.42.3.5. Executing PROC_ARST pass (detect async resets in processes).

21.42.3.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

21.42.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28448'.
Creating decoders for process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28424'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28422_EN[3:0]$28430
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28422_DATA[3:0]$28429
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28422_ADDR[3:0]$28428
Creating decoders for process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$28423'.

21.42.3.8. Executing PROC_DLATCH pass (convert process syncs to latches).

21.42.3.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.\i' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28448'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28421_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28448'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28415_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28448'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28409_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28448'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28406_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28448'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28410_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28448'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28411_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28448'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28412_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28448'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28416_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28448'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28417_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28448'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28407_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28448'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28418_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28448'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28408_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28448'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28413_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28448'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28414_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28448'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28419_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28448'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28420_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28448'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28422_ADDR' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28424'.
  created $dff cell `$procdff$28474' with positive edge clock.
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28422_DATA' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28424'.
  created $dff cell `$procdff$28475' with positive edge clock.
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28422_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28424'.
  created $dff cell `$procdff$28476' with positive edge clock.
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.\muxwre' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$28423'.
  created direct connection (no actual register cell created).

21.42.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

21.42.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28448'.
Found and cleaned up 1 empty switch in `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28424'.
Removing empty process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$28423'.
Cleaned up 1 empty switch.

21.42.3.12. Executing OPT_EXPR pass (perform const folding).

21.42.4. Executing PROC pass (convert processes to netlists).

21.42.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$28494'.
Cleaned up 1 empty switch.

21.42.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28495 in module $paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

21.42.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

21.42.4.4. Executing PROC_INIT pass (extract init attributes).

21.42.4.5. Executing PROC_ARST pass (detect async resets in processes).

21.42.4.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

21.42.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28519'.
Creating decoders for process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28495'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28493_EN[3:0]$28500
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28493_DATA[3:0]$28499
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28493_ADDR[3:0]$28501
Creating decoders for process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$28494'.

21.42.4.8. Executing PROC_DLATCH pass (convert process syncs to latches).

21.42.4.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.\i' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28519'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28489_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28519'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28484_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28519'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28479_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28519'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28477_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28519'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28480_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28519'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28481_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28519'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28485_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28519'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28486_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28519'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28490_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28519'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28482_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28519'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28491_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28519'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28478_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28519'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28487_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28519'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28483_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28519'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28492_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28519'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28488_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28519'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28493_DATA' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28495'.
  created $dff cell `$procdff$28545' with positive edge clock.
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28493_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28495'.
  created $dff cell `$procdff$28546' with positive edge clock.
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28493_ADDR' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28495'.
  created $dff cell `$procdff$28547' with positive edge clock.
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.\muxwre' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$28494'.
  created direct connection (no actual register cell created).

21.42.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

21.42.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28519'.
Found and cleaned up 1 empty switch in `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28495'.
Removing empty process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$28494'.
Cleaned up 1 empty switch.

21.42.4.12. Executing OPT_EXPR pass (perform const folding).

21.42.5. Executing PROC pass (convert processes to netlists).

21.42.5.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$28565'.
Cleaned up 1 empty switch.

21.42.5.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28566 in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

21.42.5.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

21.42.5.4. Executing PROC_INIT pass (extract init attributes).

21.42.5.5. Executing PROC_ARST pass (detect async resets in processes).

21.42.5.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

21.42.5.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28590'.
Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28566'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28564_EN[3:0]$28572
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28564_DATA[3:0]$28571
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28564_ADDR[3:0]$28570
Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$28565'.

21.42.5.8. Executing PROC_DLATCH pass (convert process syncs to latches).

21.42.5.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.\i' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28590'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28562_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28590'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28557_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28590'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28552_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28590'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28548_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28590'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28549_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28590'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28553_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28590'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28554_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28590'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28558_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28590'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28550_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28590'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28559_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28590'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28563_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28590'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28555_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28590'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28551_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28590'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28560_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28590'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28556_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28590'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28561_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28590'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28564_ADDR' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28566'.
  created $dff cell `$procdff$28616' with positive edge clock.
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28564_DATA' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28566'.
  created $dff cell `$procdff$28617' with positive edge clock.
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28564_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28566'.
  created $dff cell `$procdff$28618' with positive edge clock.
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.\muxwre' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$28565'.
  created direct connection (no actual register cell created).

21.42.5.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

21.42.5.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28590'.
Found and cleaned up 1 empty switch in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28566'.
Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$28565'.
Cleaned up 1 empty switch.

21.42.5.12. Executing OPT_EXPR pass (perform const folding).

21.42.6. Executing PROC pass (convert processes to netlists).

21.42.6.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$28636'.
Cleaned up 1 empty switch.

21.42.6.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28637 in module $paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

21.42.6.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

21.42.6.4. Executing PROC_INIT pass (extract init attributes).

21.42.6.5. Executing PROC_ARST pass (detect async resets in processes).

21.42.6.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

21.42.6.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28661'.
Creating decoders for process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28637'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28635_EN[3:0]$28643
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28635_DATA[3:0]$28642
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28635_ADDR[3:0]$28641
Creating decoders for process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$28636'.

21.42.6.8. Executing PROC_DLATCH pass (convert process syncs to latches).

21.42.6.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.\i' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28661'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28630_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28661'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28625_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28661'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28620_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28661'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28619_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28661'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28621_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28661'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28622_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28661'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28626_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28661'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28627_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28661'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28631_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28661'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28623_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28661'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28632_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28661'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28628_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28661'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28624_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28661'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28633_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28661'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28629_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28661'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28634_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28661'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28635_ADDR' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28637'.
  created $dff cell `$procdff$28687' with positive edge clock.
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28635_DATA' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28637'.
  created $dff cell `$procdff$28688' with positive edge clock.
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28635_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28637'.
  created $dff cell `$procdff$28689' with positive edge clock.
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.\muxwre' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$28636'.
  created direct connection (no actual register cell created).

21.42.6.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

21.42.6.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28661'.
Found and cleaned up 1 empty switch in `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28637'.
Removing empty process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$28636'.
Cleaned up 1 empty switch.

21.42.6.12. Executing OPT_EXPR pass (perform const folding).

21.42.7. Executing PROC pass (convert processes to netlists).

21.42.7.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$28707'.
Cleaned up 1 empty switch.

21.42.7.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28708 in module $paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

21.42.7.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

21.42.7.4. Executing PROC_INIT pass (extract init attributes).

21.42.7.5. Executing PROC_ARST pass (detect async resets in processes).

21.42.7.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

21.42.7.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28732'.
Creating decoders for process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28708'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28706_EN[3:0]$28712
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28706_DATA[3:0]$28714
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28706_ADDR[3:0]$28713
Creating decoders for process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$28707'.

21.42.7.8. Executing PROC_DLATCH pass (convert process syncs to latches).

21.42.7.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.\i' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28732'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28703_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28732'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28698_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28732'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28693_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28732'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28690_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28732'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28695_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28732'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28694_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28732'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28699_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28732'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28700_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28732'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28704_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28732'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28696_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28732'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28692_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28732'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28701_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28732'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28702_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28732'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28691_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28732'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28705_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28732'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28697_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28732'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28706_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28708'.
  created $dff cell `$procdff$28758' with positive edge clock.
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28706_ADDR' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28708'.
  created $dff cell `$procdff$28759' with positive edge clock.
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28706_DATA' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28708'.
  created $dff cell `$procdff$28760' with positive edge clock.
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.\muxwre' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$28707'.
  created direct connection (no actual register cell created).

21.42.7.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

21.42.7.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28732'.
Found and cleaned up 1 empty switch in `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28708'.
Removing empty process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$28707'.
Cleaned up 1 empty switch.

21.42.7.12. Executing OPT_EXPR pass (perform const folding).

21.42.8. Executing PROC pass (convert processes to netlists).

21.42.8.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$28778'.
Cleaned up 1 empty switch.

21.42.8.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28779 in module $paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

21.42.8.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

21.42.8.4. Executing PROC_INIT pass (extract init attributes).

21.42.8.5. Executing PROC_ARST pass (detect async resets in processes).

21.42.8.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

21.42.8.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28803'.
Creating decoders for process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28779'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28777_EN[3:0]$28784
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28777_DATA[3:0]$28785
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28777_ADDR[3:0]$28783
Creating decoders for process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$28778'.

21.42.8.8. Executing PROC_DLATCH pass (convert process syncs to latches).

21.42.8.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.\i' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28803'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28775_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28803'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28769_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28803'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28763_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28803'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28761_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28803'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28770_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28803'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28765_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28803'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28766_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28803'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28764_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28803'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28767_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28803'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28773_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28803'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28774_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28803'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28776_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28803'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28762_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28803'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28768_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28803'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28772_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28803'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28771_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28803'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28777_ADDR' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28779'.
  created $dff cell `$procdff$28829' with positive edge clock.
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28777_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28779'.
  created $dff cell `$procdff$28830' with positive edge clock.
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28777_DATA' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28779'.
  created $dff cell `$procdff$28831' with positive edge clock.
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.\muxwre' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$28778'.
  created direct connection (no actual register cell created).

21.42.8.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

21.42.8.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28803'.
Found and cleaned up 1 empty switch in `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28779'.
Removing empty process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$28778'.
Cleaned up 1 empty switch.

21.42.8.12. Executing OPT_EXPR pass (perform const folding).

21.42.9. Executing PROC pass (convert processes to netlists).

21.42.9.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$28849'.
Cleaned up 1 empty switch.

21.42.9.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28850 in module $paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

21.42.9.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

21.42.9.4. Executing PROC_INIT pass (extract init attributes).

21.42.9.5. Executing PROC_ARST pass (detect async resets in processes).

21.42.9.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

21.42.9.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28874'.
Creating decoders for process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28850'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28848_EN[3:0]$28856
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28848_DATA[3:0]$28855
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28848_ADDR[3:0]$28854
Creating decoders for process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$28849'.

21.42.9.8. Executing PROC_DLATCH pass (convert process syncs to latches).

21.42.9.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.\i' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28874'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28845_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28874'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28839_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28874'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28833_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28874'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28832_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28874'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28834_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28874'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28835_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28874'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28836_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28874'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28840_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28874'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28841_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28874'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28842_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28874'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28846_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28874'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28847_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28874'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28837_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28874'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28838_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28874'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28843_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28874'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28844_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28874'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28848_ADDR' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28850'.
  created $dff cell `$procdff$28900' with positive edge clock.
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28848_DATA' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28850'.
  created $dff cell `$procdff$28901' with positive edge clock.
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28848_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28850'.
  created $dff cell `$procdff$28902' with positive edge clock.
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.\muxwre' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$28849'.
  created direct connection (no actual register cell created).

21.42.9.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

21.42.9.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28874'.
Found and cleaned up 1 empty switch in `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28850'.
Removing empty process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$28849'.
Cleaned up 1 empty switch.

21.42.9.12. Executing OPT_EXPR pass (perform const folding).

21.42.10. Executing PROC pass (convert processes to netlists).

21.42.10.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$28920'.
Cleaned up 1 empty switch.

21.42.10.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28921 in module $paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

21.42.10.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

21.42.10.4. Executing PROC_INIT pass (extract init attributes).

21.42.10.5. Executing PROC_ARST pass (detect async resets in processes).

21.42.10.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

21.42.10.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28945'.
Creating decoders for process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28921'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28919_EN[3:0]$28925
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28919_DATA[3:0]$28927
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28919_ADDR[3:0]$28926
Creating decoders for process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$28920'.

21.42.10.8. Executing PROC_DLATCH pass (convert process syncs to latches).

21.42.10.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.\i' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28945'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28915_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28945'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28909_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28945'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28903_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28945'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28904_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28945'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28905_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28945'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28906_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28945'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28910_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28945'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28911_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28945'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28912_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28945'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28916_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28945'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28917_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28945'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28907_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28945'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28918_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28945'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28908_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28945'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28913_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28945'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28914_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28945'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28919_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28921'.
  created $dff cell `$procdff$28971' with positive edge clock.
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28919_ADDR' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28921'.
  created $dff cell `$procdff$28972' with positive edge clock.
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28919_DATA' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28921'.
  created $dff cell `$procdff$28973' with positive edge clock.
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.\muxwre' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$28920'.
  created direct connection (no actual register cell created).

21.42.10.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

21.42.10.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28945'.
Found and cleaned up 1 empty switch in `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28921'.
Removing empty process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$28920'.
Cleaned up 1 empty switch.

21.42.10.12. Executing OPT_EXPR pass (perform const folding).

21.42.11. Executing PROC pass (convert processes to netlists).

21.42.11.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$28991'.
Cleaned up 1 empty switch.

21.42.11.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28992 in module $paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

21.42.11.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

21.42.11.4. Executing PROC_INIT pass (extract init attributes).

21.42.11.5. Executing PROC_ARST pass (detect async resets in processes).

21.42.11.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

21.42.11.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$29016'.
Creating decoders for process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28992'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28990_EN[3:0]$28997
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28990_DATA[3:0]$28996
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28990_ADDR[3:0]$28998
Creating decoders for process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$28991'.

21.42.11.8. Executing PROC_DLATCH pass (convert process syncs to latches).

21.42.11.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.\i' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$29016'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28986_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$29016'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28981_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$29016'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28976_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$29016'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28974_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$29016'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28977_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$29016'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28978_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$29016'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28982_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$29016'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28983_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$29016'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28987_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$29016'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28979_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$29016'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28988_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$29016'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28975_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$29016'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28984_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$29016'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28980_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$29016'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28989_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$29016'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28985_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$29016'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28990_DATA' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28992'.
  created $dff cell `$procdff$29042' with positive edge clock.
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28990_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28992'.
  created $dff cell `$procdff$29043' with positive edge clock.
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28990_ADDR' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28992'.
  created $dff cell `$procdff$29044' with positive edge clock.
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.\muxwre' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$28991'.
  created direct connection (no actual register cell created).

21.42.11.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

21.42.11.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$29016'.
Found and cleaned up 1 empty switch in `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28992'.
Removing empty process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$28991'.
Cleaned up 1 empty switch.

21.42.11.12. Executing OPT_EXPR pass (perform const folding).

21.42.12. Executing SCC pass (detecting logic loops).
Found an SCC: $techmap$auto$ff.cc:266:slice$12102.$auto$simplemap.cc:267:simplemap_mux$28321
Found an SCC: $techmap$auto$ff.cc:266:slice$12101.$auto$simplemap.cc:267:simplemap_mux$28321
Found an SCC: $techmap$auto$ff.cc:266:slice$12100.$auto$simplemap.cc:267:simplemap_mux$28321
Found an SCC: $techmap$auto$ff.cc:266:slice$12099.$auto$simplemap.cc:267:simplemap_mux$28321
Found an SCC: $auto$opt_expr.cc:613:replace_const_cells$26131 $auto$simplemap.cc:267:simplemap_mux$17933 $auto$simplemap.cc:126:simplemap_reduce$17918 $auto$simplemap.cc:126:simplemap_reduce$17915 $auto$simplemap.cc:38:simplemap_not$14963 $auto$ff.cc:266:slice$7770 $auto$opt_expr.cc:613:replace_const_cells$26055 $auto$ff.cc:266:slice$7773 $auto$simplemap.cc:126:simplemap_reduce$7948 $auto$simplemap.cc:126:simplemap_reduce$7963 $auto$ff.cc:266:slice$7772 $auto$opt_expr.cc:613:replace_const_cells$26453 $auto$simplemap.cc:225:simplemap_logbin$7933 $auto$simplemap.cc:196:simplemap_lognot$7952 $auto$simplemap.cc:126:simplemap_reduce$7950 $auto$simplemap.cc:126:simplemap_reduce$7947 $auto$simplemap.cc:75:simplemap_bitop$17928 $auto$simplemap.cc:196:simplemap_lognot$7967 $auto$simplemap.cc:126:simplemap_reduce$7965 $auto$simplemap.cc:126:simplemap_reduce$7962 $auto$ff.cc:266:slice$7771 $auto$simplemap.cc:126:simplemap_reduce$7475 $auto$simplemap.cc:126:simplemap_reduce$7473 $auto$simplemap.cc:225:simplemap_logbin$7869 $auto$simplemap.cc:196:simplemap_lognot$7879 $auto$simplemap.cc:126:simplemap_reduce$7877 $auto$opt_expr.cc:613:replace_const_cells$26133 $auto$simplemap.cc:267:simplemap_mux$17932 $auto$simplemap.cc:126:simplemap_reduce$17923 $auto$simplemap.cc:126:simplemap_reduce$17920 $auto$simplemap.cc:75:simplemap_bitop$17930
Found an SCC: $auto$ff.cc:266:slice$7774 $auto$ff.cc:266:slice$7786 $auto$opt_expr.cc:613:replace_const_cells$26129 $auto$ff.cc:266:slice$7785 $auto$simplemap.cc:126:simplemap_reduce$7991 $auto$ff.cc:266:slice$7784 $auto$simplemap.cc:38:simplemap_not$18004 $auto$ff.cc:266:slice$7783 $auto$simplemap.cc:126:simplemap_reduce$7998 $auto$simplemap.cc:126:simplemap_reduce$7995 $auto$simplemap.cc:126:simplemap_reduce$7990 $auto$ff.cc:266:slice$7782 $auto$ff.cc:266:slice$7781 $auto$simplemap.cc:126:simplemap_reduce$7989 $auto$ff.cc:266:slice$7780 $auto$ff.cc:266:slice$7779 $auto$ff.cc:266:slice$7778 $auto$simplemap.cc:38:simplemap_not$17998 $auto$ff.cc:266:slice$7777 $auto$simplemap.cc:126:simplemap_reduce$7987 $auto$simplemap.cc:38:simplemap_not$17997 $auto$ff.cc:266:slice$7776 $auto$simplemap.cc:126:simplemap_reduce$7993 $auto$simplemap.cc:126:simplemap_reduce$7986 $auto$ff.cc:266:slice$7775 $auto$simplemap.cc:167:logic_reduce$7456 $auto$simplemap.cc:196:simplemap_lognot$8002 $auto$simplemap.cc:126:simplemap_reduce$8000 $auto$simplemap.cc:126:simplemap_reduce$7997 $auto$simplemap.cc:126:simplemap_reduce$7994 $auto$simplemap.cc:126:simplemap_reduce$7988 $auto$simplemap.cc:38:simplemap_not$18000
Found an SCC: $auto$simplemap.cc:38:simplemap_not$17856 $auto$ff.cc:266:slice$4422 $auto$ff.cc:266:slice$4395 $auto$simplemap.cc:38:simplemap_not$17855 $auto$ff.cc:266:slice$4421 $auto$simplemap.cc:38:simplemap_not$17851 $auto$ff.cc:266:slice$4417 $auto$ff.cc:266:slice$4414 $auto$ff.cc:266:slice$4411 $auto$simplemap.cc:126:simplemap_reduce$7363 $auto$ff.cc:266:slice$4416 $auto$simplemap.cc:126:simplemap_reduce$7374 $auto$simplemap.cc:126:simplemap_reduce$7362 $auto$simplemap.cc:38:simplemap_not$17849 $auto$ff.cc:266:slice$4415 $auto$ff.cc:266:slice$4408 $auto$simplemap.cc:126:simplemap_reduce$7360 $auto$ff.cc:266:slice$4410 $auto$simplemap.cc:126:simplemap_reduce$7359 $auto$simplemap.cc:38:simplemap_not$17843 $auto$ff.cc:266:slice$4409 $auto$ff.cc:266:slice$4405 $auto$simplemap.cc:38:simplemap_not$17836 $auto$ff.cc:266:slice$4402 $auto$simplemap.cc:126:simplemap_reduce$7357 $auto$ff.cc:266:slice$4404 $auto$simplemap.cc:126:simplemap_reduce$7371 $auto$simplemap.cc:126:simplemap_reduce$7356 $auto$ff.cc:266:slice$4403 $auto$simplemap.cc:126:simplemap_reduce$7365 $auto$simplemap.cc:38:simplemap_not$17854 $auto$ff.cc:266:slice$4420 $auto$simplemap.cc:38:simplemap_not$17835 $auto$ff.cc:266:slice$4401 $auto$ff.cc:266:slice$4396 $auto$simplemap.cc:126:simplemap_reduce$7366 $auto$simplemap.cc:38:simplemap_not$17857 $auto$ff.cc:266:slice$4423 $auto$simplemap.cc:38:simplemap_not$17833 $auto$ff.cc:266:slice$4399 $auto$simplemap.cc:126:simplemap_reduce$7355 $auto$simplemap.cc:38:simplemap_not$17834 $auto$ff.cc:266:slice$4400 $auto$ff.cc:266:slice$4406 $auto$ff.cc:266:slice$4412 $auto$simplemap.cc:38:simplemap_not$17852 $auto$ff.cc:266:slice$4418 $auto$simplemap.cc:38:simplemap_not$17858 $auto$ff.cc:266:slice$4424 $auto$simplemap.cc:126:simplemap_reduce$7352 $auto$ff.cc:266:slice$4394 $auto$simplemap.cc:126:simplemap_reduce$7376 $auto$simplemap.cc:126:simplemap_reduce$7367 $auto$simplemap.cc:38:simplemap_not$15177 $auto$ff.cc:266:slice$4425 $auto$ff.cc:266:slice$4419 $auto$simplemap.cc:126:simplemap_reduce$7380 $auto$simplemap.cc:126:simplemap_reduce$7373 $auto$simplemap.cc:126:simplemap_reduce$7361 $auto$ff.cc:266:slice$4413 $auto$simplemap.cc:126:simplemap_reduce$7379 $auto$simplemap.cc:126:simplemap_reduce$7372 $auto$simplemap.cc:126:simplemap_reduce$7358 $auto$simplemap.cc:38:simplemap_not$17841 $auto$ff.cc:266:slice$4407 $auto$simplemap.cc:38:simplemap_not$7387 $auto$alumacc.cc:485:replace_alu$2656.slice[26].ccu2c_i $auto$alumacc.cc:485:replace_alu$2656.slice[24].ccu2c_i $auto$alumacc.cc:485:replace_alu$2656.slice[22].ccu2c_i $auto$alumacc.cc:485:replace_alu$2656.slice[20].ccu2c_i $auto$alumacc.cc:485:replace_alu$2656.slice[18].ccu2c_i $auto$alumacc.cc:485:replace_alu$2656.slice[16].ccu2c_i $auto$alumacc.cc:485:replace_alu$2656.slice[14].ccu2c_i $auto$alumacc.cc:485:replace_alu$2656.slice[12].ccu2c_i $auto$alumacc.cc:485:replace_alu$2656.slice[10].ccu2c_i $auto$alumacc.cc:485:replace_alu$2656.slice[8].ccu2c_i $auto$alumacc.cc:485:replace_alu$2656.slice[6].ccu2c_i $auto$alumacc.cc:485:replace_alu$2656.slice[4].ccu2c_i $auto$alumacc.cc:485:replace_alu$2656.slice[2].ccu2c_i $auto$alumacc.cc:485:replace_alu$2656.slice[0].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$7370 $auto$simplemap.cc:126:simplemap_reduce$7354 $auto$simplemap.cc:38:simplemap_not$17832 $auto$ff.cc:266:slice$4398 $auto$simplemap.cc:126:simplemap_reduce$7383 $auto$simplemap.cc:126:simplemap_reduce$7378 $auto$simplemap.cc:126:simplemap_reduce$7369 $auto$simplemap.cc:126:simplemap_reduce$7353 $auto$ff.cc:266:slice$4397 $auto$simplemap.cc:126:simplemap_reduce$8212 $auto$simplemap.cc:126:simplemap_reduce$8210 $auto$simplemap.cc:126:simplemap_reduce$7386 $auto$simplemap.cc:126:simplemap_reduce$7384 $auto$simplemap.cc:126:simplemap_reduce$7381 $auto$simplemap.cc:126:simplemap_reduce$7375 $auto$simplemap.cc:126:simplemap_reduce$7364 $auto$simplemap.cc:38:simplemap_not$17853
Found an SCC: $auto$simplemap.cc:38:simplemap_not$17905 $auto$ff.cc:266:slice$7577 $auto$simplemap.cc:38:simplemap_not$17901 $auto$ff.cc:266:slice$7573 $auto$simplemap.cc:38:simplemap_not$17902 $auto$ff.cc:266:slice$7574 $auto$opt_expr.cc:613:replace_const_cells$26099 $auto$ff.cc:266:slice$7582 $auto$simplemap.cc:126:simplemap_reduce$7717 $auto$simplemap.cc:126:simplemap_reduce$7756 $auto$opt_expr.cc:613:replace_const_cells$26109 $auto$ff.cc:266:slice$7583 $auto$simplemap.cc:38:simplemap_not$17909 $auto$ff.cc:266:slice$7581 $auto$simplemap.cc:126:simplemap_reduce$7760 $auto$simplemap.cc:126:simplemap_reduce$7755 $auto$simplemap.cc:126:simplemap_reduce$7721 $auto$simplemap.cc:126:simplemap_reduce$7716 $auto$simplemap.cc:38:simplemap_not$17908 $auto$ff.cc:266:slice$7580 $auto$simplemap.cc:126:simplemap_reduce$7724 $auto$simplemap.cc:126:simplemap_reduce$7763 $auto$ff.cc:266:slice$7584 $auto$simplemap.cc:126:simplemap_reduce$7753 $auto$simplemap.cc:126:simplemap_reduce$7714 $auto$simplemap.cc:38:simplemap_not$17904 $auto$ff.cc:266:slice$7576 $auto$simplemap.cc:126:simplemap_reduce$7752 $auto$simplemap.cc:38:simplemap_not$17903 $auto$ff.cc:266:slice$7575 $auto$simplemap.cc:126:simplemap_reduce$7712 $auto$simplemap.cc:126:simplemap_reduce$7758 $auto$simplemap.cc:126:simplemap_reduce$7751 $auto$ff.cc:266:slice$7572 $auto$ff.cc:266:slice$7578 $auto$simplemap.cc:126:simplemap_reduce$7720 $auto$simplemap.cc:196:simplemap_lognot$7767 $auto$simplemap.cc:126:simplemap_reduce$7765 $auto$simplemap.cc:126:simplemap_reduce$7762 $auto$simplemap.cc:126:simplemap_reduce$7759 $auto$simplemap.cc:126:simplemap_reduce$7754 $auto$ff.cc:266:slice$7579 $auto$simplemap.cc:167:logic_reduce$7586 $auto$simplemap.cc:225:simplemap_logbin$7692 $auto$simplemap.cc:225:simplemap_logbin$7693 $auto$simplemap.cc:196:simplemap_lognot$7728 $auto$simplemap.cc:126:simplemap_reduce$7726 $auto$simplemap.cc:126:simplemap_reduce$7723 $auto$simplemap.cc:126:simplemap_reduce$7719 $auto$simplemap.cc:126:simplemap_reduce$7713
Found an SCC: $auto$opt_expr.cc:613:replace_const_cells$26197 $auto$simplemap.cc:126:simplemap_reduce$8332 $auto$simplemap.cc:38:simplemap_not$7388 $auto$simplemap.cc:38:simplemap_not$24726 $auto$ff.cc:266:slice$4187 $auto$ff.cc:479:convert_ce_over_srst$26947 $auto$simplemap.cc:126:simplemap_reduce$7393 $auto$ff.cc:266:slice$4186 $auto$ff.cc:479:convert_ce_over_srst$26945 $auto$ff.cc:266:slice$4185 $auto$ff.cc:479:convert_ce_over_srst$26943 $auto$ff.cc:266:slice$4184 $auto$ff.cc:479:convert_ce_over_srst$26941 $auto$simplemap.cc:126:simplemap_reduce$7391 $auto$simplemap.cc:38:simplemap_not$15121 $auto$ff.cc:266:slice$4183 $auto$ff.cc:479:convert_ce_over_srst$26939 $auto$simplemap.cc:126:simplemap_reduce$8172 $auto$simplemap.cc:75:simplemap_bitop$7389 $auto$simplemap.cc:38:simplemap_not$7398 $auto$alumacc.cc:485:replace_alu$2645.slice[4].ccu2c_i $auto$alumacc.cc:485:replace_alu$2645.slice[2].ccu2c_i $auto$alumacc.cc:485:replace_alu$2645.slice[0].ccu2c_i $auto$ff.cc:266:slice$4182 $auto$ff.cc:479:convert_ce_over_srst$26937 $auto$simplemap.cc:126:simplemap_reduce$8257 $auto$simplemap.cc:126:simplemap_reduce$8255 $auto$simplemap.cc:126:simplemap_reduce$8334 $auto$simplemap.cc:126:simplemap_reduce$8331 $auto$simplemap.cc:126:simplemap_reduce$7397 $auto$simplemap.cc:126:simplemap_reduce$7395 $auto$simplemap.cc:126:simplemap_reduce$7392 $auto$simplemap.cc:38:simplemap_not$15123
Found 9 SCCs in module top.
Found 9 SCCs.

21.42.13. Executing ABC9_OPS pass (helper functions for ABC9).

21.42.14. Executing PROC pass (convert processes to netlists).

21.42.14.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

21.42.14.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

21.42.14.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 0 assignments to connections.

21.42.14.4. Executing PROC_INIT pass (extract init attributes).

21.42.14.5. Executing PROC_ARST pass (detect async resets in processes).

21.42.14.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

21.42.14.7. Executing PROC_MUX pass (convert decision trees to multiplexers).

21.42.14.8. Executing PROC_DLATCH pass (convert process syncs to latches).

21.42.14.9. Executing PROC_DFF pass (convert process syncs to FFs).

21.42.14.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

21.42.14.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

21.42.14.12. Executing OPT_EXPR pass (perform const folding).

21.42.15. Executing TECHMAP pass (map to technology primitives).

21.42.15.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/techmap.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

21.42.15.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~178 debug messages>

21.42.16. Executing OPT pass (performing simple optimizations).

21.42.16.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module $paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.
Optimizing module $paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.
Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Optimizing module $paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.
Optimizing module $paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.
Optimizing module $paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.
Optimizing module $paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.
Optimizing module $paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.
Optimizing module $paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.

21.42.16.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4'.
Removed a total of 0 cells.

21.42.16.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module $paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

21.42.16.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module $paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.
Performed a total of 0 changes.

21.42.16.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4'.
Removed a total of 0 cells.

21.42.16.6. Executing OPT_DFF pass (perform DFF optimizations).

21.42.16.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module $paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4..

21.42.16.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Optimizing module $paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.
Optimizing module $paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.
Optimizing module $paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.
Optimizing module $paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.
Optimizing module $paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.
Optimizing module $paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.
Optimizing module $paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.
Optimizing module $paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.

21.42.16.9. Finished OPT passes. (There is nothing left to do.)

21.42.17. Executing TECHMAP pass (map to technology primitives).

21.42.17.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/abc9_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/abc9_map.v' to AST representation.
Successfully finished Verilog frontend.

21.42.17.2. Continuing TECHMAP pass.
Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Using template $paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4 for cells of type $paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.
Using template $paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4 for cells of type $paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.
Using template $paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4 for cells of type $paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.
Using template $paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4 for cells of type $paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.
Using template $paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4 for cells of type $paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.
Using template $paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4 for cells of type $paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.
Using template $paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4 for cells of type $paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.
Using template $paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4 for cells of type $paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.
No more expansions possible.
<suppressed ~523 debug messages>

21.42.18. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/abc9_model.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/abc9_model.v' to AST representation.
Generating RTLIL representation for module `$__ABC9_DELAY'.
Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'.
Generating RTLIL representation for module `$__DFF_N__$abc9_flop'.
Generating RTLIL representation for module `$__DFF_P__$abc9_flop'.
Successfully finished Verilog frontend.

21.42.19. Executing ABC9_OPS pass (helper functions for ABC9).
<suppressed ~2 debug messages>

21.42.20. Executing ABC9_OPS pass (helper functions for ABC9).

21.42.21. Executing ABC9_OPS pass (helper functions for ABC9).
<suppressed ~2 debug messages>

21.42.22. Executing TECHMAP pass (map to technology primitives).

21.42.22.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/techmap.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

21.42.22.2. Continuing TECHMAP pass.
Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C.
Using template $paramod\LUT4\INIT=16'1001011010101010 for cells of type LUT4.
Using extmapper simplemap for cells of type $and.
Using template $paramod\LUT2\INIT=4'1010 for cells of type LUT2.
Using extmapper simplemap for cells of type $not.
Using extmapper simplemap for cells of type $or.
Using extmapper simplemap for cells of type $xor.
Using extmapper simplemap for cells of type $mux.
No more expansions possible.
<suppressed ~217 debug messages>

21.42.23. Executing OPT pass (performing simple optimizations).

21.42.23.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~18 debug messages>

21.42.23.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~6 debug messages>
Removed a total of 2 cells.

21.42.23.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

21.42.23.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

21.42.23.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

21.42.23.6. Executing OPT_DFF pass (perform DFF optimizations).

21.42.23.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 55 unused wires.
<suppressed ~1 debug messages>

21.42.23.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

21.42.23.9. Rerunning OPT passes. (Maybe there is more to do..)

21.42.23.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

21.42.23.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

21.42.23.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

21.42.23.13. Executing OPT_DFF pass (perform DFF optimizations).

21.42.23.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

21.42.23.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

21.42.23.16. Finished OPT passes. (There is nothing left to do.)

21.42.24. Executing AIGMAP pass (map logic to AIG).
Module top: replaced 18 cells with 120 new cells, skipped 39 cells.
  replaced 3 cell types:
       2 $_OR_
       2 $_XOR_
      14 $_MUX_
  not replaced 3 cell types:
      31 $specify2
       4 $_NOT_
       4 $_AND_

21.42.25. Executing AIGMAP pass (map logic to AIG).
Module top: replaced 6075 cells with 33792 new cells, skipped 5857 cells.
  replaced 3 cell types:
    2911 $_OR_
      70 $_XOR_
    3094 $_MUX_
  not replaced 24 cell types:
     407 $_NOT_
    2834 $_AND_
       6 $_TBUF_
    1353 TRELLIS_FF
       1 $paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4
       1 $paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4
       1 $paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4_$abc9_byp
     232 $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C
       1 $paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4_$abc9_byp
     504 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp
       1 $__ABC9_SCC_BREAKER
       1 $paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4
       1 $paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4
     504 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4
       1 $paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4
       1 $paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4
       1 $paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4
       1 $paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4

21.42.25.1. Executing ABC9_OPS pass (helper functions for ABC9).

21.42.25.2. Executing ABC9_OPS pass (helper functions for ABC9).

21.42.25.3. Executing XAIGER backend.
<suppressed ~11 debug messages>
Extracted 15237 AND gates and 43653 wires from module `top' to a netlist network with 3419 inputs and 547 outputs.

21.42.25.4. Executing ABC9_EXE pass (technology mapping using ABC9).

21.42.25.5. Executing ABC9.
Running ABC command: "<yosys-exe-dir>/yosys-abc" -s -f <abc-temp-dir>/abc.script 2>&1
ABC: ABC command line: "source <abc-temp-dir>/abc.script".
ABC: 
ABC: + read_lut <abc-temp-dir>/input.lut 
ABC: + read_box <abc-temp-dir>/input.box 
ABC: + &read <abc-temp-dir>/input.xaig 
ABC: + &ps 
ABC: <abc-temp-dir>/input : i/o =   3419/    547  and =   13954  lev =   44 (6.05)  mem = 0.36 MB  box = 744  bb = 512
ABC: + &scorr 
ABC: Warning: The network is combinational.
ABC: + &sweep 
ABC: + &dc2 
ABC: + &dch -f 
ABC: + &ps 
ABC: <abc-temp-dir>/input : i/o =   3419/    547  and =   20029  lev =   59 (3.13)  mem = 0.41 MB  ch = 1387  box = 668  bb = 512
ABC: + &if -W 300 -v 
ABC: K = 7. Memory (bytes): Truth =    0. Cut =   60. Obj =  140. Set =  636. CutMin = no
ABC: Node =   20029.  Ch =   998.  Total mem =    4.76 MB. Peak cut mem =    0.23 MB.
ABC: P:  Del = 6727.00.  Ar =   21265.0.  Edge =    23622.  Cut =   314662.  T =     0.07 sec
ABC: P:  Del = 6691.00.  Ar =   21717.0.  Edge =    24108.  Cut =   291349.  T =     0.07 sec
ABC: P:  Del = 6691.00.  Ar =    8031.0.  Edge =    18824.  Cut =   658609.  T =     0.15 sec
ABC: F:  Del = 6691.00.  Ar =    5944.0.  Edge =    16667.  Cut =   594716.  T =     0.14 sec
ABC: A:  Del = 6691.00.  Ar =    5460.0.  Edge =    15677.  Cut =   477912.  T =     0.20 sec
ABC: A:  Del = 6691.00.  Ar =    5419.0.  Edge =    15619.  Cut =   582226.  T =     0.24 sec
ABC: Total time =     0.86 sec
ABC: + &write -n <abc-temp-dir>/output.aig 
ABC: + &mfs 
ABC: + &ps -l 
ABC: <abc-temp-dir>/input : i/o =   3419/    547  and =   12821  lev =   38 (3.55)  mem = 0.33 MB  box = 668  bb = 512
ABC: Mapping (K=7)  :  lut =   3872  edge =   15603  lev =   14 (1.56)  levB =   25  mem = 0.18 MB
ABC: LUT = 3872 : 2=268 6.9 %  3=320 8.3 %  4=2640 68.2 %  5=438 11.3 %  6=85 2.2 %  7=121 3.1 %  Ave = 4.03
ABC: + &write -n <abc-temp-dir>/output.aig 
ABC: + time 
ABC: elapse: 5.03 seconds, total: 5.03 seconds

21.42.25.6. Executing AIGER frontend.
<suppressed ~8020 debug messages>
Removed 16422 unused cells and 30578 unused wires.

21.42.25.7. Executing ABC9_OPS pass (helper functions for ABC9).
ABC RESULTS:              $lut cells:     3895
ABC RESULTS:   $paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C cells:      156
ABC RESULTS:   $paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp cells:      504
ABC RESULTS:   $paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:           input signals:      574
ABC RESULTS:          output signals:      135
Removing temp directory.

21.42.26. Executing TECHMAP pass (map to technology primitives).

21.42.26.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/abc9_unmap.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/abc9_unmap.v' to AST representation.
Generating RTLIL representation for module `\$__DFF_x__$abc9_flop'.
Generating RTLIL representation for module `\$__ABC9_SCC_BREAKER'.
Successfully finished Verilog frontend.

21.42.26.2. Continuing TECHMAP pass.
Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C.
Using template $paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4 for cells of type $paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.
Using template $paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4 for cells of type $paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.
Using template $paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4 for cells of type $paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.
Using template $paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4 for cells of type $paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.
Using template $paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4 for cells of type $paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.
Using template $paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4 for cells of type $paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.
Using template $paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4 for cells of type $paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.
Using template $paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4 for cells of type $paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.
Using template $paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod\$__ABC9_SCC_BREAKER\WIDTH=32'00000000000000000000000000001001 for cells of type $__ABC9_SCC_BREAKER.
Using template $paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4_$abc9_byp.
No more expansions possible.
<suppressed ~1216 debug messages>
Removed 223 unused cells and 49882 unused wires.

21.43. Executing TECHMAP pass (map to technology primitives).

21.43.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v' to AST representation.
Generating RTLIL representation for module `\$_DFF_N_'.
Generating RTLIL representation for module `\$_DFF_P_'.
Generating RTLIL representation for module `\$_DFFE_NN_'.
Generating RTLIL representation for module `\$_DFFE_PN_'.
Generating RTLIL representation for module `\$_DFFE_NP_'.
Generating RTLIL representation for module `\$_DFFE_PP_'.
Generating RTLIL representation for module `\$_DFF_NP0_'.
Generating RTLIL representation for module `\$_DFF_NP1_'.
Generating RTLIL representation for module `\$_DFF_PP0_'.
Generating RTLIL representation for module `\$_DFF_PP1_'.
Generating RTLIL representation for module `\$_SDFF_NP0_'.
Generating RTLIL representation for module `\$_SDFF_NP1_'.
Generating RTLIL representation for module `\$_SDFF_PP0_'.
Generating RTLIL representation for module `\$_SDFF_PP1_'.
Generating RTLIL representation for module `\$_DFFE_NP0P_'.
Generating RTLIL representation for module `\$_DFFE_NP1P_'.
Generating RTLIL representation for module `\$_DFFE_PP0P_'.
Generating RTLIL representation for module `\$_DFFE_PP1P_'.
Generating RTLIL representation for module `\$_DFFE_NP0N_'.
Generating RTLIL representation for module `\$_DFFE_NP1N_'.
Generating RTLIL representation for module `\$_DFFE_PP0N_'.
Generating RTLIL representation for module `\$_DFFE_PP1N_'.
Generating RTLIL representation for module `\$_SDFFE_NP0P_'.
Generating RTLIL representation for module `\$_SDFFE_NP1P_'.
Generating RTLIL representation for module `\$_SDFFE_PP0P_'.
Generating RTLIL representation for module `\$_SDFFE_PP1P_'.
Generating RTLIL representation for module `\$_SDFFE_NP0N_'.
Generating RTLIL representation for module `\$_SDFFE_NP1N_'.
Generating RTLIL representation for module `\$_SDFFE_PP0N_'.
Generating RTLIL representation for module `\$_SDFFE_PP1N_'.
Generating RTLIL representation for module `\$_ALDFF_NP_'.
Generating RTLIL representation for module `\$_ALDFF_PP_'.
Generating RTLIL representation for module `\$_ALDFFE_NPN_'.
Generating RTLIL representation for module `\$_ALDFFE_NPP_'.
Generating RTLIL representation for module `\$_ALDFFE_PPN_'.
Generating RTLIL representation for module `\$_ALDFFE_PPP_'.
Generating RTLIL representation for module `\FD1P3AX'.
Generating RTLIL representation for module `\FD1P3AY'.
Generating RTLIL representation for module `\FD1P3BX'.
Generating RTLIL representation for module `\FD1P3DX'.
Generating RTLIL representation for module `\FD1P3IX'.
Generating RTLIL representation for module `\FD1P3JX'.
Generating RTLIL representation for module `\FD1S3AX'.
Generating RTLIL representation for module `\FD1S3AY'.
Generating RTLIL representation for module `\FD1S3BX'.
Generating RTLIL representation for module `\FD1S3DX'.
Generating RTLIL representation for module `\FD1S3IX'.
Generating RTLIL representation for module `\FD1S3JX'.
Generating RTLIL representation for module `\IFS1P3BX'.
Generating RTLIL representation for module `\IFS1P3DX'.
Generating RTLIL representation for module `\IFS1P3IX'.
Generating RTLIL representation for module `\IFS1P3JX'.
Generating RTLIL representation for module `\OFS1P3BX'.
Generating RTLIL representation for module `\OFS1P3DX'.
Generating RTLIL representation for module `\OFS1P3IX'.
Generating RTLIL representation for module `\OFS1P3JX'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\IBPU'.
Generating RTLIL representation for module `\IBPD'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\OBZPU'.
Generating RTLIL representation for module `\OBZPD'.
Generating RTLIL representation for module `\OBCO'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\BBPU'.
Generating RTLIL representation for module `\BBPD'.
Generating RTLIL representation for module `\ILVDS'.
Generating RTLIL representation for module `\OLVDS'.
Generating RTLIL representation for module `\$lut'.
Successfully finished Verilog frontend.

21.43.2. Continuing TECHMAP pass.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut.
Using template $paramod$7aa8140c7d6de3160b21e7ff84e0f93f69f7fcc6\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11010000 for cells of type $lut.
Using template $paramod$394086530b97e2ede4325cfef07483589916f736\$lut for cells of type $lut.
Using template $paramod$f9813472aa48e533b3838c6f2316dc2e78c66111\$lut for cells of type $lut.
Using template $paramod$2c1875de701f39453798b76f5b327fe456cc0991\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut.
Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0110 for cells of type $lut.
Using template $paramod$272652f6c6fbe9a75eff76e45cc7e2788835518b\$lut for cells of type $lut.
Using template $paramod$c28a8b7ce0535d090c4cfb52e9c74affd52b110c\$lut for cells of type $lut.
Using template $paramod$3ccc23db184ad4ca7ed34ebe2511de41d5d97e78\$lut for cells of type $lut.
Using template $paramod$7202672b7332febf25cdbe5424cf24593f5449be\$lut for cells of type $lut.
Using template $paramod$f28c2e49975958241d4d835ef97e799ed72256e5\$lut for cells of type $lut.
Using template $paramod$a5516fc31d1e552de2435200bb732b4d4ad63a9c\$lut for cells of type $lut.
Using template $paramod$f28a4401e00366386f5c9da01093cb438d2ef37a\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0010 for cells of type $lut.
Using template $paramod$5e2c4e05bbdd2eaa20212f01bb8e88597c0f6680\$lut for cells of type $lut.
Using template $paramod$68cb09a5d00037369a2af39e1778bf17484c020a\$lut for cells of type $lut.
Using template $paramod$6d6beead1425af15cf78b27fd9b11b41b5d4bce8\$lut for cells of type $lut.
Using template $paramod$505ef859daf333cd3708b17e0847e5ec5b9043b5\$lut for cells of type $lut.
Using template $paramod$ce44877a8aba311086973ef3ef648b154684306e\$lut for cells of type $lut.
Using template $paramod$136e57387592793f9592847d05ef6a1e5556813e\$lut for cells of type $lut.
Using template $paramod$6fc23ce09f2013cb9de2228dbcdda21841008f92\$lut for cells of type $lut.
Using template $paramod$c10d596c07d5001e21dac13e8cd350ccb2e683d4\$lut for cells of type $lut.
Using template $paramod$cf48b29332194ed05b4e63a678acb5324e9f6648\$lut for cells of type $lut.
Using template $paramod$7172af407489522b2f646d9852a99086208a433b\$lut for cells of type $lut.
Using template $paramod$0d3ac82cf5b8a192d5ff4c23e3143360366ae882\$lut for cells of type $lut.
Using template $paramod$2d52a1d6cf603c98ba7b908cd4e344a0536dbeca\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000010 for cells of type $lut.
Using template $paramod$d82743395a00cb844fb11eee66626018a89da412\$lut for cells of type $lut.
Using template $paramod$17f6f52626416ccc9898c40c1a3d8d16e0c2ee7f\$lut for cells of type $lut.
Using template $paramod$ec4a21f896d8babdcea50998bb320a7741366e32\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000000 for cells of type $lut.
Using template $paramod$6e238df02989b317f10820a22773676e71120644\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001000 for cells of type $lut.
Using template $paramod$33e58adf67c6b686a154c9ce8ebbc4b04b8cabc5\$lut for cells of type $lut.
Using template $paramod$0f9a5ffb15c1e481b6b1d423325ea99a60119726\$lut for cells of type $lut.
Using template $paramod$08466811901d5e03ed77c75ae1ee4f324a7c22b7\$lut for cells of type $lut.
Using template $paramod$f7bd536f0a874c7bb7aaa1ac909bf2d4656af121\$lut for cells of type $lut.
Using template $paramod$f8f63b209b7230e81958663ff24fef1613156af7\$lut for cells of type $lut.
Using template $paramod$0fe8fbf45fc9407b7d9f6cdf3b662e78e91e9b55\$lut for cells of type $lut.
Using template $paramod$744b384e063a538c8fc1764eeb3ce03ca86b5d60\$lut for cells of type $lut.
Using template $paramod$e3f83e7a511873fca56dd26ab54d1b2a157d3092\$lut for cells of type $lut.
Using template $paramod$1780b599fad82e57d6459b81ca42390759dd97e1\$lut for cells of type $lut.
Using template $paramod$fd3c6f7cd86ebd08275158b099051f4b085cb906\$lut for cells of type $lut.
Using template $paramod$eba7de026ff587370e320127e266317dae097a89\$lut for cells of type $lut.
Using template $paramod$e9c77024ca501b890c641f9c0b10e27242db8730\$lut for cells of type $lut.
Using template $paramod$dbbb2dcc1235dff546a9ff803c838ac813f9b44a\$lut for cells of type $lut.
Using template $paramod$f3ada871809f362efd8eb0c4fb952bb5c98f0750\$lut for cells of type $lut.
Using template $paramod$173257c402a3003de28bff8c2a49d358e5f4004c\$lut for cells of type $lut.
Using template $paramod$aa80fa079a227cf1e98cdb6bd2973d3412c30daf\$lut for cells of type $lut.
Using template $paramod$097592bb16245531f0716c5ddb18d7090f9c7d9d\$lut for cells of type $lut.
Using template $paramod$4cab3b31c601551ff65536bf4f533afa0b2094ee\$lut for cells of type $lut.
Using template $paramod$c19ac226b2328a9dc00b76bc0a6d1e025c6f4fca\$lut for cells of type $lut.
Using template $paramod$803fb2e411cd759897bb32714c4cd91d7f11ca86\$lut for cells of type $lut.
Using template $paramod$de04cb9fed08da92a34d101e5e82912c17d40d8e\$lut for cells of type $lut.
Using template $paramod$f18573f960aa698bb5df0e9a5dc3a7659aca4c2e\$lut for cells of type $lut.
Using template $paramod$701ea6ba0841e6999295fed3aa14992b0c563e58\$lut for cells of type $lut.
Using template $paramod$16773ebb5e5d8dbce266b8a86bb4af4574d61ffd\$lut for cells of type $lut.
Using template $paramod$251994398653c4cf8de320f1e306e535d5d2d624\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001100 for cells of type $lut.
Using template $paramod$3bcd6f633cdf31745ccb53511038b0b3fe05b606\$lut for cells of type $lut.
Using template $paramod$30fd64b647b1ad124867d9d40acc2cf185e45687\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000000 for cells of type $lut.
Using template $paramod$c97bcad21440836b1df0dc8f4860bb61034e5b37\$lut for cells of type $lut.
Using template $paramod$c54cd3c191caafdd71d4c723568325f413996bca\$lut for cells of type $lut.
Using template $paramod$6be1c8f14b3d20f109fab904f0aa9f4d6a208357\$lut for cells of type $lut.
Using template $paramod$2c31dde2f08728e7c94a017b410e16120a6d61e3\$lut for cells of type $lut.
Using template $paramod$b20b44b7ecee5be956e2b152bbe403b0db4146a7\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1001 for cells of type $lut.
Using template $paramod$5dc745bb48e2cf535179547ba13f0fe5364d6d54\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001110 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10010000 for cells of type $lut.
Using template $paramod$fc9cc857e8c016cc96968856c0dbbde95fb6af22\$lut for cells of type $lut.
Using template $paramod$6e9b258f5435fac718cd2baa1aec208a0e0447c0\$lut for cells of type $lut.
Using template $paramod$f1ec2ef3bb606499638ac17aeaf23ffb19b08a3f\$lut for cells of type $lut.
Using template $paramod$3affdfcea8a178bd21333137031dbb8bbc1b8287\$lut for cells of type $lut.
Using template $paramod$857512ea84a5fe5464efcd374b77666399ea78e1\$lut for cells of type $lut.
Using template $paramod$f45429e380905f064bb0bad3a8bdb941708e63a7\$lut for cells of type $lut.
Using template $paramod$efd9db50f639c84b61057002b4119366b96c7abc\$lut for cells of type $lut.
Using template $paramod$2ad7381dcc035b7d70badddc72b624e0fba0ba3e\$lut for cells of type $lut.
Using template $paramod$8d7a8d6e3356de09670738ba85f2c6b874f6b06d\$lut for cells of type $lut.
Using template $paramod$2628cef747ff322acd4f4da54f21d8e909b565c6\$lut for cells of type $lut.
Using template $paramod$df196ed0a1da5c4a58c5e08a1dac304fd3fccaab\$lut for cells of type $lut.
Using template $paramod$71d86193eda4b73cc90c4fe64cd8b24c8360b2ce\$lut for cells of type $lut.
Using template $paramod$79483857d6ba4b246820ed05b10f427b2b501c84\$lut for cells of type $lut.
Using template $paramod$221240dfda8dc9c346904fde6cd15350403c66d4\$lut for cells of type $lut.
Using template $paramod$3e4a83d2fa2084cfeb06b5014f9e61d02128ab94\$lut for cells of type $lut.
Using template $paramod$e3e4230bb990723642112b292aa705ee0cbad0d4\$lut for cells of type $lut.
Using template $paramod$5e840e204c7ef814c92b7cd2300006f99e318d12\$lut for cells of type $lut.
Using template $paramod$4eb848e991ac2a992be9b4be01f278b220c0efac\$lut for cells of type $lut.
Using template $paramod$e374f099c1946d555f0a6a12c0ce5d3ec931f9a3\$lut for cells of type $lut.
Using template $paramod$11d98a734fddb972e4bcf061987d6c0007a7bbfa\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001111 for cells of type $lut.
Using template $paramod$c217e185eb8e6463ca272982ba8c5940fa90d81f\$lut for cells of type $lut.
Using template $paramod$517625bf4a7b846fd553901d881a35fcc8afe4c4\$lut for cells of type $lut.
Using template $paramod$47a8214374025465e226fa66bee690ff33268a25\$lut for cells of type $lut.
Using template $paramod$364c9ffbffac467d60dfec81bba4e18476c15602\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0001 for cells of type $lut.
Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9\$lut for cells of type $lut.
Using template $paramod$ddace04fba544e6adc4cdda6a50048ddd7c111af\$lut for cells of type $lut.
Using template $paramod$bba54c1ef87367812b4c15f4aed5ac70773df775\$lut for cells of type $lut.
Using template $paramod$873c285bdccf0ac2b60d2304ea5cd14bf211d2a6\$lut for cells of type $lut.
Using template $paramod$30305e55a780880b9c824fe3509a4d981acb0f2b\$lut for cells of type $lut.
Using template $paramod$a15fd389a2f54cb7b94707b25934d226e68d9e2e\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001010 for cells of type $lut.
Using template $paramod$e01a027fedb28671a20c130493a89c7afd4e87d3\$lut for cells of type $lut.
Using template $paramod$af2687fd5fb9a9e3acf03acbf02c6dad53202781\$lut for cells of type $lut.
Using template $paramod$b8113752b08bd47f69a1c8c2bca1cfb157e800c9\$lut for cells of type $lut.
Using template $paramod$7ae4a405e3704cc6576bad5ded0ecf182ff805b6\$lut for cells of type $lut.
Using template $paramod$863c404e3b83348ee34171710337d8e8efb7f8b2\$lut for cells of type $lut.
Using template $paramod$a8b2b0f3a3fd7b01c99e8d61bb72f602bd41af54\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101100 for cells of type $lut.
Using template $paramod$c1a19a87ccbbb03d43a72335db63f692ddf82cc1\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100100 for cells of type $lut.
Using template $paramod$0481307368cf4a85ae92b0215b3a5fbde430998f\$lut for cells of type $lut.
Using template $paramod$ab8bb87959c5d7cfa27886cee1355b38e054a61a\$lut for cells of type $lut.
Using template $paramod$e85b6eba0dacefc5f73f8748159b8b9599212afc\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00110001 for cells of type $lut.
Using template $paramod$7d813eb49700f971f2635a434700eafdfa816bc3\$lut for cells of type $lut.
Using template $paramod$faace351d5336ef9147b65874a3ba6a2f4c9f8ee\$lut for cells of type $lut.
Using template $paramod$2645ed3928f2726e8ccb403cb23252de43b617d7\$lut for cells of type $lut.
Using template $paramod$6023c671e114c4eb0467aa8a0b08e183f33ec2fd\$lut for cells of type $lut.
Using template $paramod$7ccb46ee9b56c39e0a7d82a185b08cb026e04fbc\$lut for cells of type $lut.
Using template $paramod$af0e77ed704529a8b8c89a9a361eee89099fc0f9\$lut for cells of type $lut.
Using template $paramod$49637ade734e07e8ad89eefc6628a06bcc57ebe2\$lut for cells of type $lut.
Using template $paramod$221832ea6a41a3208cd6f3411a952b5811695f4c\$lut for cells of type $lut.
Using template $paramod$a05170b3f2d3fcb0bf88d37e810984e864962880\$lut for cells of type $lut.
Using template $paramod$db08fd84fb3c4d6a41eaec6adfffe445fb7eb17f\$lut for cells of type $lut.
Using template $paramod$a1d323730045824cfc84bb9f4ee8031f1c4dcc9e\$lut for cells of type $lut.
Using template $paramod$a6b2d4693fada6bebbe4480262641915d709d280\$lut for cells of type $lut.
Using template $paramod$e49f6e3576ef1a6d2f58c54414dbb786af8cc869\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100000 for cells of type $lut.
Using template $paramod$b9cbb0f16a176e4b2e9dbca6aee127ce97922bd2\$lut for cells of type $lut.
Using template $paramod$3416dacc8eaab1f89b3d6b7398df3da766d29ef2\$lut for cells of type $lut.
Using template $paramod$219b71aec9a19e7a27754ed85a7d6cdad9e5ec96\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110000 for cells of type $lut.
Using template $paramod$193d365ba3260f56de4ca734b1cedcf9dc72302b\$lut for cells of type $lut.
Using template $paramod$5552b23a89809fed2b1588e8f91bb3893be2e6ce\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000001 for cells of type $lut.
Using template $paramod$8e44661def013b6bf9fe6f8b049ef2c838d749f9\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut.
Using template $paramod$57400e123f0147f905d2ec980ae5b64230fc0a43\$lut for cells of type $lut.
Using template $paramod$f0de73e203daef8f8580918556298273e538cabc\$lut for cells of type $lut.
Using template $paramod$153c6cdaaddbc43e6ef3facd06aa851de33910ae\$lut for cells of type $lut.
Using template $paramod$f6cb3fdab41e95c971e90994829351e95bc70e14\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000100 for cells of type $lut.
Using template $paramod$66caeb00a39d236782a97659e3bd99621b74681b\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001101 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01111111 for cells of type $lut.
Using template $paramod$fca001e3e0b52158a872e76e56c01ec10dfbb1de\$lut for cells of type $lut.
Using template $paramod$b93d1ea7a612a32c185108f67a153d44ffb9aac2\$lut for cells of type $lut.
Using template $paramod$75ae9627805e0c99d176bdce0ae8ff0c02687aab\$lut for cells of type $lut.
Using template $paramod$7b733f5b3466ec911060896fccc5c2626cbe3d64\$lut for cells of type $lut.
Using template $paramod$d7ec878ecfa8f5f7604d3e91692b5d4c2ee758ad\$lut for cells of type $lut.
Using template $paramod$101238f3d8d49ab12a9b49a2f01cd503b26e9c61\$lut for cells of type $lut.
Using template $paramod$1843b3c15f2447d117e2d5de9b00f791ef5f9fa3\$lut for cells of type $lut.
Using template $paramod$bf52fe08de03e5ab1b0a82e3f7a26b8429740a24\$lut for cells of type $lut.
Using template $paramod$6be53ab59e0a69757fc32adb071ddcb64e8c87b6\$lut for cells of type $lut.
Using template $paramod$018d71a0fe325d6362687fe53ac13dd6340e400d\$lut for cells of type $lut.
Using template $paramod$ad2fbd8be3a819ebcd6b7ffdf7b499b345b7099d\$lut for cells of type $lut.
Using template $paramod$d7372df0dc02a6c940130cc6e3dbb5dc0398486d\$lut for cells of type $lut.
Using template $paramod$920c30c965b89e85bc6c38e2211cf7b09d4fb168\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111101 for cells of type $lut.
Using template $paramod$adce9c89515a4e83641fc3471eb3c01ec7b082ff\$lut for cells of type $lut.
Using template $paramod$a191129d10a368b82781b98ff31865427345b51c\$lut for cells of type $lut.
Using template $paramod$92c3899764cd8074859d6a5a5b733cffe8a391b3\$lut for cells of type $lut.
Using template $paramod$be95f3a2132281eadd1adcfe6229e43dbc3353c9\$lut for cells of type $lut.
Using template $paramod$81728d032460d14d3a85b50b268e8e543c74dbb6\$lut for cells of type $lut.
Using template $paramod$3b374b0454c507d1efadee363d480c52c3b3f58f\$lut for cells of type $lut.
Using template $paramod$cd77d5e7596a750e2c0ed130aacde2f323347f26\$lut for cells of type $lut.
Using template $paramod$d3d930b472d69efc17cf72f398b6109bf4f6c442\$lut for cells of type $lut.
Using template $paramod$0331e023d83b8009e60defb446ce9fa640b122c7\$lut for cells of type $lut.
Using template $paramod$6b0849254d6c87461fb93e37cc18f089f61eb912\$lut for cells of type $lut.
Using template $paramod$be7b9b4fe304f35e2a126a3893cf799cf6d216a8\$lut for cells of type $lut.
Using template $paramod$865395c0228487a64a8e4011cecafc2c64b79f2b\$lut for cells of type $lut.
Using template $paramod$ff78dd6c60f6ec3c4835fa808434b34b1e6b8920\$lut for cells of type $lut.
Using template $paramod$f4257f9b9dfe762de25d0a149f2ea6e405c888f2\$lut for cells of type $lut.
Using template $paramod$b2153d8b4466d4a8f8649eafb88b32b9356a5968\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111011 for cells of type $lut.
Using template $paramod$2a4b250d89be3556c74aa0e719a4f6242369d42f\$lut for cells of type $lut.
Using template $paramod$81d8a60fd95b1a9f9ef71c12a774ae6988cb9fd5\$lut for cells of type $lut.
Using template $paramod$b4f85a6321a00b090afc4e21d68e7b99eb94d149\$lut for cells of type $lut.
Using template $paramod$4d7dc822e6ac78c7574e16060f5e26124cddca40\$lut for cells of type $lut.
Using template $paramod$2e42f4cdfa2b7be54cbecc74818d81b621a7793c\$lut for cells of type $lut.
Using template $paramod$6784ab7fe1a4fcf5f8959675595f138ff658d2b6\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10110000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101000 for cells of type $lut.
Using template $paramod$7fc325150916e09e21db63cc9672b99a89ef9301\$lut for cells of type $lut.
Using template $paramod$317896915d4231f6dc91bdcfc9a7afe4e091e68c\$lut for cells of type $lut.
Using template $paramod$cad45b6c9da81941161a13849773fe2ed4bc1c6f\$lut for cells of type $lut.
Using template $paramod$c1a909080ec76944fa258a19c3ca35c98563249f\$lut for cells of type $lut.
Using template $paramod$ee700feb78d1f78a2275689013e0e783764ce7f3\$lut for cells of type $lut.
Using template $paramod$849d013d096d73269ca4beb768f8e399745d37f2\$lut for cells of type $lut.
Using template $paramod$ffc2ea81a65101fbef8a332deddf112494d27163\$lut for cells of type $lut.
Using template $paramod$89ca3723ebb4dfdb3c4024f3f04b784a3e88f188\$lut for cells of type $lut.
Using template $paramod$0ae4e6ad7e07e634c7166b50dfaeb6b360dcb05d\$lut for cells of type $lut.
Using template $paramod$a20c05dc9676052a7e2b6a7867c7b438a00b8727\$lut for cells of type $lut.
Using template $paramod$3b013216d6c8b5b177ea79de7803f6bb4c74e84b\$lut for cells of type $lut.
Using template $paramod$e6dfe5b1a1a5899545d0bf3f012990e128646c56\$lut for cells of type $lut.
Using template $paramod$179512a187da069f3b79ef6612a41e494e7d54b6\$lut for cells of type $lut.
Using template $paramod$9e1755e3954600257bb9b9ab192e2c0243b0f35a\$lut for cells of type $lut.
Using template $paramod$b0cead1f76b95bf15933fb262b7a0b5c2f45d8d0\$lut for cells of type $lut.
Using template $paramod$492e9e33b4a4328542bb2090128975a352c861cb\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00011011 for cells of type $lut.
Using template $paramod$ed458aa2b76c4f1924dbd08807ece22875878611\$lut for cells of type $lut.
Using template $paramod$4c019fad677a6751d10c7683062ad8483ed51b71\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1101 for cells of type $lut.
Using template $paramod$d08ae3e2fee668f1a68bd32fd012d46d229cb782\$lut for cells of type $lut.
Using template $paramod$4a91aab924d413dd66e54355a6653bf40aebbe71\$lut for cells of type $lut.
Using template $paramod$a2636977f628344828cab2c26b213b1edc5ab815\$lut for cells of type $lut.
Using template $paramod$373d637619c29cb9150902df9528107e5f3b8288\$lut for cells of type $lut.
Using template $paramod$b587e1dcd8f8a9800d395e4aeecac52c55d6f585\$lut for cells of type $lut.
Using template $paramod$8b2d4da05a775f7705e7bcda27120d70b71d57db\$lut for cells of type $lut.
Using template $paramod$2f35f125a78690286f0cd2faecbaee9c64828b65\$lut for cells of type $lut.
Using template $paramod$365dd8078b852950805086d7574f5d3d720e964d\$lut for cells of type $lut.
Using template $paramod$9cf976b4f3a576aa2cd6b51304cf5de7fc836fbd\$lut for cells of type $lut.
Using template $paramod$22b1ff0b4852266feb9ec5563b367168a88c8675\$lut for cells of type $lut.
Using template $paramod$785fe2f670ffa8391ffc746f273c145bd3d86aab\$lut for cells of type $lut.
Using template $paramod$eb8ee64d6896d4e161956bf1d7f5e559a366f7d8\$lut for cells of type $lut.
Using template $paramod$0b55939a1d751753d28d0d9309dcfe8066575a9c\$lut for cells of type $lut.
Using template $paramod$9cbecc08f7d93dedd76783f6f3f7afce4ea7b941\$lut for cells of type $lut.
Using template $paramod$7f88ae8b0ca78f7b736f446522956805c49fb79f\$lut for cells of type $lut.
Using template $paramod$729e309efb767462e04d0f5bc6a998dfe103a51f\$lut for cells of type $lut.
Using template $paramod$68abdd159e9c42c231f94cdf32a7ea81ff92f7d2\$lut for cells of type $lut.
Using template $paramod$749ed67294097b0577fc6e639a481c35ff1e8e6a\$lut for cells of type $lut.
Using template $paramod$0f19b1c588a47c675d00132b243b5e3308ffab5d\$lut for cells of type $lut.
Using template $paramod$6f9324703e8fcc3b6df2bc2bec54ec19a446ae96\$lut for cells of type $lut.
Using template $paramod$a4640096cbef09c4ef8613155a589c40164ac034\$lut for cells of type $lut.
Using template $paramod$64c26e3b45d8718f97412a5efc0d7874f19d09e7\$lut for cells of type $lut.
Using template $paramod$14f95f5f355a7b50108d088fd87a65d6553aa458\$lut for cells of type $lut.
Using template $paramod$d8119e7cf18bdd1d72e1822e569d9c40a2fc5848\$lut for cells of type $lut.
Using template $paramod$0dfe5e755f31cad126590ddcdfa89fc7bbe95290\$lut for cells of type $lut.
Using template $paramod$71b74dd9870bd6fb645429d9459a2dd87b035cdd\$lut for cells of type $lut.
Using template $paramod$b4410865e8124402796f9dfbf73ef8d279fdbd08\$lut for cells of type $lut.
Using template $paramod$2e9afba29670cc6475874639e7c1b3979c8ebde3\$lut for cells of type $lut.
Using template $paramod$4f7f30fb8da10e34653124e504f4b00f64c20a39\$lut for cells of type $lut.
Using template $paramod$6648c16856470047a915b30f34c7e1d81c145425\$lut for cells of type $lut.
Using template $paramod$5a9ae901a0103997ddb70add99b4a981140f1ba5\$lut for cells of type $lut.
Using template $paramod$dbdbcb07b9994e498bb1324e5c006c6aa08a7a37\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11011000 for cells of type $lut.
Using template $paramod$a29dc9226a883358910d3758606f48686bda2689\$lut for cells of type $lut.
Using template $paramod$cf73134d1cf2a84eaa86671fe57a901cff49434a\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010011 for cells of type $lut.
Using template $paramod$2a80452bcf264f58f3fa971a9e77b49f18691a20\$lut for cells of type $lut.
Using template $paramod$01b636f2759ab594c2741266b3c22685988e291c\$lut for cells of type $lut.
Using template $paramod$90dde3ec335fc6daa3fb20f8db8c84b4ceeaa590\$lut for cells of type $lut.
Using template $paramod$cf652acbfbf67d2248e3045cd0f09c58ca55886c\$lut for cells of type $lut.
Using template $paramod$1b567725d0de5626682abeb929588de81db733d0\$lut for cells of type $lut.
Using template $paramod$d79e8c7f0cb3bd049a34d82ec5fe688d444e5a52\$lut for cells of type $lut.
Using template $paramod$302ba22a83dfb50189674147c5c2626b9e9dab7e\$lut for cells of type $lut.
Using template $paramod$1dbc005c3ca46176ed5f71d3318762a2498d170f\$lut for cells of type $lut.
Using template $paramod$ca27e3bcba040e99ab298ab2a561faf6e08a6e19\$lut for cells of type $lut.
Using template $paramod$712505941a295086314c22735153725461a87f4a\$lut for cells of type $lut.
Using template $paramod$2ec6422db00d358fc7469efce6208bffbc8521cd\$lut for cells of type $lut.
Using template $paramod$20aecb9a781743d0e93608b1c1e7d62ffc3a69a9\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001110 for cells of type $lut.
Using template $paramod$cf93df6a751c015d454aef52e32716809f254f3e\$lut for cells of type $lut.
Using template $paramod$332530260df33f1e6567b344a898a29636fd4f0f\$lut for cells of type $lut.
Using template $paramod$757c055b2d591f99a56beeb4bd1bdff266f67334\$lut for cells of type $lut.
Using template $paramod$b1fb29d9d868019dc056d6ac4291eb7e79746944\$lut for cells of type $lut.
Using template $paramod$8b5edd505331ea1322066a97b8d3ee73c26bc941\$lut for cells of type $lut.
Using template $paramod$48c19eb209dd8ad2c18334e4df384d3b3b74d5ec\$lut for cells of type $lut.
Using template $paramod$e332cff882edd417f410bab5fe07a0f88572cce3\$lut for cells of type $lut.
Using template $paramod$20ae971f03a8aabd14bc9c90601f9bed8100c9da\$lut for cells of type $lut.
Using template $paramod$e6a488add0b5a2d742e2ae29f62ce7616e04271d\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001010 for cells of type $lut.
Using template $paramod$37c9af120c85145419565a9ccf4ceb7397fbbe92\$lut for cells of type $lut.
Using template $paramod$000fa2164e1f538c16460571efee2b6209a086cc\$lut for cells of type $lut.
Using template $paramod$78f5590b0462181d8749c9e6ed8a771b22dfb9ed\$lut for cells of type $lut.
Using template $paramod$f1ce835237190a5ae4ef9c8edac6943620aaa1a9\$lut for cells of type $lut.
Using template $paramod$f1e30f3cce5e20267fc4b3d95c7953433215787a\$lut for cells of type $lut.
Using template $paramod$e381ae436be6e323ec8dfb917fdc2175ab9a3bff\$lut for cells of type $lut.
Using template $paramod$15ac410ea5b84c303864da98179081473b96983a\$lut for cells of type $lut.
Using template $paramod$0d4742cff20cb0e0e40b9af6c0257e3a276c0c2b\$lut for cells of type $lut.
Using template $paramod$b7d5a1d13a95755f80d49e78f7fe57dd63a6cfbe\$lut for cells of type $lut.
Using template $paramod$58bd588a49a6a3b9d057d75f907cb4932e1635f6\$lut for cells of type $lut.
Using template $paramod$92730f5a8a4aea1eaf6c696475735f4203b441f9\$lut for cells of type $lut.
Using template $paramod$1de9021fb76c1bea0009f13ccf50560f3cbb28c2\$lut for cells of type $lut.
Using template $paramod$8091f1055b08cf62a067eb9c712980d4ac8978e3\$lut for cells of type $lut.
Using template $paramod$162e63c109358bf87c7c7fa3982b10ead2d0adf8\$lut for cells of type $lut.
Using template $paramod$a78184bd86c835516b7930a5184bc2412fb81021\$lut for cells of type $lut.
Using template $paramod$760fc4e34b8e49274570cdcfa8d830e31250b6b0\$lut for cells of type $lut.
Using template $paramod$672e798a02b8bcc43378b3bcf167b71b5747401f\$lut for cells of type $lut.
Using template $paramod$7d35f3eb4056e6484203c99fe42cfcf1dfaba704\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001100 for cells of type $lut.
Using template $paramod$e019cb14313283ce60b57907d30cf3eefa00a93d\$lut for cells of type $lut.
Using template $paramod$84c5cfa8d7481774250caab0fcdd6d249a376a31\$lut for cells of type $lut.
Using template $paramod$30fc4e1e8746ea71f124b99a7add7bd3b1dc22d9\$lut for cells of type $lut.
Using template $paramod$6f2dff8ceb94e43f02dede3fce5227f780f6fc38\$lut for cells of type $lut.
Using template $paramod$1d976bc954653b91c2dfa54d38dd9f92125922d7\$lut for cells of type $lut.
Using template $paramod$b98c5cad3e4b1575461e7c6b454efd7b9d35666f\$lut for cells of type $lut.
Using template $paramod$a50f1c411368f4b7b265d7b2b2e06d07b921e41d\$lut for cells of type $lut.
Using template $paramod$57cf7fbf84518d9e7604ec42b59ba9511e1f3caf\$lut for cells of type $lut.
Using template $paramod$16425e5925a6c8b25e1a4c719c9f7f6442e0151b\$lut for cells of type $lut.
Using template $paramod$2955ab75367a3dc9d6f50d3655eebcd4f615031f\$lut for cells of type $lut.
Using template $paramod$5b4991ef8e215d9f18839630c2afa21273bf9421\$lut for cells of type $lut.
Using template $paramod$6eaff21d3c29251343ef497052cf2c77fea3c8e9\$lut for cells of type $lut.
Using template $paramod$513a778195c93be1386c60c04e2e2ab6c33ba551\$lut for cells of type $lut.
Using template $paramod$eabde4761c91679426ef5401ae1b2c95bf56e107\$lut for cells of type $lut.
Using template $paramod$e6473e79f5d2cbf19c2c630ef8419195f85c06fb\$lut for cells of type $lut.
Using template $paramod$127d42c61791e2b6b8fd39133e126a67cbdb52bc\$lut for cells of type $lut.
Using template $paramod$c5e9409d868ac22b0d04fa66386bddf5c7c8858c\$lut for cells of type $lut.
Using template $paramod$99a108227aaa9c10a44f35da25380139e2ce7c0f\$lut for cells of type $lut.
Using template $paramod$27d1fd562eca397af0bcf374fcecce96bb10480e\$lut for cells of type $lut.
Using template $paramod$8545389b02a7d1f8b3b033f01b168e67cb15be78\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100011 for cells of type $lut.
Using template $paramod$8d64e576629e8d7c655e0c65958ea61e649cd93e\$lut for cells of type $lut.
Using template $paramod$83a094b6fe9fb738dfff353a8cb39fb4b34c4f40\$lut for cells of type $lut.
Using template $paramod$2057882d892d7588b23e158ac1d718d8092a4bce\$lut for cells of type $lut.
Using template $paramod$19f568890ed784cb1efc3ce1b67eed20a6c54d9a\$lut for cells of type $lut.
Using template $paramod$f0e4a8b607f0a018301991aec7b151de2101f82c\$lut for cells of type $lut.
Using template $paramod$b35ee89894fcd81b08d11016fdcb0d9daf8a7509\$lut for cells of type $lut.
Using template $paramod$a7ac7753d98f089d63b99f1499db53ac78ea00a6\$lut for cells of type $lut.
Using template $paramod$295ed90166f07390f20c9bb174fd57fd290bf845\$lut for cells of type $lut.
Using template $paramod$d0970c92f0876d74087b98f276ab94838de3d221\$lut for cells of type $lut.
Using template $paramod$f13784ede300b12a5285177c86c7721a54cf9e12\$lut for cells of type $lut.
Using template $paramod$b287726797d0722f64e731f1134f7c05af8f1578\$lut for cells of type $lut.
Using template $paramod$baa9d2fb2d21010939721b85aa9f11effe0b53c4\$lut for cells of type $lut.
Using template $paramod$97ad2011bfd0fc904987f254f82f2ce770c16e3a\$lut for cells of type $lut.
Using template $paramod$428455bf683af997b0aced216a36aa68a8816e79\$lut for cells of type $lut.
Using template $paramod$0c058dfc29825e1ea89fdfb7507eb91d68500897\$lut for cells of type $lut.
Using template $paramod$6e8412e945297528d3f6f3ce2a821de69911673c\$lut for cells of type $lut.
Using template $paramod$bad4cdba09f4dc8eed8a2fe5758bfc8c15a902a7\$lut for cells of type $lut.
Using template $paramod$d1b32a3234ea567ce392e1c37146cb799a57bef8\$lut for cells of type $lut.
Using template $paramod$bad5fb17289759f3d3edb9963a5cb94e16476717\$lut for cells of type $lut.
Using template $paramod$de96da5f1bbfbd6e78889c4a280998249b52831c\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001000 for cells of type $lut.
Using template $paramod$07a2ef7981161e54efaee79229f25ad8488124d1\$lut for cells of type $lut.
Using template $paramod$6069048ea7c45159713a0558424cdfb243a46dfe\$lut for cells of type $lut.
Using template $paramod$d07b370dde847ff102dfeea99a3d78ed7f287f4e\$lut for cells of type $lut.
Using template $paramod$b2649106a625a0704077b7f703e411239478cf3e\$lut for cells of type $lut.
Using template $paramod$20f82dd03802038bc013e5804609eaebb5d257db\$lut for cells of type $lut.
Using template $paramod$a977fb3a4e30b200887394f8ff6c3df1befab9e3\$lut for cells of type $lut.
Using template $paramod$9a92da23c4e9c4048c7590dc07955b118f9b4d07\$lut for cells of type $lut.
Using template $paramod$72148f3545efac6f48701d6c21ae5eeb7a5f865b\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01010001 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100000 for cells of type $lut.
Using template $paramod$5b4b4ed558983d9f3ab4c896a7a011d129b0db9a\$lut for cells of type $lut.
Using template $paramod$2b2b3565ec13859d2b24f2fa297fa46249270140\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111000 for cells of type $lut.
Using template $paramod$70ebb6cf5bc7d63c5c1a98ccefefa2af79e8f2a9\$lut for cells of type $lut.
Using template $paramod$c5f3c57a6d466a2f42208bafb8985b96ce884440\$lut for cells of type $lut.
Using template $paramod$651e836885d95717c36e69441422c3fe04ee5f4d\$lut for cells of type $lut.
Using template $paramod$75020cdf7715bd4a5f7067d80cafc74eabba6a01\$lut for cells of type $lut.
Using template $paramod$e934877433e628b9aa4b7cb2bee8957bca3e1db5\$lut for cells of type $lut.
Using template $paramod$86a69f95bdbfc36792b7c7498d3544468c88bd9a\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111110 for cells of type $lut.
Using template $paramod$4d9437f28ee827cf4006287c53ecaa1266100fca\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1110 for cells of type $lut.
Using template $paramod$18e50808df562b188523e13714b96fedec6427c1\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11101100 for cells of type $lut.
Using template $paramod$5d91ae8bf13f169f64fe2e993cae12295d19d8d3\$lut for cells of type $lut.
Using template $paramod$19be9597b788c07653b8e254f519518a1572fd5b\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01101010 for cells of type $lut.
Using template $paramod$b1eed235f4595099c4d6771c299862db0590e4ad\$lut for cells of type $lut.
Using template $paramod$70f68cc10fbeada9b6fa90c3bb75475e348ca467\$lut for cells of type $lut.
Using template $paramod$619b7c9a4d44585e10b42f7fb79b16304cca97c5\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00111011 for cells of type $lut.
Using template $paramod$0328e568d609989242dcb98a1c5328d4372a6e9c\$lut for cells of type $lut.
No more expansions possible.
<suppressed ~8713 debug messages>

21.44. Executing OPT_LUT_INS pass (discard unused LUT inputs).
Optimizing LUTs in top.
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97644.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97644.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97644.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97644.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97644.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97666.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$9552.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9552.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9462.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9355.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9071.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9071.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9071.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9071.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9071.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9071.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8971.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8971.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8971.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8971.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8971.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8971.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8628.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8628.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8628.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8628.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8628.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8258.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8258.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8258.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8143.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8143.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8143.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8018.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8018.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97661.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97661.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97661.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97661.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7892.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$7892.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7892.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7892.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7892.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7892.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8013.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$7945.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7945.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7945.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$7945.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7945.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7872.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7872.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7822.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7822.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7822.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$7822.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7822.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97656.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97656.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97656.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8462.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$8462.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8457.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$7937.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7937.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7937.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7937.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7937.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7814.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7814.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7814.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7814.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7814.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8253.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8247.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$8247.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8247.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$8247.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8247.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$8247.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8543.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$8537.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8537.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$8537.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8537.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$8537.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8537.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8491.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$7807.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$7800.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7800.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7800.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7800.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7800.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7800.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8901.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$8901.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$8901.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$8893.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8893.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8893.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8893.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8893.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8893.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8876.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$8876.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$8876.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$8867.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$8867.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$8867.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$8867.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$8867.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$8406.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8406.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8406.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8406.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8406.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7926.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7926.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7926.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7926.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7926.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7926.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7912.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7912.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7912.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$7912.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$7912.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$7912.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$8723.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8717.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8717.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8717.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8717.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$8717.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$8717.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97651.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8828.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$7847.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7847.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7847.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7847.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7847.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7847.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97652.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97652.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97652.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97652.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97652.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8799.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$8799.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$8794.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$8658.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$8658.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$8658.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$8658.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$8658.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$8153.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8153.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8153.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$8153.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$8153.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$8153.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$7902.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7902.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7902.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$7902.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$7902.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$7902.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$8688.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$8955.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$7836.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7836.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7836.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$7836.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$7836.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$7836.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97657.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97657.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97657.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97657.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8348.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8348.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8348.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8348.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8348.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8341.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8341.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8341.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8341.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8341.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8341.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8320.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8075.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8075.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8075.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$8075.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$8075.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$8075.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$7970.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7970.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7970.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7970.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$7970.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$7970.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$7970.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97654.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97654.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8617.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$8617.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7781.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7781.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7781.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7781.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$7781.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$7781.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$7781.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$8442.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8442.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8442.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$8442.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$8442.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8442.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8469.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8469.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8469.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8469.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8469.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8469.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8085.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8085.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8085.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8085.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$8085.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$8085.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$8085.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$9010.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9010.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9010.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7960.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7960.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7960.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7960.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$7960.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$7960.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$7960.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$8990.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$8990.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$8990.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$9259.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$7771.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7771.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7771.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$7771.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$7771.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$7771.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97649.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97649.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9076.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8385.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8385.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8385.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$8385.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$8385.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$8385.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$9304.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$9304.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$8118.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$8111.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8111.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8111.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8111.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8111.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8111.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97648.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7983.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7983.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7983.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7983.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$7983.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$7983.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$7983.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$9159.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9159.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9159.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7761.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7761.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7761.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7761.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$7761.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$7761.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$7761.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97645.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97645.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97645.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97645.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97645.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9389.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$8375.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8375.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8375.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8375.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$8375.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$8375.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$8375.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$7257.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7257.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7257.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7257.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$7257.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$7257.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$7257.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$7232.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7232.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7232.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7232.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$7232.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$7232.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$7232.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$7200.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7200.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7200.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7200.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$7200.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$7200.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$7200.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$9516.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8104.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$8097.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8097.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8097.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8097.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8097.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8097.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7279.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7279.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7279.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$7279.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$7279.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$7279.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$7153.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7153.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7153.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7153.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$7153.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$7153.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$7153.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$7175.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7175.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7175.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$7175.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$7175.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$7175.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97659.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97659.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$7710.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$7703.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7703.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7703.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7703.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7703.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7703.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7687.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7687.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7687.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7687.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7687.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7687.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7681.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7681.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7681.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7681.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$7681.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$7681.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$7681.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$7751.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7751.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$7751.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$9493.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$9493.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$9493.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$9493.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$9196.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9196.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9196.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$9196.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$9196.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$9196.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$9186.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9186.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9186.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9186.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$9186.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$9186.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$9186.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$8575.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8575.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8575.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8575.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$8575.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$8575.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$8575.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$8588.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8588.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8588.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$8588.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$8588.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$8588.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$8565.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8565.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8565.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8565.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$8565.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$8565.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$8565.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$8520.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8520.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8520.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$8520.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$8520.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$8520.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$7879.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7879.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7879.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7879.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7879.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9369.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9369.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9369.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9369.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9369.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9114.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9114.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9114.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9114.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9114.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9114.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9107.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9107.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9107.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9107.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9107.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9107.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8300.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8300.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8300.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8300.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8300.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8300.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8289.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8289.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8289.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$8289.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$8289.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$8289.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$8276.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8276.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8276.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$8276.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$8276.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$8276.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$8266.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8266.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$8266.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$7032.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7032.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7032.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$7032.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$7032.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$7032.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$7671.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7671.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7671.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$7671.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$7671.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$7671.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$7661.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$7654.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7654.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7654.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7654.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7654.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7654.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7647.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7647.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7647.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7647.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7647.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7647.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7628.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7628.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7628.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7628.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$7628.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$7628.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$7628.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$7608.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7608.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7608.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7608.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$7608.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$7608.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$7608.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$7598.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7598.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7598.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7598.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$7598.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$7598.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$7598.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$7618.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7618.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7618.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7618.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$7618.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$7618.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$7618.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$7543.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7543.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7487.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7487.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7466.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$7451.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$7451.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$7451.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$7451.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$7438.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7421.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$7398.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$7398.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$7398.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$7398.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$7367.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7367.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7334.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$7334.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$7334.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$7334.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$7321.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7321.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7321.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$7321.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$7321.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$7309.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$7309.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$7309.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$7309.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$7309.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$7222.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$7222.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$7222.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$7287.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97850.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97850.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$7093.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$7083.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$7083.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97853.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$7003.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7003.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7003.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7003.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7126.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$7111.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$6937.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6937.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6937.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6937.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6937.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6937.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97806.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97806.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$6880.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6880.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6880.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$6880.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$6880.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$6880.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97809.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$6853.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6853.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6853.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$6853.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$6853.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$6853.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$6925.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6925.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6925.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$6925.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$6925.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$6925.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$6908.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6908.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$6908.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$6908.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$6908.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$6839.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6839.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6839.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6839.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6839.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6839.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97802.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97802.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$6762.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6762.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$6762.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$6762.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$6762.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97798.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97798.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$6782.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6782.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6782.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$6782.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$6782.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$6782.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$6827.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6827.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6827.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6827.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6827.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6810.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6810.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$6810.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$6810.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$6810.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$6748.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6748.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6748.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6748.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6748.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6748.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97816.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97816.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$6700.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6700.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$6700.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$6700.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$6700.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$6737.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6737.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$6737.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$6737.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$6737.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$6720.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6720.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$6720.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$6720.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$6720.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97828.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97828.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$6667.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6667.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$6667.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$6667.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$6667.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97829.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$6628.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6628.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$6628.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$6628.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$6628.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$6606.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6606.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6606.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$6606.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$6606.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$6606.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97832.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$6648.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6648.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$6648.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$6648.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$6648.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$6592.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6592.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97840.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97840.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97840.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$6554.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6554.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97820.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$6540.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6540.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$6540.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$6540.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$6540.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$6490.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6520.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6520.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6520.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$6520.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$6520.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$6520.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97841.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97841.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97844.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97844.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$6453.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6453.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6453.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6453.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6453.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6439.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6439.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97845.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97845.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97845.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$6420.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6420.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6420.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6420.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6420.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6406.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6406.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7526.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6951.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$7072.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$7072.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$7072.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7072.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$6323.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6329.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$10203.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$10264.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$10373.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$10389.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$10405.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$10421.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$10440.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$10473.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$10489.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$10524.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$10537.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$10630.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$10664.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$10680.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$10696.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$10712.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$10741.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$10749.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$10756.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$10873.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$10940.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$10956.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$10969.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$10973.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$10983.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$11078.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$11146.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$11207.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$11303.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$11337.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$11370.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$11403.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$11423.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$11489.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$11505.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$11590.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$11606.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$11633.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$11697.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$11759.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$11775.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$11791.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$11807.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$11859.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$11875.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$11917.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$11969.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$11985.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$12001.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$12017.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$12036.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$12052.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$12068.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$12084.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$12109.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$12175.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$12306.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$12367.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$12400.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$12434.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$12450.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$12466.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$12482.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$12524.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$12595.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$12611.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$12641.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$12657.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$12664.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$12707.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$12723.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$12742.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$12758.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$12780.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$12842.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$12858.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$12874.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$12890.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$12909.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$12925.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$12932.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$12942.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$12958.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$12980.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$12995.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$13032.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$13057.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$13120.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$13136.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$13143.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$13153.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$13187.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$13220.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$13236.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$13324.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$13386.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$13402.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$13418.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$13434.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$13453.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$13486.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$13502.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$13545.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$13561.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$13574.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$13581.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$13597.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$13613.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$13629.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$13657.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$13697.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$13713.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$13735.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$13797.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$13865.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$13942.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$13958.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$13992.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$14008.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$14024.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$14040.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$14059.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$14092.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$14108.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$14146.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$14162.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$14194.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$14227.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$14243.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$14253.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$14260.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$14276.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$14295.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$14311.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$14332.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$14400.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$14463.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$14479.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$14489.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$14496.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$14530.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$14546.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$14580.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$14614.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$14675.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$14742.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$14803.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$14836.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$14869.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$14885.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$14904.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$14920.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$14949.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$15030.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$15046.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$15076.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$15142.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$15158.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$15177.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$15193.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$15230.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$15281.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$15347.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$15363.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$15382.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$15398.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$15422.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$15435.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$15488.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$15552.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$15614.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$15630.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$15646.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$15662.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$15681.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$15714.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$15730.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$15759.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$15772.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$15782.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$15789.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$15802.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$15830.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$15843.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$15853.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$15860.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$15873.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$15901.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$15963.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$16044.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$16110.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$16126.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$16162.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$16172.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$16185.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$16192.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$16205.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$16233.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$16246.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$16256.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$16263.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$16276.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$16303.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$16319.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$16332.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$16348.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$16365.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$16377.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$16390.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$16400.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$16407.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$16420.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$16462.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$16478.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$16491.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$16498.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$16525.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$16541.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$16594.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$16610.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$16641.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$16705.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$16726.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$16736.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$16740.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$16762.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$16778.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$16791.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$16807.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$16840.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$16856.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$16932.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$16948.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$16979.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$17000.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$17010.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$17014.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$17036.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$17052.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$17065.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$17081.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$17114.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$17134.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$17150.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$17166.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$17179.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$17201.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$17214.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$17230.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$17252.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$17263.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$17279.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$17341.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$17422.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$17438.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$17451.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$17458.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$17468.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$17542.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$17558.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$17571.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$17593.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$17609.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$17622.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$17638.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$17660.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$17671.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$17682.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$17703.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$17713.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$17717.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$17739.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$17755.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$17768.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$17784.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$17817.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$17829.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$17890.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$17960.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$18038.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$18054.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$18094.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$18109.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$18119.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$18123.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$18145.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$18161.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$18174.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$18190.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$18223.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$7826.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$18241.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$18262.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$18272.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$18279.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$18298.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$18314.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$18327.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$18343.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$18365.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$18376.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$18391.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$18406.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$18422.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$18454.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$18540.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$18556.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$18589.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$18605.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$18621.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$18634.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$18656.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$18669.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$18685.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$18718.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$5983.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7671.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6255.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6323.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6329.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97841.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$6350.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7072.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97844.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$6385.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6406.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6420.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6439.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6453.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97821.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$6490.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6499.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$6490.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6520.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6540.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6540.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6549.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6554.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6566.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6606.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6610.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6628.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6628.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6592.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$6648.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6648.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6667.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6667.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6677.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6700.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6700.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6720.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6720.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6737.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6737.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6748.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$6762.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6762.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6782.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6810.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6810.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6827.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6831.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$6839.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$6853.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6880.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6908.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6908.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6925.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6929.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6937.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$6941.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6951.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97856.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$7126.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$7003.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7032.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7526.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7046.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6329.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6323.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7072.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7032.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7083.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7093.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7111.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7126.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$7153.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7175.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7200.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7232.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7257.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7279.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7287.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7309.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$7321.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7334.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$7348.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7367.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7385.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7398.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$7438.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7451.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$7466.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$7482.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7487.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97846.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97847.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$7543.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$7055.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7598.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7608.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7618.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7628.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7647.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7654.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7661.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7671.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7681.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7687.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7703.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7710.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7724.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$7751.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7761.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7771.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7781.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7800.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7807.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7814.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7822.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7836.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7847.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7858.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$7872.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7879.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7883.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7892.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$7902.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7912.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7912.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7926.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7937.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7945.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7960.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7970.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7983.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7998.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8013.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8054.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$8075.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8085.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8075.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8018.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8097.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8104.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8111.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8118.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8128.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8138.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8153.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8153.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7814.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8191.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$8209.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8238.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$8238.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$8247.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8253.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8266.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8276.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8276.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8289.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8289.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8300.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8328.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$8334.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$8341.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8348.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8348.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8375.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8385.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8385.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7937.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8406.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8442.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8448.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$8462.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8469.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8491.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7879.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8520.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8528.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$8537.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$8543.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$8565.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8575.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8588.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8617.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8628.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8640.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$8651.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8658.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$8673.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$8683.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8688.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$8688.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$7902.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8628.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8717.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8723.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8731.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8768.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$8768.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$8777.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8781.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8794.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8799.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$8808.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$8828.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$8828.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$8406.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8867.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$8876.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8893.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8901.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8906.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$8917.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7771.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7836.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8949.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8955.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$8520.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8588.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8971.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8990.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9002.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$9010.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97834.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$9071.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$9084.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$9107.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9114.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9139.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9150.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9159.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9186.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9196.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9233.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$9259.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$9275.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9290.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9304.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9304.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9315.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9322.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9334.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$8442.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9369.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9389.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9369.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9445.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$7175.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7279.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9196.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9507.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$9516.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9533.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$9547.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$9552.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9585.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9657.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9675.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9695.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9712.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9728.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9746.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9801.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9909.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$auto$fsm_map.cc:170:map_fsm$2191[2].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$auto$fsm_map.cc:170:map_fsm$2234[1].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$auto$opt_dff.cc:219:make_patterns_logic$2449.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97646.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97658.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97657.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97651.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97659.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97648.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97649.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97644.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97644.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97645.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97648.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97649.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97650.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97651.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97652.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97654.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97656.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97657.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8013.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8777.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97640.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97749.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97779.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97791.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97798.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97802.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$7438.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97806.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$7421.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$7287.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97816.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97817.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$7334.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$7321.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97824.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97825.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$7398.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97828.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$7367.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7309.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97837.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$7451.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$7466.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97850.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Removed 0 unused cells and 11165 unused wires.

21.45. Executing AUTONAME pass.
Renamed 299839 objects in module top (220 iterations).
<suppressed ~14189 debug messages>

21.46. Executing HIERARCHY pass (managing design hierarchy).

21.46.1. Analyzing design hierarchy..
Top module:  \top

21.46.2. Analyzing design hierarchy..
Top module:  \top
Removed 0 unused modules.

21.47. Printing statistics.

=== top ===

   Number of wires:               5906
   Number of wire bits:          16269
   Number of public wires:        5906
   Number of public wire bits:   16269
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:               9003
     $_TBUF_                         6
     CCU2C                         156
     L6MUX21                       448
     LUT4                         5436
     PFUMX                        1092
     TRELLIS_DPR16X4               512
     TRELLIS_FF                   1353

21.48. Executing CHECK pass (checking for obvious problems).
Checking module top...
Found and reported 0 problems.

21.49. Executing JSON backend.

Warnings: 226 unique messages, 227 total
End of script. Logfile hash: bb8caca09a, CPU: user 8.58s system 0.13s, MEM: 218.71 MB peak
Yosys 0.36+8 (git sha1 fb4cbfa73, clang 10.0.0-4ubuntu1 -fPIC -Os)
Time spent: 36% 1x abc9_exe (5 sec), 13% 11x techmap (1 sec), ...
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (NextPNR)
[Pipeline] sh
+ /eda/oss-cad-suite/bin/nextpnr-ecp5 --json ./build/out.json --write ./build/out_pnr.json --45k --lpf Risco-5/fpga/ecp5/pinout.lpf --textcfg ./build/out.config --package CABGA381 --speed 6 --ignore-loops --lpf-allow-unconstrained
Info: constraining clock net 'clk' to 25.00 MHz

Info: Logic utilisation before packing:
Info:     Total LUT4s:      8820/43848    20%
Info:         logic LUTs:   5436/43848    12%
Info:         carry LUTs:    312/43848     0%
Info:           RAM LUTs:   2048/ 5481    37%
Info:          RAMW LUTs:   1024/10962     9%

Info:      Total DFFs:      1353/43848     3%

Info: Packing IOs..
Info: $gpios[5]$iobuf_i: gpios_$_TBUF__Y.Y
Info: pin 'gpios[5]$tr_io' constrained to Bel 'X0/Y23/PIOC'.
Info: $gpios[4]$iobuf_i: gpios_$_TBUF__Y_1.Y
Info: pin 'gpios[4]$tr_io' constrained to Bel 'X0/Y44/PIOA'.
Info: $gpios[3]$iobuf_i: gpios_$_TBUF__Y_2.Y
Info: pin 'gpios[3]$tr_io' constrained to Bel 'X0/Y23/PIOA'.
Info: $gpios[2]$iobuf_i: gpios_$_TBUF__Y_3.Y
Info: pin 'gpios[2]$tr_io' constrained to Bel 'X90/Y23/PIOD'.
Info: $gpios[1]$iobuf_i: gpios_$_TBUF__Y_4.Y
Info: pin 'gpios[1]$tr_io' constrained to Bel 'X0/Y14/PIOD'.
Info: $gpios[0]$iobuf_i: gpios_$_TBUF__Y_5.Y
Info: pin 'gpios[0]$tr_io' constrained to Bel 'X0/Y44/PIOB'.
Info: pin 'tx$tr_io' constrained to Bel 'X90/Y20/PIOC'.
Info: pin 'rx$tr_io' constrained to Bel 'X90/Y20/PIOA'.
Info: pin 'reset$tr_io' constrained to Bel 'X0/Y29/PIOA'.
Info: pin 'led[7]$tr_io' constrained to Bel 'X90/Y20/PIOD'.
Info: pin 'led[6]$tr_io' constrained to Bel 'X0/Y44/PIOD'.
Info: pin 'led[5]$tr_io' constrained to Bel 'X0/Y59/PIOA'.
Info: pin 'led[4]$tr_io' constrained to Bel 'X15/Y71/PIOB'.
Info: pin 'led[3]$tr_io' constrained to Bel 'X90/Y29/PIOC'.
Info: pin 'led[2]$tr_io' constrained to Bel 'X90/Y44/PIOB'.
Info: pin 'led[1]$tr_io' constrained to Bel 'X0/Y44/PIOC'.
Info: pin 'led[0]$tr_io' constrained to Bel 'X0/Y59/PIOC'.
Info: pin 'clk$tr_io' constrained to Bel 'X0/Y68/PIOC'.
Info: Packing constants..
Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info:     309 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info: Promoting globals...
Info:     promoting clock net clk_o to global network
Info:     promoting clock net clk$TRELLIS_IO_IN to global network
Info: Checksum: 0x76590d4c

Info: Device utilisation:
Info: 	          TRELLIS_IO:    18/  245     7%
Info: 	                DCCA:     2/   56     3%
Info: 	              DP16KD:     0/  108     0%
Info: 	          MULT18X18D:     0/   72     0%
Info: 	              ALU54B:     0/   36     0%
Info: 	             EHXPLLL:     0/    4     0%
Info: 	             EXTREFB:     0/    2     0%
Info: 	                DCUA:     0/    2     0%
Info: 	           PCSCLKDIV:     0/    2     0%
Info: 	             IOLOGIC:     0/  160     0%
Info: 	            SIOLOGIC:     0/   85     0%
Info: 	                 GSR:     0/    1     0%
Info: 	               JTAGG:     0/    1     0%
Info: 	                OSCG:     0/    1     0%
Info: 	               SEDGA:     0/    1     0%
Info: 	                 DTR:     0/    1     0%
Info: 	             USRMCLK:     0/    1     0%
Info: 	             CLKDIVF:     0/    4     0%
Info: 	           ECLKSYNCB:     0/   10     0%
Info: 	             DLLDELD:     0/    8     0%
Info: 	              DDRDLL:     0/    4     0%
Info: 	             DQSBUFM:     0/   10     0%
Info: 	     TRELLIS_ECLKBUF:     0/    8     0%
Info: 	        ECLKBRIDGECS:     0/    2     0%
Info: 	                DCSC:     0/    2     0%
Info: 	          TRELLIS_FF:  1353/43848     3%
Info: 	        TRELLIS_COMB:  8884/43848    20%
Info: 	        TRELLIS_RAMW:   512/ 5481     9%

Info: Placed 18 cells based on constraints.
Info: Creating initial analytic placement for 5474 cells, random placement wirelen = 454857.
Info:     at initial placer iter 0, wirelen = 2052
Info:     at initial placer iter 1, wirelen = 2122
Info:     at initial placer iter 2, wirelen = 1752
Info:     at initial placer iter 3, wirelen = 1925
Info: Running main analytical placer, max placement attempts per cell = 14496420.
Info:     at iteration #1, type ALL: wirelen solved = 1919, spread = 67888, legal = 68703; time = 0.27s
Info:     at iteration #2, type ALL: wirelen solved = 8717, spread = 45061, legal = 46305; time = 0.27s
Info:     at iteration #3, type ALL: wirelen solved = 13098, spread = 43964, legal = 45055; time = 0.26s
Info:     at iteration #4, type ALL: wirelen solved = 16419, spread = 40981, legal = 42094; time = 0.26s
Info:     at iteration #5, type ALL: wirelen solved = 18783, spread = 42884, legal = 43851; time = 0.25s
Info:     at iteration #6, type ALL: wirelen solved = 20818, spread = 39285, legal = 40221; time = 0.25s
Info:     at iteration #7, type ALL: wirelen solved = 21820, spread = 37495, legal = 39091; time = 0.25s
Info:     at iteration #8, type ALL: wirelen solved = 21133, spread = 38510, legal = 39737; time = 0.25s
Info:     at iteration #9, type ALL: wirelen solved = 22777, spread = 37841, legal = 39201; time = 0.24s
Info:     at iteration #10, type ALL: wirelen solved = 23017, spread = 37761, legal = 39108; time = 0.24s
Info:     at iteration #11, type ALL: wirelen solved = 23693, spread = 37074, legal = 38564; time = 0.24s
Info:     at iteration #12, type ALL: wirelen solved = 23689, spread = 36726, legal = 38046; time = 0.24s
Info:     at iteration #13, type ALL: wirelen solved = 23961, spread = 40823, legal = 41467; time = 0.24s
Info:     at iteration #14, type ALL: wirelen solved = 27226, spread = 40938, legal = 41632; time = 0.24s
Info:     at iteration #15, type ALL: wirelen solved = 28233, spread = 40008, legal = 40873; time = 0.23s
Info:     at iteration #16, type ALL: wirelen solved = 27412, spread = 38748, legal = 39818; time = 0.23s
Info:     at iteration #17, type ALL: wirelen solved = 26593, spread = 42682, legal = 43176; time = 0.24s
Info: HeAP Placer Time: 6.81s
Info:   of which solving equations: 4.07s
Info:   of which spreading cells: 0.58s
Info:   of which strict legalisation: 0.18s

Info: Running simulated annealing placer for refinement.
Info:   at iteration #1: temp = 0.000000, timing cost = 10599, wirelen = 38046
Info:   at iteration #5: temp = 0.000000, timing cost = 12616, wirelen = 33165
Info:   at iteration #10: temp = 0.000000, timing cost = 11538, wirelen = 31728
Info:   at iteration #15: temp = 0.000000, timing cost = 11383, wirelen = 30844
Info:   at iteration #20: temp = 0.000000, timing cost = 10836, wirelen = 30368
Info:   at iteration #25: temp = 0.000000, timing cost = 11888, wirelen = 30216
Info:   at iteration #30: temp = 0.000000, timing cost = 12111, wirelen = 30149
Info:   at iteration #31: temp = 0.000000, timing cost = 11891, wirelen = 30132 
Info: SA placement time 30.47s

Info: Max frequency for clock             '$glbnet$clk_o': 28.53 MHz (PASS at 12.00 MHz)
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 146.33 MHz (PASS at 25.00 MHz)

Info: Max delay <async>                           -> posedge $glbnet$clk$TRELLIS_IO_IN: 12.18 ns
Info: Max delay <async>                           -> posedge $glbnet$clk_o            : 11.44 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async>                          : 10.84 ns
Info: Max delay posedge $glbnet$clk_o             -> <async>                          : 15.40 ns

Info: Slack histogram:
Info:  legend: * represents 102 endpoint(s)
Info:          + represents [1,102) endpoint(s)
Info: [ 33166,  35637) |+
Info: [ 35637,  38108) |+
Info: [ 38108,  40579) |+
Info: [ 40579,  43050) | 
Info: [ 43050,  45521) | 
Info: [ 45521,  47992) | 
Info: [ 47992,  50463) |+
Info: [ 50463,  52934) |+
Info: [ 52934,  55405) |+
Info: [ 55405,  57876) |+
Info: [ 57876,  60347) |*************+
Info: [ 60347,  62818) |************************************************************ 
Info: [ 62818,  65289) |******************************************+
Info: [ 65289,  67760) |*****+
Info: [ 67760,  70231) |**+
Info: [ 70231,  72702) |**********+
Info: [ 72702,  75173) |*******+
Info: [ 75173,  77644) |**+
Info: [ 77644,  80115) |*+
Info: [ 80115,  82586) |+
Info: Checksum: 0x42af33bb
Info: Routing globals...
Info:     routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
Info:     routing clock net $glbnet$clk_o using global 1

Info: Routing..
Info: Setting up routing queue.
Info: Routing 42922 arcs.
Info:            |   (re-)routed arcs  |   delta    | remaining|       time spent     |
Info:    IterCnt |  w/ripup   wo/ripup |  w/r  wo/r |      arcs| batch(sec) total(sec)|
Info:       1000 |      219        780 |  219   780 |     42411|       0.65       0.65|
Info:       2000 |      493       1506 |  274   726 |     42075|       0.17       0.83|
Info:       3000 |      667       2332 |  174   826 |     41706|       0.15       0.98|
Info:       4000 |      863       3136 |  196   804 |     41509|       0.15       1.12|
Info:       5000 |     1042       3957 |  179   821 |     41635|       0.15       1.27|
Info:       6000 |     1243       4756 |  201   799 |     41376|       0.18       1.45|
Info:       7000 |     1413       5586 |  170   830 |     40781|       0.16       1.61|
Info:       8000 |     1590       6409 |  177   823 |     40571|       0.17       1.78|
Info:       9000 |     1785       7214 |  195   805 |     40230|       0.16       1.94|
Info:      10000 |     2044       7955 |  259   741 |     40248|       0.17       2.10|
Info:      11000 |     2218       8781 |  174   826 |     40105|       0.14       2.25|
Info:      12000 |     2406       9593 |  188   812 |     39761|       0.16       2.41|
Info:      13000 |     2635      10364 |  229   771 |     39385|       0.16       2.57|
Info:      14000 |     2784      11215 |  149   851 |     39038|       0.18       2.75|
Info:      15000 |     2908      12091 |  124   876 |     38898|       0.17       2.91|
Info:      16000 |     3153      12846 |  245   755 |     38583|       0.17       3.08|
Info:      17000 |     3340      13659 |  187   813 |     38226|       0.18       3.26|
Info:      18000 |     3476      14523 |  136   864 |     38201|       0.15       3.41|
Info:      19000 |     3578      15421 |  102   898 |     37777|       0.15       3.56|
Info:      20000 |     3750      16249 |  172   828 |     37463|       0.17       3.73|
Info:      21000 |     3923      17076 |  173   827 |     36898|       0.16       3.89|
Info:      22000 |     4099      17900 |  176   824 |     36568|       0.19       4.08|
Info:      23000 |     4316      18683 |  217   783 |     36080|       0.17       4.26|
Info:      24000 |     4481      19518 |  165   835 |     35886|       0.15       4.41|
Info:      25000 |     4564      20435 |   83   917 |     35642|       0.15       4.55|
Info:      26000 |     4747      21252 |  183   817 |     35381|       0.16       4.72|
Info:      27000 |     4888      22111 |  141   859 |     35150|       0.17       4.88|
Info:      28000 |     5077      22922 |  189   811 |     34808|       0.17       5.05|
Info:      29000 |     5297      23702 |  220   780 |     34456|       0.18       5.24|
Info:      30000 |     5439      24560 |  142   858 |     34481|       0.19       5.43|
Info:      31000 |     5604      25395 |  165   835 |     34209|       0.19       5.62|
Info:      32000 |     5825      26174 |  221   779 |     33798|       0.18       5.80|
Info:      33000 |     6040      26959 |  215   785 |     33513|       0.19       5.98|
Info:      34000 |     6296      27703 |  256   744 |     33258|       0.18       6.17|
Info:      35000 |     6541      28458 |  245   755 |     32776|       0.19       6.36|
Info:      36000 |     6744      29255 |  203   797 |     32321|       0.17       6.53|
Info:      37000 |     6958      30041 |  214   786 |     31977|       0.20       6.73|
Info:      38000 |     7122      30877 |  164   836 |     31854|       0.17       6.90|
Info:      39000 |     7367      31632 |  245   755 |     31577|       0.18       7.07|
Info:      40000 |     7545      32454 |  178   822 |     31492|       0.18       7.25|
Info:      41000 |     7710      33289 |  165   835 |     31251|       0.20       7.45|
Info:      42000 |     7832      34167 |  122   878 |     31335|       0.19       7.64|
Info:      43000 |     8075      34924 |  243   757 |     30961|       0.20       7.85|
Info:      44000 |     8310      35689 |  235   765 |     30629|       0.21       8.05|
Info:      45000 |     8412      36587 |  102   898 |     30543|       0.16       8.21|
Info:      46000 |     8565      37434 |  153   847 |     30404|       0.19       8.40|
Info:      47000 |     8843      38156 |  278   722 |     30121|       0.20       8.60|
Info:      48000 |     8992      39007 |  149   851 |     30280|       0.19       8.79|
Info:      49000 |     9000      39999 |    8   992 |     30332|       0.15       8.95|
Info:      50000 |     9184      40815 |  184   816 |     29845|       0.20       9.15|
Info:      51000 |     9445      41554 |  261   739 |     29426|       0.20       9.35|
Info:      52000 |     9696      42303 |  251   749 |     28995|       0.20       9.54|
Info:      53000 |     9943      43056 |  247   753 |     28631|       0.20       9.74|
Info:      54000 |    10197      43802 |  254   746 |     28262|       0.20       9.94|
Info:      55000 |    10484      44515 |  287   713 |     27988|       0.25      10.19|
Info:      56000 |    10691      45308 |  207   793 |     27793|       0.20      10.39|
Info:      57000 |    10981      46018 |  290   710 |     27513|       0.23      10.62|
Info:      58000 |    11189      46810 |  208   792 |     27347|       0.23      10.85|
Info:      59000 |    11296      47703 |  107   893 |     27255|       0.20      11.04|
Info:      60000 |    11596      48403 |  300   700 |     26846|       0.21      11.25|
Info:      61000 |    11915      49084 |  319   681 |     26462|       0.22      11.48|
Info:      62000 |    12108      49891 |  193   807 |     26442|       0.19      11.67|
Info:      63000 |    12358      50641 |  250   750 |     26167|       0.22      11.89|
Info:      64000 |    12637      51362 |  279   721 |     25835|       0.23      12.12|
Info:      65000 |    12928      52071 |  291   709 |     25417|       0.24      12.36|
Info:      66000 |    13197      52802 |  269   731 |     25647|       0.24      12.60|
Info:      67000 |    13294      53705 |   97   903 |     25167|       0.20      12.80|
Info:      68000 |    13584      54415 |  290   710 |     24954|       0.26      13.06|
Info:      69000 |    13871      55128 |  287   713 |     24578|       0.22      13.28|
Info:      70000 |    14163      55836 |  292   708 |     24924|       0.24      13.53|
Info:      71000 |    14279      56720 |  116   884 |     24378|       0.19      13.72|
Info:      72000 |    14557      57442 |  278   722 |     24282|       0.23      13.94|
Info:      73000 |    14898      58101 |  341   659 |     24021|       0.26      14.20|
Info:      74000 |    15215      58784 |  317   683 |     23737|       0.24      14.45|
Info:      75000 |    15419      59580 |  204   796 |     23750|       0.26      14.70|
Info:      76000 |    15744      60255 |  325   675 |     23375|       0.24      14.94|
Info:      77000 |    15979      61020 |  235   765 |     23171|       0.24      15.18|
Info:      78000 |    16288      61711 |  309   691 |     23005|       0.25      15.44|
Info:      79000 |    16508      62491 |  220   780 |     23242|       0.25      15.68|
Info:      80000 |    16627      63372 |  119   881 |     22929|       0.22      15.90|
Info:      81000 |    16967      64032 |  340   660 |     22835|       0.28      16.19|
Info:      82000 |    17216      64783 |  249   751 |     22587|       0.21      16.39|
Info:      83000 |    17575      65424 |  359   641 |     22215|       0.24      16.64|
Info:      84000 |    17981      66018 |  406   594 |     21859|       0.24      16.87|
Info:      85000 |    18369      66630 |  388   612 |     21468|       0.23      17.11|
Info:      86000 |    18684      67315 |  315   685 |     21264|       0.24      17.35|
Info:      87000 |    18896      68103 |  212   788 |     21776|       0.23      17.58|
Info:      88000 |    18967      69032 |   71   929 |     21671|       0.20      17.77|
Info:      89000 |    19160      69839 |  193   807 |     21573|       0.22      17.99|
Info:      90000 |    19379      70620 |  219   781 |     21129|       0.24      18.23|
Info:      91000 |    19713      71286 |  334   666 |     20797|       0.24      18.47|
Info:      92000 |    20064      71935 |  351   649 |     20617|       0.25      18.72|
Info:      93000 |    20455      72544 |  391   609 |     20285|       0.26      18.98|
Info:      94000 |    20911      73088 |  456   544 |     20103|       0.25      19.23|
Info:      95000 |    21360      73639 |  449   551 |     19845|       0.25      19.48|
Info:      96000 |    21857      74142 |  497   503 |     19621|       0.24      19.72|
Info:      97000 |    22048      74951 |  191   809 |     19586|       0.22      19.94|
Info:      98000 |    22457      75542 |  409   591 |     19366|       0.25      20.19|
Info:      99000 |    22869      76130 |  412   588 |     19163|       0.26      20.45|
Info:     100000 |    23276      76723 |  407   593 |     19601|       0.24      20.69|
Info:     101000 |    23613      77386 |  337   663 |     20023|       0.23      20.92|
Info:     102000 |    23865      78134 |  252   748 |     19690|       0.25      21.16|
Info:     103000 |    24134      78865 |  269   731 |     19234|       0.26      21.42|
Info:     104000 |    24524      79475 |  390   610 |     19032|       0.26      21.68|
Info:     105000 |    24953      80046 |  429   571 |     18819|       0.27      21.95|
Info:     106000 |    25408      80591 |  455   545 |     18557|       0.29      22.24|
Info:     107000 |    25837      81162 |  429   571 |     18360|       0.28      22.51|
Info:     108000 |    26290      81709 |  453   547 |     18149|       0.28      22.79|
Info:     109000 |    26844      82155 |  554   446 |     18021|       0.27      23.06|
Info:     110000 |    27212      82787 |  368   632 |     17907|       0.26      23.32|
Info:     111000 |    27740      83259 |  528   472 |     17710|       0.27      23.60|
Info:     112000 |    28343      83656 |  603   397 |     17496|       0.25      23.85|
Info:     113000 |    28911      84088 |  568   432 |     17320|       0.25      24.10|
Info:     114000 |    29444      84555 |  533   467 |     17120|       0.25      24.36|
Info:     115000 |    30010      84989 |  566   434 |     16913|       0.26      24.62|
Info:     116000 |    30547      85452 |  537   463 |     16702|       0.25      24.87|
Info:     117000 |    30988      86011 |  441   559 |     16644|       0.25      25.13|
Info:     118000 |    31500      86499 |  512   488 |     16534|       0.27      25.40|
Info:     119000 |    32006      86993 |  506   494 |     16427|       0.28      25.68|
Info:     120000 |    32508      87491 |  502   498 |     16342|       0.27      25.94|
Info:     121000 |    32758      88241 |  250   750 |     16203|       0.26      26.21|
Info:     122000 |    33185      88814 |  427   573 |     15998|       0.27      26.48|
Info:     123000 |    33613      89386 |  428   572 |     15915|       0.28      26.76|
Info:     124000 |    34124      89875 |  511   489 |     15744|       0.28      27.04|
Info:     125000 |    34538      90438 |  414   563 |     15627|       0.27      27.31|
Info:     126000 |    34948      91008 |  410   570 |     15480|       0.30      27.61|
Info:     127000 |    35481      91440 |  533   432 |     15239|       0.26      27.87|
Info:     128000 |    36007      91885 |  526   445 |     15049|       0.28      28.15|
Info:     129000 |    36548      92303 |  541   418 |     14848|       0.26      28.41|
Info:     130000 |    37137      92663 |  589   360 |     14578|       0.26      28.67|
Info:     131000 |    37694      93032 |  557   369 |     14201|       0.23      28.91|
Info:     132000 |    38192      93457 |  498   425 |     13886|       0.24      29.14|
Info:     133000 |    38769      93819 |  577   362 |     13616|       0.25      29.40|
Info:     134000 |    39399      94144 |  630   325 |     13380|       0.26      29.65|
Info:     135000 |    39850      94667 |  451   523 |     13239|       0.25      29.91|
Info:     136000 |    40370      95115 |  520   448 |     13102|       0.27      30.17|
Info:     137000 |    40911      95515 |  541   400 |     12735|       0.25      30.42|
Info:     138000 |    41359      96037 |  448   522 |     12538|       0.33      30.75|
Info:     139000 |    41717      96561 |  358   524 |     11946|       0.21      30.96|
Info:     140000 |    42017      97182 |  300   621 |     11684|       0.27      31.23|
Info:     141000 |    42444      97750 |  427   568 |     11464|       0.33      31.56|
Info:     142000 |    42699      98477 |  255   727 |     10908|       0.22      31.78|
Info:     143000 |    42835      99330 |  136   853 |     10180|       0.17      31.95|
Info:     144000 |    42970     100192 |  135   862 |      9484|       0.17      32.11|
Info:     145000 |    43002     101156 |   32   964 |      8517|       0.09      32.20|
Info:     146000 |    43038     102118 |   36   962 |      7563|       0.10      32.30|
Info:     147000 |    43074     103077 |   36   959 |      6637|       0.11      32.41|
Info:     148000 |    43152     103990 |   78   913 |      5731|       0.11      32.52|
Info:     149000 |    43268     104870 |  116   880 |      4891|       0.15      32.68|
Info:     150000 |    43524     105612 |  256   742 |      4386|       0.22      32.90|
Info:     151000 |    43766     106346 |  242   734 |      3788|       0.22      33.12|
Info:     152000 |    44116     106993 |  350   647 |      3409|       0.31      33.43|
Info:     153000 |    44518     107575 |  402   582 |      3191|       0.35      33.79|
Info:     154000 |    44930     108152 |  412   577 |      3022|       0.37      34.15|
Info:     155000 |    45384     108684 |  454   532 |      2719|       0.35      34.50|
Info:     156000 |    45830     109230 |  446   546 |      2272|       0.28      34.78|
Info:     157000 |    46237     109814 |  407   584 |      1857|       0.31      35.09|
Info:     158000 |    46683     110364 |  446   550 |      1581|       0.38      35.47|
Info:     159000 |    47119     110926 |  436   562 |      1187|       0.31      35.78|
Info:     160000 |    47707     111338 |  588   412 |       903|       0.38      36.16|
Info:     161000 |    48272     111758 |  565   420 |       610|       0.38      36.54|
Info:     161763 |    48377     112110 |  105   352 |         0|       0.19      36.73|
Info: Routing complete.
Info: Router1 time 36.73s
Info: Checksum: 0xa37f1f53

Info: Critical path report for clock '$glbnet$clk_o' (posedge -> posedge):
Info: curr total
Info:  0.5  0.5  Source SOC.Core.Control_Unit.state_TRELLIS_FF_Q_3.Q
Info:  1.0  1.5    Net SOC.Core.Control_Unit.nextstate_LUT4_Z_C[3] (38,17) -> (38,17)
Info:                Sink SOC.Memory.address_LUT4_Z_C_LUT4_Z_D_LUT4_Z.D
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:42.3-49.2
Info:                  Risco-5/src/core/core.v:97.14-114.2
Info:                  Risco-5/src/core/control_unit.v:48.11-48.16
Info:                  Risco-5/src/peripheral/soc.v:28.3-36.2
Info:  0.2  1.7  Source SOC.Memory.address_LUT4_Z_C_LUT4_Z_D_LUT4_Z.F
Info:  1.6  3.4    Net SOC.Memory.address_LUT4_Z_C_LUT4_Z_D[2] (38,17) -> (29,9)
Info:                Sink SOC.Memory.memory.0.323_DO_LUT4_C_Z_LUT4_Z_B_CCU2C_B0_COUT_CCU2C_CIN_B1_LUT4_Z.D
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2  3.6  Source SOC.Memory.memory.0.323_DO_LUT4_C_Z_LUT4_Z_B_CCU2C_B0_COUT_CCU2C_CIN_B1_LUT4_Z.F
Info:  2.0  5.6    Net SOC.Memory.memory.0.323_DO_LUT4_C_Z_LUT4_Z_B_CCU2C_B0_COUT_CCU2C_CIN_B1 (29,9) -> (41,16)
Info:                Sink SOC.Memory.memory.0.323_DO_LUT4_C_Z_LUT4_Z_B_CCU2C_B0_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB1.B
Info:  0.4  6.1  Source SOC.Memory.memory.0.323_DO_LUT4_C_Z_LUT4_Z_B_CCU2C_B0_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB1.FCO
Info:  0.0  6.1    Net SOC.Memory.memory.0.323_DO_LUT4_C_Z_LUT4_Z_B_CCU2C_B0_COUT_CCU2C_CIN_B0_CCU2C_B0_COUT (41,16) -> (41,16)
Info:                Sink SOC.Memory.memory.0.323_DO_LUT4_C_Z_LUT4_Z_B_CCU2C_B0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:42.3-49.2
Info:                  Risco-5/src/peripheral/bus.v:54.5-54.37
Info:                  Risco-5/src/peripheral/soc.v:51.5-81.2
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  6.1  Source SOC.Memory.memory.0.323_DO_LUT4_C_Z_LUT4_Z_B_CCU2C_B0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB0.FCO
Info:  0.0  6.1    Net SOC.Memory.memory.0.323_DO_LUT4_C_Z_LUT4_Z_B_CCU2C_B0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_FCI_INT (41,16) -> (41,16)
Info:                Sink SOC.Memory.memory.0.323_DO_LUT4_C_Z_LUT4_Z_B_CCU2C_B0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB1.FCI
Info:  0.0  6.1  Source SOC.Memory.memory.0.323_DO_LUT4_C_Z_LUT4_Z_B_CCU2C_B0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB1.FCO
Info:  0.0  6.1    Net SOC.Memory.memory.0.323_DO_LUT4_C_Z_LUT4_Z_B_CCU2C_B0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0_COUT (41,16) -> (41,16)
Info:                Sink SOC.Memory.memory.0.323_DO_LUT4_C_Z_LUT4_Z_B_CCU2C_B0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:42.3-49.2
Info:                  Risco-5/src/peripheral/bus.v:54.5-54.37
Info:                  Risco-5/src/peripheral/soc.v:51.5-81.2
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  6.2  Source SOC.Memory.memory.0.323_DO_LUT4_C_Z_LUT4_Z_B_CCU2C_B0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB0.FCO
Info:  0.0  6.2    Net SOC.Memory.memory.0.323_DO_LUT4_C_Z_LUT4_Z_B_CCU2C_B0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_FCI_INT (41,16) -> (41,16)
Info:                Sink SOC.Memory.memory.0.323_DO_LUT4_C_Z_LUT4_Z_B_CCU2C_B0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB1.FCI
Info:  0.0  6.2  Source SOC.Memory.memory.0.323_DO_LUT4_C_Z_LUT4_Z_B_CCU2C_B0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB1.FCO
Info:  0.0  6.2    Net SOC.Memory.memory.0.323_DO_LUT4_C_Z_LUT4_Z_B_CCU2C_B0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0_COUT (41,16) -> (42,16)
Info:                Sink SOC.Memory.memory.0.323_DO_LUT4_C_Z_LUT4_Z_B_CCU2C_B0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:42.3-49.2
Info:                  Risco-5/src/peripheral/bus.v:54.5-54.37
Info:                  Risco-5/src/peripheral/soc.v:51.5-81.2
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  6.3  Source SOC.Memory.memory.0.323_DO_LUT4_C_Z_LUT4_Z_B_CCU2C_B0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB0.FCO
Info:  0.0  6.3    Net SOC.Memory.memory.0.323_DO_LUT4_C_Z_LUT4_Z_B_CCU2C_B0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_FCI_INT (42,16) -> (42,16)
Info:                Sink SOC.Memory.memory.0.323_DO_LUT4_C_Z_LUT4_Z_B_CCU2C_B0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB1.FCI
Info:  0.0  6.3  Source SOC.Memory.memory.0.323_DO_LUT4_C_Z_LUT4_Z_B_CCU2C_B0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB1.FCO
Info:  0.0  6.3    Net SOC.Memory.memory.0.323_DO_LUT4_C_Z_LUT4_Z_B_CCU2C_B0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0_COUT (42,16) -> (42,16)
Info:                Sink SOC.Memory.memory.0.323_DO_LUT4_C_Z_LUT4_Z_B_CCU2C_B0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:42.3-49.2
Info:                  Risco-5/src/peripheral/bus.v:54.5-54.37
Info:                  Risco-5/src/peripheral/soc.v:51.5-81.2
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  6.3  Source SOC.Memory.memory.0.323_DO_LUT4_C_Z_LUT4_Z_B_CCU2C_B0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB0.FCO
Info:  0.0  6.3    Net SOC.Memory.memory.0.323_DO_LUT4_C_Z_LUT4_Z_B_CCU2C_B0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_FCI_INT (42,16) -> (42,16)
Info:                Sink SOC.Memory.memory.0.323_DO_LUT4_C_Z_LUT4_Z_B_CCU2C_B0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB1.FCI
Info:  0.0  6.3  Source SOC.Memory.memory.0.323_DO_LUT4_C_Z_LUT4_Z_B_CCU2C_B0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB1.FCO
Info:  0.0  6.3    Net SOC.Memory.memory.0.323_DO_LUT4_C_Z_LUT4_Z_B_CCU2C_B0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0_COUT (42,16) -> (42,16)
Info:                Sink SOC.Memory.memory.0.323_DO_LUT4_C_Z_LUT4_Z_B_CCU2C_B0_2_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:42.3-49.2
Info:                  Risco-5/src/peripheral/bus.v:54.5-54.37
Info:                  Risco-5/src/peripheral/soc.v:51.5-81.2
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  6.4  Source SOC.Memory.memory.0.323_DO_LUT4_C_Z_LUT4_Z_B_CCU2C_B0_2_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB0.FCO
Info:  0.0  6.4    Net SOC.Memory.memory.0.323_DO_LUT4_C_Z_LUT4_Z_B_CCU2C_B0_2_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_FCI_INT (42,16) -> (42,16)
Info:                Sink SOC.Memory.memory.0.323_DO_LUT4_C_Z_LUT4_Z_B_CCU2C_B0_2_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB1.FCI
Info:  0.0  6.4  Source SOC.Memory.memory.0.323_DO_LUT4_C_Z_LUT4_Z_B_CCU2C_B0_2_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB1.FCO
Info:  0.0  6.4    Net SOC.Memory.memory.0.323_DO_LUT4_C_Z_LUT4_Z_B_CCU2C_B0_2_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0_COUT (42,16) -> (42,16)
Info:                Sink SOC.Core.ALU_Control.aluop_out_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z_C_LUT4_D_Z_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:42.3-49.2
Info:                  Risco-5/src/peripheral/bus.v:54.5-54.37
Info:                  Risco-5/src/peripheral/soc.v:51.5-81.2
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  6.5  Source SOC.Core.ALU_Control.aluop_out_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z_C_LUT4_D_Z_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info:  0.0  6.5    Net SOC.Core.ALU_Control.aluop_out_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z_C_LUT4_D_Z_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (42,16) -> (42,16)
Info:                Sink SOC.Core.ALU_Control.aluop_out_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z_C_LUT4_D_Z_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info:  0.0  6.5  Source SOC.Core.ALU_Control.aluop_out_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z_C_LUT4_D_Z_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info:  0.0  6.5    Net SOC.Core.ALU_Control.aluop_out_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z_C_LUT4_D_Z_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_COUT (42,16) -> (43,16)
Info:                Sink SOC.Core.ALU_Control.aluop_out_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z_C_LUT4_D_Z_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:42.3-49.2
Info:                  Risco-5/src/peripheral/bus.v:54.5-54.37
Info:                  Risco-5/src/peripheral/soc.v:51.5-81.2
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  6.5  Source SOC.Core.ALU_Control.aluop_out_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z_C_LUT4_D_Z_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info:  0.0  6.5    Net SOC.Core.ALU_Control.aluop_out_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z_C_LUT4_D_Z_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (43,16) -> (43,16)
Info:                Sink SOC.Core.ALU_Control.aluop_out_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z_C_LUT4_D_Z_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info:  0.0  6.5  Source SOC.Core.ALU_Control.aluop_out_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z_C_LUT4_D_Z_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info:  0.0  6.5    Net SOC.Core.ALU_Control.aluop_out_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z_C_LUT4_D_Z_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_COUT (43,16) -> (43,16)
Info:                Sink SOC.Core.ALU_Control.aluop_out_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z_C_LUT4_D_Z_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:42.3-49.2
Info:                  Risco-5/src/peripheral/bus.v:54.5-54.37
Info:                  Risco-5/src/peripheral/soc.v:51.5-81.2
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  6.6  Source SOC.Core.ALU_Control.aluop_out_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z_C_LUT4_D_Z_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info:  0.0  6.6    Net SOC.Core.ALU_Control.aluop_out_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z_C_LUT4_D_Z_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (43,16) -> (43,16)
Info:                Sink SOC.Core.ALU_Control.aluop_out_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z_C_LUT4_D_Z_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info:  0.0  6.6  Source SOC.Core.ALU_Control.aluop_out_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z_C_LUT4_D_Z_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info:  0.0  6.6    Net SOC.Core.ALU_Control.aluop_out_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z_C_LUT4_D_Z_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_COUT (43,16) -> (43,16)
Info:                Sink SOC.Core.ALU_Control.aluop_out_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z_C_LUT4_D_Z_LUT4_Z_C_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:42.3-49.2
Info:                  Risco-5/src/peripheral/bus.v:54.5-54.37
Info:                  Risco-5/src/peripheral/soc.v:51.5-81.2
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  6.7  Source SOC.Core.ALU_Control.aluop_out_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z_C_LUT4_D_Z_LUT4_Z_C_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info:  0.0  6.7    Net SOC.Core.ALU_Control.aluop_out_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z_C_LUT4_D_Z_LUT4_Z_C_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (43,16) -> (43,16)
Info:                Sink SOC.Core.ALU_Control.aluop_out_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z_C_LUT4_D_Z_LUT4_Z_C_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info:  0.0  6.7  Source SOC.Core.ALU_Control.aluop_out_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z_C_LUT4_D_Z_LUT4_Z_C_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info:  0.0  6.7    Net $nextpnr_CCU2C_19$CIN (43,16) -> (43,16)
Info:                Sink $nextpnr_CCU2C_19$CCU2_COMB0.FCI
Info:  0.4  7.1  Source $nextpnr_CCU2C_19$CCU2_COMB0.F
Info:  2.8  9.9    Net SOC.Memory.address_LUT4_Z_1_C[1] (43,16) -> (14,25)
Info:                Sink SOC.Memory.address_LUT4_Z_2.D
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2 10.1  Source SOC.Memory.address_LUT4_Z_2.F
Info:  2.9 13.0    Net SOC.slave_address[3] (14,25) -> (5,5)
Info:                Sink SOC.Memory.memory.0.414$DPRAM_COMB2.B
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:42.3-49.2
Info:                  Risco-5/src/peripheral/soc.v:21.5-21.18
Info:  0.2 13.3  Source SOC.Memory.memory.0.414$DPRAM_COMB2.F
Info:  1.1 14.4    Net SOC.Memory.memory.0.414_DO_1[3] (5,5) -> (4,6)
Info:                Sink SOC.Memory.memory.0.390_DO_1_LUT4_Z_1.D
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2 14.6  Source SOC.Memory.memory.0.390_DO_1_LUT4_Z_1.F
Info:  0.7 15.3    Net SOC.Memory.memory.0.390_DO_1[4] (4,6) -> (4,7)
Info:                Sink SOC.Memory.memory.0.446_DO_PFUMX_Z_BLUT_LUT4_Z.M
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.3 15.6  Source SOC.Memory.memory.0.446_DO_PFUMX_Z_BLUT_LUT4_Z.OFX
Info:  0.8 16.4    Net SOC.Memory.memory.0.446_DO[3] (4,7) -> (4,8)
Info:                Sink SOC.Memory.memory.0.446_DO_LUT4_B.D
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2 16.7  Source SOC.Memory.memory.0.446_DO_LUT4_B.F
Info:  0.9 17.5    Net SOC.Core.read_data_LUT4_Z_24_D_LUT4_Z_C_PFUMX_Z_C0[1] (4,8) -> (6,8)
Info:                Sink SOC.Core.read_data_LUT4_Z_24_D_LUT4_Z_C_PFUMX_Z_ALUT_LUT4_Z.C
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2 17.8  Source SOC.Core.read_data_LUT4_Z_24_D_LUT4_Z_C_PFUMX_Z_ALUT_LUT4_Z.F
Info:  0.0 17.8    Net SOC.Core.read_data_LUT4_Z_24_D_LUT4_Z_C_PFUMX_Z_ALUT (6,8) -> (6,8)
Info:                Sink SOC.Core.read_data_LUT4_Z_24_D_LUT4_Z_C_PFUMX_Z_BLUT_LUT4_Z.F1
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:133.22-133.24
Info:  0.2 17.9  Source SOC.Core.read_data_LUT4_Z_24_D_LUT4_Z_C_PFUMX_Z_BLUT_LUT4_Z.OFX
Info:  1.0 18.9    Net SOC.Core.read_data_LUT4_Z_24_D_LUT4_Z_C[1] (6,8) -> (11,9)
Info:                Sink SOC.Core.read_data_LUT4_Z_24_D_LUT4_Z.C
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2 19.2  Source SOC.Core.read_data_LUT4_Z_24_D_LUT4_Z.F
Info:  1.8 21.0    Net SOC.Core.read_data_LUT4_Z_24_D[3] (11,9) -> (27,11)
Info:                Sink SOC.Core.read_data_LUT4_Z_24.D
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2 21.2  Source SOC.Core.read_data_LUT4_Z_24.F
Info:  1.0 22.2    Net SOC.read_data[26] (27,11) -> (28,14)
Info:                Sink SOC.Core.instruction_register_TRELLIS_FF_Q_5.M
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:42.3-49.2
Info:                  Risco-5/src/peripheral/soc.v:20.34-20.43
Info:  0.0 22.2  Setup SOC.Core.instruction_register_TRELLIS_FF_Q_5.M
Info: 4.6 ns logic, 17.6 ns routing

Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
Info: curr total
Info:  0.5  0.5  Source ClkDivider.clk_counter_TRELLIS_FF_Q_27.Q
Info:  1.2  1.7    Net ClkDivider.clk_counter[4] (47,3) -> (48,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.B
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:15.3-23.2
Info:                  Risco-5/debug/clk_divider.v:14.26-14.37
Info:  0.4  2.1  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info:  0.0  2.1    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (48,2) -> (48,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info:  0.0  2.1  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info:  0.0  2.1    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (48,2) -> (48,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:15.3-23.2
Info:                  Risco-5/debug/clk_divider.v:40.12-40.38
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  2.2  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info:  0.0  2.2    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (48,2) -> (48,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info:  0.0  2.2  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info:  0.0  2.2    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (48,2) -> (48,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:15.3-23.2
Info:                  Risco-5/debug/clk_divider.v:40.12-40.38
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  2.3  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info:  0.0  2.3    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (48,2) -> (48,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info:  0.0  2.3  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info:  0.0  2.3    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (48,2) -> (49,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:15.3-23.2
Info:                  Risco-5/debug/clk_divider.v:40.12-40.38
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  2.3  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info:  0.0  2.3    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (49,2) -> (49,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info:  0.0  2.3  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info:  0.0  2.3    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (49,2) -> (49,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:15.3-23.2
Info:                  Risco-5/debug/clk_divider.v:40.12-40.38
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  2.4  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info:  0.0  2.4    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (49,2) -> (49,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info:  0.0  2.4  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info:  0.0  2.4    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (49,2) -> (49,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:15.3-23.2
Info:                  Risco-5/debug/clk_divider.v:40.12-40.38
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  2.5  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info:  0.0  2.5    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (49,2) -> (49,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info:  0.0  2.5  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info:  0.0  2.5    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (49,2) -> (49,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:15.3-23.2
Info:                  Risco-5/debug/clk_divider.v:40.12-40.38
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  2.5  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info:  0.0  2.5    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (49,2) -> (49,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info:  0.0  2.5  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info:  0.0  2.5    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (49,2) -> (50,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:15.3-23.2
Info:                  Risco-5/debug/clk_divider.v:40.12-40.38
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  2.6  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info:  0.0  2.6    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (50,2) -> (50,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info:  0.0  2.6  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info:  0.0  2.6    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (50,2) -> (50,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:15.3-23.2
Info:                  Risco-5/debug/clk_divider.v:40.12-40.38
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  2.7  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info:  0.0  2.7    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (50,2) -> (50,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info:  0.0  2.7  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info:  0.0  2.7    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (50,2) -> (50,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:15.3-23.2
Info:                  Risco-5/debug/clk_divider.v:40.12-40.38
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  2.8  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info:  0.0  2.8    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (50,2) -> (50,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info:  0.0  2.8  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info:  0.0  2.8    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (50,2) -> (50,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:15.3-23.2
Info:                  Risco-5/debug/clk_divider.v:40.12-40.38
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  2.8  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info:  0.0  2.8    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (50,2) -> (50,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info:  0.0  2.8  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info:  0.0  2.8    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (50,2) -> (51,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:15.3-23.2
Info:                  Risco-5/debug/clk_divider.v:40.12-40.38
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  2.9  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info:  0.0  2.9    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (51,2) -> (51,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info:  0.0  2.9  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info:  0.0  2.9    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN (51,2) -> (51,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:15.3-23.2
Info:                  Risco-5/debug/clk_divider.v:40.12-40.38
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  3.0  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info:  0.0  3.0    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (51,2) -> (51,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info:  0.0  3.0  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info:  0.0  3.0    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN (51,2) -> (51,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:15.3-23.2
Info:                  Risco-5/debug/clk_divider.v:40.12-40.38
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  3.0  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT$CCU2_COMB0.FCO
Info:  0.0  3.0    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT$CCU2_FCI_INT (51,2) -> (51,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT$CCU2_COMB1.FCI
Info:  0.0  3.0  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT$CCU2_COMB1.FCO
Info:  0.0  3.0    Net $nextpnr_CCU2C_3$CIN (51,2) -> (51,2)
Info:                Sink $nextpnr_CCU2C_3$CCU2_COMB0.FCI
Info:  0.4  3.5  Source $nextpnr_CCU2C_3$CCU2_COMB0.F
Info:  0.7  4.2    Net reset_LUT4_B_C_LUT4_Z_D (51,2) -> (51,4)
Info:                Sink reset_LUT4_B_C_LUT4_Z.D
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2  4.4  Source reset_LUT4_B_C_LUT4_Z.F
Info:  0.9  5.3    Net reset_LUT4_B_C[1] (51,4) -> (49,4)
Info:                Sink reset_LUT4_B.C
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2  5.5  Source reset_LUT4_B.F
Info:  0.7  6.2    Net reset_LUT4_B_Z (49,4) -> (49,3)
Info:                Sink ClkDivider.clk_counter_TRELLIS_FF_Q_17.LSR
Info:  0.4  6.6  Setup ClkDivider.clk_counter_TRELLIS_FF_Q_17.LSR
Info: 3.2 ns logic, 3.3 ns routing

Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
Info: curr total
Info:  0.0  0.0  Source reset$tr_io.O
Info:  3.8  3.8    Net reset$TRELLIS_IO_IN (0,29) -> (49,4)
Info:                Sink reset_LUT4_B.B
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2  4.0  Source reset_LUT4_B.F
Info:  0.7  4.7    Net reset_LUT4_B_Z (49,4) -> (49,3)
Info:                Sink ClkDivider.clk_counter_TRELLIS_FF_Q_17.LSR
Info:  0.4  5.1  Setup ClkDivider.clk_counter_TRELLIS_FF_Q_17.LSR
Info: 0.7 ns logic, 4.4 ns routing

Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk_o':
Info: curr total
Info:  0.0  0.0  Source gpios[2]$tr_io.O
Info:  5.0  5.0    Net gpios[2]$TRELLIS_IO_IN (90,23) -> (26,16)
Info:                Sink SOC.Core.read_data_LUT4_Z_1.A
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:7.16-7.21
Info:  0.2  5.2  Source SOC.Core.read_data_LUT4_Z_1.F
Info:  0.9  6.1    Net SOC.read_data[2] (26,16) -> (28,15)
Info:                Sink SOC.Core.instruction_register_TRELLIS_FF_Q_29.M
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:42.3-49.2
Info:                  Risco-5/src/peripheral/soc.v:20.34-20.43
Info:  0.0  6.1  Setup SOC.Core.instruction_register_TRELLIS_FF_Q_29.M
Info: 0.2 ns logic, 5.9 ns routing

Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
Info: curr total
Info:  0.5  0.5  Source ClkDivider.clk_o_auto_TRELLIS_FF_Q.Q
Info:  1.7  2.2    Net clk_o (48,4) -> (55,14)
Info:                Sink led_LUT4_Z_3.D
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:10.6-10.11
Info:  0.2  2.5  Source led_LUT4_Z_3.F
Info:  3.0  5.4    Net led[7]$TRELLIS_IO_OUT (55,14) -> (90,20)
Info:                Sink led[7]$tr_io.I
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:6.22-6.25
Info: 0.8 ns logic, 4.7 ns routing

Info: Critical path report for cross-domain path 'posedge $glbnet$clk_o' -> '<async>':
Info: curr total
Info:  0.5  0.5  Source SOC.GPIOS.Gpios[2].direction_TRELLIS_FF_Q.Q
Info:  3.0  3.5    Net SOC.Core.read_data_LUT4_Z_1_D[1] (25,16) -> (53,23)
Info:                Sink SOC.GPIOS.Gpios[2].direction_LUT4_D.D
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:42.3-49.2
Info:                  Risco-5/src/peripheral/gpios.v:14.19-14.33
Info:                  Risco-5/src/peripheral/soc.v:111.3-120.2
Info:  0.2  3.7  Source SOC.GPIOS.Gpios[2].direction_LUT4_D.F
Info:  1.8  5.5    Net gpios_$_TBUF__Y_3_E (53,23) -> (78,23)
Info:                Sink gpios[2]$tr_io$invert_T.A
Info:  0.2  5.8  Source gpios[2]$tr_io$invert_T.F
Info:  1.5  7.3    Net gpios[2]$tr_io$invert_T$conn$Z (78,23) -> (90,23)
Info:                Sink gpios[2]$tr_io.T
Info: 1.0 ns logic, 6.3 ns routing

Info: Max frequency for clock             '$glbnet$clk_o': 45.01 MHz (PASS at 12.00 MHz)
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 152.00 MHz (PASS at 25.00 MHz)

Info: Max delay <async>                           -> posedge $glbnet$clk$TRELLIS_IO_IN: 5.10 ns
Info: Max delay <async>                           -> posedge $glbnet$clk_o            : 6.14 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async>                          : 5.44 ns
Info: Max delay posedge $glbnet$clk_o             -> <async>                          : 7.27 ns

Info: Slack histogram:
Info:  legend: * represents 165 endpoint(s)
Info:          + represents [1,165) endpoint(s)
Info: [ 33421,  35870) |+
Info: [ 35870,  38319) |+
Info: [ 38319,  40768) |+
Info: [ 40768,  43217) | 
Info: [ 43217,  45666) | 
Info: [ 45666,  48115) | 
Info: [ 48115,  50564) | 
Info: [ 50564,  53013) | 
Info: [ 53013,  55462) | 
Info: [ 55462,  57911) | 
Info: [ 57911,  60360) | 
Info: [ 60360,  62809) |+
Info: [ 62809,  65258) |+
Info: [ 65258,  67707) |+
Info: [ 67707,  70156) |**************+
Info: [ 70156,  72605) |************************************************************ 
Info: [ 72605,  75054) |**+
Info: [ 75054,  77503) |**********+
Info: [ 77503,  79952) |*+
Info: [ 79952,  82401) |*+

Info: Program finished normally.
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (ECPPACK)
[Pipeline] sh
+ /eda/oss-cad-suite/bin/ecppack --compress --input ./build/out.config --bit ./build/out.bit
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (FPGA Flash)
[Pipeline] parallel
[Pipeline] { (Branch: openFPGAloader ECP5)
[Pipeline] { (Branch: openFPGAloader Tangnano 20k)
[Pipeline] stage
[Pipeline] { (openFPGAloader ECP5)
[Pipeline] stage
[Pipeline] { (openFPGAloader Tangnano 20k)
[Pipeline] script
[Pipeline] {
[Pipeline] script
[Pipeline] {
[Pipeline] lock
Trying to acquire lock on [ecp5]
Resource [ecp5] did not exist. Created.
Lock acquired on [ecp5]
[Pipeline] {
[Pipeline] lock
Trying to acquire lock on [tangnano20k]
Resource [tangnano20k] did not exist. Created.
Lock acquired on [tangnano20k]
[Pipeline] {
[Pipeline] echo
FPGA ECP5 Broqueada
[Pipeline] sh
[Pipeline] echo
FPGA TangNano Broqueada
[Pipeline] sh
+ /eda/oss-cad-suite/bin/openFPGALoader -b colorlight-i9 ./build/out.bit
Found 1 compatible device:
	0x0d28 0x0204 0x3 DAPLink CMSIS-DAP
Open file: DONE
Parse file: DONE
Enable configuration: DONE
SRAM erase: DONE
+ echo gravando na tang nano
gravando na tang nano
[Pipeline] }
Lock released on resource [tangnano20k]
[Pipeline] // lock
[Pipeline] }
[Pipeline] // script
[Pipeline] }
[Pipeline] // stage
[Pipeline] }

Loading: [=====                                             ] 9.49%
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Loading: [========================                          ] 47.46%
Loading: [=============================                     ] 56.95%
Loading: [==================================                ] 66.44%
Loading: [======================================            ] 75.93%
Loading: [===========================================       ] 85.42%
Loading: [================================================  ] 94.92%
Loading: [==================================================] 100.00%
Done
Disable configuration: DONE
[Pipeline] }
Lock released on resource [ecp5]
[Pipeline] // lock
[Pipeline] }
[Pipeline] // script
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Testes)
[Pipeline] parallel
[Pipeline] { (Branch: ECP5 - Testes)
[Pipeline] { (Branch: TangNano - Testes)
[Pipeline] stage
[Pipeline] { (ECP5 - Testes)
[Pipeline] stage
[Pipeline] { (TangNano - Testes)
[Pipeline] script
[Pipeline] {
[Pipeline] script
[Pipeline] {
[Pipeline] echo
Rodando teste na ECP5
[Pipeline] lock
Trying to acquire lock on [ecp5]
Resource [ecp5] did not exist. Created.
Lock acquired on [ecp5]
[Pipeline] {
[Pipeline] echo
Rodando teste na tang nano
[Pipeline] lock
Trying to acquire lock on [tangnano20k]
Resource [tangnano20k] did not exist. Created.
Lock acquired on [tangnano20k]
[Pipeline] {
[Pipeline] echo
FPGA ECP5 Broqueada
[Pipeline] sh
[Pipeline] echo
FPGA TangNano Broqueada
[Pipeline] sh
+ echo testando na ecp5
testando na ecp5
[Pipeline] }
Lock released on resource [ecp5]
+ echo testando na tang nano
testando na tang nano
[Pipeline] // lock
[Pipeline] echo
ECP5 liberada
[Pipeline] }
[Pipeline] }
Lock released on resource [tangnano20k]
[Pipeline] // script
[Pipeline] // lock
[Pipeline] }
[Pipeline] echo
TangNano liberada
[Pipeline] }
[Pipeline] // stage
[Pipeline] // script
[Pipeline] }
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // node
[Pipeline] End of Pipeline
Finished: SUCCESS