Skip to content
[Jenkins]Jenkins
log in
Success

Console Output

Download View as plain text
Skipping 502 KB.. Full Log
  Optimizing lut $abc$97631$lut$aiger97630$14295.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$14311.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$14332.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$14400.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$14463.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$14479.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$14489.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$14496.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$14530.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$14546.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$14580.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$14614.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$14675.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$14742.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$14803.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$14836.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$14869.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$14885.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$14904.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$14920.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$14949.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$15030.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$15046.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$15076.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$15142.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$15158.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$15177.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$15193.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$15230.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$15281.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$15347.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$15363.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$15382.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$15398.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$15422.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$15435.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$15488.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$15552.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$15614.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$15630.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$15646.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$15662.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$15681.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$15714.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$15730.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$15759.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$15772.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$15782.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$15789.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$15802.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$15830.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$15843.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$15853.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$15860.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$15873.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$15901.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$15963.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$16044.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$16110.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$16126.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$16162.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$16172.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$16185.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$16192.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$16205.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$16233.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$16246.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$16256.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$16263.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$16276.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$16303.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$16319.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$16332.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$16348.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$16365.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$16377.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$16390.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$16400.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$16407.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$16420.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$16462.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$16478.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$16491.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$16498.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$16525.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$16541.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$16594.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$16610.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$16641.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$16705.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$16726.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$16736.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$16740.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$16762.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$16778.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$16791.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$16807.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$16840.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$16856.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$16932.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$16948.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$16979.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$17000.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$17010.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$17014.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$17036.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$17052.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$17065.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$17081.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$17114.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$17134.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$17150.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$17166.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$17179.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$17201.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$17214.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$17230.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$17252.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$17263.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$17279.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$17341.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$17422.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$17438.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$17451.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$17458.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$17468.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$17542.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$17558.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$17571.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$17593.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$17609.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$17622.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$17638.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$17660.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$17671.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$17682.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$17703.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$17713.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$17717.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$17739.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$17755.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$17768.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$17784.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$17817.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$17829.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$17890.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$17960.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$18038.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$18054.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$18094.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$18109.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$18119.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$18123.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$18145.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$18161.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$18174.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$18190.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$18223.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$7826.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$18241.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$18262.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$18272.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$18279.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$18298.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$18314.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$18327.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$18343.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$18365.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$18376.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$18391.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$18406.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$18422.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$18454.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$18540.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$18556.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$18589.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$18605.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$18621.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$18634.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$18656.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$18669.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$18685.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$18718.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$5983.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7671.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6255.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6323.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6329.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97841.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$6350.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7072.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97844.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$6385.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6406.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6420.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6439.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6453.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97821.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$6490.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6499.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$6490.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6520.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6540.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6540.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6549.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6554.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6566.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6606.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6610.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6628.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6628.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6592.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$6648.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6648.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6667.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6667.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6677.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6700.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6700.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6720.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6720.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6737.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6737.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6748.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$6762.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6762.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6782.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6810.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6810.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6827.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6831.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$6839.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$6853.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6880.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6908.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6908.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6925.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6929.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6937.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$6941.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6951.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97856.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$7126.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$7003.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7032.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7526.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7046.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6329.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$6323.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7072.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7032.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7083.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7093.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7111.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7126.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$7153.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7175.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7200.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7232.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7257.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7279.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7287.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7309.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$7321.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7334.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$7348.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7367.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7385.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7398.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$7438.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7451.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$7466.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$7482.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7487.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97846.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97847.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$7543.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$7055.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7598.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7608.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7618.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7628.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7647.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7654.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7661.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7671.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7681.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7687.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7703.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7710.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7724.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$7751.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7761.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7771.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7781.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7800.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7807.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7814.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7822.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7836.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7847.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7858.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$7872.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7879.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7883.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7892.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$7902.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7912.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7912.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7926.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7937.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7945.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7960.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7970.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7983.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7998.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8013.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8054.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$8075.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8085.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8075.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8018.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8097.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8104.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8111.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8118.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8128.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8138.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8153.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8153.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7814.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8191.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$8209.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8238.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$8238.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$8247.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8253.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8266.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8276.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8276.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8289.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8289.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8300.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8328.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$8334.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$8341.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8348.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8348.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8375.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8385.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8385.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7937.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8406.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8442.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8448.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$8462.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8469.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8491.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7879.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8520.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8528.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$8537.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$8543.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$8565.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8575.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8588.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8617.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8628.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8640.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$8651.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8658.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$8673.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$8683.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8688.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$8688.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$7902.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8628.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8717.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8723.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8731.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8768.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$8768.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$8777.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8781.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8794.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8799.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$8808.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$8828.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$8828.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$8406.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8867.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$8876.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8893.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8901.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8906.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$8917.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7771.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7836.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8949.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8955.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$8520.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8588.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8971.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8990.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9002.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$9010.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97834.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$9071.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$9084.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$9107.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9114.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9139.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9150.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9159.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9186.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9196.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9233.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$9259.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$9275.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9290.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9304.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9304.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9315.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9322.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9334.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$8442.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9369.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9389.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9369.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9445.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$7175.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7279.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9196.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9507.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$9516.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9533.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$9547.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$97631$lut$aiger97630$9552.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9585.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9657.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9675.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9695.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9712.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9728.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9746.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9801.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$9909.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$auto$fsm_map.cc:170:map_fsm$2191[2].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$auto$fsm_map.cc:170:map_fsm$2234[1].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$auto$opt_dff.cc:219:make_patterns_logic$2449.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97646.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97658.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97657.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97651.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97659.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97648.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97649.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97644.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97644.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97645.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97648.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97649.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97650.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97651.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97652.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97654.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97656.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97657.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8013.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$8777.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97640.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97749.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97779.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97791.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97798.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97802.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$7438.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97806.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$7421.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$7287.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97816.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97817.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$7334.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$7321.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97824.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97825.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$7398.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97828.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$7367.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$97631$lut$aiger97630$7309.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97837.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$97631$lut$aiger97630$7451.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$97631$lut$aiger97630$7466.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$97850.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Removed 0 unused cells and 11165 unused wires.

21.45. Executing AUTONAME pass.
Renamed 299839 objects in module top (220 iterations).
<suppressed ~14189 debug messages>

21.46. Executing HIERARCHY pass (managing design hierarchy).

21.46.1. Analyzing design hierarchy..
Top module:  \top

21.46.2. Analyzing design hierarchy..
Top module:  \top
Removed 0 unused modules.

21.47. Printing statistics.

=== top ===

   Number of wires:               5906
   Number of wire bits:          16269
   Number of public wires:        5906
   Number of public wire bits:   16269
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:               9003
     $_TBUF_                         6
     CCU2C                         156
     L6MUX21                       448
     LUT4                         5436
     PFUMX                        1092
     TRELLIS_DPR16X4               512
     TRELLIS_FF                   1353

21.48. Executing CHECK pass (checking for obvious problems).
Checking module top...
Found and reported 0 problems.

21.49. Executing JSON backend.

Warnings: 226 unique messages, 227 total
End of script. Logfile hash: bb8caca09a, CPU: user 8.58s system 0.13s, MEM: 218.71 MB peak
Yosys 0.36+8 (git sha1 fb4cbfa73, clang 10.0.0-4ubuntu1 -fPIC -Os)
Time spent: 36% 1x abc9_exe (5 sec), 13% 11x techmap (1 sec), ...
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (NextPNR)
[Pipeline] sh
+ /eda/oss-cad-suite/bin/nextpnr-ecp5 --json ./build/out.json --write ./build/out_pnr.json --45k --lpf Risco-5/fpga/ecp5/pinout.lpf --textcfg ./build/out.config --package CABGA381 --speed 6 --ignore-loops --lpf-allow-unconstrained
Info: constraining clock net 'clk' to 25.00 MHz

Info: Logic utilisation before packing:
Info:     Total LUT4s:      8820/43848    20%
Info:         logic LUTs:   5436/43848    12%
Info:         carry LUTs:    312/43848     0%
Info:           RAM LUTs:   2048/ 5481    37%
Info:          RAMW LUTs:   1024/10962     9%

Info:      Total DFFs:      1353/43848     3%

Info: Packing IOs..
Info: $gpios[5]$iobuf_i: gpios_$_TBUF__Y.Y
Info: pin 'gpios[5]$tr_io' constrained to Bel 'X0/Y23/PIOC'.
Info: $gpios[4]$iobuf_i: gpios_$_TBUF__Y_1.Y
Info: pin 'gpios[4]$tr_io' constrained to Bel 'X0/Y44/PIOA'.
Info: $gpios[3]$iobuf_i: gpios_$_TBUF__Y_2.Y
Info: pin 'gpios[3]$tr_io' constrained to Bel 'X0/Y23/PIOA'.
Info: $gpios[2]$iobuf_i: gpios_$_TBUF__Y_3.Y
Info: pin 'gpios[2]$tr_io' constrained to Bel 'X90/Y23/PIOD'.
Info: $gpios[1]$iobuf_i: gpios_$_TBUF__Y_4.Y
Info: pin 'gpios[1]$tr_io' constrained to Bel 'X0/Y14/PIOD'.
Info: $gpios[0]$iobuf_i: gpios_$_TBUF__Y_5.Y
Info: pin 'gpios[0]$tr_io' constrained to Bel 'X0/Y44/PIOB'.
Info: pin 'tx$tr_io' constrained to Bel 'X90/Y20/PIOC'.
Info: pin 'rx$tr_io' constrained to Bel 'X90/Y20/PIOA'.
Info: pin 'reset$tr_io' constrained to Bel 'X0/Y29/PIOA'.
Info: pin 'led[7]$tr_io' constrained to Bel 'X90/Y20/PIOD'.
Info: pin 'led[6]$tr_io' constrained to Bel 'X0/Y44/PIOD'.
Info: pin 'led[5]$tr_io' constrained to Bel 'X0/Y59/PIOA'.
Info: pin 'led[4]$tr_io' constrained to Bel 'X15/Y71/PIOB'.
Info: pin 'led[3]$tr_io' constrained to Bel 'X90/Y29/PIOC'.
Info: pin 'led[2]$tr_io' constrained to Bel 'X90/Y44/PIOB'.
Info: pin 'led[1]$tr_io' constrained to Bel 'X0/Y44/PIOC'.
Info: pin 'led[0]$tr_io' constrained to Bel 'X0/Y59/PIOC'.
Info: pin 'clk$tr_io' constrained to Bel 'X0/Y68/PIOC'.
Info: Packing constants..
Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info:     309 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info: Promoting globals...
Info:     promoting clock net clk_o to global network
Info:     promoting clock net clk$TRELLIS_IO_IN to global network
Info: Checksum: 0x76590d4c

Info: Device utilisation:
Info: 	          TRELLIS_IO:    18/  245     7%
Info: 	                DCCA:     2/   56     3%
Info: 	              DP16KD:     0/  108     0%
Info: 	          MULT18X18D:     0/   72     0%
Info: 	              ALU54B:     0/   36     0%
Info: 	             EHXPLLL:     0/    4     0%
Info: 	             EXTREFB:     0/    2     0%
Info: 	                DCUA:     0/    2     0%
Info: 	           PCSCLKDIV:     0/    2     0%
Info: 	             IOLOGIC:     0/  160     0%
Info: 	            SIOLOGIC:     0/   85     0%
Info: 	                 GSR:     0/    1     0%
Info: 	               JTAGG:     0/    1     0%
Info: 	                OSCG:     0/    1     0%
Info: 	               SEDGA:     0/    1     0%
Info: 	                 DTR:     0/    1     0%
Info: 	             USRMCLK:     0/    1     0%
Info: 	             CLKDIVF:     0/    4     0%
Info: 	           ECLKSYNCB:     0/   10     0%
Info: 	             DLLDELD:     0/    8     0%
Info: 	              DDRDLL:     0/    4     0%
Info: 	             DQSBUFM:     0/   10     0%
Info: 	     TRELLIS_ECLKBUF:     0/    8     0%
Info: 	        ECLKBRIDGECS:     0/    2     0%
Info: 	                DCSC:     0/    2     0%
Info: 	          TRELLIS_FF:  1353/43848     3%
Info: 	        TRELLIS_COMB:  8884/43848    20%
Info: 	        TRELLIS_RAMW:   512/ 5481     9%

Info: Placed 18 cells based on constraints.
Info: Creating initial analytic placement for 5474 cells, random placement wirelen = 454857.
Info:     at initial placer iter 0, wirelen = 2052
Info:     at initial placer iter 1, wirelen = 2122
Info:     at initial placer iter 2, wirelen = 1752
Info:     at initial placer iter 3, wirelen = 1925
Info: Running main analytical placer, max placement attempts per cell = 14496420.
Info:     at iteration #1, type ALL: wirelen solved = 1919, spread = 67888, legal = 68703; time = 0.27s
Info:     at iteration #2, type ALL: wirelen solved = 8717, spread = 45061, legal = 46305; time = 0.27s
Info:     at iteration #3, type ALL: wirelen solved = 13098, spread = 43964, legal = 45055; time = 0.26s
Info:     at iteration #4, type ALL: wirelen solved = 16419, spread = 40981, legal = 42094; time = 0.26s
Info:     at iteration #5, type ALL: wirelen solved = 18783, spread = 42884, legal = 43851; time = 0.25s
Info:     at iteration #6, type ALL: wirelen solved = 20818, spread = 39285, legal = 40221; time = 0.25s
Info:     at iteration #7, type ALL: wirelen solved = 21820, spread = 37495, legal = 39091; time = 0.25s
Info:     at iteration #8, type ALL: wirelen solved = 21133, spread = 38510, legal = 39737; time = 0.25s
Info:     at iteration #9, type ALL: wirelen solved = 22777, spread = 37841, legal = 39201; time = 0.24s
Info:     at iteration #10, type ALL: wirelen solved = 23017, spread = 37761, legal = 39108; time = 0.24s
Info:     at iteration #11, type ALL: wirelen solved = 23693, spread = 37074, legal = 38564; time = 0.24s
Info:     at iteration #12, type ALL: wirelen solved = 23689, spread = 36726, legal = 38046; time = 0.24s
Info:     at iteration #13, type ALL: wirelen solved = 23961, spread = 40823, legal = 41467; time = 0.24s
Info:     at iteration #14, type ALL: wirelen solved = 27226, spread = 40938, legal = 41632; time = 0.24s
Info:     at iteration #15, type ALL: wirelen solved = 28233, spread = 40008, legal = 40873; time = 0.23s
Info:     at iteration #16, type ALL: wirelen solved = 27412, spread = 38748, legal = 39818; time = 0.23s
Info:     at iteration #17, type ALL: wirelen solved = 26593, spread = 42682, legal = 43176; time = 0.24s
Info: HeAP Placer Time: 6.81s
Info:   of which solving equations: 4.07s
Info:   of which spreading cells: 0.58s
Info:   of which strict legalisation: 0.18s

Info: Running simulated annealing placer for refinement.
Info:   at iteration #1: temp = 0.000000, timing cost = 10599, wirelen = 38046
Info:   at iteration #5: temp = 0.000000, timing cost = 12616, wirelen = 33165
Info:   at iteration #10: temp = 0.000000, timing cost = 11538, wirelen = 31728
Info:   at iteration #15: temp = 0.000000, timing cost = 11383, wirelen = 30844
Info:   at iteration #20: temp = 0.000000, timing cost = 10836, wirelen = 30368
Info:   at iteration #25: temp = 0.000000, timing cost = 11888, wirelen = 30216
Info:   at iteration #30: temp = 0.000000, timing cost = 12111, wirelen = 30149
Info:   at iteration #31: temp = 0.000000, timing cost = 11891, wirelen = 30132 
Info: SA placement time 30.47s

Info: Max frequency for clock             '$glbnet$clk_o': 28.53 MHz (PASS at 12.00 MHz)
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 146.33 MHz (PASS at 25.00 MHz)

Info: Max delay <async>                           -> posedge $glbnet$clk$TRELLIS_IO_IN: 12.18 ns
Info: Max delay <async>                           -> posedge $glbnet$clk_o            : 11.44 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async>                          : 10.84 ns
Info: Max delay posedge $glbnet$clk_o             -> <async>                          : 15.40 ns

Info: Slack histogram:
Info:  legend: * represents 102 endpoint(s)
Info:          + represents [1,102) endpoint(s)
Info: [ 33166,  35637) |+
Info: [ 35637,  38108) |+
Info: [ 38108,  40579) |+
Info: [ 40579,  43050) | 
Info: [ 43050,  45521) | 
Info: [ 45521,  47992) | 
Info: [ 47992,  50463) |+
Info: [ 50463,  52934) |+
Info: [ 52934,  55405) |+
Info: [ 55405,  57876) |+
Info: [ 57876,  60347) |*************+
Info: [ 60347,  62818) |************************************************************ 
Info: [ 62818,  65289) |******************************************+
Info: [ 65289,  67760) |*****+
Info: [ 67760,  70231) |**+
Info: [ 70231,  72702) |**********+
Info: [ 72702,  75173) |*******+
Info: [ 75173,  77644) |**+
Info: [ 77644,  80115) |*+
Info: [ 80115,  82586) |+
Info: Checksum: 0x42af33bb
Info: Routing globals...
Info:     routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
Info:     routing clock net $glbnet$clk_o using global 1

Info: Routing..
Info: Setting up routing queue.
Info: Routing 42922 arcs.
Info:            |   (re-)routed arcs  |   delta    | remaining|       time spent     |
Info:    IterCnt |  w/ripup   wo/ripup |  w/r  wo/r |      arcs| batch(sec) total(sec)|
Info:       1000 |      219        780 |  219   780 |     42411|       0.65       0.65|
Info:       2000 |      493       1506 |  274   726 |     42075|       0.17       0.83|
Info:       3000 |      667       2332 |  174   826 |     41706|       0.15       0.98|
Info:       4000 |      863       3136 |  196   804 |     41509|       0.15       1.12|
Info:       5000 |     1042       3957 |  179   821 |     41635|       0.15       1.27|
Info:       6000 |     1243       4756 |  201   799 |     41376|       0.18       1.45|
Info:       7000 |     1413       5586 |  170   830 |     40781|       0.16       1.61|
Info:       8000 |     1590       6409 |  177   823 |     40571|       0.17       1.78|
Info:       9000 |     1785       7214 |  195   805 |     40230|       0.16       1.94|
Info:      10000 |     2044       7955 |  259   741 |     40248|       0.17       2.10|
Info:      11000 |     2218       8781 |  174   826 |     40105|       0.14       2.25|
Info:      12000 |     2406       9593 |  188   812 |     39761|       0.16       2.41|
Info:      13000 |     2635      10364 |  229   771 |     39385|       0.16       2.57|
Info:      14000 |     2784      11215 |  149   851 |     39038|       0.18       2.75|
Info:      15000 |     2908      12091 |  124   876 |     38898|       0.17       2.91|
Info:      16000 |     3153      12846 |  245   755 |     38583|       0.17       3.08|
Info:      17000 |     3340      13659 |  187   813 |     38226|       0.18       3.26|
Info:      18000 |     3476      14523 |  136   864 |     38201|       0.15       3.41|
Info:      19000 |     3578      15421 |  102   898 |     37777|       0.15       3.56|
Info:      20000 |     3750      16249 |  172   828 |     37463|       0.17       3.73|
Info:      21000 |     3923      17076 |  173   827 |     36898|       0.16       3.89|
Info:      22000 |     4099      17900 |  176   824 |     36568|       0.19       4.08|
Info:      23000 |     4316      18683 |  217   783 |     36080|       0.17       4.26|
Info:      24000 |     4481      19518 |  165   835 |     35886|       0.15       4.41|
Info:      25000 |     4564      20435 |   83   917 |     35642|       0.15       4.55|
Info:      26000 |     4747      21252 |  183   817 |     35381|       0.16       4.72|
Info:      27000 |     4888      22111 |  141   859 |     35150|       0.17       4.88|
Info:      28000 |     5077      22922 |  189   811 |     34808|       0.17       5.05|
Info:      29000 |     5297      23702 |  220   780 |     34456|       0.18       5.24|
Info:      30000 |     5439      24560 |  142   858 |     34481|       0.19       5.43|
Info:      31000 |     5604      25395 |  165   835 |     34209|       0.19       5.62|
Info:      32000 |     5825      26174 |  221   779 |     33798|       0.18       5.80|
Info:      33000 |     6040      26959 |  215   785 |     33513|       0.19       5.98|
Info:      34000 |     6296      27703 |  256   744 |     33258|       0.18       6.17|
Info:      35000 |     6541      28458 |  245   755 |     32776|       0.19       6.36|
Info:      36000 |     6744      29255 |  203   797 |     32321|       0.17       6.53|
Info:      37000 |     6958      30041 |  214   786 |     31977|       0.20       6.73|
Info:      38000 |     7122      30877 |  164   836 |     31854|       0.17       6.90|
Info:      39000 |     7367      31632 |  245   755 |     31577|       0.18       7.07|
Info:      40000 |     7545      32454 |  178   822 |     31492|       0.18       7.25|
Info:      41000 |     7710      33289 |  165   835 |     31251|       0.20       7.45|
Info:      42000 |     7832      34167 |  122   878 |     31335|       0.19       7.64|
Info:      43000 |     8075      34924 |  243   757 |     30961|       0.20       7.85|
Info:      44000 |     8310      35689 |  235   765 |     30629|       0.21       8.05|
Info:      45000 |     8412      36587 |  102   898 |     30543|       0.16       8.21|
Info:      46000 |     8565      37434 |  153   847 |     30404|       0.19       8.40|
Info:      47000 |     8843      38156 |  278   722 |     30121|       0.20       8.60|
Info:      48000 |     8992      39007 |  149   851 |     30280|       0.19       8.79|
Info:      49000 |     9000      39999 |    8   992 |     30332|       0.15       8.95|
Info:      50000 |     9184      40815 |  184   816 |     29845|       0.20       9.15|
Info:      51000 |     9445      41554 |  261   739 |     29426|       0.20       9.35|
Info:      52000 |     9696      42303 |  251   749 |     28995|       0.20       9.54|
Info:      53000 |     9943      43056 |  247   753 |     28631|       0.20       9.74|
Info:      54000 |    10197      43802 |  254   746 |     28262|       0.20       9.94|
Info:      55000 |    10484      44515 |  287   713 |     27988|       0.25      10.19|
Info:      56000 |    10691      45308 |  207   793 |     27793|       0.20      10.39|
Info:      57000 |    10981      46018 |  290   710 |     27513|       0.23      10.62|
Info:      58000 |    11189      46810 |  208   792 |     27347|       0.23      10.85|
Info:      59000 |    11296      47703 |  107   893 |     27255|       0.20      11.04|
Info:      60000 |    11596      48403 |  300   700 |     26846|       0.21      11.25|
Info:      61000 |    11915      49084 |  319   681 |     26462|       0.22      11.48|
Info:      62000 |    12108      49891 |  193   807 |     26442|       0.19      11.67|
Info:      63000 |    12358      50641 |  250   750 |     26167|       0.22      11.89|
Info:      64000 |    12637      51362 |  279   721 |     25835|       0.23      12.12|
Info:      65000 |    12928      52071 |  291   709 |     25417|       0.24      12.36|
Info:      66000 |    13197      52802 |  269   731 |     25647|       0.24      12.60|
Info:      67000 |    13294      53705 |   97   903 |     25167|       0.20      12.80|
Info:      68000 |    13584      54415 |  290   710 |     24954|       0.26      13.06|
Info:      69000 |    13871      55128 |  287   713 |     24578|       0.22      13.28|
Info:      70000 |    14163      55836 |  292   708 |     24924|       0.24      13.53|
Info:      71000 |    14279      56720 |  116   884 |     24378|       0.19      13.72|
Info:      72000 |    14557      57442 |  278   722 |     24282|       0.23      13.94|
Info:      73000 |    14898      58101 |  341   659 |     24021|       0.26      14.20|
Info:      74000 |    15215      58784 |  317   683 |     23737|       0.24      14.45|
Info:      75000 |    15419      59580 |  204   796 |     23750|       0.26      14.70|
Info:      76000 |    15744      60255 |  325   675 |     23375|       0.24      14.94|
Info:      77000 |    15979      61020 |  235   765 |     23171|       0.24      15.18|
Info:      78000 |    16288      61711 |  309   691 |     23005|       0.25      15.44|
Info:      79000 |    16508      62491 |  220   780 |     23242|       0.25      15.68|
Info:      80000 |    16627      63372 |  119   881 |     22929|       0.22      15.90|
Info:      81000 |    16967      64032 |  340   660 |     22835|       0.28      16.19|
Info:      82000 |    17216      64783 |  249   751 |     22587|       0.21      16.39|
Info:      83000 |    17575      65424 |  359   641 |     22215|       0.24      16.64|
Info:      84000 |    17981      66018 |  406   594 |     21859|       0.24      16.87|
Info:      85000 |    18369      66630 |  388   612 |     21468|       0.23      17.11|
Info:      86000 |    18684      67315 |  315   685 |     21264|       0.24      17.35|
Info:      87000 |    18896      68103 |  212   788 |     21776|       0.23      17.58|
Info:      88000 |    18967      69032 |   71   929 |     21671|       0.20      17.77|
Info:      89000 |    19160      69839 |  193   807 |     21573|       0.22      17.99|
Info:      90000 |    19379      70620 |  219   781 |     21129|       0.24      18.23|
Info:      91000 |    19713      71286 |  334   666 |     20797|       0.24      18.47|
Info:      92000 |    20064      71935 |  351   649 |     20617|       0.25      18.72|
Info:      93000 |    20455      72544 |  391   609 |     20285|       0.26      18.98|
Info:      94000 |    20911      73088 |  456   544 |     20103|       0.25      19.23|
Info:      95000 |    21360      73639 |  449   551 |     19845|       0.25      19.48|
Info:      96000 |    21857      74142 |  497   503 |     19621|       0.24      19.72|
Info:      97000 |    22048      74951 |  191   809 |     19586|       0.22      19.94|
Info:      98000 |    22457      75542 |  409   591 |     19366|       0.25      20.19|
Info:      99000 |    22869      76130 |  412   588 |     19163|       0.26      20.45|
Info:     100000 |    23276      76723 |  407   593 |     19601|       0.24      20.69|
Info:     101000 |    23613      77386 |  337   663 |     20023|       0.23      20.92|
Info:     102000 |    23865      78134 |  252   748 |     19690|       0.25      21.16|
Info:     103000 |    24134      78865 |  269   731 |     19234|       0.26      21.42|
Info:     104000 |    24524      79475 |  390   610 |     19032|       0.26      21.68|
Info:     105000 |    24953      80046 |  429   571 |     18819|       0.27      21.95|
Info:     106000 |    25408      80591 |  455   545 |     18557|       0.29      22.24|
Info:     107000 |    25837      81162 |  429   571 |     18360|       0.28      22.51|
Info:     108000 |    26290      81709 |  453   547 |     18149|       0.28      22.79|
Info:     109000 |    26844      82155 |  554   446 |     18021|       0.27      23.06|
Info:     110000 |    27212      82787 |  368   632 |     17907|       0.26      23.32|
Info:     111000 |    27740      83259 |  528   472 |     17710|       0.27      23.60|
Info:     112000 |    28343      83656 |  603   397 |     17496|       0.25      23.85|
Info:     113000 |    28911      84088 |  568   432 |     17320|       0.25      24.10|
Info:     114000 |    29444      84555 |  533   467 |     17120|       0.25      24.36|
Info:     115000 |    30010      84989 |  566   434 |     16913|       0.26      24.62|
Info:     116000 |    30547      85452 |  537   463 |     16702|       0.25      24.87|
Info:     117000 |    30988      86011 |  441   559 |     16644|       0.25      25.13|
Info:     118000 |    31500      86499 |  512   488 |     16534|       0.27      25.40|
Info:     119000 |    32006      86993 |  506   494 |     16427|       0.28      25.68|
Info:     120000 |    32508      87491 |  502   498 |     16342|       0.27      25.94|
Info:     121000 |    32758      88241 |  250   750 |     16203|       0.26      26.21|
Info:     122000 |    33185      88814 |  427   573 |     15998|       0.27      26.48|
Info:     123000 |    33613      89386 |  428   572 |     15915|       0.28      26.76|
Info:     124000 |    34124      89875 |  511   489 |     15744|       0.28      27.04|
Info:     125000 |    34538      90438 |  414   563 |     15627|       0.27      27.31|
Info:     126000 |    34948      91008 |  410   570 |     15480|       0.30      27.61|
Info:     127000 |    35481      91440 |  533   432 |     15239|       0.26      27.87|
Info:     128000 |    36007      91885 |  526   445 |     15049|       0.28      28.15|
Info:     129000 |    36548      92303 |  541   418 |     14848|       0.26      28.41|
Info:     130000 |    37137      92663 |  589   360 |     14578|       0.26      28.67|
Info:     131000 |    37694      93032 |  557   369 |     14201|       0.23      28.91|
Info:     132000 |    38192      93457 |  498   425 |     13886|       0.24      29.14|
Info:     133000 |    38769      93819 |  577   362 |     13616|       0.25      29.40|
Info:     134000 |    39399      94144 |  630   325 |     13380|       0.26      29.65|
Info:     135000 |    39850      94667 |  451   523 |     13239|       0.25      29.91|
Info:     136000 |    40370      95115 |  520   448 |     13102|       0.27      30.17|
Info:     137000 |    40911      95515 |  541   400 |     12735|       0.25      30.42|
Info:     138000 |    41359      96037 |  448   522 |     12538|       0.33      30.75|
Info:     139000 |    41717      96561 |  358   524 |     11946|       0.21      30.96|
Info:     140000 |    42017      97182 |  300   621 |     11684|       0.27      31.23|
Info:     141000 |    42444      97750 |  427   568 |     11464|       0.33      31.56|
Info:     142000 |    42699      98477 |  255   727 |     10908|       0.22      31.78|
Info:     143000 |    42835      99330 |  136   853 |     10180|       0.17      31.95|
Info:     144000 |    42970     100192 |  135   862 |      9484|       0.17      32.11|
Info:     145000 |    43002     101156 |   32   964 |      8517|       0.09      32.20|
Info:     146000 |    43038     102118 |   36   962 |      7563|       0.10      32.30|
Info:     147000 |    43074     103077 |   36   959 |      6637|       0.11      32.41|
Info:     148000 |    43152     103990 |   78   913 |      5731|       0.11      32.52|
Info:     149000 |    43268     104870 |  116   880 |      4891|       0.15      32.68|
Info:     150000 |    43524     105612 |  256   742 |      4386|       0.22      32.90|
Info:     151000 |    43766     106346 |  242   734 |      3788|       0.22      33.12|
Info:     152000 |    44116     106993 |  350   647 |      3409|       0.31      33.43|
Info:     153000 |    44518     107575 |  402   582 |      3191|       0.35      33.79|
Info:     154000 |    44930     108152 |  412   577 |      3022|       0.37      34.15|
Info:     155000 |    45384     108684 |  454   532 |      2719|       0.35      34.50|
Info:     156000 |    45830     109230 |  446   546 |      2272|       0.28      34.78|
Info:     157000 |    46237     109814 |  407   584 |      1857|       0.31      35.09|
Info:     158000 |    46683     110364 |  446   550 |      1581|       0.38      35.47|
Info:     159000 |    47119     110926 |  436   562 |      1187|       0.31      35.78|
Info:     160000 |    47707     111338 |  588   412 |       903|       0.38      36.16|
Info:     161000 |    48272     111758 |  565   420 |       610|       0.38      36.54|
Info:     161763 |    48377     112110 |  105   352 |         0|       0.19      36.73|
Info: Routing complete.
Info: Router1 time 36.73s
Info: Checksum: 0xa37f1f53

Info: Critical path report for clock '$glbnet$clk_o' (posedge -> posedge):
Info: curr total
Info:  0.5  0.5  Source SOC.Core.Control_Unit.state_TRELLIS_FF_Q_3.Q
Info:  1.0  1.5    Net SOC.Core.Control_Unit.nextstate_LUT4_Z_C[3] (38,17) -> (38,17)
Info:                Sink SOC.Memory.address_LUT4_Z_C_LUT4_Z_D_LUT4_Z.D
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:42.3-49.2
Info:                  Risco-5/src/core/core.v:97.14-114.2
Info:                  Risco-5/src/core/control_unit.v:48.11-48.16
Info:                  Risco-5/src/peripheral/soc.v:28.3-36.2
Info:  0.2  1.7  Source SOC.Memory.address_LUT4_Z_C_LUT4_Z_D_LUT4_Z.F
Info:  1.6  3.4    Net SOC.Memory.address_LUT4_Z_C_LUT4_Z_D[2] (38,17) -> (29,9)
Info:                Sink SOC.Memory.memory.0.323_DO_LUT4_C_Z_LUT4_Z_B_CCU2C_B0_COUT_CCU2C_CIN_B1_LUT4_Z.D
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2  3.6  Source SOC.Memory.memory.0.323_DO_LUT4_C_Z_LUT4_Z_B_CCU2C_B0_COUT_CCU2C_CIN_B1_LUT4_Z.F
Info:  2.0  5.6    Net SOC.Memory.memory.0.323_DO_LUT4_C_Z_LUT4_Z_B_CCU2C_B0_COUT_CCU2C_CIN_B1 (29,9) -> (41,16)
Info:                Sink SOC.Memory.memory.0.323_DO_LUT4_C_Z_LUT4_Z_B_CCU2C_B0_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB1.B
Info:  0.4  6.1  Source SOC.Memory.memory.0.323_DO_LUT4_C_Z_LUT4_Z_B_CCU2C_B0_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB1.FCO
Info:  0.0  6.1    Net SOC.Memory.memory.0.323_DO_LUT4_C_Z_LUT4_Z_B_CCU2C_B0_COUT_CCU2C_CIN_B0_CCU2C_B0_COUT (41,16) -> (41,16)
Info:                Sink SOC.Memory.memory.0.323_DO_LUT4_C_Z_LUT4_Z_B_CCU2C_B0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:42.3-49.2
Info:                  Risco-5/src/peripheral/bus.v:54.5-54.37
Info:                  Risco-5/src/peripheral/soc.v:51.5-81.2
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  6.1  Source SOC.Memory.memory.0.323_DO_LUT4_C_Z_LUT4_Z_B_CCU2C_B0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB0.FCO
Info:  0.0  6.1    Net SOC.Memory.memory.0.323_DO_LUT4_C_Z_LUT4_Z_B_CCU2C_B0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_FCI_INT (41,16) -> (41,16)
Info:                Sink SOC.Memory.memory.0.323_DO_LUT4_C_Z_LUT4_Z_B_CCU2C_B0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB1.FCI
Info:  0.0  6.1  Source SOC.Memory.memory.0.323_DO_LUT4_C_Z_LUT4_Z_B_CCU2C_B0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB1.FCO
Info:  0.0  6.1    Net SOC.Memory.memory.0.323_DO_LUT4_C_Z_LUT4_Z_B_CCU2C_B0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0_COUT (41,16) -> (41,16)
Info:                Sink SOC.Memory.memory.0.323_DO_LUT4_C_Z_LUT4_Z_B_CCU2C_B0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:42.3-49.2
Info:                  Risco-5/src/peripheral/bus.v:54.5-54.37
Info:                  Risco-5/src/peripheral/soc.v:51.5-81.2
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  6.2  Source SOC.Memory.memory.0.323_DO_LUT4_C_Z_LUT4_Z_B_CCU2C_B0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB0.FCO
Info:  0.0  6.2    Net SOC.Memory.memory.0.323_DO_LUT4_C_Z_LUT4_Z_B_CCU2C_B0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_FCI_INT (41,16) -> (41,16)
Info:                Sink SOC.Memory.memory.0.323_DO_LUT4_C_Z_LUT4_Z_B_CCU2C_B0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB1.FCI
Info:  0.0  6.2  Source SOC.Memory.memory.0.323_DO_LUT4_C_Z_LUT4_Z_B_CCU2C_B0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB1.FCO
Info:  0.0  6.2    Net SOC.Memory.memory.0.323_DO_LUT4_C_Z_LUT4_Z_B_CCU2C_B0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0_COUT (41,16) -> (42,16)
Info:                Sink SOC.Memory.memory.0.323_DO_LUT4_C_Z_LUT4_Z_B_CCU2C_B0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:42.3-49.2
Info:                  Risco-5/src/peripheral/bus.v:54.5-54.37
Info:                  Risco-5/src/peripheral/soc.v:51.5-81.2
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  6.3  Source SOC.Memory.memory.0.323_DO_LUT4_C_Z_LUT4_Z_B_CCU2C_B0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB0.FCO
Info:  0.0  6.3    Net SOC.Memory.memory.0.323_DO_LUT4_C_Z_LUT4_Z_B_CCU2C_B0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_FCI_INT (42,16) -> (42,16)
Info:                Sink SOC.Memory.memory.0.323_DO_LUT4_C_Z_LUT4_Z_B_CCU2C_B0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB1.FCI
Info:  0.0  6.3  Source SOC.Memory.memory.0.323_DO_LUT4_C_Z_LUT4_Z_B_CCU2C_B0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB1.FCO
Info:  0.0  6.3    Net SOC.Memory.memory.0.323_DO_LUT4_C_Z_LUT4_Z_B_CCU2C_B0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0_COUT (42,16) -> (42,16)
Info:                Sink SOC.Memory.memory.0.323_DO_LUT4_C_Z_LUT4_Z_B_CCU2C_B0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:42.3-49.2
Info:                  Risco-5/src/peripheral/bus.v:54.5-54.37
Info:                  Risco-5/src/peripheral/soc.v:51.5-81.2
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  6.3  Source SOC.Memory.memory.0.323_DO_LUT4_C_Z_LUT4_Z_B_CCU2C_B0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB0.FCO
Info:  0.0  6.3    Net SOC.Memory.memory.0.323_DO_LUT4_C_Z_LUT4_Z_B_CCU2C_B0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_FCI_INT (42,16) -> (42,16)
Info:                Sink SOC.Memory.memory.0.323_DO_LUT4_C_Z_LUT4_Z_B_CCU2C_B0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB1.FCI
Info:  0.0  6.3  Source SOC.Memory.memory.0.323_DO_LUT4_C_Z_LUT4_Z_B_CCU2C_B0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB1.FCO
Info:  0.0  6.3    Net SOC.Memory.memory.0.323_DO_LUT4_C_Z_LUT4_Z_B_CCU2C_B0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0_COUT (42,16) -> (42,16)
Info:                Sink SOC.Memory.memory.0.323_DO_LUT4_C_Z_LUT4_Z_B_CCU2C_B0_2_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:42.3-49.2
Info:                  Risco-5/src/peripheral/bus.v:54.5-54.37
Info:                  Risco-5/src/peripheral/soc.v:51.5-81.2
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  6.4  Source SOC.Memory.memory.0.323_DO_LUT4_C_Z_LUT4_Z_B_CCU2C_B0_2_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB0.FCO
Info:  0.0  6.4    Net SOC.Memory.memory.0.323_DO_LUT4_C_Z_LUT4_Z_B_CCU2C_B0_2_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_FCI_INT (42,16) -> (42,16)
Info:                Sink SOC.Memory.memory.0.323_DO_LUT4_C_Z_LUT4_Z_B_CCU2C_B0_2_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB1.FCI
Info:  0.0  6.4  Source SOC.Memory.memory.0.323_DO_LUT4_C_Z_LUT4_Z_B_CCU2C_B0_2_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0$CCU2_COMB1.FCO
Info:  0.0  6.4    Net SOC.Memory.memory.0.323_DO_LUT4_C_Z_LUT4_Z_B_CCU2C_B0_2_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B0_CCU2C_B0_COUT (42,16) -> (42,16)
Info:                Sink SOC.Core.ALU_Control.aluop_out_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z_C_LUT4_D_Z_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:42.3-49.2
Info:                  Risco-5/src/peripheral/bus.v:54.5-54.37
Info:                  Risco-5/src/peripheral/soc.v:51.5-81.2
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  6.5  Source SOC.Core.ALU_Control.aluop_out_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z_C_LUT4_D_Z_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info:  0.0  6.5    Net SOC.Core.ALU_Control.aluop_out_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z_C_LUT4_D_Z_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (42,16) -> (42,16)
Info:                Sink SOC.Core.ALU_Control.aluop_out_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z_C_LUT4_D_Z_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info:  0.0  6.5  Source SOC.Core.ALU_Control.aluop_out_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z_C_LUT4_D_Z_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info:  0.0  6.5    Net SOC.Core.ALU_Control.aluop_out_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z_C_LUT4_D_Z_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_COUT (42,16) -> (43,16)
Info:                Sink SOC.Core.ALU_Control.aluop_out_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z_C_LUT4_D_Z_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:42.3-49.2
Info:                  Risco-5/src/peripheral/bus.v:54.5-54.37
Info:                  Risco-5/src/peripheral/soc.v:51.5-81.2
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  6.5  Source SOC.Core.ALU_Control.aluop_out_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z_C_LUT4_D_Z_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info:  0.0  6.5    Net SOC.Core.ALU_Control.aluop_out_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z_C_LUT4_D_Z_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (43,16) -> (43,16)
Info:                Sink SOC.Core.ALU_Control.aluop_out_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z_C_LUT4_D_Z_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info:  0.0  6.5  Source SOC.Core.ALU_Control.aluop_out_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z_C_LUT4_D_Z_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info:  0.0  6.5    Net SOC.Core.ALU_Control.aluop_out_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z_C_LUT4_D_Z_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_COUT (43,16) -> (43,16)
Info:                Sink SOC.Core.ALU_Control.aluop_out_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z_C_LUT4_D_Z_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:42.3-49.2
Info:                  Risco-5/src/peripheral/bus.v:54.5-54.37
Info:                  Risco-5/src/peripheral/soc.v:51.5-81.2
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  6.6  Source SOC.Core.ALU_Control.aluop_out_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z_C_LUT4_D_Z_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info:  0.0  6.6    Net SOC.Core.ALU_Control.aluop_out_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z_C_LUT4_D_Z_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (43,16) -> (43,16)
Info:                Sink SOC.Core.ALU_Control.aluop_out_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z_C_LUT4_D_Z_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info:  0.0  6.6  Source SOC.Core.ALU_Control.aluop_out_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z_C_LUT4_D_Z_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info:  0.0  6.6    Net SOC.Core.ALU_Control.aluop_out_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z_C_LUT4_D_Z_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_COUT (43,16) -> (43,16)
Info:                Sink SOC.Core.ALU_Control.aluop_out_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z_C_LUT4_D_Z_LUT4_Z_C_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:42.3-49.2
Info:                  Risco-5/src/peripheral/bus.v:54.5-54.37
Info:                  Risco-5/src/peripheral/soc.v:51.5-81.2
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  6.7  Source SOC.Core.ALU_Control.aluop_out_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z_C_LUT4_D_Z_LUT4_Z_C_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info:  0.0  6.7    Net SOC.Core.ALU_Control.aluop_out_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z_C_LUT4_D_Z_LUT4_Z_C_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (43,16) -> (43,16)
Info:                Sink SOC.Core.ALU_Control.aluop_out_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z_C_LUT4_D_Z_LUT4_Z_C_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info:  0.0  6.7  Source SOC.Core.ALU_Control.aluop_out_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z_C_LUT4_D_Z_LUT4_Z_C_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info:  0.0  6.7    Net $nextpnr_CCU2C_19$CIN (43,16) -> (43,16)
Info:                Sink $nextpnr_CCU2C_19$CCU2_COMB0.FCI
Info:  0.4  7.1  Source $nextpnr_CCU2C_19$CCU2_COMB0.F
Info:  2.8  9.9    Net SOC.Memory.address_LUT4_Z_1_C[1] (43,16) -> (14,25)
Info:                Sink SOC.Memory.address_LUT4_Z_2.D
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2 10.1  Source SOC.Memory.address_LUT4_Z_2.F
Info:  2.9 13.0    Net SOC.slave_address[3] (14,25) -> (5,5)
Info:                Sink SOC.Memory.memory.0.414$DPRAM_COMB2.B
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:42.3-49.2
Info:                  Risco-5/src/peripheral/soc.v:21.5-21.18
Info:  0.2 13.3  Source SOC.Memory.memory.0.414$DPRAM_COMB2.F
Info:  1.1 14.4    Net SOC.Memory.memory.0.414_DO_1[3] (5,5) -> (4,6)
Info:                Sink SOC.Memory.memory.0.390_DO_1_LUT4_Z_1.D
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2 14.6  Source SOC.Memory.memory.0.390_DO_1_LUT4_Z_1.F
Info:  0.7 15.3    Net SOC.Memory.memory.0.390_DO_1[4] (4,6) -> (4,7)
Info:                Sink SOC.Memory.memory.0.446_DO_PFUMX_Z_BLUT_LUT4_Z.M
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.3 15.6  Source SOC.Memory.memory.0.446_DO_PFUMX_Z_BLUT_LUT4_Z.OFX
Info:  0.8 16.4    Net SOC.Memory.memory.0.446_DO[3] (4,7) -> (4,8)
Info:                Sink SOC.Memory.memory.0.446_DO_LUT4_B.D
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2 16.7  Source SOC.Memory.memory.0.446_DO_LUT4_B.F
Info:  0.9 17.5    Net SOC.Core.read_data_LUT4_Z_24_D_LUT4_Z_C_PFUMX_Z_C0[1] (4,8) -> (6,8)
Info:                Sink SOC.Core.read_data_LUT4_Z_24_D_LUT4_Z_C_PFUMX_Z_ALUT_LUT4_Z.C
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2 17.8  Source SOC.Core.read_data_LUT4_Z_24_D_LUT4_Z_C_PFUMX_Z_ALUT_LUT4_Z.F
Info:  0.0 17.8    Net SOC.Core.read_data_LUT4_Z_24_D_LUT4_Z_C_PFUMX_Z_ALUT (6,8) -> (6,8)
Info:                Sink SOC.Core.read_data_LUT4_Z_24_D_LUT4_Z_C_PFUMX_Z_BLUT_LUT4_Z.F1
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:133.22-133.24
Info:  0.2 17.9  Source SOC.Core.read_data_LUT4_Z_24_D_LUT4_Z_C_PFUMX_Z_BLUT_LUT4_Z.OFX
Info:  1.0 18.9    Net SOC.Core.read_data_LUT4_Z_24_D_LUT4_Z_C[1] (6,8) -> (11,9)
Info:                Sink SOC.Core.read_data_LUT4_Z_24_D_LUT4_Z.C
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2 19.2  Source SOC.Core.read_data_LUT4_Z_24_D_LUT4_Z.F
Info:  1.8 21.0    Net SOC.Core.read_data_LUT4_Z_24_D[3] (11,9) -> (27,11)
Info:                Sink SOC.Core.read_data_LUT4_Z_24.D
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2 21.2  Source SOC.Core.read_data_LUT4_Z_24.F
Info:  1.0 22.2    Net SOC.read_data[26] (27,11) -> (28,14)
Info:                Sink SOC.Core.instruction_register_TRELLIS_FF_Q_5.M
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:42.3-49.2
Info:                  Risco-5/src/peripheral/soc.v:20.34-20.43
Info:  0.0 22.2  Setup SOC.Core.instruction_register_TRELLIS_FF_Q_5.M
Info: 4.6 ns logic, 17.6 ns routing

Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
Info: curr total
Info:  0.5  0.5  Source ClkDivider.clk_counter_TRELLIS_FF_Q_27.Q
Info:  1.2  1.7    Net ClkDivider.clk_counter[4] (47,3) -> (48,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.B
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:15.3-23.2
Info:                  Risco-5/debug/clk_divider.v:14.26-14.37
Info:  0.4  2.1  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info:  0.0  2.1    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (48,2) -> (48,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info:  0.0  2.1  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info:  0.0  2.1    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (48,2) -> (48,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:15.3-23.2
Info:                  Risco-5/debug/clk_divider.v:40.12-40.38
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  2.2  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info:  0.0  2.2    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (48,2) -> (48,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info:  0.0  2.2  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info:  0.0  2.2    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (48,2) -> (48,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:15.3-23.2
Info:                  Risco-5/debug/clk_divider.v:40.12-40.38
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  2.3  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info:  0.0  2.3    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (48,2) -> (48,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info:  0.0  2.3  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info:  0.0  2.3    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (48,2) -> (49,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:15.3-23.2
Info:                  Risco-5/debug/clk_divider.v:40.12-40.38
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  2.3  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info:  0.0  2.3    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (49,2) -> (49,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info:  0.0  2.3  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info:  0.0  2.3    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (49,2) -> (49,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:15.3-23.2
Info:                  Risco-5/debug/clk_divider.v:40.12-40.38
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  2.4  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info:  0.0  2.4    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (49,2) -> (49,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info:  0.0  2.4  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info:  0.0  2.4    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (49,2) -> (49,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:15.3-23.2
Info:                  Risco-5/debug/clk_divider.v:40.12-40.38
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  2.5  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info:  0.0  2.5    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (49,2) -> (49,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info:  0.0  2.5  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info:  0.0  2.5    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (49,2) -> (49,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:15.3-23.2
Info:                  Risco-5/debug/clk_divider.v:40.12-40.38
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  2.5  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info:  0.0  2.5    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (49,2) -> (49,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info:  0.0  2.5  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info:  0.0  2.5    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (49,2) -> (50,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:15.3-23.2
Info:                  Risco-5/debug/clk_divider.v:40.12-40.38
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  2.6  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info:  0.0  2.6    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (50,2) -> (50,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info:  0.0  2.6  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info:  0.0  2.6    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (50,2) -> (50,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:15.3-23.2
Info:                  Risco-5/debug/clk_divider.v:40.12-40.38
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  2.7  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info:  0.0  2.7    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (50,2) -> (50,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info:  0.0  2.7  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info:  0.0  2.7    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (50,2) -> (50,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:15.3-23.2
Info:                  Risco-5/debug/clk_divider.v:40.12-40.38
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  2.8  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info:  0.0  2.8    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (50,2) -> (50,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info:  0.0  2.8  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info:  0.0  2.8    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (50,2) -> (50,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:15.3-23.2
Info:                  Risco-5/debug/clk_divider.v:40.12-40.38
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  2.8  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info:  0.0  2.8    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (50,2) -> (50,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info:  0.0  2.8  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info:  0.0  2.8    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (50,2) -> (51,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:15.3-23.2
Info:                  Risco-5/debug/clk_divider.v:40.12-40.38
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  2.9  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info:  0.0  2.9    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (51,2) -> (51,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info:  0.0  2.9  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info:  0.0  2.9    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN (51,2) -> (51,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:15.3-23.2
Info:                  Risco-5/debug/clk_divider.v:40.12-40.38
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  3.0  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info:  0.0  3.0    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (51,2) -> (51,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info:  0.0  3.0  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info:  0.0  3.0    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN (51,2) -> (51,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:15.3-23.2
Info:                  Risco-5/debug/clk_divider.v:40.12-40.38
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  3.0  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT$CCU2_COMB0.FCO
Info:  0.0  3.0    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT$CCU2_FCI_INT (51,2) -> (51,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT$CCU2_COMB1.FCI
Info:  0.0  3.0  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT$CCU2_COMB1.FCO
Info:  0.0  3.0    Net $nextpnr_CCU2C_3$CIN (51,2) -> (51,2)
Info:                Sink $nextpnr_CCU2C_3$CCU2_COMB0.FCI
Info:  0.4  3.5  Source $nextpnr_CCU2C_3$CCU2_COMB0.F
Info:  0.7  4.2    Net reset_LUT4_B_C_LUT4_Z_D (51,2) -> (51,4)
Info:                Sink reset_LUT4_B_C_LUT4_Z.D
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2  4.4  Source reset_LUT4_B_C_LUT4_Z.F
Info:  0.9  5.3    Net reset_LUT4_B_C[1] (51,4) -> (49,4)
Info:                Sink reset_LUT4_B.C
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2  5.5  Source reset_LUT4_B.F
Info:  0.7  6.2    Net reset_LUT4_B_Z (49,4) -> (49,3)
Info:                Sink ClkDivider.clk_counter_TRELLIS_FF_Q_17.LSR
Info:  0.4  6.6  Setup ClkDivider.clk_counter_TRELLIS_FF_Q_17.LSR
Info: 3.2 ns logic, 3.3 ns routing

Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
Info: curr total
Info:  0.0  0.0  Source reset$tr_io.O
Info:  3.8  3.8    Net reset$TRELLIS_IO_IN (0,29) -> (49,4)
Info:                Sink reset_LUT4_B.B
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2  4.0  Source reset_LUT4_B.F
Info:  0.7  4.7    Net reset_LUT4_B_Z (49,4) -> (49,3)
Info:                Sink ClkDivider.clk_counter_TRELLIS_FF_Q_17.LSR
Info:  0.4  5.1  Setup ClkDivider.clk_counter_TRELLIS_FF_Q_17.LSR
Info: 0.7 ns logic, 4.4 ns routing

Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk_o':
Info: curr total
Info:  0.0  0.0  Source gpios[2]$tr_io.O
Info:  5.0  5.0    Net gpios[2]$TRELLIS_IO_IN (90,23) -> (26,16)
Info:                Sink SOC.Core.read_data_LUT4_Z_1.A
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:7.16-7.21
Info:  0.2  5.2  Source SOC.Core.read_data_LUT4_Z_1.F
Info:  0.9  6.1    Net SOC.read_data[2] (26,16) -> (28,15)
Info:                Sink SOC.Core.instruction_register_TRELLIS_FF_Q_29.M
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:42.3-49.2
Info:                  Risco-5/src/peripheral/soc.v:20.34-20.43
Info:  0.0  6.1  Setup SOC.Core.instruction_register_TRELLIS_FF_Q_29.M
Info: 0.2 ns logic, 5.9 ns routing

Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
Info: curr total
Info:  0.5  0.5  Source ClkDivider.clk_o_auto_TRELLIS_FF_Q.Q
Info:  1.7  2.2    Net clk_o (48,4) -> (55,14)
Info:                Sink led_LUT4_Z_3.D
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:10.6-10.11
Info:  0.2  2.5  Source led_LUT4_Z_3.F
Info:  3.0  5.4    Net led[7]$TRELLIS_IO_OUT (55,14) -> (90,20)
Info:                Sink led[7]$tr_io.I
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:6.22-6.25
Info: 0.8 ns logic, 4.7 ns routing

Info: Critical path report for cross-domain path 'posedge $glbnet$clk_o' -> '<async>':
Info: curr total
Info:  0.5  0.5  Source SOC.GPIOS.Gpios[2].direction_TRELLIS_FF_Q.Q
Info:  3.0  3.5    Net SOC.Core.read_data_LUT4_Z_1_D[1] (25,16) -> (53,23)
Info:                Sink SOC.GPIOS.Gpios[2].direction_LUT4_D.D
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:42.3-49.2
Info:                  Risco-5/src/peripheral/gpios.v:14.19-14.33
Info:                  Risco-5/src/peripheral/soc.v:111.3-120.2
Info:  0.2  3.7  Source SOC.GPIOS.Gpios[2].direction_LUT4_D.F
Info:  1.8  5.5    Net gpios_$_TBUF__Y_3_E (53,23) -> (78,23)
Info:                Sink gpios[2]$tr_io$invert_T.A
Info:  0.2  5.8  Source gpios[2]$tr_io$invert_T.F
Info:  1.5  7.3    Net gpios[2]$tr_io$invert_T$conn$Z (78,23) -> (90,23)
Info:                Sink gpios[2]$tr_io.T
Info: 1.0 ns logic, 6.3 ns routing

Info: Max frequency for clock             '$glbnet$clk_o': 45.01 MHz (PASS at 12.00 MHz)
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 152.00 MHz (PASS at 25.00 MHz)

Info: Max delay <async>                           -> posedge $glbnet$clk$TRELLIS_IO_IN: 5.10 ns
Info: Max delay <async>                           -> posedge $glbnet$clk_o            : 6.14 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async>                          : 5.44 ns
Info: Max delay posedge $glbnet$clk_o             -> <async>                          : 7.27 ns

Info: Slack histogram:
Info:  legend: * represents 165 endpoint(s)
Info:          + represents [1,165) endpoint(s)
Info: [ 33421,  35870) |+
Info: [ 35870,  38319) |+
Info: [ 38319,  40768) |+
Info: [ 40768,  43217) | 
Info: [ 43217,  45666) | 
Info: [ 45666,  48115) | 
Info: [ 48115,  50564) | 
Info: [ 50564,  53013) | 
Info: [ 53013,  55462) | 
Info: [ 55462,  57911) | 
Info: [ 57911,  60360) | 
Info: [ 60360,  62809) |+
Info: [ 62809,  65258) |+
Info: [ 65258,  67707) |+
Info: [ 67707,  70156) |**************+
Info: [ 70156,  72605) |************************************************************ 
Info: [ 72605,  75054) |**+
Info: [ 75054,  77503) |**********+
Info: [ 77503,  79952) |*+
Info: [ 79952,  82401) |*+

Info: Program finished normally.
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (ECPPACK)
[Pipeline] sh
+ /eda/oss-cad-suite/bin/ecppack --compress --input ./build/out.config --bit ./build/out.bit
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (FPGA Flash)
[Pipeline] parallel
[Pipeline] { (Branch: openFPGAloader ECP5)
[Pipeline] { (Branch: openFPGAloader Tangnano 20k)
[Pipeline] stage
[Pipeline] { (openFPGAloader ECP5)
[Pipeline] stage
[Pipeline] { (openFPGAloader Tangnano 20k)
[Pipeline] script
[Pipeline] {
[Pipeline] script
[Pipeline] {
[Pipeline] lock
Trying to acquire lock on [ecp5]
Resource [ecp5] did not exist. Created.
Lock acquired on [ecp5]
[Pipeline] {
[Pipeline] lock
Trying to acquire lock on [tangnano20k]
Resource [tangnano20k] did not exist. Created.
Lock acquired on [tangnano20k]
[Pipeline] {
[Pipeline] echo
FPGA ECP5 Broqueada
[Pipeline] sh
[Pipeline] echo
FPGA TangNano Broqueada
[Pipeline] sh
+ /eda/oss-cad-suite/bin/openFPGALoader -b colorlight-i9 ./build/out.bit
Found 1 compatible device:
	0x0d28 0x0204 0x3 DAPLink CMSIS-DAP
Open file: DONE
Parse file: DONE
Enable configuration: DONE
SRAM erase: DONE
+ echo gravando na tang nano
gravando na tang nano
[Pipeline] }
Lock released on resource [tangnano20k]
[Pipeline] // lock
[Pipeline] }
[Pipeline] // script
[Pipeline] }
[Pipeline] // stage
[Pipeline] }

Loading: [=====                                             ] 9.49%
Loading: [==========                                        ] 18.98%
Loading: [===============                                   ] 28.47%
Loading: [===================                               ] 37.97%
Loading: [========================                          ] 47.46%
Loading: [=============================                     ] 56.95%
Loading: [==================================                ] 66.44%
Loading: [======================================            ] 75.93%
Loading: [===========================================       ] 85.42%
Loading: [================================================  ] 94.92%
Loading: [==================================================] 100.00%
Done
Disable configuration: DONE
[Pipeline] }
Lock released on resource [ecp5]
[Pipeline] // lock
[Pipeline] }
[Pipeline] // script
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Testes)
[Pipeline] parallel
[Pipeline] { (Branch: ECP5 - Testes)
[Pipeline] { (Branch: TangNano - Testes)
[Pipeline] stage
[Pipeline] { (ECP5 - Testes)
[Pipeline] stage
[Pipeline] { (TangNano - Testes)
[Pipeline] script
[Pipeline] {
[Pipeline] script
[Pipeline] {
[Pipeline] echo
Rodando teste na ECP5
[Pipeline] lock
Trying to acquire lock on [ecp5]
Resource [ecp5] did not exist. Created.
Lock acquired on [ecp5]
[Pipeline] {
[Pipeline] echo
Rodando teste na tang nano
[Pipeline] lock
Trying to acquire lock on [tangnano20k]
Resource [tangnano20k] did not exist. Created.
Lock acquired on [tangnano20k]
[Pipeline] {
[Pipeline] echo
FPGA ECP5 Broqueada
[Pipeline] sh
[Pipeline] echo
FPGA TangNano Broqueada
[Pipeline] sh
+ echo testando na ecp5
testando na ecp5
[Pipeline] }
Lock released on resource [ecp5]
+ echo testando na tang nano
testando na tang nano
[Pipeline] // lock
[Pipeline] echo
ECP5 liberada
[Pipeline] }
[Pipeline] }
Lock released on resource [tangnano20k]
[Pipeline] // script
[Pipeline] // lock
[Pipeline] }
[Pipeline] echo
TangNano liberada
[Pipeline] }
[Pipeline] // stage
[Pipeline] // script
[Pipeline] }
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // node
[Pipeline] End of Pipeline
Finished: SUCCESS