Console Output
+ /eda/oss-cad-suite/bin/nextpnr-ecp5 --json ./build/out.json --write ./build/out_pnr.json --45k --lpf Risco-5/fpga/ecp5/pinout.lpf --textcfg ./build/out.config --package CABGA381 --speed 6
Info: constraining clock net 'clk' to 25.00 MHz
Info: Logic utilisation before packing:
Info: Total LUT4s: 8869/43848 20%
Info: logic LUTs: 5533/43848 12%
Info: carry LUTs: 264/43848 0%
Info: RAM LUTs: 2048/ 5481 37%
Info: RAMW LUTs: 1024/10962 9%
Info: Total DFFs: 1291/43848 2%
Info: Packing IOs..
Info: pin 'tx$tr_io' constrained to Bel 'X90/Y20/PIOC'.
Info: pin 'rx$tr_io' constrained to Bel 'X90/Y20/PIOA'.
Info: pin 'reset$tr_io' constrained to Bel 'X0/Y29/PIOA'.
Info: pin 'led[7]$tr_io' constrained to Bel 'X90/Y20/PIOD'.
Info: pin 'led[6]$tr_io' constrained to Bel 'X0/Y44/PIOD'.
Info: pin 'led[5]$tr_io' constrained to Bel 'X0/Y59/PIOA'.
Info: pin 'led[4]$tr_io' constrained to Bel 'X15/Y71/PIOB'.
Info: pin 'led[3]$tr_io' constrained to Bel 'X90/Y29/PIOC'.
Info: pin 'led[2]$tr_io' constrained to Bel 'X90/Y44/PIOB'.
Info: pin 'led[1]$tr_io' constrained to Bel 'X0/Y44/PIOC'.
Info: pin 'led[0]$tr_io' constrained to Bel 'X0/Y59/PIOC'.
Info: pin 'clk$tr_io' constrained to Bel 'X0/Y68/PIOC'.
Info: Packing constants..
Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info: 263 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info: Promoting globals...
Info: promoting clock net clk_o to global network
Info: promoting clock net clk$TRELLIS_IO_IN to global network
Info: Checksum: 0x0a832edc
Info: Device utilisation:
Info: TRELLIS_IO: 12/ 245 4%
Info: DCCA: 2/ 56 3%
Info: DP16KD: 0/ 108 0%
Info: MULT18X18D: 0/ 72 0%
Info: ALU54B: 0/ 36 0%
Info: EHXPLLL: 0/ 4 0%
Info: EXTREFB: 0/ 2 0%
Info: DCUA: 0/ 2 0%
Info: PCSCLKDIV: 0/ 2 0%
Info: IOLOGIC: 0/ 160 0%
Info: SIOLOGIC: 0/ 85 0%
Info: GSR: 0/ 1 0%
Info: JTAGG: 0/ 1 0%
Info: OSCG: 0/ 1 0%
Info: SEDGA: 0/ 1 0%
Info: DTR: 0/ 1 0%
Info: USRMCLK: 0/ 1 0%
Info: CLKDIVF: 0/ 4 0%
Info: ECLKSYNCB: 0/ 10 0%
Info: DLLDELD: 0/ 8 0%
Info: DDRDLL: 0/ 4 0%
Info: DQSBUFM: 0/ 10 0%
Info: TRELLIS_ECLKBUF: 0/ 8 0%
Info: ECLKBRIDGECS: 0/ 2 0%
Info: DCSC: 0/ 2 0%
Info: TRELLIS_FF: 1291/43848 2%
Info: TRELLIS_COMB: 8919/43848 20%
Info: TRELLIS_RAMW: 512/ 5481 9%
Info: Placed 12 cells based on constraints.
Info: Creating initial analytic placement for 5352 cells, random placement wirelen = 448469.
Info: at initial placer iter 0, wirelen = 1031
Info: at initial placer iter 1, wirelen = 956
Info: at initial placer iter 2, wirelen = 1112
Info: at initial placer iter 3, wirelen = 1146
Info: Running main analytical placer, max placement attempts per cell = 14407712.
Info: at iteration #1, type ALL: wirelen solved = 1183, spread = 69322, legal = 70040; time = 0.27s
Info: at iteration #2, type ALL: wirelen solved = 4630, spread = 48043, legal = 49049; time = 0.31s
Info: at iteration #3, type ALL: wirelen solved = 11069, spread = 43139, legal = 44150; time = 0.30s
Info: at iteration #4, type ALL: wirelen solved = 13423, spread = 42676, legal = 43750; time = 0.29s
Info: at iteration #5, type ALL: wirelen solved = 15549, spread = 39468, legal = 40469; time = 0.28s
Info: at iteration #6, type ALL: wirelen solved = 16622, spread = 37283, legal = 38795; time = 0.28s
Info: at iteration #7, type ALL: wirelen solved = 17886, spread = 39244, legal = 39982; time = 0.28s
Info: at iteration #8, type ALL: wirelen solved = 19682, spread = 38584, legal = 39316; time = 0.28s
Info: at iteration #9, type ALL: wirelen solved = 20648, spread = 40100, legal = 40776; time = 0.28s
Info: at iteration #10, type ALL: wirelen solved = 21914, spread = 41036, legal = 41688; time = 0.28s
Info: at iteration #11, type ALL: wirelen solved = 22606, spread = 42519, legal = 43094; time = 0.27s
Info: HeAP Placer Time: 5.29s
Info: of which solving equations: 3.32s
Info: of which spreading cells: 0.41s
Info: of which strict legalisation: 0.12s
Info: Running simulated annealing placer for refinement.
Info: at iteration #1: temp = 0.000000, timing cost = 10751, wirelen = 38795
Info: at iteration #5: temp = 0.000000, timing cost = 12100, wirelen = 31492
Info: at iteration #10: temp = 0.000000, timing cost = 10343, wirelen = 29857
Info: at iteration #15: temp = 0.000000, timing cost = 10632, wirelen = 28992
Info: at iteration #20: temp = 0.000000, timing cost = 10398, wirelen = 28303
Info: at iteration #25: temp = 0.000000, timing cost = 10594, wirelen = 28064
Info: at iteration #30: temp = 0.000000, timing cost = 9094, wirelen = 27940
Info: at iteration #33: temp = 0.000000, timing cost = 9039, wirelen = 27911
Info: SA placement time 33.06s
Info: Max frequency for clock '$glbnet$clk_o': 27.82 MHz (PASS at 12.00 MHz)
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 143.78 MHz (PASS at 25.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 11.51 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 9.52 ns
Info: Max delay posedge $glbnet$clk_o -> <async> : 13.84 ns
Info: Slack histogram:
Info: legend: * represents 88 endpoint(s)
Info: + represents [1,88) endpoint(s)
Info: [ 33045, 35522) |+
Info: [ 35522, 37999) |+
Info: [ 37999, 40476) |+
Info: [ 40476, 42953) |
Info: [ 42953, 45430) |
Info: [ 45430, 47907) |+
Info: [ 47907, 50384) |+
Info: [ 50384, 52861) |+
Info: [ 52861, 55338) |+
Info: [ 55338, 57815) |******+
Info: [ 57815, 60292) |*************+
Info: [ 60292, 62769) |**********************************************************+
Info: [ 62769, 65246) |************************************************************
Info: [ 65246, 67723) |******+
Info: [ 67723, 70200) |*****+
Info: [ 70200, 72677) |**+
Info: [ 72677, 75154) |****+
Info: [ 75154, 77631) |*******+
Info: [ 77631, 80108) |**+
Info: [ 80108, 82585) |+
Info: Checksum: 0x2038011c
Info: Routing globals...
Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
Info: routing clock net $glbnet$clk_o using global 1
Info: Routing..
Info: Setting up routing queue.
Info: Routing 43137 arcs.
Info: | (re-)routed arcs | delta | remaining| time spent |
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
Info: 1000 | 161 838 | 161 838 | 42812| 0.68 0.68|
Info: 2000 | 240 1759 | 79 921 | 42557| 0.15 0.83|
Info: 3000 | 409 2590 | 169 831 | 42461| 0.16 0.98|
Info: 4000 | 572 3427 | 163 837 | 42359| 0.16 1.14|
Info: 5000 | 736 4263 | 164 836 | 41827| 0.15 1.29|
Info: 6000 | 913 5086 | 177 823 | 41294| 0.16 1.46|
Info: 7000 | 1080 5919 | 167 833 | 41502| 0.17 1.63|
Info: 8000 | 1255 6744 | 175 825 | 40976| 0.16 1.78|
Info: 9000 | 1457 7542 | 202 798 | 40670| 0.17 1.95|
Info: 10000 | 1568 8431 | 111 889 | 40916| 0.16 2.12|
Info: 11000 | 1668 9331 | 100 900 | 40298| 0.16 2.28|
Info: 12000 | 1845 10154 | 177 823 | 39880| 0.18 2.46|
Info: 13000 | 2054 10945 | 209 791 | 39705| 0.16 2.62|
Info: 14000 | 2226 11773 | 172 828 | 39571| 0.17 2.79|
Info: 15000 | 2303 12696 | 77 923 | 39456| 0.16 2.95|
Info: 16000 | 2468 13531 | 165 835 | 39089| 0.16 3.11|
Info: 17000 | 2638 14361 | 170 830 | 38538| 0.17 3.29|
Info: 18000 | 2822 15177 | 184 816 | 38447| 0.19 3.47|
Info: 19000 | 3003 15996 | 181 819 | 38071| 0.18 3.65|
Info: 20000 | 3173 16826 | 170 830 | 37742| 0.17 3.83|
Info: 21000 | 3228 17771 | 55 945 | 37694| 0.17 3.99|
Info: 22000 | 3420 18579 | 192 808 | 37422| 0.19 4.18|
Info: 23000 | 3582 19417 | 162 838 | 37819| 0.19 4.37|
Info: 24000 | 3671 20328 | 89 911 | 38241| 0.16 4.52|
Info: 25000 | 3724 21275 | 53 947 | 37825| 0.14 4.67|
Info: 26000 | 3877 22122 | 153 847 | 37457| 0.17 4.83|
Info: 27000 | 4008 22991 | 131 869 | 37599| 0.17 5.00|
Info: 28000 | 4168 23831 | 160 840 | 37085| 0.17 5.17|
Info: 29000 | 4394 24605 | 226 774 | 36797| 0.20 5.37|
Info: 30000 | 4532 25467 | 138 862 | 36701| 0.20 5.58|
Info: 31000 | 4722 26277 | 190 810 | 36429| 0.17 5.75|
Info: 32000 | 4962 27037 | 240 760 | 35965| 0.19 5.94|
Info: 33000 | 5134 27865 | 172 828 | 35677| 0.18 6.12|
Info: 34000 | 5294 28705 | 160 840 | 35719| 0.20 6.32|
Info: 35000 | 5529 29470 | 235 765 | 35362| 0.20 6.52|
Info: 36000 | 5785 30214 | 256 744 | 35120| 0.19 6.72|
Info: 37000 | 6032 30967 | 247 753 | 34654| 0.20 6.92|
Info: 38000 | 6278 31721 | 246 754 | 34137| 0.21 7.13|
Info: 39000 | 6502 32497 | 224 776 | 33718| 0.19 7.33|
Info: 40000 | 6703 33296 | 201 799 | 33370| 0.20 7.53|
Info: 41000 | 6952 34047 | 249 751 | 33030| 0.21 7.74|
Info: 42000 | 7179 34820 | 227 773 | 32753| 0.20 7.94|
Info: 43000 | 7390 35609 | 211 789 | 32554| 0.21 8.15|
Info: 44000 | 7640 36359 | 250 750 | 32116| 0.21 8.35|
Info: 45000 | 7965 37034 | 325 675 | 32020| 0.22 8.57|
Info: 46000 | 8232 37767 | 267 733 | 31694| 0.22 8.79|
Info: 47000 | 8518 38481 | 286 714 | 31333| 0.22 9.02|
Info: 48000 | 8853 39146 | 335 665 | 31075| 0.22 9.24|
Info: 49000 | 9141 39858 | 288 712 | 30718| 0.22 9.46|
Info: 50000 | 9460 40539 | 319 681 | 30466| 0.25 9.71|
Info: 51000 | 9827 41172 | 367 633 | 30262| 0.26 9.97|
Info: 52000 | 10117 41882 | 290 710 | 29964| 0.24 10.21|
Info: 53000 | 10446 42553 | 329 671 | 29915| 0.24 10.45|
Info: 54000 | 10687 43312 | 241 759 | 29640| 0.20 10.66|
Info: 55000 | 10719 44280 | 32 968 | 30061| 0.16 10.81|
Info: 56000 | 10760 45239 | 41 959 | 29567| 0.16 10.98|
Info: 57000 | 11027 45972 | 267 733 | 29360| 0.23 11.21|
Info: 58000 | 11318 46681 | 291 709 | 29114| 0.23 11.44|
Info: 59000 | 11626 47373 | 308 692 | 28814| 0.24 11.67|
Info: 60000 | 11959 48040 | 333 667 | 28456| 0.27 11.94|
Info: 61000 | 12243 48756 | 284 716 | 28707| 0.26 12.20|
Info: 62000 | 12425 49574 | 182 818 | 28205| 0.20 12.41|
Info: 63000 | 12747 50252 | 322 678 | 27869| 0.24 12.64|
Info: 64000 | 12992 51007 | 245 755 | 27795| 0.23 12.88|
Info: 65000 | 13249 51750 | 257 743 | 27523| 0.24 13.11|
Info: 66000 | 13553 52446 | 304 696 | 27316| 0.27 13.38|
Info: 67000 | 13866 53133 | 313 687 | 27077| 0.25 13.63|
Info: 68000 | 14300 53699 | 434 566 | 27101| 0.32 13.96|
Info: 69000 | 14640 54359 | 340 660 | 26861| 0.26 14.22|
Info: 70000 | 14935 55064 | 295 705 | 26783| 0.29 14.51|
Info: 71000 | 15322 55677 | 387 613 | 26536| 0.32 14.83|
Info: 72000 | 15704 56295 | 382 618 | 26287| 0.29 15.12|
Info: 73000 | 16002 56997 | 298 702 | 25975| 0.24 15.36|
Info: 74000 | 16319 57680 | 317 683 | 25641| 0.26 15.62|
Info: 75000 | 16607 58392 | 288 712 | 25434| 0.27 15.89|
Info: 76000 | 16924 59075 | 317 683 | 25119| 0.27 16.16|
Info: 77000 | 17304 59695 | 380 620 | 24825| 0.28 16.44|
Info: 78000 | 17671 60328 | 367 633 | 24644| 0.31 16.75|
Info: 79000 | 18018 60981 | 347 653 | 24399| 0.31 17.06|
Info: 80000 | 18395 61604 | 377 623 | 24333| 0.36 17.42|
Info: 81000 | 18644 62355 | 249 751 | 24740| 0.25 17.67|
Info: 82000 | 18810 63189 | 166 834 | 24108| 0.24 17.91|
Info: 83000 | 19078 63921 | 268 732 | 23882| 0.25 18.17|
Info: 84000 | 19411 64588 | 333 667 | 23742| 0.29 18.46|
Info: 85000 | 19752 65247 | 341 659 | 23471| 0.33 18.78|
Info: 86000 | 20145 65854 | 393 607 | 23540| 0.28 19.07|
Info: 87000 | 20511 66488 | 366 634 | 23220| 0.30 19.36|
Info: 88000 | 20765 67234 | 254 746 | 23126| 0.28 19.64|
Info: 89000 | 21129 67870 | 364 636 | 23024| 0.33 19.97|
Info: 90000 | 21476 68523 | 347 653 | 22904| 0.27 20.23|
Info: 91000 | 21868 69131 | 392 608 | 22658| 0.30 20.53|
Info: 92000 | 22229 69770 | 361 639 | 22385| 0.30 20.83|
Info: 93000 | 22567 70432 | 338 662 | 22153| 0.27 21.10|
Info: 94000 | 22888 71111 | 321 679 | 21891| 0.28 21.38|
Info: 95000 | 23279 71720 | 391 609 | 21690| 0.38 21.76|
Info: 96000 | 23678 72321 | 399 601 | 21446| 0.34 22.09|
Info: 97000 | 24028 72971 | 350 650 | 21679| 0.31 22.40|
Info: 98000 | 24258 73741 | 230 770 | 21395| 0.26 22.66|
Info: 99000 | 24615 74384 | 357 643 | 21192| 0.32 22.98|
Info: 100000 | 24940 75059 | 325 675 | 20972| 0.30 23.27|
Info: 101000 | 25275 75724 | 335 665 | 20675| 0.29 23.56|
Info: 102000 | 25656 76343 | 381 619 | 20502| 0.29 23.85|
Info: 103000 | 25824 77175 | 168 832 | 20368| 0.25 24.09|
Info: 104000 | 26161 77838 | 337 663 | 20082| 0.28 24.37|
Info: 105000 | 26383 78616 | 222 778 | 21007| 0.24 24.61|
Info: 106000 | 26624 79375 | 241 759 | 20991| 0.25 24.86|
Info: 107000 | 26834 80165 | 210 790 | 20844| 0.25 25.12|
Info: 108000 | 27044 80955 | 210 790 | 20298| 0.25 25.37|
Info: 109000 | 27424 81575 | 380 620 | 19986| 0.32 25.70|
Info: 110000 | 27861 82138 | 437 563 | 19678| 0.27 25.97|
Info: 111000 | 28286 82713 | 425 575 | 19533| 0.33 26.30|
Info: 112000 | 28722 83277 | 436 564 | 19365| 0.29 26.58|
Info: 113000 | 29138 83861 | 416 584 | 19116| 0.28 26.86|
Info: 114000 | 29588 84411 | 450 550 | 19024| 0.33 27.19|
Info: 115000 | 29915 85084 | 327 673 | 18917| 0.29 27.49|
Info: 116000 | 30290 85709 | 375 625 | 18800| 0.29 27.78|
Info: 117000 | 30512 86487 | 222 778 | 18748| 0.27 28.05|
Info: 118000 | 30886 87113 | 374 626 | 18472| 0.27 28.32|
Info: 119000 | 31162 87837 | 276 724 | 18378| 0.27 28.59|
Info: 120000 | 31465 88534 | 303 697 | 18364| 0.30 28.89|
Info: 121000 | 31883 89116 | 418 582 | 18175| 0.31 29.20|
Info: 122000 | 32292 89707 | 409 591 | 17936| 0.28 29.48|
Info: 123000 | 32786 90213 | 494 506 | 17755| 0.30 29.79|
Info: 124000 | 33247 90752 | 461 539 | 17605| 0.27 30.05|
Info: 125000 | 33769 91230 | 522 478 | 17388| 0.30 30.36|
Info: 126000 | 34237 91762 | 468 532 | 17231| 0.32 30.68|
Info: 127000 | 34754 92245 | 517 483 | 17094| 0.29 30.97|
Info: 128000 | 35238 92761 | 484 516 | 16928| 0.33 31.29|
Info: 129000 | 35826 93173 | 588 412 | 16725| 0.27 31.56|
Info: 130000 | 36251 93748 | 425 575 | 16633| 0.31 31.87|
Info: 131000 | 36760 94239 | 509 491 | 16429| 0.27 32.14|
Info: 132000 | 37246 94753 | 486 514 | 16231| 0.31 32.45|
Info: 133000 | 37739 95260 | 493 507 | 16021| 0.27 32.72|
Info: 134000 | 38110 95889 | 371 629 | 16157| 0.27 32.99|
Info: 135000 | 38490 96509 | 380 620 | 15821| 0.30 33.29|
Info: 136000 | 38983 96994 | 493 485 | 15607| 0.30 33.58|
Info: 137000 | 39342 97635 | 359 641 | 15544| 0.31 33.89|
Info: 138000 | 39793 98171 | 451 536 | 15320| 0.32 34.21|
Info: 139000 | 40318 98599 | 525 428 | 15039| 0.29 34.50|
Info: 140000 | 40730 99180 | 412 581 | 15010| 0.42 34.92|
Info: 141000 | 41215 99641 | 485 461 | 14776| 0.31 35.23|
Info: 142000 | 41760 100072 | 545 431 | 14606| 0.31 35.54|
Info: 143000 | 42216 100564 | 456 492 | 14361| 0.29 35.83|
Info: 144000 | 42758 100942 | 542 378 | 13992| 0.29 36.12|
Info: 145000 | 43296 101346 | 538 404 | 13683| 0.25 36.37|
Info: 146000 | 43801 101764 | 505 418 | 13326| 0.25 36.62|
Info: 147000 | 44266 102226 | 465 462 | 12915| 0.24 36.86|
Info: 148000 | 44686 102720 | 420 494 | 12536| 0.26 37.11|
Info: 149000 | 45144 103198 | 458 478 | 12246| 0.28 37.39|
Info: 150000 | 45633 103657 | 489 459 | 12029| 0.27 37.67|
Info: 151000 | 46006 104275 | 373 618 | 11943| 0.36 38.03|
Info: 152000 | 46425 104841 | 419 566 | 11871| 0.40 38.43|
Info: 153000 | 46675 105533 | 250 692 | 12194| 0.27 38.70|
Info: 154000 | 46925 106283 | 250 750 | 11788| 0.32 39.02|
Info: 155000 | 47329 106851 | 404 568 | 11414| 0.29 39.32|
Info: 156000 | 47534 107601 | 205 750 | 10697| 0.19 39.50|
Info: 157000 | 47645 108479 | 111 878 | 9852| 0.12 39.63|
Info: 158000 | 47722 109394 | 77 915 | 8988| 0.13 39.75|
Info: 159000 | 47795 110315 | 73 921 | 8128| 0.14 39.90|
Info: 160000 | 47848 111259 | 53 944 | 7195| 0.11 40.01|
Info: 161000 | 47973 112129 | 125 870 | 6376| 0.15 40.16|
Info: 162000 | 48053 113048 | 80 919 | 5475| 0.14 40.30|
Info: 163000 | 48150 113946 | 97 898 | 4621| 0.15 40.44|
Info: 164000 | 48392 114683 | 242 737 | 4033| 0.26 40.70|
Info: 165000 | 48759 115312 | 367 629 | 3623| 0.34 41.04|
Info: 166000 | 49130 115939 | 371 627 | 3156| 0.33 41.38|
Info: 167000 | 49546 116510 | 416 571 | 2691| 0.33 41.70|
Info: 168000 | 50038 117005 | 492 495 | 2294| 0.37 42.08|
Info: 169000 | 50469 117560 | 431 555 | 1842| 0.33 42.40|
Info: 170000 | 50968 118054 | 499 494 | 1609| 0.46 42.86|
Info: 171000 | 51487 118535 | 519 481 | 1444| 0.45 43.31|
Info: 172000 | 51996 119025 | 509 490 | 1086| 0.39 43.70|
Info: 173000 | 52540 119481 | 544 456 | 869| 0.40 44.10|
Info: 174000 | 53113 119899 | 573 418 | 615| 0.44 44.54|
Info: 174943 | 53320 120256 | 207 357 | 0| 0.27 44.81|
Info: Routing complete.
Info: Router1 time 44.81s
Info: Checksum: 0x8f8648c6
Info: Critical path report for clock '$glbnet$clk_o' (posedge -> posedge):
Info: curr total
Info: 0.5 0.5 Source SOC.Core.Control_Unit.state_TRELLIS_FF_Q.Q
Info: 0.9 1.4 Net SOC.Core.ALU_Control.aluop_out_LUT4_Z_D_PFUMX_Z_C0_LUT4_C_1_B_LUT4_D_C_LUT4_D_A[0] (28,39) -> (28,39)
Info: Sink SOC.Core.ALU_Control.aluop_out_LUT4_Z_D_PFUMX_Z_C0_LUT4_C_1_B_LUT4_Z.B
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:40.3-46.2
Info: Risco-5/src/core/core.v:97.14-113.2
Info: Risco-5/src/core/control_unit.v:25.11-25.16
Info: Risco-5/src/peripheral/soc.v:25.3-33.2
Info: 0.2 1.6 Source SOC.Core.ALU_Control.aluop_out_LUT4_Z_D_PFUMX_Z_C0_LUT4_C_1_B_LUT4_Z.F
Info: 1.0 2.7 Net SOC.Core.ALU_Control.aluop_out_LUT4_Z_D_PFUMX_Z_C0_LUT4_C_1_B[3] (28,39) -> (30,36)
Info: Sink SOC.Core.ALU_Control.aluop_out_LUT4_Z_D_PFUMX_Z_C0_LUT4_C_1_B_LUT4_D.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 2.9 Source SOC.Core.ALU_Control.aluop_out_LUT4_Z_D_PFUMX_Z_C0_LUT4_C_1_B_LUT4_D.F
Info: 2.3 5.2 Net SOC.Core.ALU_Control.aluop_out_LUT4_Z_D_PFUMX_Z_C0_LUT4_C_1_B_LUT4_D_Z[2] (30,36) -> (40,21)
Info: Sink SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 5.4 Source SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_LUT4_Z.F
Info: 2.1 7.5 Net SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0 (40,21) -> (29,28)
Info: Sink SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.B
Info: 0.4 7.9 Source SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info: 0.0 7.9 Net SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (29,28) -> (29,28)
Info: Sink SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info: 0.0 7.9 Source SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info: 0.0 7.9 Net SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_CIN (29,28) -> (29,28)
Info: Sink SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:40.3-46.2
Info: Risco-5/src/peripheral/bus.v:44.5-44.37
Info: Risco-5/src/peripheral/soc.v:48.5-72.2
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 8.0 Source SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info: 0.0 8.0 Net SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (29,28) -> (29,28)
Info: Sink SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info: 0.0 8.0 Source SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info: 0.0 8.0 Net SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_CIN (29,28) -> (29,28)
Info: Sink SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:40.3-46.2
Info: Risco-5/src/peripheral/bus.v:44.5-44.37
Info: Risco-5/src/peripheral/soc.v:48.5-72.2
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 8.1 Source SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info: 0.0 8.1 Net SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (29,28) -> (29,28)
Info: Sink SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info: 0.0 8.1 Source SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info: 0.0 8.1 Net SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_CIN (29,28) -> (29,28)
Info: Sink SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:40.3-46.2
Info: Risco-5/src/peripheral/bus.v:44.5-44.37
Info: Risco-5/src/peripheral/soc.v:48.5-72.2
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 8.1 Source SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info: 0.0 8.1 Net SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (29,28) -> (29,28)
Info: Sink SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info: 0.0 8.1 Source SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info: 0.0 8.1 Net SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_CIN (29,28) -> (30,28)
Info: Sink SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:40.3-46.2
Info: Risco-5/src/peripheral/bus.v:44.5-44.37
Info: Risco-5/src/peripheral/soc.v:48.5-72.2
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 8.2 Source SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info: 0.0 8.2 Net SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (30,28) -> (30,28)
Info: Sink SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info: 0.0 8.2 Source SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info: 0.0 8.2 Net SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_CIN (30,28) -> (30,28)
Info: Sink SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:40.3-46.2
Info: Risco-5/src/peripheral/bus.v:44.5-44.37
Info: Risco-5/src/peripheral/soc.v:48.5-72.2
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 8.3 Source SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info: 0.0 8.3 Net SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (30,28) -> (30,28)
Info: Sink SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info: 0.0 8.3 Source SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info: 0.0 8.3 Net SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_COUT (30,28) -> (30,28)
Info: Sink SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:40.3-46.2
Info: Risco-5/src/peripheral/bus.v:44.5-44.37
Info: Risco-5/src/peripheral/soc.v:48.5-72.2
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 8.3 Source SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info: 0.0 8.3 Net SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (30,28) -> (30,28)
Info: Sink SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info: 0.0 8.3 Source SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info: 0.0 8.3 Net $nextpnr_CCU2C_3$CIN (30,28) -> (30,28)
Info: Sink $nextpnr_CCU2C_3$CCU2_COMB0.FCI
Info: 0.4 8.8 Source $nextpnr_CCU2C_3$CCU2_COMB0.F
Info: 1.8 10.6 Net SOC.Core.read_data_PFUMX_Z_8_C0_LUT4_Z_1_A[1] (30,28) -> (11,27)
Info: Sink SOC.Memory.address_LUT4_Z_2.D
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:40.3-46.2
Info: Risco-5/src/peripheral/bus.v:44.5-44.37
Info: Risco-5/src/peripheral/soc.v:48.5-72.2
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.2 10.8 Source SOC.Memory.address_LUT4_Z_2.F
Info: 2.4 13.2 Net SOC.slave_address[3] (11,27) -> (9,12)
Info: Sink SOC.Memory.memory.0.398$DPRAM_COMB1.B
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:40.3-46.2
Info: Risco-5/src/peripheral/soc.v:19.5-19.18
Info: 0.2 13.4 Source SOC.Memory.memory.0.398$DPRAM_COMB1.F
Info: 1.4 14.8 Net SOC.Memory.memory.0.398_DO_1[3] (9,12) -> (4,11)
Info: Sink SOC.Memory.memory.0.422_DO_2_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 15.1 Source SOC.Memory.memory.0.422_DO_2_LUT4_Z.F
Info: 0.9 15.9 Net SOC.Memory.memory.0.422_DO_2[3] (4,11) -> (3,11)
Info: Sink SOC.Memory.memory.0.390_DO_2_PFUMX_Z_ALUT_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 16.2 Source SOC.Memory.memory.0.390_DO_2_PFUMX_Z_ALUT_LUT4_Z.F
Info: 0.0 16.2 Net SOC.Memory.memory.0.390_DO_2_PFUMX_Z_ALUT (3,11) -> (3,11)
Info: Sink SOC.Memory.memory.0.390_DO_2_PFUMX_Z_BLUT_LUT4_Z.F1
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:133.22-133.24
Info: 0.2 16.3 Source SOC.Memory.memory.0.390_DO_2_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: 0.7 17.0 Net SOC.Memory.memory.0.390_DO_2[3] (3,11) -> (5,12)
Info: Sink SOC.Memory.memory.0.390_DO_2_LUT4_B.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 17.3 Source SOC.Memory.memory.0.390_DO_2_LUT4_B.F
Info: 1.1 18.4 Net SOC.Memory.memory.0.462_DO_2_LUT4_B_Z[2] (5,12) -> (3,14)
Info: Sink SOC.Core.read_data_PFUMX_Z_11_C0_LUT4_Z_1_B_LUT4_Z.C
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 18.7 Source SOC.Core.read_data_PFUMX_Z_11_C0_LUT4_Z_1_B_LUT4_Z.F
Info: 1.0 19.7 Net SOC.Core.read_data_PFUMX_Z_11_C0_LUT4_Z_1_B[3] (3,14) -> (3,18)
Info: Sink SOC.Core.read_data_PFUMX_Z_11_C0_LUT4_Z_1.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 19.9 Source SOC.Core.read_data_PFUMX_Z_11_C0_LUT4_Z_1.F
Info: 1.3 21.2 Net SOC.Core.read_data_PFUMX_Z_11_C0[4] (3,18) -> (14,19)
Info: Sink SOC.Core.read_data_PFUMX_Z_11_BLUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 21.5 Source SOC.Core.read_data_PFUMX_Z_11_BLUT_LUT4_Z.OFX
Info: 2.1 23.6 Net SOC.read_data[25] (14,19) -> (28,32)
Info: Sink SOC.Core.memory_register_TRELLIS_FF_Q_6.M
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:40.3-46.2
Info: Risco-5/src/peripheral/soc.v:18.34-18.43
Info: 0.0 23.6 Setup SOC.Core.memory_register_TRELLIS_FF_Q_6.M
Info: 4.6 ns logic, 19.0 ns routing
Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
Info: curr total
Info: 0.5 0.5 Source ClkDivider.clk_counter_TRELLIS_FF_Q_19.Q
Info: 1.4 1.9 Net ClkDivider.clk_counter[12] (44,11) -> (45,13)
Info: Sink reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.B
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:14.3-22.2
Info: Risco-5/debug/clk_divider.v:14.26-14.37
Info: 0.4 2.3 Source reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: 0.0 2.3 Net reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (45,13) -> (45,13)
Info: Sink reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: 0.0 2.3 Source reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: 0.0 2.3 Net reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (45,13) -> (45,13)
Info: Sink reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:14.3-22.2
Info: Risco-5/debug/clk_divider.v:40.12-40.38
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 2.4 Source reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: 0.0 2.4 Net reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (45,13) -> (45,13)
Info: Sink reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: 0.0 2.4 Source reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: 0.0 2.4 Net reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (45,13) -> (45,13)
Info: Sink reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:14.3-22.2
Info: Risco-5/debug/clk_divider.v:40.12-40.38
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 2.5 Source reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: 0.0 2.5 Net reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (45,13) -> (45,13)
Info: Sink reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: 0.0 2.5 Source reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: 0.0 2.5 Net reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (45,13) -> (45,13)
Info: Sink reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:14.3-22.2
Info: Risco-5/debug/clk_divider.v:40.12-40.38
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 2.5 Source reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: 0.0 2.5 Net reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (45,13) -> (45,13)
Info: Sink reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: 0.0 2.5 Source reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: 0.0 2.5 Net reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (45,13) -> (46,13)
Info: Sink reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:14.3-22.2
Info: Risco-5/debug/clk_divider.v:40.12-40.38
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 2.6 Source reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: 0.0 2.6 Net reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (46,13) -> (46,13)
Info: Sink reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: 0.0 2.6 Source reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: 0.0 2.6 Net reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (46,13) -> (46,13)
Info: Sink reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:14.3-22.2
Info: Risco-5/debug/clk_divider.v:40.12-40.38
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 2.7 Source reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: 0.0 2.7 Net reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (46,13) -> (46,13)
Info: Sink reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: 0.0 2.7 Source reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: 0.0 2.7 Net reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (46,13) -> (46,13)
Info: Sink reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:14.3-22.2
Info: Risco-5/debug/clk_divider.v:40.12-40.38
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 2.8 Source reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: 0.0 2.8 Net reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (46,13) -> (46,13)
Info: Sink reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: 0.0 2.8 Source reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: 0.0 2.8 Net reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (46,13) -> (46,13)
Info: Sink reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:14.3-22.2
Info: Risco-5/debug/clk_divider.v:40.12-40.38
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 2.8 Source reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: 0.0 2.8 Net reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (46,13) -> (46,13)
Info: Sink reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: 0.0 2.8 Source reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: 0.0 2.8 Net reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN (46,13) -> (47,13)
Info: Sink reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:14.3-22.2
Info: Risco-5/debug/clk_divider.v:40.12-40.38
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 2.9 Source reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: 0.0 2.9 Net reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (47,13) -> (47,13)
Info: Sink reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: 0.0 2.9 Source reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: 0.0 2.9 Net reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN (47,13) -> (47,13)
Info: Sink reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:14.3-22.2
Info: Risco-5/debug/clk_divider.v:40.12-40.38
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 3.0 Source reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT$CCU2_COMB0.FCO
Info: 0.0 3.0 Net reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT$CCU2_FCI_INT (47,13) -> (47,13)
Info: Sink reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT$CCU2_COMB1.FCI
Info: 0.0 3.0 Source reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT$CCU2_COMB1.FCO
Info: 0.0 3.0 Net $nextpnr_CCU2C_7$CIN (47,13) -> (47,13)
Info: Sink $nextpnr_CCU2C_7$CCU2_COMB0.FCI
Info: 0.4 3.4 Source $nextpnr_CCU2C_7$CCU2_COMB0.F
Info: 0.4 3.8 Net reset_LUT4_C_D_LUT4_Z_D (47,13) -> (47,13)
Info: Sink reset_LUT4_C_D_LUT4_Z.D
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:14.3-22.2
Info: Risco-5/debug/clk_divider.v:40.12-40.38
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.2 4.1 Source reset_LUT4_C_D_LUT4_Z.F
Info: 1.1 5.2 Net reset_LUT4_C_D[1] (47,13) -> (45,12)
Info: Sink reset_LUT4_A.B
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 5.4 Source reset_LUT4_A.F
Info: 0.0 5.4 Net reset_LUT4_A_Z (45,12) -> (45,12)
Info: Sink reset_LUT4_C.F1
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:133.22-133.24
Info: 0.2 5.6 Source reset_LUT4_C.OFX
Info: 0.8 6.4 Net reset_LUT4_A_Z_PFUMX_ALUT_Z (45,12) -> (43,14)
Info: Sink ClkDivider.clk_counter_TRELLIS_FF_Q_31.LSR
Info: 0.4 6.8 Setup ClkDivider.clk_counter_TRELLIS_FF_Q_31.LSR
Info: 3.1 ns logic, 3.7 ns routing
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
Info: curr total
Info: 0.0 0.0 Source reset$tr_io.O
Info: 4.1 4.1 Net reset$TRELLIS_IO_IN (0,29) -> (45,12)
Info: Sink reset_LUT4_A.A
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 4.3 Source reset_LUT4_A.F
Info: 0.0 4.3 Net reset_LUT4_A_Z (45,12) -> (45,12)
Info: Sink reset_LUT4_C.F1
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:133.22-133.24
Info: 0.2 4.5 Source reset_LUT4_C.OFX
Info: 0.8 5.3 Net reset_LUT4_A_Z_PFUMX_ALUT_Z (45,12) -> (43,14)
Info: Sink ClkDivider.clk_counter_TRELLIS_FF_Q_31.LSR
Info: 0.4 5.7 Setup ClkDivider.clk_counter_TRELLIS_FF_Q_31.LSR
Info: 0.8 ns logic, 4.9 ns routing
Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
Info: curr total
Info: 0.5 0.5 Source ClkDivider.clk_o_auto_TRELLIS_FF_Q.Q
Info: 3.0 3.5 Net clk_o (47,12) -> (85,19)
Info: Sink led_LUT4_Z_6.D
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:9.6-9.11
Info: 0.2 3.7 Source led_LUT4_Z_6.F
Info: 1.4 5.1 Net led[7]$TRELLIS_IO_OUT (85,19) -> (90,20)
Info: Sink led[7]$tr_io.I
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:6.22-6.25
Info: 0.8 ns logic, 4.3 ns routing
Info: Critical path report for cross-domain path 'posedge $glbnet$clk_o' -> '<async>':
Info: curr total
Info: 0.5 0.5 Source SOC.Leds.data_TRELLIS_FF_Q_29.Q
Info: 4.4 5.0 Net SOC.Core.read_data_LUT4_Z_D[0] (22,29) -> (78,37)
Info: Sink led_LUT4_Z_7.D
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:40.3-46.2
Info: Risco-5/src/peripheral/leds.v:15.12-15.16
Info: Risco-5/src/peripheral/soc.v:74.6-83.2
Info: 0.2 5.2 Source led_LUT4_Z_7.F
Info: 2.1 7.3 Net led[2]$TRELLIS_IO_OUT (78,37) -> (90,44)
Info: Sink led[2]$tr_io.I
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:6.22-6.25
Info: 0.8 ns logic, 6.5 ns routing
Info: Max frequency for clock '$glbnet$clk_o': 42.31 MHz (PASS at 12.00 MHz)
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 146.24 MHz (PASS at 25.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 5.69 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 5.10 ns
Info: Max delay posedge $glbnet$clk_o -> <async> : 7.27 ns
Info: Slack histogram:
Info: legend: * represents 144 endpoint(s)
Info: + represents [1,144) endpoint(s)
Info: [ 33162, 35615) |+
Info: [ 35615, 38068) |+
Info: [ 38068, 40521) |+
Info: [ 40521, 42974) |
Info: [ 42974, 45427) |
Info: [ 45427, 47880) |
Info: [ 47880, 50333) |
Info: [ 50333, 52786) |
Info: [ 52786, 55239) |
Info: [ 55239, 57692) |
Info: [ 57692, 60145) |+
Info: [ 60145, 62598) |+
Info: [ 62598, 65051) |+
Info: [ 65051, 67504) |****+
Info: [ 67504, 69957) |*********************+
Info: [ 69957, 72410) |************************************************************
Info: [ 72410, 74863) |*****+
Info: [ 74863, 77316) |*****+
Info: [ 77316, 79769) |*****+
Info: [ 79769, 82222) |+
Info: Program finished normally.
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