Console Output

+ /eda/oss-cad-suite/bin/nextpnr-ecp5 --json ./build/out.json --write ./build/out_pnr.json --45k --lpf Risco-5/fpga/ecp5/pinout.lpf --textcfg ./build/out.config --package CABGA381 --speed 6
Info: constraining clock net 'clk' to 25.00 MHz

Info: Logic utilisation before packing:
Info:     Total LUT4s:      8869/43848    20%
Info:         logic LUTs:   5533/43848    12%
Info:         carry LUTs:    264/43848     0%
Info:           RAM LUTs:   2048/ 5481    37%
Info:          RAMW LUTs:   1024/10962     9%

Info:      Total DFFs:      1291/43848     2%

Info: Packing IOs..
Info: pin 'tx$tr_io' constrained to Bel 'X90/Y20/PIOC'.
Info: pin 'rx$tr_io' constrained to Bel 'X90/Y20/PIOA'.
Info: pin 'reset$tr_io' constrained to Bel 'X0/Y29/PIOA'.
Info: pin 'led[7]$tr_io' constrained to Bel 'X90/Y20/PIOD'.
Info: pin 'led[6]$tr_io' constrained to Bel 'X0/Y44/PIOD'.
Info: pin 'led[5]$tr_io' constrained to Bel 'X0/Y59/PIOA'.
Info: pin 'led[4]$tr_io' constrained to Bel 'X15/Y71/PIOB'.
Info: pin 'led[3]$tr_io' constrained to Bel 'X90/Y29/PIOC'.
Info: pin 'led[2]$tr_io' constrained to Bel 'X90/Y44/PIOB'.
Info: pin 'led[1]$tr_io' constrained to Bel 'X0/Y44/PIOC'.
Info: pin 'led[0]$tr_io' constrained to Bel 'X0/Y59/PIOC'.
Info: pin 'clk$tr_io' constrained to Bel 'X0/Y68/PIOC'.
Info: Packing constants..
Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info:     263 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info: Promoting globals...
Info:     promoting clock net clk_o to global network
Info:     promoting clock net clk$TRELLIS_IO_IN to global network
Info: Checksum: 0x0a832edc

Info: Device utilisation:
Info: 	          TRELLIS_IO:    12/  245     4%
Info: 	                DCCA:     2/   56     3%
Info: 	              DP16KD:     0/  108     0%
Info: 	          MULT18X18D:     0/   72     0%
Info: 	              ALU54B:     0/   36     0%
Info: 	             EHXPLLL:     0/    4     0%
Info: 	             EXTREFB:     0/    2     0%
Info: 	                DCUA:     0/    2     0%
Info: 	           PCSCLKDIV:     0/    2     0%
Info: 	             IOLOGIC:     0/  160     0%
Info: 	            SIOLOGIC:     0/   85     0%
Info: 	                 GSR:     0/    1     0%
Info: 	               JTAGG:     0/    1     0%
Info: 	                OSCG:     0/    1     0%
Info: 	               SEDGA:     0/    1     0%
Info: 	                 DTR:     0/    1     0%
Info: 	             USRMCLK:     0/    1     0%
Info: 	             CLKDIVF:     0/    4     0%
Info: 	           ECLKSYNCB:     0/   10     0%
Info: 	             DLLDELD:     0/    8     0%
Info: 	              DDRDLL:     0/    4     0%
Info: 	             DQSBUFM:     0/   10     0%
Info: 	     TRELLIS_ECLKBUF:     0/    8     0%
Info: 	        ECLKBRIDGECS:     0/    2     0%
Info: 	                DCSC:     0/    2     0%
Info: 	          TRELLIS_FF:  1291/43848     2%
Info: 	        TRELLIS_COMB:  8919/43848    20%
Info: 	        TRELLIS_RAMW:   512/ 5481     9%

Info: Placed 12 cells based on constraints.
Info: Creating initial analytic placement for 5352 cells, random placement wirelen = 448469.
Info:     at initial placer iter 0, wirelen = 1031
Info:     at initial placer iter 1, wirelen = 956
Info:     at initial placer iter 2, wirelen = 1112
Info:     at initial placer iter 3, wirelen = 1146
Info: Running main analytical placer, max placement attempts per cell = 14407712.
Info:     at iteration #1, type ALL: wirelen solved = 1183, spread = 69322, legal = 70040; time = 0.30s
Info:     at iteration #2, type ALL: wirelen solved = 4630, spread = 48043, legal = 49049; time = 0.32s
Info:     at iteration #3, type ALL: wirelen solved = 11069, spread = 43139, legal = 44150; time = 0.29s
Info:     at iteration #4, type ALL: wirelen solved = 13423, spread = 42676, legal = 43750; time = 0.30s
Info:     at iteration #5, type ALL: wirelen solved = 15549, spread = 39468, legal = 40469; time = 0.29s
Info:     at iteration #6, type ALL: wirelen solved = 16622, spread = 37283, legal = 38795; time = 0.29s
Info:     at iteration #7, type ALL: wirelen solved = 17886, spread = 39244, legal = 39982; time = 0.27s
Info:     at iteration #8, type ALL: wirelen solved = 19682, spread = 38584, legal = 39316; time = 0.27s
Info:     at iteration #9, type ALL: wirelen solved = 20648, spread = 40100, legal = 40776; time = 0.27s
Info:     at iteration #10, type ALL: wirelen solved = 21914, spread = 41036, legal = 41688; time = 0.27s
Info:     at iteration #11, type ALL: wirelen solved = 22606, spread = 42519, legal = 43094; time = 0.27s
Info: HeAP Placer Time: 5.33s
Info:   of which solving equations: 3.35s
Info:   of which spreading cells: 0.43s
Info:   of which strict legalisation: 0.12s

Info: Running simulated annealing placer for refinement.
Info:   at iteration #1: temp = 0.000000, timing cost = 10751, wirelen = 38795
Info:   at iteration #5: temp = 0.000000, timing cost = 12100, wirelen = 31492
Sending interrupt signal to process
Terminated
script returned exit code 143