Console Output

Started by user Julio Nunes Avelar
[Pipeline] Start of Pipeline
[Pipeline] node
Running on Jenkins in /var/lib/jenkins/workspace/Risco 5
[Pipeline] {
[Pipeline] stage
[Pipeline] { (Git Clone)
[Pipeline] sh
+ rm -Rf Risco-5/ build/
[Pipeline] sh
+ git clone https://github.com/JN513/Risco-5
Cloning into 'Risco-5'...
[Pipeline] sh
+ cd Risco-5
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (IVerilog)
[Pipeline] sh
+ mkdir -p build
[Pipeline] sh
+ cp Risco-5/software/memory/add.hex Risco-5/software/memory/generic.hex
[Pipeline] sh
+ /eda/oss-cad-suite/bin/iverilog -o build/soc_test.o -s soc_tb Risco-5/src/core/alu.v Risco-5/src/core/alu_control.v Risco-5/src/core/control_unit.v Risco-5/src/core/core.v Risco-5/src/core/csr_unit.v Risco-5/src/core/immediate_generator.v Risco-5/src/core/mux.v Risco-5/src/core/pc.v Risco-5/src/core/registers.v Risco-5/src/peripheral/bus.v Risco-5/src/peripheral/fifo.v Risco-5/src/peripheral/gpio.v Risco-5/src/peripheral/gpios.v Risco-5/src/peripheral/leds.v Risco-5/src/peripheral/memory.v Risco-5/src/peripheral/soc.v Risco-5/src/peripheral/uart.v Risco-5/src/peripheral/uart_rx.v Risco-5/src/peripheral/uart_tx.v Risco-5/tests/soc_test.v
[Pipeline] sh
+ /eda/oss-cad-suite/bin/vvp build/soc_test.o
ERROR: Risco-5/src/peripheral/memory.v:29: $readmemh: Unable to open software/memory/generic.hex for reading.
VCD info: dumpfile build/soc.vcd opened for output.
Risco-5/tests/soc_test.v:32: $finish called at 566 (1s)
[Pipeline] sh
+ rm -f Risco-5/software/memory/generic.hex
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Síntese)
[Pipeline] parallel
[Pipeline] { (Branch: OSS-Cad-Suite)
[Pipeline] { (Branch: Gowin)
[Pipeline] stage
[Pipeline] { (OSS-Cad-Suite)
[Pipeline] stage
[Pipeline] { (Gowin)
[Pipeline] stage
[Pipeline] { (Yosys)
[Pipeline] sh
[Pipeline] sh
+ rm -rf Risco-5/impl/pnr
+ /eda/oss-cad-suite/bin/yosys -p                                          read_verilog Risco-5/fpga/ecp5/main.v;                                         read_verilog Risco-5/debug/clk_divider.v;                                         read_verilog Risco-5/debug/reset.v;                                         read_verilog Risco-5/src/core/*.v;                                         read_verilog Risco-5/src/peripheral/*.v;                                         synth_ecp5 -json ./build/out.json -abc9                                     

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2024  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.38+120 (git sha1 1e42b4f0f, clang++ 14.0.0-1ubuntu1.1 -fPIC -Os)

-- Running command `                                         read_verilog Risco-5/fpga/ecp5/main.v;                                         read_verilog Risco-5/debug/clk_divider.v;                                         read_verilog Risco-5/debug/reset.v;                                         read_verilog Risco-5/src/core/*.v;                                         read_verilog Risco-5/src/peripheral/*.v;                                         synth_ecp5 -json ./build/out.json -abc9                                     ' --

1. Executing Verilog-2005 frontend: Risco-5/fpga/ecp5/main.v
Parsing Verilog input from `Risco-5/fpga/ecp5/main.v' to AST representation.
Generating RTLIL representation for module `\top'.
Successfully finished Verilog frontend.

2. Executing Verilog-2005 frontend: Risco-5/debug/clk_divider.v
Parsing Verilog input from `Risco-5/debug/clk_divider.v' to AST representation.
Generating RTLIL representation for module `\ClkDivider'.
Successfully finished Verilog frontend.

3. Executing Verilog-2005 frontend: Risco-5/debug/reset.v
Parsing Verilog input from `Risco-5/debug/reset.v' to AST representation.
Generating RTLIL representation for module `\ResetBootSystem'.
Successfully finished Verilog frontend.

4. Executing Verilog-2005 frontend: Risco-5/src/core/alu.v
Parsing Verilog input from `Risco-5/src/core/alu.v' to AST representation.
Generating RTLIL representation for module `\Alu'.
Successfully finished Verilog frontend.

5. Executing Verilog-2005 frontend: Risco-5/src/core/alu_control.v
Parsing Verilog input from `Risco-5/src/core/alu_control.v' to AST representation.
Generating RTLIL representation for module `\ALU_Control'.
Successfully finished Verilog frontend.

6. Executing Verilog-2005 frontend: Risco-5/src/core/control_unit.v
Parsing Verilog input from `Risco-5/src/core/control_unit.v' to AST representation.
Generating RTLIL representation for module `\Control_Unit'.
Successfully finished Verilog frontend.

7. Executing Verilog-2005 frontend: Risco-5/src/core/core.v
Parsing Verilog input from `Risco-5/src/core/core.v' to AST representation.
Generating RTLIL representation for module `\Core'.
Risco-5/src/core/core.v:106: Warning: Identifier `\pc_source' is implicitly declared.
Successfully finished Verilog frontend.

8. Executing Verilog-2005 frontend: Risco-5/src/core/csr_unit.v
Parsing Verilog input from `Risco-5/src/core/csr_unit.v' to AST representation.
Generating RTLIL representation for module `\CSR_Unit'.
Successfully finished Verilog frontend.

9. Executing Verilog-2005 frontend: Risco-5/src/core/immediate_generator.v
Parsing Verilog input from `Risco-5/src/core/immediate_generator.v' to AST representation.
Generating RTLIL representation for module `\Immediate_Generator'.
Successfully finished Verilog frontend.

10. Executing Verilog-2005 frontend: Risco-5/src/core/mux.v
Parsing Verilog input from `Risco-5/src/core/mux.v' to AST representation.
Generating RTLIL representation for module `\MUX'.
Successfully finished Verilog frontend.

11. Executing Verilog-2005 frontend: Risco-5/src/core/pc.v
Parsing Verilog input from `Risco-5/src/core/pc.v' to AST representation.
Generating RTLIL representation for module `\PC'.
Successfully finished Verilog frontend.

12. Executing Verilog-2005 frontend: Risco-5/src/core/registers.v
Parsing Verilog input from `Risco-5/src/core/registers.v' to AST representation.
Generating RTLIL representation for module `\Registers'.
Successfully finished Verilog frontend.

13. Executing Verilog-2005 frontend: Risco-5/src/peripheral/bus.v
Parsing Verilog input from `Risco-5/src/peripheral/bus.v' to AST representation.
Generating RTLIL representation for module `\BUS'.
Successfully finished Verilog frontend.

14. Executing Verilog-2005 frontend: Risco-5/src/peripheral/fifo.v
Parsing Verilog input from `Risco-5/src/peripheral/fifo.v' to AST representation.
Generating RTLIL representation for module `\FIFO'.
Successfully finished Verilog frontend.

15. Executing Verilog-2005 frontend: Risco-5/src/peripheral/gpio.v
Parsing Verilog input from `Risco-5/src/peripheral/gpio.v' to AST representation.
Warning: Yosys has only limited support for tri-state logic at the moment. (Risco-5/src/peripheral/gpio.v:9)
Generating RTLIL representation for module `\GPIO'.
Successfully finished Verilog frontend.

16. Executing Verilog-2005 frontend: Risco-5/src/peripheral/gpios.v
Parsing Verilog input from `Risco-5/src/peripheral/gpios.v' to AST representation.
Generating RTLIL representation for module `\GPIOS'.
Successfully finished Verilog frontend.

17. Executing Verilog-2005 frontend: Risco-5/src/peripheral/leds.v
Parsing Verilog input from `Risco-5/src/peripheral/leds.v' to AST representation.
Generating RTLIL representation for module `\LEDs'.
Successfully finished Verilog frontend.

18. Executing Verilog-2005 frontend: Risco-5/src/peripheral/memory.v
Parsing Verilog input from `Risco-5/src/peripheral/memory.v' to AST representation.
Generating RTLIL representation for module `\Memory'.
Successfully finished Verilog frontend.

19. Executing Verilog-2005 frontend: Risco-5/src/peripheral/soc.v
Parsing Verilog input from `Risco-5/src/peripheral/soc.v' to AST representation.
Generating RTLIL representation for module `\Risco_5_SOC'.
Successfully finished Verilog frontend.

20. Executing Verilog-2005 frontend: Risco-5/src/peripheral/uart.v
Parsing Verilog input from `Risco-5/src/peripheral/uart.v' to AST representation.
Generating RTLIL representation for module `\UART'.
Successfully finished Verilog frontend.

21. Executing Verilog-2005 frontend: Risco-5/src/peripheral/uart_rx.v
Parsing Verilog input from `Risco-5/src/peripheral/uart_rx.v' to AST representation.
Generating RTLIL representation for module `\uart_tool_rx'.
Successfully finished Verilog frontend.

22. Executing Verilog-2005 frontend: Risco-5/src/peripheral/uart_tx.v
Parsing Verilog input from `Risco-5/src/peripheral/uart_tx.v' to AST representation.
Generating RTLIL representation for module `\uart_tool_tx'.
Successfully finished Verilog frontend.

23. Executing SYNTH_ECP5 pass.

23.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v' to AST representation.
Generating RTLIL representation for module `\LUT4'.
Generating RTLIL representation for module `\$__ABC9_LUT5'.
Generating RTLIL representation for module `\$__ABC9_LUT6'.
Generating RTLIL representation for module `\$__ABC9_LUT7'.
Generating RTLIL representation for module `\L6MUX21'.
Generating RTLIL representation for module `\CCU2C'.
Generating RTLIL representation for module `\TRELLIS_RAM16X2'.
Generating RTLIL representation for module `\PFUMX'.
Generating RTLIL representation for module `\TRELLIS_DPR16X4'.
Generating RTLIL representation for module `\DPR16X4C'.
Generating RTLIL representation for module `\LUT2'.
Generating RTLIL representation for module `\TRELLIS_FF'.
Generating RTLIL representation for module `\TRELLIS_IO'.
Generating RTLIL representation for module `\INV'.
Generating RTLIL representation for module `\TRELLIS_COMB'.
Generating RTLIL representation for module `\DP16KD'.
Generating RTLIL representation for module `\FD1P3AX'.
Generating RTLIL representation for module `\FD1P3AY'.
Generating RTLIL representation for module `\FD1P3BX'.
Generating RTLIL representation for module `\FD1P3DX'.
Generating RTLIL representation for module `\FD1P3IX'.
Generating RTLIL representation for module `\FD1P3JX'.
Generating RTLIL representation for module `\FD1S3AX'.
Generating RTLIL representation for module `\FD1S3AY'.
Generating RTLIL representation for module `\FD1S3BX'.
Generating RTLIL representation for module `\FD1S3DX'.
Generating RTLIL representation for module `\FD1S3IX'.
Generating RTLIL representation for module `\FD1S3JX'.
Generating RTLIL representation for module `\IFS1P3BX'.
Generating RTLIL representation for module `\IFS1P3DX'.
Generating RTLIL representation for module `\IFS1P3IX'.
Generating RTLIL representation for module `\IFS1P3JX'.
Generating RTLIL representation for module `\OFS1P3BX'.
Generating RTLIL representation for module `\OFS1P3DX'.
Generating RTLIL representation for module `\OFS1P3IX'.
Generating RTLIL representation for module `\OFS1P3JX'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\IBPU'.
Generating RTLIL representation for module `\IBPD'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\OBZPU'.
Generating RTLIL representation for module `\OBZPD'.
Generating RTLIL representation for module `\OBCO'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\BBPU'.
Generating RTLIL representation for module `\BBPD'.
Generating RTLIL representation for module `\ILVDS'.
Generating RTLIL representation for module `\OLVDS'.
Successfully finished Verilog frontend.

23.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_bb.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_bb.v' to AST representation.
Generating RTLIL representation for module `\MULT18X18D'.
Generating RTLIL representation for module `\ALU54B'.
Generating RTLIL representation for module `\EHXPLLL'.
Generating RTLIL representation for module `\DTR'.
Generating RTLIL representation for module `\OSCG'.
Generating RTLIL representation for module `\USRMCLK'.
Generating RTLIL representation for module `\JTAGG'.
Generating RTLIL representation for module `\DELAYF'.
Generating RTLIL representation for module `\DELAYG'.
Generating RTLIL representation for module `\IDDRX1F'.
Generating RTLIL representation for module `\IDDRX2F'.
Generating RTLIL representation for module `\IDDR71B'.
Generating RTLIL representation for module `\IDDRX2DQA'.
Generating RTLIL representation for module `\ODDRX1F'.
Generating RTLIL representation for module `\ODDRX2F'.
Generating RTLIL representation for module `\ODDR71B'.
Generating RTLIL representation for module `\OSHX2A'.
Generating RTLIL representation for module `\ODDRX2DQA'.
Generating RTLIL representation for module `\ODDRX2DQSB'.
Generating RTLIL representation for module `\TSHX2DQA'.
Generating RTLIL representation for module `\TSHX2DQSA'.
Generating RTLIL representation for module `\DQSBUFM'.
Generating RTLIL representation for module `\DDRDLLA'.
Generating RTLIL representation for module `\DLLDELD'.
Generating RTLIL representation for module `\CLKDIVF'.
Generating RTLIL representation for module `\ECLKSYNCB'.
Generating RTLIL representation for module `\ECLKBRIDGECS'.
Generating RTLIL representation for module `\DCCA'.
Generating RTLIL representation for module `\DCSC'.
Generating RTLIL representation for module `\DCUA'.
Generating RTLIL representation for module `\EXTREFB'.
Generating RTLIL representation for module `\PCSCLKDIV'.
Generating RTLIL representation for module `\PUR'.
Generating RTLIL representation for module `\GSR'.
Generating RTLIL representation for module `\SGSR'.
Generating RTLIL representation for module `\PDPW16KD'.
Successfully finished Verilog frontend.

23.3. Executing HIERARCHY pass (managing design hierarchy).

23.3.1. Finding top of design hierarchy..
root of   0 design levels: uart_tool_tx        
root of   0 design levels: uart_tool_rx        
root of   1 design levels: UART                
root of   2 design levels: Risco_5_SOC         
root of   0 design levels: Memory              
root of   0 design levels: LEDs                
root of   1 design levels: GPIOS               
root of   0 design levels: GPIO                
root of   0 design levels: FIFO                
root of   0 design levels: BUS                 
root of   0 design levels: Registers           
root of   0 design levels: PC                  
root of   0 design levels: MUX                 
root of   0 design levels: Immediate_Generator 
root of   0 design levels: CSR_Unit            
root of   1 design levels: Core                
root of   0 design levels: Control_Unit        
root of   0 design levels: ALU_Control         
root of   0 design levels: Alu                 
root of   0 design levels: ResetBootSystem     
root of   0 design levels: ClkDivider          
root of   3 design levels: top                 
Automatically selected top as design top module.

23.3.2. Analyzing design hierarchy..
Top module:  \top
Used module:     \Risco_5_SOC
Used module:         \GPIOS
Used module:             \GPIO
Used module:         \UART
Used module:             \uart_tool_tx
Used module:             \uart_tool_rx
Used module:             \FIFO
Used module:         \LEDs
Used module:         \BUS
Used module:         \Memory
Used module:         \Core
Used module:             \CSR_Unit
Used module:             \Immediate_Generator
Used module:             \Alu
Used module:             \ALU_Control
Used module:             \Control_Unit
Used module:             \Registers
Used module:             \MUX
Used module:             \PC
Used module:     \ResetBootSystem
Parameter \CLOCK_FREQ = 25000000
Parameter \BIT_RATE = 9600
Parameter \MEMORY_SIZE = 2048
Parameter \MEMORY_FILE = 296'00101110001011100010111100101110001011100010111101110011011011110110011001110100011101110110000101110010011001010010111101101101011001010110110101101111011100100111100100101111011001100111000001100111011000010101111101110100011001010111001101110100010111110011001100101110011010000110010101111000
Parameter \GPIO_WIDHT = 6

23.3.3. Executing AST frontend in derive mode using pre-parsed AST for module `\Risco_5_SOC'.
Parameter \CLOCK_FREQ = 25000000
Parameter \BIT_RATE = 9600
Parameter \MEMORY_SIZE = 2048
Parameter \MEMORY_FILE = 296'00101110001011100010111100101110001011100010111101110011011011110110011001110100011101110110000101110010011001010010111101101101011001010110110101101111011100100111100100101111011001100111000001100111011000010101111101110100011001010111001101110100010111110011001100101110011010000110010101111000
Parameter \GPIO_WIDHT = 6
Generating RTLIL representation for module `$paramod$3a9006d2d69ee0c2bdc9f053e7d4480adeb7a508\Risco_5_SOC'.
Parameter \CYCLES = 20

23.3.4. Executing AST frontend in derive mode using pre-parsed AST for module `\ResetBootSystem'.
Parameter \CYCLES = 20
Generating RTLIL representation for module `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100'.
Parameter \WIDHT = 5

23.3.5. Executing AST frontend in derive mode using pre-parsed AST for module `\GPIOS'.
Parameter \WIDHT = 5
Generating RTLIL representation for module `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000101'.
Parameter \CLOCK_FREQ = 25000000
Parameter \BIT_RATE = 9600

23.3.6. Executing AST frontend in derive mode using pre-parsed AST for module `\UART'.
Parameter \CLOCK_FREQ = 25000000
Parameter \BIT_RATE = 9600
Generating RTLIL representation for module `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART'.
Parameter \MEMORY_FILE = { }
Parameter \MEMORY_SIZE = 4096

23.3.7. Executing AST frontend in derive mode using pre-parsed AST for module `\Memory'.
Parameter \MEMORY_FILE = { }
Parameter \MEMORY_SIZE = 4096
Generating RTLIL representation for module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'.
Parameter \BOOT_ADDRESS = 0

23.3.8. Executing AST frontend in derive mode using pre-parsed AST for module `\Core'.
Parameter \BOOT_ADDRESS = 0
Generating RTLIL representation for module `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000'.
Risco-5/src/core/core.v:106: Warning: Identifier `\pc_source' is implicitly declared.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8

23.3.9. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tool_tx'.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8
Generating RTLIL representation for module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx'.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8

23.3.10. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tool_rx'.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8
Generating RTLIL representation for module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx'.
Parameter \DEPTH = 8
Parameter \WIDTH = 8

23.3.11. Executing AST frontend in derive mode using pre-parsed AST for module `\FIFO'.
Parameter \DEPTH = 8
Parameter \WIDTH = 8
Generating RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'.
Parameter \DEPTH = 8
Parameter \WIDTH = 8
Found cached RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'.

23.3.12. Analyzing design hierarchy..
Top module:  \top
Used module:     $paramod$3a9006d2d69ee0c2bdc9f053e7d4480adeb7a508\Risco_5_SOC
Used module:         \GPIOS
Used module:             \GPIO
Used module:         \UART
Used module:             $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx
Used module:             $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx
Used module:             $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO
Used module:         \LEDs
Used module:         \BUS
Used module:         \Memory
Used module:         \Core
Used module:             \CSR_Unit
Used module:             \Immediate_Generator
Used module:             \Alu
Used module:             \ALU_Control
Used module:             \Control_Unit
Used module:             \Registers
Used module:             \MUX
Used module:             \PC
Used module:     $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100
Parameter \WIDHT = 6

23.3.13. Executing AST frontend in derive mode using pre-parsed AST for module `\GPIOS'.
Parameter \WIDHT = 6
Generating RTLIL representation for module `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110'.
Parameter \CLOCK_FREQ = 25000000
Parameter \BIT_RATE = 9600
Found cached RTLIL representation for module `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART'.
Parameter \MEMORY_FILE = 296'00101110001011100010111100101110001011100010111101110011011011110110011001110100011101110110000101110010011001010010111101101101011001010110110101101111011100100111100100101111011001100111000001100111011000010101111101110100011001010111001101110100010111110011001100101110011010000110010101111000
Parameter \MEMORY_SIZE = 2048

23.3.14. Executing AST frontend in derive mode using pre-parsed AST for module `\Memory'.
Parameter \MEMORY_FILE = 296'00101110001011100010111100101110001011100010111101110011011011110110011001110100011101110110000101110010011001010010111101101101011001010110110101101111011100100111100100101111011001100111000001100111011000010101111101110100011001010111001101110100010111110011001100101110011010000110010101111000
Parameter \MEMORY_SIZE = 2048
Generating RTLIL representation for module `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory'.
Parameter \BOOT_ADDRESS = 0
Found cached RTLIL representation for module `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000'.

23.3.15. Analyzing design hierarchy..
Top module:  \top
Used module:     $paramod$3a9006d2d69ee0c2bdc9f053e7d4480adeb7a508\Risco_5_SOC
Used module:         $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110
Used module:             \GPIO
Used module:         $paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART
Used module:             \uart_tool_tx
Used module:             \uart_tool_rx
Used module:             \FIFO
Used module:         \LEDs
Used module:         \BUS
Used module:         $paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory
Used module:         $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000
Used module:             \CSR_Unit
Used module:             \Immediate_Generator
Used module:             \Alu
Used module:             \ALU_Control
Used module:             \Control_Unit
Used module:             \Registers
Used module:             \MUX
Used module:             \PC
Used module:     $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8
Found cached RTLIL representation for module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx'.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8
Found cached RTLIL representation for module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx'.
Parameter \DEPTH = 8
Parameter \WIDTH = 8
Found cached RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'.
Parameter \DEPTH = 8
Parameter \WIDTH = 8
Found cached RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'.

23.3.16. Analyzing design hierarchy..
Top module:  \top
Used module:     $paramod$3a9006d2d69ee0c2bdc9f053e7d4480adeb7a508\Risco_5_SOC
Used module:         $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110
Used module:             \GPIO
Used module:         $paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART
Used module:             $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx
Used module:             $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx
Used module:             $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO
Used module:         \LEDs
Used module:         \BUS
Used module:         $paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory
Used module:         $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000
Used module:             \CSR_Unit
Used module:             \Immediate_Generator
Used module:             \Alu
Used module:             \ALU_Control
Used module:             \Control_Unit
Used module:             \Registers
Used module:             \MUX
Used module:             \PC
Used module:     $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100

23.3.17. Analyzing design hierarchy..
Top module:  \top
Used module:     $paramod$3a9006d2d69ee0c2bdc9f053e7d4480adeb7a508\Risco_5_SOC
Used module:         $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110
Used module:             \GPIO
Used module:         $paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART
Used module:             $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx
Used module:             $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx
Used module:             $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO
Used module:         \LEDs
Used module:         \BUS
Used module:         $paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory
Used module:         $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000
Used module:             \CSR_Unit
Used module:             \Immediate_Generator
Used module:             \Alu
Used module:             \ALU_Control
Used module:             \Control_Unit
Used module:             \Registers
Used module:             \MUX
Used module:             \PC
Used module:     $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100
Removing unused module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'.
Removing unused module `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000101'.
Removing unused module `\uart_tool_tx'.
Removing unused module `\uart_tool_rx'.
Removing unused module `\UART'.
Removing unused module `\Risco_5_SOC'.
Removing unused module `\Memory'.
Removing unused module `\GPIOS'.
Removing unused module `\FIFO'.
Removing unused module `\Core'.
Removing unused module `\ResetBootSystem'.
Removing unused module `\ClkDivider'.
Removed 12 unused modules.

23.4. Executing PROC pass (convert processes to netlists).

23.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$520'.
Found and cleaned up 1 empty switch in `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$proc$Risco-5/src/peripheral/memory.v:0$893'.
Removing empty process `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$proc$Risco-5/src/peripheral/memory.v:0$893'.
Cleaned up 2 empty switches.

23.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$627 in module TRELLIS_FF.
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$579 in module DPR16X4C.
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$521 in module TRELLIS_DPR16X4.
Marked 2 switch rules as full_case in process $proc$Risco-5/src/peripheral/fifo.v:23$821 in module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:197$808 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:186$806 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.
Marked 2 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:171$798 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:160$795 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.
Marked 2 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:148$789 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.
Marked 3 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:133$784 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:116$779 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:97$770 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.
Marked 4 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:173$757 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:162$755 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.
Marked 2 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:147$747 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.
Marked 4 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:130$733 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.
Marked 3 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:115$727 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:98$722 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/core.v:179$712 in module $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/memory.v:45$891 in module $paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.
Marked 3 switch rules as full_case in process $proc$Risco-5/src/peripheral/memory.v:33$854 in module $paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/leds.v:23$237 in module LEDs.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart.v:84$659 in module $paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart.v:42$642 in module $paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART.
Marked 2 switch rules as full_case in process $proc$Risco-5/src/peripheral/gpios.v:29$846 in module $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.
Marked 2 switch rules as full_case in process $proc$Risco-5/src/core/registers.v:22$95 in module Registers.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/pc.v:15$85 in module PC.
Removed 1 dead cases from process $proc$Risco-5/src/core/mux.v:10$84 in module MUX.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/mux.v:10$84 in module MUX.
Marked 4 switch rules as full_case in process $proc$Risco-5/src/core/immediate_generator.v:18$82 in module Immediate_Generator.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/csr_unit.v:181$80 in module CSR_Unit.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/csr_unit.v:172$76 in module CSR_Unit.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/csr_unit.v:158$74 in module CSR_Unit.
Marked 2 switch rules as full_case in process $proc$Risco-5/src/core/csr_unit.v:113$67 in module CSR_Unit.
Marked 5 switch rules as full_case in process $proc$Risco-5/debug/reset.v:24$630 in module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.
Removed 1 dead cases from process $proc$Risco-5/src/core/control_unit.v:121$55 in module Control_Unit.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/control_unit.v:121$55 in module Control_Unit.
Removed 1 dead cases from process $proc$Risco-5/src/core/control_unit.v:79$53 in module Control_Unit.
Marked 3 switch rules as full_case in process $proc$Risco-5/src/core/control_unit.v:79$53 in module Control_Unit.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/control_unit.v:71$52 in module Control_Unit.
Removed 1 dead cases from process $proc$Risco-5/src/core/alu_control.v:9$48 in module ALU_Control.
Marked 4 switch rules as full_case in process $proc$Risco-5/src/core/alu_control.v:9$48 in module ALU_Control.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/alu.v:23$33 in module Alu.
Removed a total of 4 dead cases.

23.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 11 redundant assignments.
Promoted 146 assignments to connections.

23.4.4. Executing PROC_INIT pass (extract init attributes).
Found init rule in `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$628'.
  Set init value: \Q = 1'0
Found init rule in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:132$810'.
  Set init value: \i = 0
Found init rule in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:114$763'.
  Set init value: \i = 0
Found init rule in `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:0$715'.
  Set init value: \instruction_register = 0
  Set init value: \memory_register = 0
  Set init value: \alu_out_register = 0
  Set init value: \register_data_1 = 0
  Set init value: \register_data_2 = 0
  Set init value: \pc_old = 0
Found init rule in `\LEDs.$proc$Risco-5/src/peripheral/leds.v:0$240'.
  Set init value: \data = 33'000000000000000000000000000000000
Found init rule in `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART.$proc$Risco-5/src/peripheral/uart.v:0$662'.
  Set init value: \uart_tx_en = 1'0
  Set init value: \tx_fifo_read = 1'0
  Set init value: \tx_fifo_write = 1'0
  Set init value: \rx_fifo_read = 1'0
  Set init value: \rx_fifo_write = 1'0
  Set init value: \buffer_full = 1'0
  Set init value: \uart_tx_data = 8'00000000
  Set init value: \tx_fifo_write_data = 8'00000000
  Set init value: \rx_fifo_write_data = 8'00000000
  Set init value: \read_buffer = 8'00000000
Found init rule in `\PC.$proc$Risco-5/src/core/pc.v:0$88'.
  Set init value: \Output = 0
Found init rule in `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:0$81'.
  Set init value: \csr_mcause = 0
  Set init value: \csr_mcycle = 64'0000000000000000000000000000000000000000000000000000000000000000
  Set init value: \csr_mepc = 0
  Set init value: \csr_mie_mfie = 16'0000000000000000
  Set init value: \csr_mie_meie = 1'0
  Set init value: \csr_mie_msie = 1'0
  Set init value: \csr_mie_mtie = 1'0
  Set init value: \csr_mip_mfip = 16'0000000000000000
  Set init value: \csr_mip_meip = 1'0
  Set init value: \csr_mip_mtip = 1'0
  Set init value: \csr_mip_msip = 1'0
  Set init value: \csr_minstret = 64'0000000000000000000000000000000000000000000000000000000000000000
  Set init value: \csr_mscratch = 0
  Set init value: \csr_mstatus_mie = 1'0
  Set init value: \csr_mstatus_mpie = 1'0
  Set init value: \csr_mtvec = 0
  Set init value: \csr_mtval = 0
  Set init value: \csr_write_data = 0
Found init rule in `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:0$636'.
  Set init value: \reset_o = 1'0
  Set init value: \state = 2'01
  Set init value: \counter = 6'000000
Found init rule in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:0$56'.
  Set init value: \state = 4'0000
  Set init value: \is_immediate = 1'0
  Set init value: \lorD = 1'0
  Set init value: \pc_write = 1'0
  Set init value: \ir_write = 1'0
  Set init value: \pc_source = 1'0
  Set init value: \reg_write = 1'0
  Set init value: \memory_read = 1'0
  Set init value: \memory_write = 1'0
  Set init value: \pc_write_cond = 1'0
  Set init value: \aluop = 2'00
  Set init value: \alu_src_a = 2'00
  Set init value: \alu_src_b = 2'00
  Set init value: \memory_to_reg = 2'00
  Set init value: \nextstate = 4'0000

23.4.5. Executing PROC_ARST pass (detect async resets in processes).

23.4.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 1 switch.
<suppressed ~89 debug messages>

23.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$628'.
Creating decoders for process `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$627'.
     1/1: $0\Q[0:0]
Creating decoders for process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$602'.
Creating decoders for process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$579'.
     1/3: $1$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$578_EN[3:0]$585
     2/3: $1$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$578_DATA[3:0]$584
     3/3: $1$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$578_ADDR[3:0]$583
Creating decoders for process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$545'.
Creating decoders for process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$521'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$519_EN[3:0]$527
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$519_DATA[3:0]$526
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$519_ADDR[3:0]$525
Creating decoders for process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$520'.
Creating decoders for process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$Risco-5/src/peripheral/fifo.v:23$821'.
     1/9: $2$memwr$\memory$Risco-5/src/peripheral/fifo.v:29$811_EN[7:0]$833
     2/9: $2$memwr$\memory$Risco-5/src/peripheral/fifo.v:29$811_DATA[7:0]$832
     3/9: $2$memwr$\memory$Risco-5/src/peripheral/fifo.v:29$811_ADDR[5:0]$831
     4/9: $1$memwr$\memory$Risco-5/src/peripheral/fifo.v:29$811_EN[7:0]$828
     5/9: $1$memwr$\memory$Risco-5/src/peripheral/fifo.v:29$811_DATA[7:0]$827
     6/9: $1$memwr$\memory$Risco-5/src/peripheral/fifo.v:29$811_ADDR[5:0]$826
     7/9: $0\write_ptr[5:0]
     8/9: $0\read_ptr[5:0]
     9/9: $0\read_data[7:0]
Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:132$810'.
Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:197$808'.
     1/2: $0\rxd_reg_0[0:0]
     2/2: $0\rxd_reg[0:0]
Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:186$806'.
     1/1: $0\fsm_state[2:0]
Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:171$798'.
     1/1: $0\cycle_counter[12:0]
Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:160$795'.
     1/1: $0\bit_sample[0:0]
Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:148$789'.
     1/1: $0\bit_counter[3:0]
Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:133$784'.
     1/11: $3\i[31:0]
     2/11: $0\recieved_data[7:0] [1]
     3/11: $0\recieved_data[7:0] [0]
     4/11: $0\recieved_data[7:0] [2]
     5/11: $0\recieved_data[7:0] [3]
     6/11: $0\recieved_data[7:0] [4]
     7/11: $0\recieved_data[7:0] [5]
     8/11: $0\recieved_data[7:0] [6]
     9/11: $0\recieved_data[7:0] [7]
    10/11: $1\i[31:0]
    11/11: $2\i[31:0]
Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:116$779'.
     1/1: $1\n_fsm_state[2:0]
Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:97$770'.
     1/1: $0\uart_rx_data[7:0]
Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:114$763'.
Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:173$757'.
     1/1: $0\txd_reg[0:0]
Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:162$755'.
     1/1: $0\fsm_state[2:0]
Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:147$747'.
     1/1: $0\cycle_counter[12:0]
Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:130$733'.
     1/1: $0\bit_counter[3:0]
Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:115$727'.
     1/11: $3\i[31:0]
     2/11: $0\data_to_send[7:0] [1]
     3/11: $0\data_to_send[7:0] [0]
     4/11: $0\data_to_send[7:0] [2]
     5/11: $0\data_to_send[7:0] [3]
     6/11: $0\data_to_send[7:0] [4]
     7/11: $0\data_to_send[7:0] [5]
     8/11: $0\data_to_send[7:0] [6]
     9/11: $0\data_to_send[7:0] [7]
    10/11: $1\i[31:0]
    11/11: $2\i[31:0]
Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:98$722'.
     1/1: $1\n_fsm_state[2:0]
Creating decoders for process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:0$715'.
Creating decoders for process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:179$712'.
     1/6: $0\alu_out_register[31:0]
     2/6: $0\register_data_2[31:0]
     3/6: $0\register_data_1[31:0]
     4/6: $0\memory_register[31:0]
     5/6: $0\pc_old[31:0]
     6/6: $0\instruction_register[31:0]
Creating decoders for process `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$proc$Risco-5/src/peripheral/memory.v:45$891'.
     1/1: $1\read_data[31:0]
Creating decoders for process `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$proc$Risco-5/src/peripheral/memory.v:33$854'.
     1/24: $3$memwr$\memory$Risco-5/src/peripheral/memory.v:38$849_EN[31:0]$887
     2/24: $3$memwr$\memory$Risco-5/src/peripheral/memory.v:38$849_DATA[31:0]$886
     3/24: $3$memwr$\memory$Risco-5/src/peripheral/memory.v:38$849_ADDR[31:0]$885
     4/24: $3$memwr$\memory$Risco-5/src/peripheral/memory.v:40$850_EN[31:0]$890
     5/24: $3$memwr$\memory$Risco-5/src/peripheral/memory.v:40$850_DATA[31:0]$889
     6/24: $3$memwr$\memory$Risco-5/src/peripheral/memory.v:40$850_ADDR[31:0]$888
     7/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:36$848_EN[31:0]$877
     8/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:36$848_DATA[31:0]$876
     9/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:36$848_ADDR[31:0]$875
    10/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:40$850_EN[31:0]$883
    11/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:40$850_DATA[31:0]$882
    12/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:40$850_ADDR[31:0]$881
    13/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:38$849_EN[31:0]$880
    14/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:38$849_DATA[31:0]$879
    15/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:38$849_ADDR[31:0]$878
    16/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:40$850_EN[31:0]$873
    17/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:40$850_DATA[31:0]$872
    18/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:40$850_ADDR[31:0]$871
    19/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:38$849_EN[31:0]$870
    20/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:38$849_DATA[31:0]$869
    21/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:38$849_ADDR[31:0]$868
    22/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:36$848_EN[31:0]$867
    23/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:36$848_DATA[31:0]$866
    24/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:36$848_ADDR[31:0]$865
Creating decoders for process `\LEDs.$proc$Risco-5/src/peripheral/leds.v:0$240'.
Creating decoders for process `\LEDs.$proc$Risco-5/src/peripheral/leds.v:23$237'.
     1/1: $0\data[32:0]
Creating decoders for process `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART.$proc$Risco-5/src/peripheral/uart.v:0$662'.
Creating decoders for process `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART.$proc$Risco-5/src/peripheral/uart.v:84$659'.
     1/1: $1\read_data[31:0]
Creating decoders for process `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART.$proc$Risco-5/src/peripheral/uart.v:42$642'.
     1/10: $0\rx_fifo_write[0:0]
     2/10: $0\rx_fifo_read[0:0]
     3/10: $0\tx_fifo_write[0:0]
     4/10: $0\tx_fifo_read[0:0]
     5/10: $0\uart_tx_en[0:0]
     6/10: $0\read_buffer[7:0]
     7/10: $0\rx_fifo_write_data[7:0]
     8/10: $0\tx_fifo_write_data[7:0]
     9/10: $0\uart_tx_data[7:0]
    10/10: $0\buffer_full[0:0]
Creating decoders for process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:29$846'.
     1/2: $0\gpio_value[5:0]
     2/2: $0\gpio_direction[5:0]
Creating decoders for process `\Registers.$proc$Risco-5/src/core/registers.v:0$113'.
Creating decoders for process `\Registers.$proc$Risco-5/src/core/registers.v:22$95'.
     1/9: $2$memwr$\registers$Risco-5/src/core/registers.v:26$91_EN[31:0]$110
     2/9: $2$memwr$\registers$Risco-5/src/core/registers.v:26$91_DATA[31:0]$109
     3/9: $2$memwr$\registers$Risco-5/src/core/registers.v:26$91_ADDR[4:0]$108
     4/9: $2$memwr$\registers$Risco-5/src/core/registers.v:28$92_EN[31:0]$111
     5/9: $1$memwr$\registers$Risco-5/src/core/registers.v:24$90_EN[31:0]$102
     6/9: $1$memwr$\registers$Risco-5/src/core/registers.v:28$92_EN[31:0]$106
     7/9: $1$memwr$\registers$Risco-5/src/core/registers.v:26$91_EN[31:0]$105
     8/9: $1$memwr$\registers$Risco-5/src/core/registers.v:26$91_DATA[31:0]$104
     9/9: $1$memwr$\registers$Risco-5/src/core/registers.v:26$91_ADDR[4:0]$103
Creating decoders for process `\PC.$proc$Risco-5/src/core/pc.v:0$88'.
Creating decoders for process `\PC.$proc$Risco-5/src/core/pc.v:15$85'.
     1/1: $0\Output[31:0]
Creating decoders for process `\MUX.$proc$Risco-5/src/core/mux.v:10$84'.
     1/1: $1\S[31:0]
Creating decoders for process `\Immediate_Generator.$proc$Risco-5/src/core/immediate_generator.v:18$82'.
     1/4: $4\immediate[31:0]
     2/4: $3\immediate[31:0]
     3/4: $2\immediate[31:0]
     4/4: $1\immediate[31:0]
Creating decoders for process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:0$81'.
Creating decoders for process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:181$80'.
     1/1: $1\csr_data_out[31:0]
Creating decoders for process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$76'.
     1/1: $1\csr_write_data[31:0]
Creating decoders for process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:158$74'.
     1/4: $0\csr_mip_msip[0:0]
     2/4: $0\csr_mip_mtip[0:0]
     3/4: $0\csr_mip_meip[0:0]
     4/4: $0\csr_mip_mfip[15:0]
Creating decoders for process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:113$67'.
     1/13: $0\csr_mtval[31:0]
     2/13: $0\csr_mtvec[31:0]
     3/13: $0\csr_mstatus_mpie[0:0]
     4/13: $0\csr_mstatus_mie[0:0]
     5/13: $0\csr_mscratch[31:0]
     6/13: $0\csr_minstret[63:0]
     7/13: $0\csr_mie_mtie[0:0]
     8/13: $0\csr_mie_msie[0:0]
     9/13: $0\csr_mie_meie[0:0]
    10/13: $0\csr_mie_mfie[15:0]
    11/13: $0\csr_mepc[31:0]
    12/13: $0\csr_mcycle[63:0]
    13/13: $0\csr_mcause[31:0]
Creating decoders for process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:0$636'.
Creating decoders for process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$630'.
     1/3: $0\counter[5:0]
     2/3: $0\state[1:0]
     3/3: $0\reset_o[0:0]
Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:0$56'.
Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:121$55'.
     1/1: { $1\pc_write[0:0] $1\alu_src_b[1:0] $1\ir_write[0:0] $1\memory_read[0:0] $1\memory_to_reg[1:0] $1\alu_src_a[1:0] $1\aluop[1:0] $1\csr_write_enable[0:0] $1\pc_write_cond[0:0] $1\memory_write[0:0] $1\reg_write[0:0] $1\pc_source[0:0] $1\lorD[0:0] $1\is_immediate[0:0] }
Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:79$53'.
     1/3: $3\nextstate[3:0]
     2/3: $2\nextstate[3:0]
     3/3: $1\nextstate[3:0]
Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:71$52'.
     1/1: $0\state[3:0]
Creating decoders for process `\ALU_Control.$proc$Risco-5/src/core/alu_control.v:9$48'.
     1/4: $4\aluop_out[3:0]
     2/4: $3\aluop_out[3:0]
     3/4: $2\aluop_out[3:0]
     4/4: $1\aluop_out[3:0]
Creating decoders for process `\Alu.$proc$Risco-5/src/core/alu.v:23$33'.
     1/1: $1\ALU_out_S[31:0]

23.4.8. Executing PROC_DLATCH pass (convert process syncs to latches).
No latch inferred for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.\n_fsm_state' from process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:116$779'.
No latch inferred for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.\n_fsm_state' from process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:98$722'.
No latch inferred for signal `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.\read_data' from process `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$proc$Risco-5/src/peripheral/memory.v:45$891'.
No latch inferred for signal `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART.\read_data' from process `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART.$proc$Risco-5/src/peripheral/uart.v:84$659'.
No latch inferred for signal `\Registers.$memwr$\registers$Risco-5/src/core/registers.v:16$89_EN' from process `\Registers.$proc$Risco-5/src/core/registers.v:0$113'.
No latch inferred for signal `\MUX.\S' from process `\MUX.$proc$Risco-5/src/core/mux.v:10$84'.
No latch inferred for signal `\Immediate_Generator.\immediate' from process `\Immediate_Generator.$proc$Risco-5/src/core/immediate_generator.v:18$82'.
No latch inferred for signal `\CSR_Unit.\csr_mcause_code' from process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:0$81'.
No latch inferred for signal `\CSR_Unit.\csr_mcause_interrupt_flag' from process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:0$81'.
No latch inferred for signal `\CSR_Unit.\csr_utime' from process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:0$81'.
No latch inferred for signal `\CSR_Unit.\csr_data_out' from process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:181$80'.
No latch inferred for signal `\CSR_Unit.\csr_write_data' from process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$76'.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [0]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$76`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [1]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$76`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [2]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$76`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [3]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$76`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [4]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$76`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [5]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$76`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [6]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$76`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [7]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$76`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [8]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$76`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [9]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$76`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [10]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$76`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [11]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$76`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [12]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$76`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [13]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$76`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [14]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$76`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [15]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$76`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [16]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$76`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [17]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$76`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [18]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$76`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [19]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$76`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [20]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$76`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [21]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$76`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [22]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$76`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [23]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$76`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [24]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$76`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [25]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$76`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [26]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$76`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [27]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$76`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [28]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$76`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [29]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$76`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [30]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$76`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [31]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$76`.
No latch inferred for signal `\Control_Unit.\is_immediate' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:121$55'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\is_immediate` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:121$55`.
No latch inferred for signal `\Control_Unit.\lorD' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:121$55'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\lorD` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:121$55`.
No latch inferred for signal `\Control_Unit.\pc_write' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:121$55'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\pc_write` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:121$55`.
No latch inferred for signal `\Control_Unit.\ir_write' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:121$55'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\ir_write` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:121$55`.
No latch inferred for signal `\Control_Unit.\pc_source' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:121$55'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\pc_source` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:121$55`.
No latch inferred for signal `\Control_Unit.\reg_write' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:121$55'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\reg_write` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:121$55`.
No latch inferred for signal `\Control_Unit.\memory_read' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:121$55'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_read` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:121$55`.
No latch inferred for signal `\Control_Unit.\memory_write' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:121$55'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_write` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:121$55`.
No latch inferred for signal `\Control_Unit.\pc_write_cond' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:121$55'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\pc_write_cond` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:121$55`.
No latch inferred for signal `\Control_Unit.\csr_write_enable' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:121$55'.
No latch inferred for signal `\Control_Unit.\aluop' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:121$55'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\aluop [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:121$55`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\aluop [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:121$55`.
No latch inferred for signal `\Control_Unit.\alu_src_a' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:121$55'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_a [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:121$55`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_a [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:121$55`.
No latch inferred for signal `\Control_Unit.\alu_src_b' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:121$55'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_b [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:121$55`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_b [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:121$55`.
No latch inferred for signal `\Control_Unit.\memory_to_reg' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:121$55'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_to_reg [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:121$55`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_to_reg [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:121$55`.
No latch inferred for signal `\Control_Unit.\nextstate' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:79$53'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:79$53`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:79$53`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [2]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:79$53`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [3]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:79$53`.
Latch inferred for signal `\ALU_Control.\aluop_out' from process `\ALU_Control.$proc$Risco-5/src/core/alu_control.v:9$48': $auto$proc_dlatch.cc:433:proc_dlatch$1958
No latch inferred for signal `\Alu.\ALU_out_S' from process `\Alu.$proc$Risco-5/src/core/alu.v:23$33'.

23.4.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `\TRELLIS_FF.\Q' using process `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$627'.
  created $dff cell `$procdff$1981' with positive edge clock.
Creating register for signal `\DPR16X4C.\i' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$602'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$563_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$602'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$564_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$602'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$565_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$602'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$566_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$602'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$567_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$602'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$568_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$602'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$569_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$602'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$570_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$602'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$571_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$602'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$572_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$602'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$573_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$602'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$574_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$602'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$575_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$602'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$576_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$602'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$577_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$602'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$578_ADDR' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$579'.
  created $dff cell `$procdff$1982' with positive edge clock.
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$578_DATA' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$579'.
  created $dff cell `$procdff$1983' with positive edge clock.
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$578_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$579'.
  created $dff cell `$procdff$1984' with positive edge clock.
Creating register for signal `\TRELLIS_DPR16X4.\i' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$545'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$503_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$545'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$504_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$545'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$505_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$545'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$506_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$545'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$507_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$545'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$508_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$545'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$509_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$545'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$510_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$545'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$511_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$545'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$512_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$545'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$513_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$545'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$514_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$545'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$515_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$545'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$516_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$545'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$517_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$545'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$518_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$545'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$519_ADDR' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$521'.
  created $dff cell `$procdff$1985' with positive edge cl[Pipeline] sh
ock.
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$519_DATA' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$521'.
  created $dff cell `$procdff$1986' with positive edge clock.
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$519_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$521'.
  created $dff cell `$procdff$1987' with positive edge clock.
Creating register for signal `\TRELLIS_DPR16X4.\muxwre' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$520'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.\read_data' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$Risco-5/src/peripheral/fifo.v:23$821'.
  created $dff cell `$procdff$1988' with positive edge clock.
Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.\read_ptr' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$Risco-5/src/peripheral/fifo.v:23$821'.
  created $dff cell `$procdff$1989' with positive edge clock.
Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.\write_ptr' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$Risco-5/src/peripheral/fifo.v:23$821'.
  created $dff cell `$procdff$1990' with positive edge clock.
Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$memwr$\memory$Risco-5/src/peripheral/fifo.v:29$811_ADDR' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$Risco-5/src/peripheral/fifo.v:23$821'.
  created $dff cell `$procdff$1991' with positive edge clock.
Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$memwr$\memory$Risco-5/src/peripheral/fifo.v:29$811_DATA' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$Risco-5/src/peripheral/fifo.v:23$821'.
  created $dff cell `$procdff$1992' with positive edge clock.
Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$memwr$\memory$Risco-5/src/peripheral/fifo.v:29$811_EN' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$Risco-5/src/peripheral/fifo.v:23$821'.
  created $dff cell `$procdff$1993' with positive edge clock.
Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.\rxd_reg' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:197$808'.
  created $dff cell `$procdff$1994' with positive edge clock.
Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.\rxd_reg_0' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:197$808'.
  created $dff cell `$procdff$1995' with positive edge clock.
Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.\fsm_state' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:186$806'.
  created $dff cell `$procdff$1996' with positive edge clock.
Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.\cycle_counter' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:171$798'.
  created $dff cell `$procdff$1997' with positive edge clock.
Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.\bit_sample' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:160$795'.
  created $dff cell `$procdff$1998' with positive edge clock.
Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.\bit_counter' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:148$789'.
  created $dff cell `$procdff$1999' with positive edge clock.
Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.\i' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:133$784'.
  created $dff cell `$procdff$2000' with positive edge clock.
Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.\recieved_data' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:133$784'.
  created $dff cell `$procdff$2001' with positive edge clock.
Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.\uart_rx_data' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:97$770'.
  created $dff cell `$procdff$2002' with positive edge clock.
Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.\txd_reg' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:173$757'.
  created $dff cell `$procdff$2003' with positive edge clock.
Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.\fsm_state' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:162$755'.
  created $dff cell `$procdff$2004' with positive edge clock.
Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.\cycle_counter' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:147$747'.
  created $dff cell `$procdff$2005' with positive edge clock.
Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.\bit_counter' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:130$733'.
  created $dff cell `$procdff$2006' with positive edge clock.
Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.\i' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:115$727'.
  created $dff cell `$procdff$2007' with positive edge clock.
Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.\data_to_send' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:115$727'.
  created $dff cell `$procdff$2008' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\instruction_register' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:179$712'.
  created $dff cell `$procdff$2009' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\memory_register' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:179$712'.
  created $dff cell `$procdff$2010' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\alu_out_register' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:179$712'.
  created $dff cell `$procdff$2011' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\register_data_1' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:179$712'.
  created $dff cell `$procdff$2012' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\register_data_2' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:179$712'.
  created $dff cell `$procdff$2013' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\pc_old' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:179$712'.
  created $dff cell `$procdff$2014' with positive edge clock.
Creating register for signal `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:36$848_ADDR' using process `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$proc$Risco-5/src/peripheral/memory.v:33$854'.
  created $dff cell `$procdff$2015' with positive edge clock.
Creating register for signal `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:36$848_DATA' using process `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$proc$Risco-5/src/peripheral/memory.v:33$854'.
  created $dff cell `$procdff$2016' with positive edge clock.
Creating register for signal `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:36$848_EN' using process `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$proc$Risco-5/src/peripheral/memory.v:33$854'.
  created $dff cell `$procdff$2017' with positive edge clock.
Creating register for signal `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:38$849_ADDR' using process `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$proc$Risco-5/src/peripheral/memory.v:33$854'.
  created $dff cell `$procdff$2018' with positive edge clock.
Creating register for signal `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:38$849_DATA' using process `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$proc$Risco-5/src/peripheral/memory.v:33$854'.
  created $dff cell `$procdff$2019' with positive edge clock.
Creating register for signal `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:38$849_EN' using process `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$proc$Risco-5/src/peripheral/memory.v:33$854'.
  created $dff cell `$procdff$2020' with positive edge clock.
Creating register for signal `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:40$850_ADDR' using process `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$proc$Risco-5/src/peripheral/memory.v:33$854'.
  created $dff cell `$procdff$2021' with positive edge clock.
Creating register for signal `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:40$850_DATA' using process `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$proc$Risco-5/src/peripheral/memory.v:33$854'.
  created $dff cell `$procdff$2022' with positive edge clock.
Creating register for signal `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:40$850_EN' using process `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$proc$Risco-5/src/peripheral/memory.v:33$854'.
  created $dff cell `$procdff$2023' with positive edge clock.
Creating register for signal `\LEDs.\data' using process `\LEDs.$proc$Risco-5/src/peripheral/leds.v:23$237'.
  created $dff cell `$procdff$2024' with positive edge clock.
Creating register for signal `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART.\uart_tx_en' using process `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART.$proc$Risco-5/src/peripheral/uart.v:42$642'.
  created $dff cell `$procdff$2025' with positive edge clock.
Creating register for signal `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART.\tx_fifo_read' using process `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART.$proc$Risco-5/src/peripheral/uart.v:42$642'.
  created $dff cell `$procdff$2026' with positive edge clock.
Creating register for signal `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART.\tx_fifo_write' using process `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART.$proc$Risco-5/src/peripheral/uart.v:42$642'.
  created $dff cell `$procdff$2027' with positive edge clock.
Creating register for signal `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART.\rx_fifo_read' using process `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART.$proc$Risco-5/src/peripheral/uart.v:42$642'.
  created $dff cell `$procdff$2028' with positive edge clock.
Creating register for signal `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART.\rx_fifo_write' using process `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART.$proc$Risco-5/src/peripheral/uart.v:42$642'.
  created $dff cell `$procdff$2029' with positive edge clock.
Creating register for signal `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART.\buffer_full' using process `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART.$proc$Risco-5/src/peripheral/uart.v:42$642'.
  created $dff cell `$procdff$2030' with positive edge clock.
Creating register for signal `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART.\uart_tx_data' using process `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART.$proc$Risco-5/src/peripheral/uart.v:42$642'.
  created $dff cell `$procdff$2031' with positive edge clock.
Creating register for signal `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART.\tx_fifo_write_data' using process `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART.$proc$Risco-5/src/peripheral/uart.v:42$642'.
  created $dff cell `$procdff$2032' with positive edge clock.
Creating register for signal `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART.\rx_fifo_write_data' using process `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART.$proc$Risco-5/src/peripheral/uart.v:42$642'.
  created $dff cell `$procdff$2033' with positive edge clock.
Creating register for signal `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART.\read_buffer' using process `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART.$proc$Risco-5/src/peripheral/uart.v:42$642'.
  created $dff cell `$procdff$2034' with positive edge clock.
Creating register for signal `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.\gpio_direction' using process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:29$846'.
  created $dff cell `$procdff$2035' with positive edge clock.
Creating register for signal `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.\gpio_value' using process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:29$846'.
  created $dff cell `$procdff$2036' with positive edge clock.
Creating register for signal `\Registers.$memwr$\registers$Risco-5/src/core/registers.v:24$90_EN' using process `\Registers.$proc$Risco-5/src/core/registers.v:22$95'.
  created $dff cell `$procdff$2037' with positive edge clock.
Creating register for signal `\Registers.$memwr$\registers$Risco-5/src/core/registers.v:26$91_ADDR' using process `\Registers.$proc$Risco-5/src/core/registers.v:22$95'.
  created $dff cell `$procdff$2038' with positive edge clock.
Creating register for signal `\Registers.$memwr$\registers$Risco-5/src/core/registers.v:26$91_DATA' using process `\Registers.$proc$Risco-5/src/core/registers.v:22$95'.
  created $dff cell `$procdff$2039' with positive edge clock.
Creating register for signal `\Registers.$memwr$\registers$Risco-5/src/core/registers.v:26$91_EN' using process `\Registers.$proc$Risco-5/src/core/registers.v:22$95'.
  created $dff cell `$procdff$2040' with positive edge clock.
Creating register for signal `\Registers.$memwr$\registers$Risco-5/src/core/registers.v:28$92_EN' using process `\Registers.$proc$Risco-5/src/core/registers.v:22$95'.
  created $dff cell `$procdff$2041' with positive edge clock.
Creating register for signal `\PC.\Output' using process `\PC.$proc$Risco-5/src/core/pc.v:15$85'.
  created $dff cell `$procdff$2042' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mip_mfip' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:158$74'.
  created $dff cell `$procdff$2043' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mip_meip' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:158$74'.
  created $dff cell `$procdff$2044' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mip_mtip' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:158$74'.
  created $dff cell `$procdff$2045' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mip_msip' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:158$74'.
  created $dff cell `$procdff$2046' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mcause' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:113$67'.
  created $dff cell `$procdff$2047' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mcycle' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:113$67'.
  created $dff cell `$procdff$2048' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mepc' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:113$67'.
  created $dff cell `$procdff$2049' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mie_mfie' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:113$67'.
  created $dff cell `$procdff$2050' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mie_meie' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:113$67'.
  created $dff cell `$procdff$2051' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mie_msie' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:113$67'.
  created $dff cell `$procdff$2052' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mie_mtie' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:113$67'.
  created $dff cell `$procdff$2053' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_minstret' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:113$67'.
  created $dff cell `$procdff$2054' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mscratch' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:113$67'.
  created $dff cell `$procdff$2055' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mstatus_mie' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:113$67'.
  created $dff cell `$procdff$2056' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mstatus_mpie' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:113$67'.
  created $dff cell `$procdff$2057' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mtvec' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:113$67'.
  created $dff cell `$procdff$2058' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mtval' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:113$67'.
  created $dff cell `$procdff$2059' with positive edge clock.
Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\reset_o' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$630'.
  created $dff cell `$procdff$2060' with positive edge clock.
Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\state' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$630'.
  created $dff cell `$procdff$2061' with positive edge clock.
Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\counter' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$630'.
  created $dff cell `$procdff$2062' with positive edge clock.
Creating register for signal `\Control_Unit.\state' using process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:71$52'.
  created $dff cell `$procdff$2063' with positive edge clock.

23.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

23.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$628'.
Found and cleaned up 2 empty switches in `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$627'.
Removing empty process `TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$627'.
Removing empty process `DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$602'.
Found and cleaned up 1 empty switch in `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$579'.
Removing empty process `TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$545'.
Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$521'.
Removing empty process `TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$520'.
Found and cleaned up 3 empty switches in `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$Risco-5/src/peripheral/fifo.v:23$821'.
Removing empty process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$Risco-5/src/peripheral/fifo.v:23$821'.
Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:132$810'.
Found and cleaned up 2 empty switches in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:197$808'.
Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:197$808'.
Found and cleaned up 1 empty switch in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:186$806'.
Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:186$806'.
Found and cleaned up 3 empty switches in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:171$798'.
Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:171$798'.
Found and cleaned up 2 empty switches in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:160$795'.
Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:160$795'.
Found and cleaned up 3 empty switches in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:148$789'.
Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:148$789'.
Found and cleaned up 3 empty switches in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:133$784'.
Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:133$784'.
Found and cleaned up 1 empty switch in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:116$779'.
Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:116$779'.
Found and cleaned up 2 empty switches in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:97$770'.
Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:97$770'.
Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:114$763'.
Found and cleaned up 5 empty switches in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:173$757'.
Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:173$757'.
Found and cleaned up 1 empty switch in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:162$755'.
Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:162$755'.
Found and cleaned up 3 empty switches in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:147$747'.
Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:147$747'.
Found and cleaned up 5 empty switches in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:130$733'.
Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:130$733'.
Found and cleaned up 3 empty switches in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:115$727'.
Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:115$727'.
Found and cleaned up 1 empty switch in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:98$722'.
Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:98$722'.
Removing empty process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:0$715'.
Found and cleaned up 2 empty switches in `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:179$712'.
Removing empty process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:179$712'.
Found and cleaned up 1 empty switch in `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$proc$Risco-5/src/peripheral/memory.v:45$891'.
Removing empty process `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$proc$Risco-5/src/peripheral/memory.v:45$891'.
Found and cleaned up 3 empty switches in `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$proc$Risco-5/src/peripheral/memory.v:33$854'.
Removing empty process `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$proc$Risco-5/src/peripheral/memory.v:33$854'.
Removing empty process `LEDs.$proc$Risco-5/src/peripheral/leds.v:0$240'.
Found and cleaned up 2 empty switches in `\LEDs.$proc$Risco-5/src/peripheral/leds.v:23$237'.
Removing empty process `LEDs.$proc$Risco-5/src/peripheral/leds.v:23$237'.
Removing empty process `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART.$proc$Risco-5/src/peripheral/uart.v:0$662'.
Found and cleaned up 1 empty switch in `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART.$proc$Risco-5/src/peripheral/uart.v:84$659'.
Removing empty process `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART.$proc$Risco-5/src/peripheral/uart.v:84$659'.
Found and cleaned up 6 empty switches in `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART.$proc$Risco-5/src/peripheral/uart.v:42$642'.
Removing empty process `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART.$proc$Risco-5/src/peripheral/uart.v:42$642'.
Found and cleaned up 3 empty switches in `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:29$846'.
Removing empty process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:29$846'.
Removing empty process `Registers.$proc$Risco-5/src/core/registers.v:0$113'.
Found and cleaned up 2 empty switches in `\Registers.$proc$Risco-5/src/core/registers.v:22$95'.
Removing empty process `Registers.$proc$Risco-5/src/core/registers.v:22$95'.
Removing empty process `PC.$proc$Risco-5/src/core/pc.v:0$88'.
Found and cleaned up 2 empty switches in `\PC.$proc$Risco-5/src/core/pc.v:15$85'.
Removing empty process `PC.$proc$Risco-5/src/core/pc.v:15$85'.
Found and cleaned up 1 empty switch in `\MUX.$proc$Risco-5/src/core/mux.v:10$84'.
Removing empty process `MUX.$proc$Risco-5/src/core/mux.v:10$84'.
Found and cleaned up 4 empty switches in `\Immediate_Generator.$proc$Risco-5/src/core/immediate_generator.v:18$82'.
Removing empty process `Immediate_Generator.$proc$Risco-5/src/core/immediate_generator.v:18$82'.
Removing empty process `CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:0$81'.
Found and cleaned up 1 empty switch in `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:181$80'.
Removing empty process `CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:181$80'.
Found and cleaned up 1 empty switch in `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$76'.
Removing empty process `CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$76'.
Found and cleaned up 1 empty switch in `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:158$74'.
Removing empty process `CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:158$74'.
Found and cleaned up 3 empty switches in `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:113$67'.
Removing empty process `CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:113$67'.
Removing empty process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:0$636'.
Found and cleaned up 5 empty switches in `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$630'.
Removing empty process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$630'.
Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:0$56'.
Found and cleaned up 1 empty switch in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:121$55'.
Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:121$55'.
Found and cleaned up 3 empty switches in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:79$53'.
Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:79$53'.
Found and cleaned up 1 empty switch in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:71$52'.
Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:71$52'.
Found and cleaned up 4 empty switches in `\ALU_Control.$proc$Risco-5/src/core/alu_control.v:9$48'.
Removing empty process `ALU_Control.$proc$Risco-5/src/core/alu_control.v:9$48'.
Found and cleaned up 1 empty switch in `\Alu.$proc$Risco-5/src/core/alu.v:23$33'.
Removing empty process `Alu.$proc$Risco-5/src/core/alu.v:23$33'.
Cleaned up 90 empty switches.

23.4.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.
<suppressed ~4 debug messages>
Optimizing module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.
<suppressed ~21 debug messages>
Optimizing module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.
<suppressed ~19 debug messages>
Optimizing module $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.
<suppressed ~4 debug messages>
Optimizing module $paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.
<suppressed ~5 debug messages>
Optimizing module LEDs.
<suppressed ~3 debug messages>
Optimizing module $paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART.
<suppressed ~11 debug messages>
Optimizing module GPIO.
<suppressed ~3 debug messages>
Optimizing module $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.
<suppressed ~4 debug messages>
Optimizing module BUS.
Optimizing module Registers.
<suppressed ~2 debug messages>
Optimizing module PC.
<suppressed ~2 debug messages>
Optimizing module MUX.
<suppressed ~1 debug messages>
Optimizing module Immediate_Generator.
<suppressed ~1 debug messages>
Optimizing module CSR_Unit.
<suppressed ~2 debug messages>
Optimizing module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.
<suppressed ~7 debug messages>
Optimizing module Control_Unit.
<suppressed ~1 debug messages>
Optimizing module ALU_Control.
<suppressed ~15 debug messages>
Optimizing module Alu.
<suppressed ~1 debug messages>
Optimizing module $paramod$3a9006d2d69ee0c2bdc9f053e7d4480adeb7a508\Risco_5_SOC.
Optimizing module top.

23.5. Executing FLATTEN pass (flatten design).
Deleting now unused module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.
Deleting now unused module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.
Deleting now unused module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.
Deleting now unused module $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.
Deleting now unused module $paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.
Deleting now unused module LEDs.
Deleting now unused module $paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART.
Deleting now unused module GPIO.
Deleting now unused module $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.
Deleting now unused module BUS.
Deleting now unused module Registers.
Deleting now unused module PC.
Deleting now unused module MUX.
Deleting now unused module Immediate_Generator.
Deleting now unused module CSR_Unit.
Deleting now unused module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.
Deleting now unused module Control_Unit.
Deleting now unused module ALU_Control.
Deleting now unused module Alu.
Deleting now unused module $paramod$3a9006d2d69ee0c2bdc9f053e7d4480adeb7a508\Risco_5_SOC.
<suppressed ~30 debug messages>

23.6. Executing TRIBUF pass.

23.7. Executing DEMINOUT pass (demote inout ports to input or output).

23.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~47 debug messages>

23.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 62 unused cells and 735 unused wires.
<suppressed ~79 debug messages>

23.10. Executing CHECK pass (checking for obvious problems).
Checking module top...
Warning: Wire top.\SOC.Core.PCSourceMUX.C [31] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [30] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [29] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [28] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [27] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [26] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [25] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [24] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [23] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [22] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [21] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [20] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [19] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [18] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [17] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [16] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [15] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [14] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [13] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [12] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [11] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [10] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [9] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [8] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [7] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [6] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [5] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [4] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [3] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [2] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [1] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [0] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [31] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [30] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [29] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [28] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [27] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [26] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [25] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [24] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [23] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [22] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [21] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [20] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [19] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [18] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [17] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [16] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [15] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [14] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [13] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [12] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [11] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [10] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [9] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [8] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [7] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [6] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [5] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [4] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [3] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [2] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [1] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [0] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [31] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [30] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [29] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [28] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [27] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [26] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [25] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [24] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [23] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [22] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [21] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [20] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [19] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [18] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [17] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [16] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [15] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [14] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [13] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [12] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [11] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [10] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [9] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [8] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [7] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [6] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [5] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [4] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [3] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [2] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [1] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [0] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [31] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [30] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [29] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [28] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [27] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [26] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [25] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [24] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [23] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [22] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [21] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [20] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [19] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [18] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [17] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [16] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [15] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [14] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [13] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [12] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [11] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [10] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [9] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [8] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [7] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [6] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [5] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [4] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [3] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [2] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [1] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [0] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [31] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [30] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [29] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [28] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [27] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [26] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [25] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [24] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [23] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [22] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [21] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [20] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [19] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [18] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [17] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [16] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [15] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [14] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [13] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [12] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [11] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [10] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [9] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [8] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [7] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [6] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [5] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [4] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [3] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [2] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [1] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [0] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.irq_fast [15] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.irq_fast [14] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.irq_fast [13] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.irq_fast [12] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.irq_fast [11] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.irq_fast [10] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.irq_fast [9] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.irq_fast [8] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.irq_fast [7] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.irq_fast [6] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.irq_fast [5] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.irq_fast [4] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.irq_fast [3] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.irq_fast [2] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.irq_fast [1] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.irq_fast [0] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.irq_external is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.irq_timer is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.irq_software is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [31] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [30] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [29] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [28] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [27] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [26] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [25] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [24] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [23] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [22] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [21] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [20] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [19] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [18] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [17] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [16] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [15] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [14] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [13] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [12] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [11] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [10] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [9] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [8] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [7] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [6] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [5] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [4] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [3] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [2] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [1] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [0] is used but has no driver.
Found and reported 211 problems.

23.11. Executing OPT pass (performing simple optimizations).

23.11.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~6 debug messages>

23.11.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~354 debug messages>
Removed a total of 118 cells.

23.11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$1852.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$1880.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Immediate_Generator.$procmux$1528.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Immediate_Generator.$procmux$1530.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Immediate_Generator.$procmux$1541.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Immediate_Generator.$procmux$1556.
    dead port 1/5 on $pmux $flatten\SOC.\Core.\MemoryAddressMUX.$procmux$1515.
    dead port 2/5 on $pmux $flatten\SOC.\Core.\MemoryAddressMUX.$procmux$1515.
    dead port 1/5 on $pmux $flatten\SOC.\Core.\PCSourceMUX.$procmux$1515.
    dead port 2/5 on $pmux $flatten\SOC.\Core.\PCSourceMUX.$procmux$1515.
    dead port 1/2 on $mux $flatten\SOC.\Core.\RegisterBank.$procmux$1475.
    dead port 1/2 on $mux $flatten\SOC.\Core.\RegisterBank.$procmux$1481.
    dead port 1/2 on $mux $flatten\SOC.\Core.\RegisterBank.$procmux$1487.
    dead port 1/2 on $mux $flatten\SOC.\Core.\RegisterBank.$procmux$1493.
    dead port 1/2 on $mux $flatten\SOC.\Memory.$procmux$1263.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1265.
    dead port 1/2 on $mux $flatten\SOC.\Memory.$procmux$1272.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1274.
    dead port 1/2 on $mux $flatten\SOC.\Memory.$procmux$1281.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1283.
    dead port 1/2 on $mux $flatten\SOC.\Memory.$procmux$1290.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1292.
    dead port 1/2 on $mux $flatten\SOC.\Memory.$procmux$1299.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1301.
    dead port 1/2 on $mux $flatten\SOC.\Memory.$procmux$1308.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1310.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1316.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1322.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1328.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1334.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1340.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1346.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1352.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1358.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1364.
    dead port 1/2 on $mux $flatten\SOC.\Uart.\RX_FIFO.$procmux$925.
    dead port 1/2 on $mux $flatten\SOC.\Uart.\RX_FIFO.$procmux$931.
    dead port 1/2 on $mux $flatten\SOC.\Uart.\RX_FIFO.$procmux$937.
    dead port 1/2 on $mux $flatten\SOC.\Uart.\TX_FIFO.$procmux$925.
    dead port 1/2 on $mux $flatten\SOC.\Uart.\TX_FIFO.$procmux$931.
    dead port 1/2 on $mux $flatten\SOC.\Uart.\TX_FIFO.$procmux$937.
Removed 41 multiplexer ports.
<suppressed ~124 debug messages>

23.11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\CSR_Unit.$procmux$1570: { $flatten\SOC.\Core.\CSR_Unit.$procmux$1591_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1590_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1583_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1582_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1581_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1580_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1579_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1578_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1577_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1576_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1575_CMP $auto$opt_reduce.cc:134:opt_pmux$2120 $auto$opt_reduce.cc:134:opt_pmux$2118 $auto$opt_reduce.cc:134:opt_pmux$2116 $auto$opt_reduce.cc:134:opt_pmux$2114 }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$1869: { $auto$opt_reduce.cc:134:opt_pmux$2122 $flatten\SOC.\Core.\Control_Unit.$procmux$1877_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1876_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1875_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1874_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1873_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1872_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1871_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1870_CMP }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\ALU_Control.$procmux$1918: { $flatten\SOC.\Core.\ALU_Control.$procmux$1925_CMP $auto$opt_reduce.cc:134:opt_pmux$2124 $flatten\SOC.\Core.\ALU_Control.$procmux$1922_CMP $flatten\SOC.\Core.\ALU_Control.$procmux$1921_CMP $flatten\SOC.\Core.\ALU_Control.$procmux$1920_CMP $flatten\SOC.\Core.\ALU_Control.$procmux$1919_CMP }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$1882: { $flatten\SOC.\Core.\Control_Unit.$procmux$1898_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1881_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1853_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1895_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1887_CMP $auto$opt_reduce.cc:134:opt_pmux$2128 $auto$opt_reduce.cc:134:opt_pmux$2126 }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Immediate_Generator.$procmux$1553: $auto$opt_reduce.cc:134:opt_pmux$2130
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Immediate_Generator.$procmux$1559: { $flatten\SOC.\Core.\Control_Unit.$procmux$1874_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1875_CMP $auto$opt_reduce.cc:134:opt_pmux$2134 $flatten\SOC.\Core.\Control_Unit.$procmux$1876_CMP $auto$opt_reduce.cc:134:opt_pmux$2132 $flatten\SOC.\Core.\Control_Unit.$procmux$1870_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1878_CMP }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\RegisterBank.$procmux$1472:
      Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\SOC.\Core.\RegisterBank.$procmux$1472_Y
      New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Core.\RegisterBank.$procmux$1472_Y [0]
      New connections: $flatten\SOC.\Core.\RegisterBank.$procmux$1472_Y [31:1] = { $flatten\SOC.\Core.\RegisterBank.$procmux$1472_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1472_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1472_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1472_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1472_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1472_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1472_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1472_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1472_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1472_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1472_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1472_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1472_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1472_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1472_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1472_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1472_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1472_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1472_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1472_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1472_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1472_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1472_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1472_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1472_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1472_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1472_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1472_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1472_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1472_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1472_Y [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\RegisterBank.$procmux$1490:
      Old ports: A=32'11111111111111111111111111111111, B=0, Y=$flatten\SOC.\Core.\RegisterBank.$procmux$1490_Y
      New ports: A=1'1, B=1'0, Y=$flatten\SOC.\Core.\RegisterBank.$procmux$1490_Y [0]
      New connections: $flatten\SOC.\Core.\RegisterBank.$procmux$1490_Y [31:1] = { $flatten\SOC.\Core.\RegisterBank.$procmux$1490_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1490_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1490_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1490_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1490_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1490_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1490_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1490_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1490_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1490_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1490_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1490_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1490_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1490_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1490_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1490_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1490_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1490_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1490_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1490_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1490_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1490_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1490_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1490_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1490_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1490_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1490_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1490_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1490_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1490_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1490_Y [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\RegisterBank.$procmux$1496:
      Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$90_EN[31:0]$96
      New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$90_EN[31:0]$96 [0]
      New connections: $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$90_EN[31:0]$96 [31:1] = { $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$90_EN[31:0]$96 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$90_EN[31:0]$96 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$90_EN[31:0]$96 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$90_EN[31:0]$96 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$90_EN[31:0]$96 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$90_EN[31:0]$96 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$90_EN[31:0]$96 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$90_EN[31:0]$96 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$90_EN[31:0]$96 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$90_EN[31:0]$96 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$90_EN[31:0]$96 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$90_EN[31:0]$96 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$90_EN[31:0]$96 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$90_EN[31:0]$96 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$90_EN[31:0]$96 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$90_EN[31:0]$96 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$90_EN[31:0]$96 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$90_EN[31:0]$96 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$90_EN[31:0]$96 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$90_EN[31:0]$96 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$90_EN[31:0]$96 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$90_EN[31:0]$96 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$90_EN[31:0]$96 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$90_EN[31:0]$96 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$90_EN[31:0]$96 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$90_EN[31:0]$96 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$90_EN[31:0]$96 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$90_EN[31:0]$96 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$90_EN[31:0]$96 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$90_EN[31:0]$96 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$90_EN[31:0]$96 [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1260:
      Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\SOC.\Memory.$procmux$1260_Y
      New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Memory.$procmux$1260_Y [0]
      New connections: $flatten\SOC.\Memory.$procmux$1260_Y [31:1] = { $flatten\SOC.\Memory.$procmux$1260_Y [0] $flatten\SOC.\Memory.$procmux$1260_Y [0] $flatten\SOC.\Memory.$procmux$1260_Y [0] $flatten\SOC.\Memory.$procmux$1260_Y [0] $flatten\SOC.\Memory.$procmux$1260_Y [0] $flatten\SOC.\Memory.$procmux$1260_Y [0] $flatten\SOC.\Memory.$procmux$1260_Y [0] $flatten\SOC.\Memory.$procmux$1260_Y [0] $flatten\SOC.\Memory.$procmux$1260_Y [0] $flatten\SOC.\Memory.$procmux$1260_Y [0] $flatten\SOC.\Memory.$procmux$1260_Y [0] $flatten\SOC.\Memory.$procmux$1260_Y [0] $flatten\SOC.\Memory.$procmux$1260_Y [0] $flatten\SOC.\Memory.$procmux$1260_Y [0] $flatten\SOC.\Memory.$procmux$1260_Y [0] $flatten\SOC.\Memory.$procmux$1260_Y [0] $flatten\SOC.\Memory.$procmux$1260_Y [0] $flatten\SOC.\Memory.$procmux$1260_Y [0] $flatten\SOC.\Memory.$procmux$1260_Y [0] $flatten\SOC.\Memory.$procmux$1260_Y [0] $flatten\SOC.\Memory.$procmux$1260_Y [0] $flatten\SOC.\Memory.$procmux$1260_Y [0] $flatten\SOC.\Memory.$procmux$1260_Y [0] $flatten\SOC.\Memory.$procmux$1260_Y [0] $flatten\SOC.\Memory.$procmux$1260_Y [0] $flatten\SOC.\Memory.$procmux$1260_Y [0] $flatten\SOC.\Memory.$procmux$1260_Y [0] $flatten\SOC.\Memory.$procmux$1260_Y [0] $flatten\SOC.\Memory.$procmux$1260_Y [0] $flatten\SOC.\Memory.$procmux$1260_Y [0] $flatten\SOC.\Memory.$procmux$1260_Y [0] }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\ALU_Control.$procmux$1932: { $auto$opt_reduce.cc:134:opt_pmux$2138 $auto$opt_reduce.cc:134:opt_pmux$2136 $flatten\SOC.\Core.\ALU_Control.$procmux$1925_CMP }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1287:
      Old ports: A=32'11111111111111111111111111111111, B=0, Y=$flatten\SOC.\Memory.$procmux$1287_Y
      New ports: A=1'1, B=1'0, Y=$flatten\SOC.\Memory.$procmux$1287_Y [0]
      New connections: $flatten\SOC.\Memory.$procmux$1287_Y [31:1] = { $flatten\SOC.\Memory.$procmux$1287_Y [0] $flatten\SOC.\Memory.$procmux$1287_Y [0] $flatten\SOC.\Memory.$procmux$1287_Y [0] $flatten\SOC.\Memory.$procmux$1287_Y [0] $flatten\SOC.\Memory.$procmux$1287_Y [0] $flatten\SOC.\Memory.$procmux$1287_Y [0] $flatten\SOC.\Memory.$procmux$1287_Y [0] $flatten\SOC.\Memory.$procmux$1287_Y [0] $flatten\SOC.\Memory.$procmux$1287_Y [0] $flatten\SOC.\Memory.$procmux$1287_Y [0] $flatten\SOC.\Memory.$procmux$1287_Y [0] $flatten\SOC.\Memory.$procmux$1287_Y [0] $flatten\SOC.\Memory.$procmux$1287_Y [0] $flatten\SOC.\Memory.$procmux$1287_Y [0] $flatten\SOC.\Memory.$procmux$1287_Y [0] $flatten\SOC.\Memory.$procmux$1287_Y [0] $flatten\SOC.\Memory.$procmux$1287_Y [0] $flatten\SOC.\Memory.$procmux$1287_Y [0] $flatten\SOC.\Memory.$procmux$1287_Y [0] $flatten\SOC.\Memory.$procmux$1287_Y [0] $flatten\SOC.\Memory.$procmux$1287_Y [0] $flatten\SOC.\Memory.$procmux$1287_Y [0] $flatten\SOC.\Memory.$procmux$1287_Y [0] $flatten\SOC.\Memory.$procmux$1287_Y [0] $flatten\SOC.\Memory.$procmux$1287_Y [0] $flatten\SOC.\Memory.$procmux$1287_Y [0] $flatten\SOC.\Memory.$procmux$1287_Y [0] $flatten\SOC.\Memory.$procmux$1287_Y [0] $flatten\SOC.\Memory.$procmux$1287_Y [0] $flatten\SOC.\Memory.$procmux$1287_Y [0] $flatten\SOC.\Memory.$procmux$1287_Y [0] }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\ALU_Control.$procmux$1941: { $flatten\SOC.\Core.\ALU_Control.$procmux$1943_CMP $flatten\SOC.\Core.\ALU_Control.$procmux$1942_CMP }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1314:
      Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\SOC.\Memory.$procmux$1314_Y
      New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Memory.$procmux$1314_Y [0]
      New connections: $flatten\SOC.\Memory.$procmux$1314_Y [31:1] = { $flatten\SOC.\Memory.$procmux$1314_Y [0] $flatten\SOC.\Memory.$procmux$1314_Y [0] $flatten\SOC.\Memory.$procmux$1314_Y [0] $flatten\SOC.\Memory.$procmux$1314_Y [0] $flatten\SOC.\Memory.$procmux$1314_Y [0] $flatten\SOC.\Memory.$procmux$1314_Y [0] $flatten\SOC.\Memory.$procmux$1314_Y [0] $flatten\SOC.\Memory.$procmux$1314_Y [0] $flatten\SOC.\Memory.$procmux$1314_Y [0] $flatten\SOC.\Memory.$procmux$1314_Y [0] $flatten\SOC.\Memory.$procmux$1314_Y [0] $flatten\SOC.\Memory.$procmux$1314_Y [0] $flatten\SOC.\Memory.$procmux$1314_Y [0] $flatten\SOC.\Memory.$procmux$1314_Y [0] $flatten\SOC.\Memory.$procmux$1314_Y [0] $flatten\SOC.\Memory.$procmux$1314_Y [0] $flatten\SOC.\Memory.$procmux$1314_Y [0] $flatten\SOC.\Memory.$procmux$1314_Y [0] $flatten\SOC.\Memory.$procmux$1314_Y [0] $flatten\SOC.\Memory.$procmux$1314_Y [0] $flatten\SOC.\Memory.$procmux$1314_Y [0] $flatten\SOC.\Memory.$procmux$1314_Y [0] $flatten\SOC.\Memory.$procmux$1314_Y [0] $flatten\SOC.\Memory.$procmux$1314_Y [0] $flatten\SOC.\Memory.$procmux$1314_Y [0] $flatten\SOC.\Memory.$procmux$1314_Y [0] $flatten\SOC.\Memory.$procmux$1314_Y [0] $flatten\SOC.\Memory.$procmux$1314_Y [0] $flatten\SOC.\Memory.$procmux$1314_Y [0] $flatten\SOC.\Memory.$procmux$1314_Y [0] $flatten\SOC.\Memory.$procmux$1314_Y [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\RX_FIFO.$procmux$922:
      Old ports: A=8'00000000, B=8'11111111, Y=$flatten\SOC.\Uart.\RX_FIFO.$procmux$922_Y
      New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Uart.\RX_FIFO.$procmux$922_Y [0]
      New connections: $flatten\SOC.\Uart.\RX_FIFO.$procmux$922_Y [7:1] = { $flatten\SOC.\Uart.\RX_FIFO.$procmux$922_Y [0] $flatten\SOC.\Uart.\RX_FIFO.$procmux$922_Y [0] $flatten\SOC.\Uart.\RX_FIFO.$procmux$922_Y [0] $flatten\SOC.\Uart.\RX_FIFO.$procmux$922_Y [0] $flatten\SOC.\Uart.\RX_FIFO.$procmux$922_Y [0] $flatten\SOC.\Uart.\RX_FIFO.$procmux$922_Y [0] $flatten\SOC.\Uart.\RX_FIFO.$procmux$922_Y [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\TX_FIFO.$procmux$922:
      Old ports: A=8'00000000, B=8'11111111, Y=$flatten\SOC.\Uart.\TX_FIFO.$procmux$922_Y
      New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Uart.\TX_FIFO.$procmux$922_Y [0]
      New connections: $flatten\SOC.\Uart.\TX_FIFO.$procmux$922_Y [7:1] = { $flatten\SOC.\Uart.\TX_FIFO.$procmux$922_Y [0] $flatten\SOC.\Uart.\TX_FIFO.$procmux$922_Y [0] $flatten\SOC.\Uart.\TX_FIFO.$procmux$922_Y [0] $flatten\SOC.\Uart.\TX_FIFO.$procmux$922_Y [0] $flatten\SOC.\Uart.\TX_FIFO.$procmux$922_Y [0] $flatten\SOC.\Uart.\TX_FIFO.$procmux$922_Y [0] $flatten\SOC.\Uart.\TX_FIFO.$procmux$922_Y [0] }
  Optimizing cells in module \top.
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\RegisterBank.$procmux$1499:
      Old ports: A=$flatten\SOC.\Core.\RegisterBank.$2$memwr$\registers$Risco-5/src/core/registers.v:28$92_EN[31:0]$111, B=0, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$92_EN[31:0]$100
      New ports: A=$flatten\SOC.\Core.\RegisterBank.$procmux$1490_Y [0], B=1'0, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$92_EN[31:0]$100 [0]
      New connections: $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$92_EN[31:0]$100 [31:1] = { $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$92_EN[31:0]$100 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$92_EN[31:0]$100 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$92_EN[31:0]$100 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$92_EN[31:0]$100 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$92_EN[31:0]$100 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$92_EN[31:0]$100 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$92_EN[31:0]$100 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$92_EN[31:0]$100 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$92_EN[31:0]$100 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$92_EN[31:0]$100 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$92_EN[31:0]$100 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$92_EN[31:0]$100 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$92_EN[31:0]$100 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$92_EN[31:0]$100 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$92_EN[31:0]$100 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$92_EN[31:0]$100 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$92_EN[31:0]$100 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$92_EN[31:0]$100 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$92_EN[31:0]$100 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$92_EN[31:0]$100 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$92_EN[31:0]$100 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$92_EN[31:0]$100 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$92_EN[31:0]$100 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$92_EN[31:0]$100 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$92_EN[31:0]$100 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$92_EN[31:0]$100 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$92_EN[31:0]$100 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$92_EN[31:0]$100 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$92_EN[31:0]$100 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$92_EN[31:0]$100 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$92_EN[31:0]$100 [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\RegisterBank.$procmux$1502:
      Old ports: A=$flatten\SOC.\Core.\RegisterBank.$2$memwr$\registers$Risco-5/src/core/registers.v:26$91_EN[31:0]$110, B=0, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$91_EN[31:0]$99
      New ports: A=$flatten\SOC.\Core.\RegisterBank.$procmux$1472_Y [0], B=1'0, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$91_EN[31:0]$99 [0]
      New connections: $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$91_EN[31:0]$99 [31:1] = { $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$91_EN[31:0]$99 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$91_EN[31:0]$99 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$91_EN[31:0]$99 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$91_EN[31:0]$99 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$91_EN[31:0]$99 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$91_EN[31:0]$99 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$91_EN[31:0]$99 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$91_EN[31:0]$99 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$91_EN[31:0]$99 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$91_EN[31:0]$99 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$91_EN[31:0]$99 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$91_EN[31:0]$99 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$91_EN[31:0]$99 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$91_EN[31:0]$99 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$91_EN[31:0]$99 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$91_EN[31:0]$99 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$91_EN[31:0]$99 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$91_EN[31:0]$99 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$91_EN[31:0]$99 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$91_EN[31:0]$99 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$91_EN[31:0]$99 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$91_EN[31:0]$99 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$91_EN[31:0]$99 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$91_EN[31:0]$99 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$91_EN[31:0]$99 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$91_EN[31:0]$99 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$91_EN[31:0]$99 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$91_EN[31:0]$99 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$91_EN[31:0]$99 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$91_EN[31:0]$99 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$91_EN[31:0]$99 [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1332:
      Old ports: A=$flatten\SOC.\Memory.$3$memwr$\memory$Risco-5/src/peripheral/memory.v:40$850_EN[31:0]$890, B=0, Y=$flatten\SOC.\Memory.$procmux$1332_Y
      New ports: A=$flatten\SOC.\Memory.$procmux$1287_Y [0], B=1'0, Y=$flatten\SOC.\Memory.$procmux$1332_Y [0]
      New connections: $flatten\SOC.\Memory.$procmux$1332_Y [31:1] = { $flatten\SOC.\Memory.$procmux$1332_Y [0] $flatten\SOC.\Memory.$procmux$1332_Y [0] $flatten\SOC.\Memory.$procmux$1332_Y [0] $flatten\SOC.\Memory.$procmux$1332_Y [0] $flatten\SOC.\Memory.$procmux$1332_Y [0] $flatten\SOC.\Memory.$procmux$1332_Y [0] $flatten\SOC.\Memory.$procmux$1332_Y [0] $flatten\SOC.\Memory.$procmux$1332_Y [0] $flatten\SOC.\Memory.$procmux$1332_Y [0] $flatten\SOC.\Memory.$procmux$1332_Y [0] $flatten\SOC.\Memory.$procmux$1332_Y [0] $flatten\SOC.\Memory.$procmux$1332_Y [0] $flatten\SOC.\Memory.$procmux$1332_Y [0] $flatten\SOC.\Memory.$procmux$1332_Y [0] $flatten\SOC.\Memory.$procmux$1332_Y [0] $flatten\SOC.\Memory.$procmux$1332_Y [0] $flatten\SOC.\Memory.$procmux$1332_Y [0] $flatten\SOC.\Memory.$procmux$1332_Y [0] $flatten\SOC.\Memory.$procmux$1332_Y [0] $flatten\SOC.\Memory.$procmux$1332_Y [0] $flatten\SOC.\Memory.$procmux$1332_Y [0] $flatten\SOC.\Memory.$procmux$1332_Y [0] $flatten\SOC.\Memory.$procmux$1332_Y [0] $flatten\SOC.\Memory.$procmux$1332_Y [0] $flatten\SOC.\Memory.$procmux$1332_Y [0] $flatten\SOC.\Memory.$procmux$1332_Y [0] $flatten\SOC.\Memory.$procmux$1332_Y [0] $flatten\SOC.\Memory.$procmux$1332_Y [0] $flatten\SOC.\Memory.$procmux$1332_Y [0] $flatten\SOC.\Memory.$procmux$1332_Y [0] $flatten\SOC.\Memory.$procmux$1332_Y [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1350:
      Old ports: A=$flatten\SOC.\Memory.$3$memwr$\memory$Risco-5/src/peripheral/memory.v:38$849_EN[31:0]$887, B=0, Y=$flatten\SOC.\Memory.$procmux$1350_Y
      New ports: A=$flatten\SOC.\Memory.$procmux$1260_Y [0], B=1'0, Y=$flatten\SOC.\Memory.$procmux$1350_Y [0]
      New connections: $flatten\SOC.\Memory.$procmux$1350_Y [31:1] = { $flatten\SOC.\Memory.$procmux$1350_Y [0] $flatten\SOC.\Memory.$procmux$1350_Y [0] $flatten\SOC.\Memory.$procmux$1350_Y [0] $flatten\SOC.\Memory.$procmux$1350_Y [0] $flatten\SOC.\Memory.$procmux$1350_Y [0] $flatten\SOC.\Memory.$procmux$1350_Y [0] $flatten\SOC.\Memory.$procmux$1350_Y [0] $flatten\SOC.\Memory.$procmux$1350_Y [0] $flatten\SOC.\Memory.$procmux$1350_Y [0] $flatten\SOC.\Memory.$procmux$1350_Y [0] $flatten\SOC.\Memory.$procmux$1350_Y [0] $flatten\SOC.\Memory.$procmux$1350_Y [0] $flatten\SOC.\Memory.$procmux$1350_Y [0] $flatten\SOC.\Memory.$procmux$1350_Y [0] $flatten\SOC.\Memory.$procmux$1350_Y [0] $flatten\SOC.\Memory.$procmux$1350_Y [0] $flatten\SOC.\Memory.$procmux$1350_Y [0] $flatten\SOC.\Memory.$procmux$1350_Y [0] $flatten\SOC.\Memory.$procmux$1350_Y [0] $flatten\SOC.\Memory.$procmux$1350_Y [0] $flatten\SOC.\Memory.$procmux$1350_Y [0] $flatten\SOC.\Memory.$procmux$1350_Y [0] $flatten\SOC.\Memory.$procmux$1350_Y [0] $flatten\SOC.\Memory.$procmux$1350_Y [0] $flatten\SOC.\Memory.$procmux$1350_Y [0] $flatten\SOC.\Memory.$procmux$1350_Y [0] $flatten\SOC.\Memory.$procmux$1350_Y [0] $flatten\SOC.\Memory.$procmux$1350_Y [0] $flatten\SOC.\Memory.$procmux$1350_Y [0] $flatten\SOC.\Memory.$procmux$1350_Y [0] $flatten\SOC.\Memory.$procmux$1350_Y [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1385:
      Old ports: A=0, B=$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:36$848_EN[31:0]$877, Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$848_EN[31:0]$857
      New ports: A=1'0, B=$flatten\SOC.\Memory.$procmux$1314_Y [0], Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$848_EN[31:0]$857 [0]
      New connections: $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$848_EN[31:0]$857 [31:1] = { $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$848_EN[31:0]$857 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$848_EN[31:0]$857 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$848_EN[31:0]$857 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$848_EN[31:0]$857 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$848_EN[31:0]$857 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$848_EN[31:0]$857 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$848_EN[31:0]$857 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$848_EN[31:0]$857 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$848_EN[31:0]$857 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$848_EN[31:0]$857 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$848_EN[31:0]$857 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$848_EN[31:0]$857 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$848_EN[31:0]$857 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$848_EN[31:0]$857 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$848_EN[31:0]$857 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$848_EN[31:0]$857 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$848_EN[31:0]$857 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$848_EN[31:0]$857 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$848_EN[31:0]$857 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$848_EN[31:0]$857 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$848_EN[31:0]$857 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$848_EN[31:0]$857 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$848_EN[31:0]$857 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$848_EN[31:0]$857 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$848_EN[31:0]$857 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$848_EN[31:0]$857 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$848_EN[31:0]$857 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$848_EN[31:0]$857 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$848_EN[31:0]$857 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$848_EN[31:0]$857 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$848_EN[31:0]$857 [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\RX_FIFO.$procmux$940:
      Old ports: A=$flatten\SOC.\Uart.\RX_FIFO.$2$memwr$\memory$Risco-5/src/peripheral/fifo.v:29$811_EN[7:0]$833, B=8'00000000, Y=$flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:29$811_EN[7:0]$824
      New ports: A=$flatten\SOC.\Uart.\RX_FIFO.$procmux$922_Y [0], B=1'0, Y=$flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:29$811_EN[7:0]$824 [0]
      New connections: $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:29$811_EN[7:0]$824 [7:1] = { $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:29$811_EN[7:0]$824 [0] $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:29$811_EN[7:0]$824 [0] $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:29$811_EN[7:0]$824 [0] $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:29$811_EN[7:0]$824 [0] $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:29$811_EN[7:0]$824 [0] $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:29$811_EN[7:0]$824 [0] $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:29$811_EN[7:0]$824 [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\TX_FIFO.$procmux$940:
      Old ports: A=$flatten\SOC.\Uart.\TX_FIFO.$2$memwr$\memory$Risco-5/src/peripheral/fifo.v:29$811_EN[7:0]$833, B=8'00000000, Y=$flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:29$811_EN[7:0]$824
      New ports: A=$flatten\SOC.\Uart.\TX_FIFO.$procmux$922_Y [0], B=1'0, Y=$flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:29$811_EN[7:0]$824 [0]
      New connections: $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:29$811_EN[7:0]$824 [7:1] = { $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:29$811_EN[7:0]$824 [0] $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:29$811_EN[7:0]$824 [0] $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:29$811_EN[7:0]$824 [0] $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:29$811_EN[7:0]$824 [0] $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:29$811_EN[7:0]$824 [0] $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:29$811_EN[7:0]$824 [0] $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:29$811_EN[7:0]$824 [0] }
  Optimizing cells in module \top.
    Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1367:
      Old ports: A=0, B=$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:40$850_EN[31:0]$883, Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$850_EN[31:0]$863
      New ports: A=1'0, B=$flatten\SOC.\Memory.$procmux$1332_Y [0], Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$850_EN[31:0]$863 [0]
      New connections: $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$850_EN[31:0]$863 [31:1] = { $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$850_EN[31:0]$863 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$850_EN[31:0]$863 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$850_EN[31:0]$863 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$850_EN[31:0]$863 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$850_EN[31:0]$863 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$850_EN[31:0]$863 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$850_EN[31:0]$863 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$850_EN[31:0]$863 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$850_EN[31:0]$863 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$850_EN[31:0]$863 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$850_EN[31:0]$863 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$850_EN[31:0]$863 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$850_EN[31:0]$863 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$850_EN[31:0]$863 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$850_EN[31:0]$863 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$850_EN[31:0]$863 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$850_EN[31:0]$863 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$850_EN[31:0]$863 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$850_EN[31:0]$863 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$850_EN[31:0]$863 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$850_EN[31:0]$863 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$850_EN[31:0]$863 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$850_EN[31:0]$863 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$850_EN[31:0]$863 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$850_EN[31:0]$863 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$850_EN[31:0]$863 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$850_EN[31:0]$863 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$850_EN[31:0]$863 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$850_EN[31:0]$863 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$850_EN[31:0]$863 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$850_EN[31:0]$863 [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1376:
      Old ports: A=0, B=$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:38$849_EN[31:0]$880, Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$849_EN[31:0]$860
      New ports: A=1'0, B=$flatten\SOC.\Memory.$procmux$1350_Y [0], Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$849_EN[31:0]$860 [0]
      New connections: $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$849_EN[31:0]$860 [31:1] = { $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$849_EN[31:0]$860 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$849_EN[31:0]$860 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$849_EN[31:0]$860 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$849_EN[31:0]$860 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$849_EN[31:0]$860 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$849_EN[31:0]$860 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$849_EN[31:0]$860 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$849_EN[31:0]$860 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$849_EN[31:0]$860 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$849_EN[31:0]$860 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$849_EN[31:0]$860 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$849_EN[31:0]$860 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$849_EN[31:0]$860 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$849_EN[31:0]$860 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$849_EN[31:0]$860 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$849_EN[31:0]$860 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$849_EN[31:0]$860 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$849_EN[31:0]$860 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$849_EN[31:0]$860 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$849_EN[31:0]$860 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$849_EN[31:0]$860 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$849_EN[31:0]$860 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$849_EN[31:0]$860 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$849_EN[31:0]$860 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$849_EN[31:0]$860 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$849_EN[31:0]$860 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$849_EN[31:0]$860 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$849_EN[31:0]$860 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$849_EN[31:0]$860 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$849_EN[31:0]$860 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$849_EN[31:0]$860 [0] }
  Optimizing cells in module \top.
Performed a total of 25 changes.

23.11.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~9 debug messages>
Removed a total of 3 cells.

23.11.6. Executing OPT_DFF pass (perform DFF optimizations).

23.11.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 3 unused cells and 170 unused wires.
<suppressed ~8 debug messages>

23.11.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

23.11.9. Rerunning OPT passes. (Maybe there is more to do..)

23.11.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~123 debug messages>

23.11.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

23.11.12. Executing OPT_MERGE pass (detect identical cells).
+ mkdir -p Risco-5/impl/pnr
[Pipeline] }
[Pipeline] // stage
Finding identical cells in module `\top'.
Removed a total of 0 cells.

23.11.13. Executing OPT_DFF pass (perform DFF optimizations).

23.11.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

23.11.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

23.11.16. Finished OPT passes. (There is nothing left to do.)

23.12. Executing FSM pass (extract and optimize FSM).

23.12.1. Executing FSM_DETECT pass (finding FSMs in design).
Not marking top.ResetBootSystem.state as FSM state register:
    Register has an initialization value.
    Circuit seems to be self-resetting.
Not marking top.SOC.Core.CSR_Unit.csr_mip_mfip as FSM state register:
    Users of register don't seem to benefit from recoding.
    Register has an initialization value.
Not marking top.SOC.Core.Control_Unit.state as FSM state register:
    Users of register don't seem to benefit from recoding.
    Register has an initialization value.
Found FSM state register top.SOC.Uart.i_uart_rx.fsm_state.
Not marking top.SOC.Uart.i_uart_tx.fsm_state as FSM state register:
    Users of register don't seem to benefit from recoding.

23.12.2. Executing FSM_EXTRACT pass (extracting FSM from design).
Extracting FSM `\SOC.Uart.i_uart_rx.fsm_state' from module `\top'.
  found $dff cell for state register: $flatten\SOC.\Uart.\i_uart_rx.$procdff$1996
  root of input selection tree: $flatten\SOC.\Uart.\i_uart_rx.$0\fsm_state[2:0]
  found reset state: 3'000 (guessed from mux tree)
  found ctrl input: \ResetBootSystem.reset_o
  found ctrl input: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:100$772_Y
  found ctrl input: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:138$787_Y
  found ctrl input: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:176$800_Y
  found ctrl input: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:136$786_Y
  found state code: 3'000
  found ctrl input: \SOC.Uart.i_uart_rx.next_bit
  found state code: 3'011
  found ctrl input: \SOC.Uart.i_uart_rx.payload_done
  found state code: 3'010
  found state code: 3'001
  found ctrl input: \SOC.Uart.i_uart_rx.rxd_reg
  found ctrl output: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:176$800_Y
  found ctrl output: $flatten\SOC.\Uart.\i_uart_rx.$ne$Risco-5/src/peripheral/uart_rx.v:151$791_Y
  found ctrl output: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:138$787_Y
  found ctrl output: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:136$786_Y
  found ctrl output: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:100$772_Y
  ctrl inputs: { \SOC.Uart.i_uart_rx.rxd_reg \SOC.Uart.i_uart_rx.next_bit \SOC.Uart.i_uart_rx.payload_done \ResetBootSystem.reset_o }
  ctrl outputs: { $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:100$772_Y $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:136$786_Y $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:138$787_Y $flatten\SOC.\Uart.\i_uart_rx.$ne$Risco-5/src/peripheral/uart_rx.v:151$791_Y $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:176$800_Y $flatten\SOC.\Uart.\i_uart_rx.$0\fsm_state[2:0] }
  transition:      3'000 4'0--0 ->      3'001 8'01010001
  transition:      3'000 4'1--0 ->      3'000 8'01010000
  transition:      3'000 4'---1 ->      3'000 8'01010000
  transition:      3'010 4'--00 ->      3'010 8'00100010
  transition:      3'010 4'--10 ->      3'011 8'00100011
  transition:      3'010 4'---1 ->      3'000 8'00100000
  transition:      3'001 4'-0-0 ->      3'001 8'00011001
  transition:      3'001 4'-1-0 ->      3'010 8'00011010
  transition:      3'001 4'---1 ->      3'000 8'00011000
  transition:      3'011 4'-0-0 ->      3'011 8'10010011
  transition:      3'011 4'-1-0 ->      3'000 8'10010000
  transition:      3'011 4'---1 ->      3'000 8'10010000

23.12.3. Executing FSM_OPT pass (simple optimizations of FSMs).
Optimizing FSM `$fsm$\SOC.Uart.i_uart_rx.fsm_state$2139' from module `\top'.

23.12.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 7 unused cells and 7 unused wires.
<suppressed ~8 debug messages>

23.12.5. Executing FSM_OPT pass (simple optimizations of FSMs).
Optimizing FSM `$fsm$\SOC.Uart.i_uart_rx.fsm_state$2139' from module `\top'.
  Removing unused output signal $flatten\SOC.\Uart.\i_uart_rx.$0\fsm_state[2:0] [0].
  Removing unused output signal $flatten\SOC.\Uart.\i_uart_rx.$0\fsm_state[2:0] [1].
  Removing unused output signal $flatten\SOC.\Uart.\i_uart_rx.$0\fsm_state[2:0] [2].

23.12.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
Recoding FSM `$fsm$\SOC.Uart.i_uart_rx.fsm_state$2139' from module `\top' using `auto' encoding:
  mapping auto encoding to `one-hot` for this FSM.
  000 -> ---1
  010 -> --1-
  001 -> -1--
  011 -> 1---

23.12.7. Executing FSM_INFO pass (dumping all available information on FSM cells).

FSM `$fsm$\SOC.Uart.i_uart_rx.fsm_state$2139' from module `top':
-------------------------------------

  Information on FSM $fsm$\SOC.Uart.i_uart_rx.fsm_state$2139 (\SOC.Uart.i_uart_rx.fsm_state):

  Number of input signals:    4
  Number of output signals:   5
  Number of state bits:       4

  Input signals:
    0: \ResetBootSystem.reset_o
    1: \SOC.Uart.i_uart_rx.payload_done
    2: \SOC.Uart.i_uart_rx.next_bit
    3: \SOC.Uart.i_uart_rx.rxd_reg

  Output signals:
    0: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:176$800_Y
    1: $flatten\SOC.\Uart.\i_uart_rx.$ne$Risco-5/src/peripheral/uart_rx.v:151$791_Y
    2: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:138$787_Y
    3: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:136$786_Y
    4: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:100$772_Y

  State encoding:
    0:     4'---1  <RESET STATE>
    1:     4'--1-
    2:     4'-1--
    3:     4'1---

  Transition Table (state_in, ctrl_in, state_out, ctrl_out):
      0:     0 4'1--0   ->     0 5'01010
      1:     0 4'---1   ->     0 5'01010
      2:     0 4'0--0   ->     2 5'01010
      3:     1 4'---1   ->     0 5'00100
      4:     1 4'--00   ->     1 5'00100
      5:     1 4'--10   ->     3 5'00100
      6:     2 4'---1   ->     0 5'00011
      7:     2 4'-1-0   ->     1 5'00011
      8:     2 4'-0-0   ->     2 5'00011
      9:     3 4'-1-0   ->     0 5'10010
     10:     3 4'---1   ->     0 5'10010
     11:     3 4'-0-0   ->     3 5'10010

-------------------------------------

23.12.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
Mapping FSM `$fsm$\SOC.Uart.i_uart_rx.fsm_state$2139' from module `\top'.

23.13. Executing OPT pass (performing simple optimizations).

23.13.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~5 debug messages>

23.13.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~6 debug messages>
Removed a total of 2 cells.

23.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~122 debug messages>

23.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

23.13.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

23.13.6. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$2008 ($dff) from module top (D = { $flatten\SOC.\Uart.\i_uart_tx.$procmux$1211_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1205_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1196_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1187_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1178_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1169_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1151_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1160_Y }, Q = \SOC.Uart.i_uart_tx.data_to_send, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$2189 ($sdff) from module top (D = \SOC.Uart.uart_tx_data [7], Q = \SOC.Uart.i_uart_tx.data_to_send [7]).
Adding EN signal on $auto$ff.cc:266:slice$2189 ($sdff) from module top (D = { $flatten\SOC.\Uart.\i_uart_tx.$procmux$1205_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1196_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1187_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1178_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1169_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1151_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1160_Y }, Q = \SOC.Uart.i_uart_tx.data_to_send [6:0]).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$2006 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$1127_Y, Q = \SOC.Uart.i_uart_tx.bit_counter, rval = 4'0000).
Adding EN signal on $auto$ff.cc:266:slice$2194 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$1127_Y, Q = \SOC.Uart.i_uart_tx.bit_counter).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$2005 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$1116_Y, Q = \SOC.Uart.i_uart_tx.cycle_counter, rval = 13'0000000000000).
Adding EN signal on $auto$ff.cc:266:slice$2200 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:155$754_Y, Q = \SOC.Uart.i_uart_tx.cycle_counter).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$2004 ($dff) from module top (D = \SOC.Uart.i_uart_tx.n_fsm_state, Q = \SOC.Uart.i_uart_tx.fsm_state, rval = 3'000).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$2003 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$1105_Y, Q = \SOC.Uart.i_uart_tx.txd_reg, rval = 1'1).
Adding EN signal on $auto$ff.cc:266:slice$2205 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$1105_Y, Q = \SOC.Uart.i_uart_tx.txd_reg).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$2002 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$procmux$1094_Y, Q = \SOC.Uart.i_uart_rx.uart_rx_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$2211 ($sdff) from module top (D = \SOC.Uart.i_uart_rx.recieved_data, Q = \SOC.Uart.i_uart_rx.uart_rx_data).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$2001 ($dff) from module top (D = { $flatten\SOC.\Uart.\i_uart_rx.$procmux$1071_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1062_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1053_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1044_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1035_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1026_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1008_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1017_Y }, Q = \SOC.Uart.i_uart_rx.recieved_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$2213 ($sdff) from module top (D = { \SOC.Uart.i_uart_rx.bit_sample \SOC.Uart.i_uart_rx.recieved_data [7:1] }, Q = \SOC.Uart.i_uart_rx.recieved_data).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$1999 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$procmux$990_Y, Q = \SOC.Uart.i_uart_rx.bit_counter, rval = 4'0000).
Adding EN signal on $auto$ff.cc:266:slice$2217 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:154$794_Y, Q = \SOC.Uart.i_uart_rx.bit_counter).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$1998 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$procmux$985_Y, Q = \SOC.Uart.i_uart_rx.bit_sample, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$2221 ($sdff) from module top (D = \SOC.Uart.i_uart_rx.rxd_reg, Q = \SOC.Uart.i_uart_rx.bit_sample).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$1997 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$procmux$977_Y, Q = \SOC.Uart.i_uart_rx.cycle_counter, rval = 13'0000000000000).
Adding EN signal on $auto$ff.cc:266:slice$2223 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:179$805_Y, Q = \SOC.Uart.i_uart_rx.cycle_counter).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$1995 ($dff) from module top (D = \rx, Q = \SOC.Uart.i_uart_rx.rxd_reg_0, rval = 1'1).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$1994 ($dff) from module top (D = \SOC.Uart.i_uart_rx.rxd_reg_0, Q = \SOC.Uart.i_uart_rx.rxd_reg, rval = 1'1).
Adding SRST signal on $flatten\SOC.\Uart.\TX_FIFO.$procdff$1990 ($dff) from module top (D = $flatten\SOC.\Uart.\TX_FIFO.$procmux$949_Y, Q = \SOC.Uart.TX_FIFO.write_ptr, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$2229 ($sdff) from module top (D = $flatten\SOC.\Uart.\TX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:30$836_Y, Q = \SOC.Uart.TX_FIFO.write_ptr).
Adding SRST signal on $flatten\SOC.\Uart.\TX_FIFO.$procdff$1989 ($dff) from module top (D = $flatten\SOC.\Uart.\TX_FIFO.$procmux$954_Y, Q = \SOC.Uart.TX_FIFO.read_ptr, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$2231 ($sdff) from module top (D = $flatten\SOC.\Uart.\TX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:34$842_Y [5:0], Q = \SOC.Uart.TX_FIFO.read_ptr).
Adding EN signal on $flatten\SOC.\Uart.\TX_FIFO.$procdff$1988 ($dff) from module top (D = $flatten\SOC.\Uart.\TX_FIFO.$memrd$\memory$Risco-5/src/peripheral/fifo.v:33$839_DATA, Q = \SOC.Uart.TX_FIFO.read_data).
Adding SRST signal on $flatten\SOC.\Uart.\RX_FIFO.$procdff$1990 ($dff) from module top (D = $flatten\SOC.\Uart.\RX_FIFO.$procmux$949_Y, Q = \SOC.Uart.RX_FIFO.write_ptr, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$2238 ($sdff) from module top (D = $flatten\SOC.\Uart.\RX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:30$836_Y, Q = \SOC.Uart.RX_FIFO.write_ptr).
Adding SRST signal on $flatten\SOC.\Uart.\RX_FIFO.$procdff$1989 ($dff) from module top (D = $flatten\SOC.\Uart.\RX_FIFO.$procmux$954_Y, Q = \SOC.Uart.RX_FIFO.read_ptr, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$2240 ($sdff) from module top (D = $flatten\SOC.\Uart.\RX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:34$842_Y [5:0], Q = \SOC.Uart.RX_FIFO.read_ptr).
Adding EN signal on $flatten\SOC.\Uart.\RX_FIFO.$procdff$1988 ($dff) from module top (D = $flatten\SOC.\Uart.\RX_FIFO.$memrd$\memory$Risco-5/src/peripheral/fifo.v:33$839_DATA, Q = \SOC.Uart.RX_FIFO.read_data).
Adding SRST signal on $flatten\SOC.\Uart.$procdff$2034 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1428_Y, Q = \SOC.Uart.read_buffer, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$2247 ($sdff) from module top (D = \SOC.Uart.RX_FIFO.read_data, Q = \SOC.Uart.read_buffer).
Adding SRST signal on $flatten\SOC.\Uart.$procdff$2033 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1433_Y, Q = \SOC.Uart.rx_fifo_write_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$2249 ($sdff) from module top (D = \SOC.Uart.i_uart_rx.uart_rx_data, Q = \SOC.Uart.rx_fifo_write_data).
Adding SRST signal on $flatten\SOC.\Uart.$procdff$2032 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1438_Y, Q = \SOC.Uart.tx_fifo_write_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$2251 ($sdff) from module top (D = \SOC.Uart.write_data [7:0], Q = \SOC.Uart.tx_fifo_write_data).
Adding SRST signal on $flatten\SOC.\Uart.$procdff$2031 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1443_Y, Q = \SOC.Uart.uart_tx_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$2253 ($sdff) from module top (D = \SOC.Uart.TX_FIFO.read_data, Q = \SOC.Uart.uart_tx_data).
Adding SRST signal on $flatten\SOC.\Uart.$procdff$2030 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1448_Y, Q = \SOC.Uart.buffer_full, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$2255 ($sdff) from module top (D = 1'1, Q = \SOC.Uart.buffer_full).
Adding SRST signal on $flatten\SOC.\Uart.$procdff$2029 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1403_Y, Q = \SOC.Uart.rx_fifo_write, rval = 1'0).
Adding SRST signal on $flatten\SOC.\Uart.$procdff$2028 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1408_Y, Q = \SOC.Uart.rx_fifo_read, rval = 1'0).
Adding SRST signal on $flatten\SOC.\Uart.$procdff$2027 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1413_Y, Q = \SOC.Uart.tx_fifo_write, rval = 1'0).
Adding SRST signal on $flatten\SOC.\Uart.$procdff$2025 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1418_Y, Q = \SOC.Uart.uart_tx_en, rval = 1'0).
Adding SRST signal on $flatten\SOC.\Leds.$procdff$2024 ($dff) from module top (D = $flatten\SOC.\Leds.$procmux$1393_Y, Q = \SOC.Leds.data, rval = 33'000000000000000000000000000000000).
Adding EN signal on $auto$ff.cc:266:slice$2263 ($sdff) from module top (D = { 1'0 \SOC.Leds.write_data }, Q = \SOC.Leds.data).
Adding SRST signal on $flatten\SOC.\GPIOS.$procdff$2036 ($dff) from module top (D = $flatten\SOC.\GPIOS.$procmux$1458_Y, Q = \SOC.GPIOS.gpio_value, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$2265 ($sdff) from module top (D = \SOC.GPIOS.write_data [5:0], Q = \SOC.GPIOS.gpio_value).
Adding SRST signal on $flatten\SOC.\GPIOS.$procdff$2035 ($dff) from module top (D = $flatten\SOC.\GPIOS.$procmux$1466_Y, Q = \SOC.GPIOS.gpio_direction, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$2269 ($sdff) from module top (D = \SOC.GPIOS.write_data [5:0], Q = \SOC.GPIOS.gpio_direction).
Adding SRST signal on $flatten\SOC.\Core.\Pc.$procdff$2042 ($dff) from module top (D = $flatten\SOC.\Core.\Pc.$procmux$1510_Y, Q = \SOC.Core.Pc.Output, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$2275 ($sdff) from module top (D = \SOC.Core.Pc.Input, Q = \SOC.Core.Pc.Output).
Adding SRST signal on $flatten\SOC.\Core.\Control_Unit.$procdff$2063 ($dff) from module top (D = \SOC.Core.Control_Unit.nextstate, Q = \SOC.Core.Control_Unit.state, rval = 4'0000).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2059 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1614_Y, Q = \SOC.Core.CSR_Unit.csr_mtval, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$2278 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data, Q = \SOC.Core.CSR_Unit.csr_mtval).
Adding EN signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2058 ($dff) from module top (D = { \SOC.Core.CSR_Unit.csr_write_data [31:2] 1'0 \SOC.Core.CSR_Unit.csr_write_data [0] }, Q = \SOC.Core.CSR_Unit.csr_mtvec).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2057 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1640_Y, Q = \SOC.Core.CSR_Unit.csr_mstatus_mpie, rval = 1'1).
Adding EN signal on $auto$ff.cc:266:slice$2287 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data [7], Q = \SOC.Core.CSR_Unit.csr_mstatus_mpie).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2056 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1657_Y, Q = \SOC.Core.CSR_Unit.csr_mstatus_mie, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$2291 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data [3], Q = \SOC.Core.CSR_Unit.csr_mstatus_mie).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2055 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1673_Y, Q = \SOC.Core.CSR_Unit.csr_mscratch, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$2295 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data, Q = \SOC.Core.CSR_Unit.csr_mscratch).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2054 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1686_Y, Q = \SOC.Core.CSR_Unit.csr_minstret, rval = 64'0000000000000000000000000000000000000000000000000000000000000000).
Adding EN signal on $auto$ff.cc:266:slice$2299 ($sdff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1686_Y, Q = \SOC.Core.CSR_Unit.csr_minstret).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2053 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1704_Y, Q = \SOC.Core.CSR_Unit.csr_mie_mtie, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$2303 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data [7], Q = \SOC.Core.CSR_Unit.csr_mie_mtie).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2052 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1722_Y, Q = \SOC.Core.CSR_Unit.csr_mie_msie, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$2307 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data [3], Q = \SOC.Core.CSR_Unit.csr_mie_msie).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2051 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1740_Y, Q = \SOC.Core.CSR_Unit.csr_mie_meie, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$2311 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data [11], Q = \SOC.Core.CSR_Unit.csr_mie_meie).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2050 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1758_Y, Q = \SOC.Core.CSR_Unit.csr_mie_mfie, rval = 16'0000000000000000).
Adding EN signal on $auto$ff.cc:266:slice$2315 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data [31:16], Q = \SOC.Core.CSR_Unit.csr_mie_mfie).
Adding EN signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2049 ($dff) from module top (D = { \SOC.Core.CSR_Unit.csr_write_data [31:2] 2'00 }, Q = \SOC.Core.CSR_Unit.csr_mepc).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2048 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1781_Y, Q = \SOC.Core.CSR_Unit.csr_mcycle, rval = 64'0000000000000000000000000000000000000000000000000000000000000000).
Adding EN signal on $auto$ff.cc:266:slice$2324 ($sdff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1781_Y, Q = \SOC.Core.CSR_Unit.csr_mcycle).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2047 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1792_Y, Q = \SOC.Core.CSR_Unit.csr_mcause, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$2328 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data, Q = \SOC.Core.CSR_Unit.csr_mcause).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2046 ($dff) from module top (D = \SOC.Core.CSR_Unit.irq_software, Q = \SOC.Core.CSR_Unit.csr_mip_msip, rval = 1'0).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2045 ($dff) from module top (D = \SOC.Core.CSR_Unit.irq_timer, Q = \SOC.Core.CSR_Unit.csr_mip_mtip, rval = 1'0).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2044 ($dff) from module top (D = \SOC.Core.CSR_Unit.irq_external, Q = \SOC.Core.CSR_Unit.csr_mip_meip, rval = 1'0).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2043 ($dff) from module top (D = \SOC.Core.CSR_Unit.irq_fast, Q = \SOC.Core.CSR_Unit.csr_mip_mfip, rval = 16'0000000000000000).
Adding SRST signal on $flatten\SOC.\Core.$procdff$2014 ($dff) from module top (D = $flatten\SOC.\Core.$procmux$1243_Y, Q = \SOC.Core.pc_old, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$2336 ($sdff) from module top (D = \SOC.Core.Pc.Output, Q = \SOC.Core.pc_old).
Adding SRST signal on $flatten\SOC.\Core.$procdff$2013 ($dff) from module top (D = \SOC.Bus.write_data, Q = \SOC.Core.register_data_2, rval = 0).
Adding SRST signal on $flatten\SOC.\Core.$procdff$2012 ($dff) from module top (D = \SOC.Core.register_data_1_out, Q = \SOC.Core.register_data_1, rval = 0).
Adding SRST signal on $flatten\SOC.\Core.$procdff$2011 ($dff) from module top (D = \SOC.Core.Alu.ALU_out_S, Q = \SOC.Core.alu_out_register, rval = 0).
Adding SRST signal on $flatten\SOC.\Core.$procdff$2010 ($dff) from module top (D = \SOC.Core.read_data, Q = \SOC.Core.memory_register, rval = 0).
Adding SRST signal on $flatten\SOC.\Core.$procdff$2009 ($dff) from module top (D = $flatten\SOC.\Core.$procmux$1248_Y, Q = \SOC.Core.instruction_register, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$2342 ($sdff) from module top (D = \SOC.Core.read_data, Q = \SOC.Core.instruction_register).
Adding EN signal on $flatten\ResetBootSystem.$procdff$2062 ($dff) from module top (D = $flatten\ResetBootSystem.$0\counter[5:0], Q = \ResetBootSystem.counter).
Adding EN signal on $flatten\ResetBootSystem.$procdff$2061 ($dff) from module top (D = $flatten\ResetBootSystem.$0\state[1:0], Q = \ResetBootSystem.state).
Adding EN signal on $flatten\ResetBootSystem.$procdff$2060 ($dff) from module top (D = $flatten\ResetBootSystem.$0\reset_o[0:0], Q = \ResetBootSystem.reset_o).
Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$2319 ($dffe) from module top.
Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$2319 ($dffe) from module top.
Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$2282 ($dffe) from module top.
Setting constant 0-bit at position 32 on $auto$ff.cc:266:slice$2264 ($sdffe) from module top.

23.13.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 139 unused cells and 135 unused wires.
<suppressed ~140 debug messages>

23.13.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~5 debug messages>

23.13.9. Rerunning OPT passes. (Maybe there is more to do..)

23.13.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~76 debug messages>

23.13.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
    New input vector for $reduce_or cell $auto$opt_dff.cc:254:combine_resets$2219: { \SOC.Uart.i_uart_rx.fsm_state [3:2] \SOC.Uart.i_uart_rx.fsm_state [0] \ResetBootSystem.reset_o }
  Optimizing cells in module \top.
Performed a total of 1 changes.

23.13.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~21 debug messages>
Removed a total of 7 cells.

23.13.13. Executing OPT_DFF pass (perform DFF optimizations).

23.13.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 1 unused cells and 8 unused wires.
<suppressed ~2 debug messages>

23.13.15. Executing OPT_EXPR pass (perform const folding).
[Pipeline] }
Optimizing module top.

23.13.16. Rerunning OPT passes. (Maybe there is more to do..)

23.13.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~76 debug messages>

23.13.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

23.13.19. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

23.13.20. Executing OPT_DFF pass (perform DFF optimizations).

23.13.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

23.13.22. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

23.13.23. Finished OPT passes. (There is nothing left to do.)

23.14. Executing WREDUCE pass (reducing word size of cells).
Removed top 28 address bits (of 32) from memory init port top.$flatten\SOC.\Core.\Control_Unit.$auto$mem.cc:328:emit$897 ($flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895).
Removed top 27 address bits (of 32) from memory init port top.$flatten\SOC.\Core.\RegisterBank.$auto$proc_memwr.cc:45:proc_memwr$2068 (SOC.Core.RegisterBank.registers).
Removed top 27 address bits (of 32) from memory init port top.$flatten\SOC.\Core.\RegisterBank.$auto$proc_memwr.cc:45:proc_memwr$2070 (SOC.Core.RegisterBank.registers).
Removed top 27 address bits (of 32) from memory init port top.$flatten\SOC.\Core.\RegisterBank.$meminit$\registers$Risco-5/src/core/registers.v:16$112 (SOC.Core.RegisterBank.registers).
Removed top 23 address bits (of 32) from memory init port top.$flatten\SOC.\Memory.$auto$proc_memwr.cc:45:proc_memwr$2065 (SOC.Memory.memory).
Removed top 23 address bits (of 32) from memory init port top.$flatten\SOC.\Memory.$auto$proc_memwr.cc:45:proc_memwr$2066 (SOC.Memory.memory).
Removed top 23 address bits (of 32) from memory init port top.$flatten\SOC.\Memory.$auto$proc_memwr.cc:45:proc_memwr$2067 (SOC.Memory.memory).
Removed top 23 address bits (of 32) from memory init port top.$flatten\SOC.\Memory.$meminit$\memory$Risco-5/src/peripheral/memory.v:0$892 (SOC.Memory.memory).
Removed top 23 address bits (of 32) from memory read port top.$flatten\SOC.\Memory.$memrd$\memory$Risco-5/src/peripheral/memory.v:19$852 (SOC.Memory.memory).
Removed top 3 address bits (of 6) from memory init port top.$flatten\SOC.\Uart.\RX_FIFO.$auto$proc_memwr.cc:45:proc_memwr$2064 (SOC.Uart.RX_FIFO.memory).
Removed top 3 address bits (of 6) from memory read port top.$flatten\SOC.\Uart.\RX_FIFO.$memrd$\memory$Risco-5/src/peripheral/fifo.v:33$839 (SOC.Uart.RX_FIFO.memory).
Removed top 3 address bits (of 6) from memory init port top.$flatten\SOC.\Uart.\TX_FIFO.$auto$proc_memwr.cc:45:proc_memwr$2064 (SOC.Uart.TX_FIFO.memory).
Removed top 3 address bits (of 6) from memory read port top.$flatten\SOC.\Uart.\TX_FIFO.$memrd$\memory$Risco-5/src/peripheral/fifo.v:33$839 (SOC.Uart.TX_FIFO.memory).
Removed top 1 bits (of 2) from port B of cell top.$flatten\ResetBootSystem.$procmux$1809_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\ResetBootSystem.$eq$Risco-5/debug/reset.v:38$634 ($eq).
Removed top 31 bits (of 32) from port B of cell top.$flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$633 ($add).
Removed top 26 bits (of 32) from port Y of cell top.$flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$633 ($add).
Removed top 27 bits (of 32) from port B of cell top.$flatten\ResetBootSystem.$lt$Risco-5/debug/reset.v:36$632 ($lt).
Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$2350 ($ne).
Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$2355 ($ne).
Removed top 26 bits (of 32) from mux cell top.$flatten\SOC.\GPIOS.$ternary$Risco-5/src/peripheral/gpios.v:20$845 ($mux).
Removed top 2 bits (of 4) from port B of cell top.$flatten\SOC.\Uart.$procmux$1400_CMP0 ($eq).
Removed top 24 bits (of 32) from mux cell top.$flatten\SOC.\Uart.$procmux$1399 ($pmux).
Removed top 1 bits (of 4) from port B of cell top.$flatten\SOC.\Uart.$procmux$1401_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell top.$flatten\SOC.\Uart.$procmux$1402_CMP0 ($eq).
Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Uart.\TX_FIFO.$procmux$946 ($mux).
Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Uart.\TX_FIFO.$procmux$934 ($mux).
Removed top 26 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\TX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:34$842 ($mux).
Removed top 26 bits (of 32) from port Y of cell top.$flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:34$841 ($add).
Removed top 3 bits (of 6) from port B of cell top.$flatten\SOC.\Uart.\TX_FIFO.$eq$Risco-5/src/peripheral/fifo.v:30$834 ($eq).
Removed top 3 bits (of 6) from port B of cell top.$flatten\SOC.\Uart.\TX_FIFO.$eq$Risco-5/src/peripheral/fifo.v:21$817 ($eq).
Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Uart.\RX_FIFO.$procmux$946 ($mux).
Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Uart.\RX_FIFO.$procmux$934 ($mux).
Removed top 26 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\RX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:34$842 ($mux).
Removed top 26 bits (of 32) from port Y of cell top.$flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:34$841 ($add).
Removed top 3 bits (of 6) from port B of cell top.$flatten\SOC.\Uart.\RX_FIFO.$eq$Risco-5/src/peripheral/fifo.v:30$834 ($eq).
Removed top 3 bits (of 6) from port B of cell top.$flatten\SOC.\Uart.\RX_FIFO.$eq$Risco-5/src/peripheral/fifo.v:21$817 ($eq).
Removed top 30 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:121$783 ($mux).
Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:120$782 ($mux).
Removed top 30 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:119$781 ($mux).
Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:118$780 ($mux).
Removed top 2 bits (of 13) from port B of cell top.$flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:111$775 ($eq).
Removed top 1 bits (of 13) from port B of cell top.$flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:109$773 ($eq).
Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:152$749 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:137$741 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:135$739 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$ne$Risco-5/src/peripheral/uart_tx.v:133$736 ($ne).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$ne$Risco-5/src/peripheral/uart_tx.v:133$735 ($ne).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:120$731 ($eq).
Removed top 30 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:103$726 ($mux).
Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:102$725 ($mux).
Removed top 30 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:101$724 ($mux).
Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:100$723 ($mux).
Removed top 3 bits (of 4) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:94$719 ($eq).
Removed top 1 bits (of 13) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:92$717 ($eq).
Removed top 1 bits (of 33) from mux cell top.$flatten\SOC.\Leds.$ternary$Risco-5/src/peripheral/leds.v:21$236 ($mux).
Removed top 20 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:54$116 ($le).
Removed top 19 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:55$119 ($ge).
Removed top 19 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:56$120 ($le).
Removed top 19 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:57$123 ($ge).
Removed top 19 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:58$124 ($le).
Removed top 19 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:59$127 ($ge).
Removed top 19 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:60$128 ($le).
Removed top 24 bits (of 32) from mux cell top.$flatten\SOC.\Bus.$ternary$Risco-5/src/peripheral/bus.v:75$158 ($mux).
Removed top 28 bits (of 32) from mux cell top.$flatten\SOC.\Bus.$ternary$Risco-5/src/peripheral/bus.v:84$174 ($mux).
Removed top 24 bits (of 32) from mux cell top.$flatten\SOC.\Bus.$ternary$Risco-5/src/peripheral/bus.v:91$188 ($mux).
Removed top 1 bits (of 2) from port B of cell top.$flatten\SOC.\Memory.$procmux$1256_CMP0 ($eq).
Removed top 23 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1373 ($mux).
Removed top 23 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1382 ($mux).
Removed top 23 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1391 ($mux).
Removed top 5 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$eq$Risco-5/src/core/control_unit.v:99$54 ($eq).
Removed top 1 bits (of 2) from port B of cell top.$flatten\SOC.\Core.\MemoryDataMUX.$procmux$1518_CMP0 ($eq).
Removed top 1 bits (of 2) from port B of cell top.$flatten\SOC.\Core.\AluInputAMUX.$procmux$1518_CMP0 ($eq).
Removed top 1 bits (of 2) from port B of cell top.$flatten\SOC.\Core.\AluInputBMUX.$procmux$1518_CMP0 ($eq).
Removed top 2 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1895_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1894_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1893_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1892_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1891_CMP0 ($eq).
Removed top 3 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1881_CMP0 ($eq).
Removed top 1 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1878_CMP0 ($eq).
Removed top 1 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1877_CMP0 ($eq).
Removed top 2 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1876_CMP0 ($eq).
Removed top 2 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1873_CMP0 ($eq).
Removed top 1 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1872_CMP0 ($eq).
Removed top 2 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1853_CMP0 ($eq).
Removed top 1 bits (of 4) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1850 ($mux).
Removed top 1 bits (of 2) from port B of cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$1943_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$1925_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$1924_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$1923_CMP0 ($eq).
Removed top 1 bits (of 4) from mux cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$1911 ($mux).
Removed top 3 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Alu.$procmux$1956_CMP0 ($eq).
Removed top 2 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Alu.$procmux$1955_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Alu.$procmux$1954_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Alu.$procmux$1953_CMP0 ($eq).
Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Core.\Alu.$ternary$Risco-5/src/core/alu.v:46$47 ($mux).
Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Core.\Alu.$ternary$Risco-5/src/core/alu.v:34$39 ($mux).
Removed top 1 bits (of 2) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1596_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1583_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1582_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1581_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1580_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1579_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1578_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1577_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1576_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1575_CMP0 ($eq).
Removed top 31 bits (of 32) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:152$73 ($add).
Removed top 31 bits (of 32) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:144$71 ($add).
Removed top 31 bits (of 32) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:143$70 ($add).
Removed top 31 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:53$115 ($ge).
Removed top 23 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1326 ($mux).
Removed top 23 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1344 ($mux).
Removed top 23 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1362 ($mux).
Removed top 23 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1278 ($mux).
Removed top 23 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1305 ($mux).
Removed top 21 bits (of 32) from mux cell top.$flatten\SOC.\Bus.$ternary$Risco-5/src/peripheral/bus.v:80$166 ($mux).
Removed top 26 bits (of 32) from wire top.$flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$633_Y.
Removed top 24 bits (of 32) from wire top.$flatten\SOC.\Bus.$ternary$Risco-5/src/peripheral/bus.v:91$188_Y.
Removed top 1 bits (of 4) from wire top.$flatten\SOC.\Core.\ALU_Control.$4\aluop_out[3:0].
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Core.\Alu.$eq$Risco-5/src/core/alu.v:40$43_Y.
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Core.\Alu.$ternary$Risco-5/src/core/alu.v:34$39_Y.
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Core.\Alu.$ternary$Risco-5/src/core/alu.v:46$47_Y.
Removed top 1 bits (of 4) from wire top.$flatten\SOC.\Core.\Control_Unit.$3\nextstate[3:0].
Removed top 23 bits (of 32) from wire top.$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$848_ADDR[31:0]$855.
Removed top 23 bits (of 32) from wire top.$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$849_ADDR[31:0]$858.
Removed top 23 bits (of 32) from wire top.$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$850_ADDR[31:0]$861.
Removed top 23 bits (of 32) from wire top.$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:36$848_ADDR[31:0]$875.
Removed top 23 bits (of 32) from wire top.$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:38$849_ADDR[31:0]$878.
Removed top 23 bits (of 32) from wire top.$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:40$850_ADDR[31:0]$881.
Removed top 23 bits (of 32) from wire top.$flatten\SOC.\Memory.$3$memwr$\memory$Risco-5/src/peripheral/memory.v:38$849_ADDR[31:0]$885.
Removed top 23 bits (of 32) from wire top.$flatten\SOC.\Memory.$3$memwr$\memory$Risco-5/src/peripheral/memory.v:40$850_ADDR[31:0]$888.
Removed top 3 bits (of 6) from wire top.$flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:29$811_ADDR[5:0]$822.
Removed top 3 bits (of 6) from wire top.$flatten\SOC.\Uart.\RX_FIFO.$2$memwr$\memory$Risco-5/src/peripheral/fifo.v:29$811_ADDR[5:0]$831.
Removed top 26 bits (of 32) from wire top.$flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:34$841_Y.
Removed top 26 bits (of 32) from wire top.$flatten\SOC.\Uart.\RX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:34$842_Y.
Removed top 3 bits (of 6) from wire top.$flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:29$811_ADDR[5:0]$822.
Removed top 1 bits (of 8) from wire top.$flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:29$811_DATA[7:0]$823.
Removed top 3 bits (of 6) from wire top.$flatten\SOC.\Uart.\TX_FIFO.$2$memwr$\memory$Risco-5/src/peripheral/fifo.v:29$811_ADDR[5:0]$831.
Removed top 26 bits (of 32) from wire top.$flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:34$841_Y.
Removed top 26 bits (of 32) from wire top.$flatten\SOC.\Uart.\TX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:34$842_Y.
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:118$780_Y.
Removed top 30 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:119$781_Y.
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:120$782_Y.
Removed top 30 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:121$783_Y.
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:100$723_Y.
Removed top 30 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:101$724_Y.
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:102$725_Y.
Removed top 30 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:103$726_Y.

23.15. Executing PEEPOPT pass (run peephole optimizers).

23.16. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 33 unused wires.
<suppressed ~1 debug messages>

23.17. Executing SHARE pass (SAT-based resource sharing).
Found 3 cells in module top that may be considered for resource sharing.
  Analyzing resource sharing options for $flatten\SOC.\Memory.$memrd$\memory$Risco-5/src/peripheral/memory.v:19$852 ($memrd):
    Found 5 activation_patterns using ctrl signal { $flatten\SOC.\Memory.$procmux$1257_CMP $flatten\SOC.\Memory.$procmux$1256_CMP \SOC.Memory.option $flatten\SOC.\Bus.$logic_and$Risco-5/src/peripheral/bus.v:53$117_Y \SOC.Bus.slave_0_write \SOC.Bus.slave_0_read }.
    No candidates found.
  Analyzing resource sharing options for $flatten\SOC.\Core.\Alu.$shr$Risco-5/src/core/alu.v:44$45 ($shr):
    Found 1 activation_patterns using ctrl signal $flatten\SOC.\Core.\Alu.$procmux$1948_CMP.
    No candidates found.
  Analyzing resource sharing options for $flatten\SOC.\Core.\Alu.$shl$Risco-5/src/core/alu.v:42$44 ($shl):
    Found 1 activation_patterns using ctrl signal $flatten\SOC.\Core.\Alu.$procmux$1949_CMP.
    No candidates found.

23.18. Executing TECHMAP pass (map to technology primitives).

23.18.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/cmp2lut.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/cmp2lut.v' to AST representation.
Generating RTLIL representation for module `\_90_lut_cmp_'.
Successfully finished Verilog frontend.

23.18.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~296 debug messages>

23.19. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

23.20. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

23.21. Executing TECHMAP pass (map to technology primitives).

23.21.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v' to AST representation.
Generating RTLIL representation for module `\_80_mul'.
Generating RTLIL representation for module `\_90_soft_mul'.
Successfully finished Verilog frontend.

23.21.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/dsp_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/dsp_map.v' to AST representation.
Generating RTLIL representation for module `\$__MUL18X18'.
Successfully finished Verilog frontend.

23.21.3. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~5 debug messages>

23.22. Executing ALUMACC pass (create $alu and $macc cells).
Extracting $alu and $macc cells in module top:
  creating $macc model for $flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$633 ($add).
  creating $macc model for $flatten\SOC.\Core.\Alu.$add$Risco-5/src/core/alu.v:30$36 ($add).
  creating $macc model for $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:32$37 ($sub).
  creating $macc model for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:141$68 ($add).
  creating $macc model for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:142$69 ($add).
  creating $macc model for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:143$70 ($add).
  creating $macc model for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:144$71 ($add).
  creating $macc model for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:151$72 ($add).
  creating $macc model for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:152$73 ($add).
  creating $macc model for $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:20$814 ($add).
  creating $macc model for $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:30$835 ($add).
  creating $macc model for $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:34$841 ($add).
  creating $macc model for $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:20$814 ($add).
  creating $macc model for $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:30$835 ($add).
  creating $macc model for $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:34$841 ($add).
  creating $macc model for $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:154$794 ($add).
  creating $macc model for $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:179$805 ($add).
  creating $macc model for $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:138$743 ($add).
  creating $macc model for $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:155$754 ($add).
  creating $alu model for $macc $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:155$754.
  creating $alu model for $macc $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:138$743.
  creating $alu model for $macc $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:179$805.
  creating $alu model for $macc $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:154$794.
  creating $alu model for $macc $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:34$841.
  creating $alu model for $macc $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:30$835.
  creating $alu model for $macc $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:20$814.
  creating $alu model for $macc $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:34$841.
  creating $alu model for $macc $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:30$835.
  creating $alu model for $macc $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:20$814.
  creating $alu model for $macc $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:152$73.
  creating $alu model for $macc $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:151$72.
  creating $alu model for $macc $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:144$71.
  creating $alu model for $macc $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:143$70.
  creating $alu model for $macc $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:142$69.
  creating $alu model for $macc $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:141$68.
  creating $alu model for $macc $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:32$37.
  creating $alu model for $macc $flatten\SOC.\Core.\Alu.$add$Risco-5/src/core/alu.v:30$36.
  creating $alu model for $macc $flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$633.
  creating $alu model for $flatten\ResetBootSystem.$lt$Risco-5/debug/reset.v:36$632 ($lt): new $alu
  creating $alu model for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:53$115 ($ge): new $alu
  creating $alu model for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:55$119 ($ge): new $alu
  creating $alu model for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:57$123 ($ge): new $alu
  creating $alu model for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:59$127 ($ge): new $alu
  creating $alu model for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:54$116 ($le): new $alu
  creating $alu model for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:56$120 ($le): new $alu
  creating $alu model for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:58$124 ($le): new $alu
  creating $alu model for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:60$128 ($le): new $alu
  creating $alu model for $flatten\SOC.\Core.\Alu.$ge$Risco-5/src/core/alu.v:46$46 ($ge): new $alu
  creating $alu model for $flatten\SOC.\Core.\Alu.$lt$Risco-5/src/core/alu.v:34$38 ($lt): merged with $flatten\SOC.\Core.\Alu.$ge$Risco-5/src/core/alu.v:46$46.
  creating $alu model for $flatten\ResetBootSystem.$eq$Risco-5/debug/reset.v:38$634 ($eq): merged with $flatten\ResetBootSystem.$lt$Risco-5/debug/reset.v:36$632.
  creating $alu model for $flatten\SOC.\Core.\Alu.$eq$Risco-5/src/core/alu.v:40$43 ($eq): merged with $flatten\SOC.\Core.\Alu.$ge$Risco-5/src/core/alu.v:46$46.
  creating $alu cell for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:60$128: $auto$alumacc.cc:485:replace_alu$2413
  creating $alu cell for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:58$124: $auto$alumacc.cc:485:replace_alu$2426
  creating $alu cell for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:56$120: $auto$alumacc.cc:485:replace_alu$2439
  creating $alu cell for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:54$116: $auto$alumacc.cc:485:replace_alu$2452
  creating $alu cell for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:59$127: $auto$alumacc.cc:485:replace_alu$2465
  creating $alu cell for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:57$123: $auto$alumacc.cc:485:replace_alu$2474
  creating $alu cell for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:55$119: $auto$alumacc.cc:485:replace_alu$2483
  creating $alu cell for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:53$115: $auto$alumacc.cc:485:replace_alu$2492
  creating $alu cell for $flatten\ResetBootSystem.$lt$Risco-5/debug/reset.v:36$632, $flatten\ResetBootSystem.$eq$Risco-5/debug/reset.v:38$634: $auto$alumacc.cc:485:replace_alu$2501
  creating $alu cell for $flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$633: $auto$alumacc.cc:485:replace_alu$2512
  creating $alu cell for $flatten\SOC.\Core.\Alu.$ge$Risco-5/src/core/alu.v:46$46, $flatten\SOC.\Core.\Alu.$lt$Risco-5/src/core/alu.v:34$38, $flatten\SOC.\Core.\Alu.$eq$Risco-5/src/core/alu.v:40$43: $auto$alumacc.cc:485:replace_alu$2515
  creating $alu cell for $flatten\SOC.\Core.\Alu.$add$Risco-5/src/core/alu.v:30$36: $auto$alumacc.cc:485:replace_alu$2528
  creating $alu cell for $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:32$37: $auto$alumacc.cc:485:replace_alu$2531
  creating $alu cell for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:141$68: $auto$alumacc.cc:485:replace_alu$2534
  creating $alu cell for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:142$69: $auto$alumacc.cc:485:replace_alu$2537
  creating $alu cell for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:143$70: $auto$alumacc.cc:485:replace_alu$2540
  creating $alu cell for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:144$71: $auto$alumacc.cc:485:replace_alu$2543
  creating $alu cell for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:151$72: $auto$alumacc.cc:485:replace_alu$2546
  creating $alu cell for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:152$73: $auto$alumacc.cc:485:replace_alu$2549
  creating $alu cell for $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:30$835: $auto$alumacc.cc:485:replace_alu$2552
  creating $alu cell for $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:20$814: $auto$alumacc.cc:485:replace_alu$2555
  creating $alu cell for $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:34$841: $auto$alumacc.cc:485:replace_alu$2558
  creating $alu cell for $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:30$835: $auto$alumacc.cc:485:replace_alu$2561
  creating $alu cell for $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:20$814: $auto$alumacc.cc:485:replace_alu$2564
  creating $alu cell for $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:34$841: $auto$alumacc.cc:485:replace_alu$2567
  creating $alu cell for $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:154$794: $auto$alumacc.cc:485:replace_alu$2570
  creating $alu cell for $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:179$805: $auto$alumacc.cc:485:replace_alu$2573
  creating $alu cell for $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:138$743: $auto$alumacc.cc:485:replace_alu$2576
  creating $alu cell for $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:155$754: $auto$alumacc.cc:485:replace_alu$2579
  created 29 $alu and 0 $macc cells.

23.23. Executing OPT pass (performing simple optimizations).

23.23.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~3 debug messages>

23.23.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~10 debug messages>
Removed a total of 2 cells.

23.23.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~76 debug messages>

23.23.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

23.23.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

23.23.6. Executing OPT_DFF pass (perform DFF optimizations).

23.23.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 1 unused cells and 20 unused wires.
<suppressed ~2 debug messages>

23.23.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

23.23.9. Rerunning OPT passes. (Maybe there is more to do..)

23.23.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~76 debug messages>

23.23.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

23.23.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

23.23.13. Executing OPT_DFF pass (perform DFF optimizations).

23.23.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

23.23.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

23.23.16. Finished OPT passes. (There is nothing left to do.)

23.24. Executing MEMORY pass.

23.24.1. Executing OPT_MEM pass (optimize memories).
Performed a total of 0 transformations.

23.24.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).
Performed a total of 0 transformations.

23.24.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).
  Analyzing top.SOC.Core.RegisterBank.registers write port 0.
  Analyzing top.SOC.Core.RegisterBank.registers write port 1.
  Analyzing top.SOC.Core.RegisterBank.registers write port 2.
  Analyzing top.SOC.Memory.memory write port 0.
  Analyzing top.SOC.Memory.memory write port 1.
  Analyzing top.SOC.Memory.memory write port 2.
  Analyzing top.SOC.Uart.RX_FIFO.memory write port 0.
  Analyzing top.SOC.Uart.TX_FIFO.memory write port 0.

23.24.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs).

23.24.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd).
Checking read port `$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895'[0] in module `\top': no output FF found.
Checking read port `\SOC.Core.RegisterBank.registers'[0] in module `\top': no output FF found.
Checking read port `\SOC.Core.RegisterBank.registers'[1] in module `\top': merging output FF to cell.
    Write port 0: don't care on collision.
    Write port 1: non-transparent.
    Write port 2: non-transparent.
Checking read port `\SOC.Memory.memory'[0] in module `\top': no output FF found.
Checking read port `\SOC.Uart.RX_FIFO.memory'[0] in module `\top': merging output FF to cell.
    Write port 0: non-transparent.
Checking read port `\SOC.Uart.TX_FIFO.memory'[0] in module `\top': merging output FF to cell.
    Write port 0: non-transparent.
Checking read port address `$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895'[0] in module `\top': address FF has fully-defined init value, not supported.
Checking read port address `\SOC.Core.RegisterBank.registers'[0] in module `\top': address FF has fully-defined init value, not supported.
Checking read port address `\SOC.Memory.memory'[0] in module `\top': no address FF found.

23.24.6. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 3 unused cells and 52 unused wires.
<suppressed ~6 debug messages>

23.24.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).
Consolidating read ports of memory top.SOC.Core.RegisterBank.registers by address:
Consolidating write ports of memory top.SOC.Core.RegisterBank.registers by address:
  Merging ports 0, 2 (address 5'00000).
Consolidating write ports of memory top.SOC.Core.RegisterBank.registers by address:
Consolidating write ports of memory top.SOC.Memory.memory by address:
  Merging ports 0, 1 (address \SOC.Memory.address [10:2]).
  Merging ports 0, 2 (address \SOC.Memory.address [10:2]).
Consolidating write ports of memory top.SOC.Core.RegisterBank.registers using sat-based resource sharing:
  Checking group clocked with posedge \clk, width 32: ports 0, 1.
  Common input cone for all EN signals: 6 cells.
  Size of unconstrained SAT problem: 40 variables, 98 clauses
  Merging port 1 into port 0.

23.24.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).
Performed a total of 0 transformations.

23.24.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 8 unused cells and 8 unused wires.
<suppressed ~9 debug messages>

23.24.10. Executing MEMORY_COLLECT pass (generating $mem cells).

23.25. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

23.26. Executing MEMORY_LIBMAP pass (mapping memories to cells).
using FF mapping for memory top.$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895
mapping memory top.SOC.Core.RegisterBank.registers via $__TRELLIS_DPR16X4_
Extracted data FF from read port 1 of top.SOC.Core.RegisterBank.registers: $\SOC.Core.RegisterBank.registers$rdreg[1]
mapping memory top.SOC.Memory.memory via $__TRELLIS_DPR16X4_
mapping memory top.SOC.Uart.RX_FIFO.memory via $__TRELLIS_DPR16X4_
Extracted data FF from read port 0 of top.SOC.Uart.RX_FIFO.memory: $\SOC.Uart.RX_FIFO.memory$rdreg[0]
mapping memory top.SOC.Uart.TX_FIFO.memory via $__TRELLIS_DPR16X4_
Extracted data FF from read port 0 of top.SOC.Uart.TX_FIFO.memory: $\SOC.Uart.TX_FIFO.memory$rdreg[0]
<suppressed ~1124 debug messages>

23.27. Executing TECHMAP pass (map to technology primitives).

23.27.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/lutrams_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/lutrams_map.v' to AST representation.
Generating RTLIL representation for module `\$__TRELLIS_DPR16X4_'.
Successfully finished Verilog frontend.

23.27.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/brams_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/brams_map.v' to AST representation.
Generating RTLIL representation for module `\$__ECP5_DP16KD_'.
Generating RTLIL representation for module `\$__ECP5_PDPW16KD_'.
Successfully finished Verilog frontend.

23.27.3. Continuing TECHMAP pass.
Using template $paramod$514fc941ac1ae997c717a8e6a1180ed8e0cf8fa9\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$04778961cc1285a5efea28f98f28381eb2862208\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$1f7528d846def63a25ef79a14688e75507487b07\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$16483afc93766dfb5fb1eddfd226d96b3663d59c\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$aaadea22aebcd84c93bb9858adaa720cf09b082d\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$4732e8e929fe8d0a57a6c959ddfc52773439ff42\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$5b36af983a34dea819263d47bd985c03f062c03b\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$5f84a8dd211265fde0680d1329e0aeb011857798\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$65b5a9049f0a0f5b9de58368be8ce2821f51e438\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$5a90b288fb430e0f24af5f61ee43ef935b86341e\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$58ddad20e9ef77e6675ec0a973f6df52cac15605\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$569f3b21b6212e6a0e436dd55c34df99d3696e0b\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$c21745a1d1b8202233eb4fd671436aaa3b71d7e7\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$eabd6f8a46e61d81805337b1dc746bfd80802602\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$98f4fff52781fee114365d416fa097fc5bdcc5a1\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$ef9fccd6f2ebbfd2f9ea51ad76fcd229dd950af9\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$f05333f47f0fac035d1d00a83ba1f91fba94d570\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$e060b64551c3d3977f3359c6d9cbc2f183f778aa\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$5e6f6332f5b0abb114a71354918e4077127fc51f\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$04114c6daf9b714920df2338bb84f1d824cfb28f\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$df0229c2445eb19cad504fc663c8894a4b8ad2c2\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$82cf4a0fd82546fec0e453cb163e0b57b514e109\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$05123d0bc673513b0e5ab3de2414f4ca493424ef\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$3d62e89fd9fe82123196169686b7825d33b36c84\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$413228b6beffb528da7ce6c18481e68814727c46\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$74d116fba5fc319cbe4b4ef6fabb137b2ff9e708\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
No more expansions possible.
<suppressed ~635 debug messages>

23.28. Executing OPT pass (performing simple optimizations).

23.28.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~143 debug messages>

23.28.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~18 debug messages>
Removed a total of 6 cells.

23.28.3. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $auto$ff.cc:266:slice$2344 ($dffe) from module top (D = $flatten\ResetBootSystem.$procmux$1806_Y, Q = \ResetBootSystem.counter, rval = 6'000000).
Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$2332 ($sdff) from module top.
Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$2335 ($sdff) from module top.
Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$2335 ($sdff) from module top.
Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$2335 ($sdff) from module top.
Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$2335 ($sdff) from module top.
Setting constant 0-bit at position 4 on $auto$ff.cc:266:slice$2335 ($sdff) from module top.
Setting constant 0-bit at position 5 on $auto$ff.cc:266:slice$2335 ($sdff) from module top.
Setting constant 0-bit at position 6 on $auto$ff.cc:266:slice$2335 ($sdff) from module top.
Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$2335 ($sdff) from module top.
Setting constant 0-bit at position 8 on $auto$ff.cc:266:slice$2335 ($sdff) from module top.
Setting constant 0-bit at position 9 on $auto$ff.cc:266:slice$2335 ($sdff) from module top.
Setting constant 0-bit at position 10 on $auto$ff.cc:266:slice$2335 ($sdff) from module top.
Setting constant 0-bit at position 11 on $auto$ff.cc:266:slice$2335 ($sdff) from module top.
Setting constant 0-bit at position 12 on $auto$ff.cc:266:slice$2335 ($sdff) from module top.
Setting constant 0-bit at position 13 on $auto$ff.cc:266:slice$2335 ($sdff) from module top.
Setting constant 0-bit at position 14 on $auto$ff.cc:266:slice$2335 ($sdff) from module top.
Setting constant 0-bit at position 15 on $auto$ff.cc:266:slice$2335 ($sdff) from module top.

23.28.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 19 unused cells and 2122 unused wires.
<suppressed ~20 debug messages>

23.28.5. Rerunning OPT passes. (Removed registers in this run.)

23.28.6. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~2 debug messages>

23.28.7. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

23.28.8. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $auto$ff.cc:266:slice$3448 ($sdffce) from module top (D = $auto$wreduce.cc:461:run$2370 [5:0], Q = \ResetBootSystem.counter, rval = 6'000000).

23.28.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 3 unused cells and 3 unused wires.
<suppressed ~4 debug messages>

23.28.10. Rerunning OPT passes. (Removed registers in this run.)

23.28.11. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

23.28.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

23.28.13. Executing OPT_DFF pass (perform DFF optimizations).

23.28.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

23.28.15. Finished fast OPT passes.

23.29. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).
Mapping memory $flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895 in module \top:
  created 16 $dff cells and 0 static cells of width 18.
  read interface: 0 $dff and 15 $mux cells.
  write interface: 0 write mux blocks.

23.30. Executing OPT pass (performing simple optimizations).

23.30.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

23.30.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

23.30.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
      Replacing known input bits on port B of cell $auto$memory_share.cc:453:consolidate_wr_using_sat$2658: $auto$rtlil.cc:2489:ReduceOr$2652 -> 1'1
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~58 debug messages>

23.30.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
    Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][3][6]$3493:
      Old ports: A=18'010000010000000000, B=18'010000011000000000, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][3]$a$3473
      New ports: A=1'0, B=1'1, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][3]$a$3473 [9]
      New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][3]$a$3473 [17:10] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][3]$a$3473 [8:0] } = 17'01000001000000000
    Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][3][5]$3490:
      Old ports: A=18'000000001010100100, B=18'101000010000000101, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][2]$b$3471
      New ports: A=2'10, B=2'01, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][2]$b$3471 [5] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][2]$b$3471 [0] }
      New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][2]$b$3471 [17:6] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][2]$b$3471 [4:1] } = { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][2]$b$3471 [0] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][2]$b$3471 [0] 4'0000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][2]$b$3471 [0] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][2]$b$3471 [5] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][2]$b$3471 [5] 5'00010 }
    Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][3][4]$3487:
      Old ports: A=18'010000001100000001, B=18'101000010000000100, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][2]$a$3470
      New ports: A=2'01, B=2'10, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][2]$a$3470 [2] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][2]$a$3470 [0] }
      New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][2]$a$3470 [17:3] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][2]$a$3470 [1] } = { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][2]$a$3470 [2] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][2]$a$3470 [0] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][2]$a$3470 [2] 4'0000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][2]$a$3470 [2] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][2]$a$3470 [0] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][2]$a$3470 [0] 6'000000 }
    Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][3][3]$3484:
      Old ports: A=18'000000001100000000, B=18'000000000000001000, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][1]$b$3468
      New ports: A=2'10, B=2'01, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][1]$b$3468 [8] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][1]$b$3468 [3] }
      New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][1]$b$3468 [17:9] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][1]$b$3468 [7:4] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][1]$b$3468 [2:0] } = { 8'00000000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][1]$b$3468 [8] 7'0000000 }
    Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][3][2]$3481:
      Old ports: A=18'000000100000001000, B=18'000000000000010010, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][1]$a$3467
      New ports: A=2'10, B=2'01, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][1]$a$3467 [3] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][1]$a$3467 [1] }
      New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][1]$a$3467 [17:4] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][1]$a$3467 [2] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][1]$a$3467 [0] } = { 6'000000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][1]$a$3467 [3] 6'000000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][1]$a$3467 [1] 2'00 }
    Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][3][1]$3478:
      Old ports: A=18'010000001000000000, B=18'000010000000000010, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][0]$b$3465
      New ports: A=2'10, B=2'01, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][0]$b$3465 [9] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][0]$b$3465 [1] }
      New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][0]$b$3465 [17:10] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][0]$b$3465 [8:2] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][0]$b$3465 [0] } = { 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][0]$b$3465 [9] 2'00 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][0]$b$3465 [1] 11'00000000000 }
    Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][3][0]$3475:
      Old ports: A=18'101110000000000000, B=18'010000010000000000, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][0]$a$3464
      New ports: A=2'10, B=2'01, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][0]$a$3464 [13] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][0]$a$3464 [10] }
      New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][0]$a$3464 [17:14] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][0]$a$3464 [12:11] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][0]$a$3464 [9:0] } = { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][0]$a$3464 [13] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][0]$a$3464 [10] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][0]$a$3464 [13] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][0]$a$3464 [13] 12'000000000000 }
    Consolidated identical input bits for $mux cell $auto$memory_share.cc:273:consolidate_wr_by_addr$2643:
      Old ports: A={ \SOC.Memory.buffer [31:16] \SOC.Memory.write_data [15:0] }, B=\SOC.Memory.write_data, Y=$auto$rtlil.cc:2582:Mux$2644
      New ports: A=\SOC.Memory.buffer [31:16], B=\SOC.Memory.write_data [31:16], Y=$auto$rtlil.cc:2582:Mux$2644 [31:16]
      New connections: $auto$rtlil.cc:2582:Mux$2644 [15:0] = \SOC.Memory.write_data [15:0]
    New ctrl vector for $pmux cell $flatten\ResetBootSystem.$procmux$1815: { $flatten\ResetBootSystem.$procmux$1810_CMP $flatten\ResetBootSystem.$procmux$1809_CMP }
    Consolidated identical input bits for $mux cell $flatten\ResetBootSystem.$procmux$1818:
      Old ports: A=2'00, B=2'10, Y=$flatten\ResetBootSystem.$procmux$1818_Y
      New ports: A=1'0, B=1'1, Y=$flatten\ResetBootSystem.$procmux$1818_Y [1]
      New connections: $flatten\ResetBootSystem.$procmux$1818_Y [0] = 1'0
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\ALU_Control.$procmux$1911:
      Old ports: A=3'010, B=3'110, Y=$auto$wreduce.cc:461:run$2372 [2:0]
      New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:461:run$2372 [2]
      New connections: $auto$wreduce.cc:461:run$2372 [1:0] = 2'10
    Consolidated identical input bits for $pmux cell $flatten\SOC.\Core.\ALU_Control.$procmux$1932:
      Old ports: A=4'0110, B=12'101101111110, Y=$flatten\SOC.\Core.\ALU_Control.$2\aluop_out[3:0]
      New ports: A=3'010, B=9'101011110, Y={ $flatten\SOC.\Core.\ALU_Control.$2\aluop_out[3:0] [3:2] $flatten\SOC.\Core.\ALU_Control.$2\aluop_out[3:0] [0] }
      New connections: $flatten\SOC.\Core.\ALU_Control.$2\aluop_out[3:0] [1] = 1'1
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\CSR_Unit.$procmux$1570: { $flatten\SOC.\Core.\CSR_Unit.$procmux$1591_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1590_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1583_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1582_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1581_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1580_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1579_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1578_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1577_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1576_CMP $auto$opt_reduce.cc:134:opt_pmux$2120 $auto$opt_reduce.cc:134:opt_pmux$2118 $auto$opt_reduce.cc:134:opt_pmux$2116 $auto$opt_reduce.cc:134:opt_pmux$2114 }
    Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][3][7]$3496:
      Old ports: A=18'010000001000000000, B=18'000001000001001000, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][3]$b$3474
      New ports: A=2'10, B=2'01, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][3]$b$3474 [9] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][3]$b$3474 [3] }
      New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][3]$b$3474 [17:10] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][3]$b$3474 [8:4] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][3]$b$3474 [2:0] } = { 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][3]$b$3474 [9] 3'000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][3]$b$3474 [3] 4'0000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][3]$b$3474 [3] 5'00000 }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$1850:
      Old ports: A=3'101, B=3'011, Y=$auto$wreduce.cc:461:run$2376 [2:0]
      New ports: A=2'10, B=2'01, Y=$auto$wreduce.cc:461:run$2376 [2:1]
      New connections: $auto$wreduce.cc:461:run$2376 [0] = 1'1
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Immediate_Generator.$procmux$1526:
      Old ports: A={ \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24:20] }, B={ 27'000000000000000000000000000 \SOC.Core.instruction_register [24:20] }, Y=$flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0]
      New ports: A=\SOC.Core.instruction_register [24], B=1'0, Y=$flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5]
      New connections: { $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [31:6] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [4:0] } = { $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] \SOC.Core.instruction_register [24:20] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Immediate_Generator.$procmux$1553:
      Old ports: A={ \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [7] \SOC.Core.instruction_register [30:25] \SOC.Core.instruction_register [11:8] 1'0 }, B={ 19'0000000000000000000 \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [7] \SOC.Core.instruction_register [30:25] \SOC.Core.instruction_register [11:8] 1'0 }, Y=$flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0]
      New ports: A=\SOC.Core.instruction_register [31], B=1'0, Y=$flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13]
      New connections: { $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [31:14] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12:0] } = { $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [7] \SOC.Core.instruction_register [30:25] \SOC.Core.instruction_register [11:8] 1'0 }
    Consolidated identical input bits for $pmux cell $flatten\SOC.\Memory.$procmux$1255:
      Old ports: A=\SOC.Memory.buffer, B={ 24'000000000000000000000000 \SOC.Memory.buffer [7:0] 16'0000000000000000 \SOC.Memory.buffer [15:0] }, Y=\SOC.Bus.slave_0_read_data
      New ports: A=\SOC.Memory.buffer [31:8], B={ 40'0000000000000000000000000000000000000000 \SOC.Memory.buffer [15:8] }, Y=\SOC.Bus.slave_0_read_data [31:8]
      New connections: \SOC.Bus.slave_0_read_data [7:0] = \SOC.Memory.buffer [7:0]
    Consolidated identical input bits for $pmux cell $flatten\SOC.\Uart.\i_uart_rx.$procmux$1089:
      Old ports: A=3'000, B={ 2'00 $auto$wreduce.cc:461:run$2394 [0] 1'0 $auto$wreduce.cc:461:run$2395 [1:0] 2'01 \SOC.Uart.i_uart_rx.payload_done 1'0 $auto$wreduce.cc:461:run$2397 [1:0] }, Y=\SOC.Uart.i_uart_rx.n_fsm_state
      New ports: A=2'00, B={ 1'0 $auto$wreduce.cc:461:run$2394 [0] $auto$wreduce.cc:461:run$2395 [1:0] 1'1 \SOC.Uart.i_uart_rx.payload_done $auto$wreduce.cc:461:run$2397 [1:0] }, Y=\SOC.Uart.i_uart_rx.n_fsm_state [1:0]
      New connections: \SOC.Uart.i_uart_rx.n_fsm_state [2] = 1'0
    Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:121$783:
      Old ports: A=2'11, B=2'00, Y=$auto$wreduce.cc:461:run$2397 [1:0]
      New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$2397 [0]
      New connections: $auto$wreduce.cc:461:run$2397 [1] = $auto$wreduce.cc:461:run$2397 [0]
    Consolidated identical input bits for $pmux cell $flatten\SOC.\Uart.\i_uart_tx.$procmux$1226:
      Old ports: A=3'000, B={ 2'00 \SOC.Uart.uart_tx_en 1'0 $auto$wreduce.cc:461:run$2399 [1:0] 2'01 \SOC.Uart.i_uart_tx.payload_done 1'0 $auto$wreduce.cc:461:run$2401 [1:0] }, Y=\SOC.Uart.i_uart_tx.n_fsm_state
      New ports: A=2'00, B={ 1'0 \SOC.Uart.uart_tx_en $auto$wreduce.cc:461:run$2399 [1:0] 1'1 \SOC.Uart.i_uart_tx.payload_done $auto$wreduce.cc:461:run$2401 [1:0] }, Y=\SOC.Uart.i_uart_tx.n_fsm_state [1:0]
      New connections: \SOC.Uart.i_uart_tx.n_fsm_state [2] = 1'0
    Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:103$726:
      Old ports: A=2'11, B=2'00, Y=$auto$wreduce.cc:461:run$2401 [1:0]
      New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$2401 [0]
      New connections: $auto$wreduce.cc:461:run$2401 [1] = $auto$wreduce.cc:461:run$2401 [0]
  Optimizing cells in module \top.
    Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][3]$3472:
      Old ports: A=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][3]$a$3473, B=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][3]$b$3474, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][1][1]$b$3462
      New ports: A={ 2'11 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][3]$a$3473 [9] 1'0 }, B={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][3]$b$3474 [9] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][3]$b$3474 [9] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][3]$b$3474 [3] }, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][1][1]$b$3462 [16] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][1][1]$b$3462 [10:9] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][1][1]$b$3462 [3] }
      New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][1][1]$b$3462 [17] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][1][1]$b$3462 [15:11] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][1][1]$b$3462 [8:4] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][1][1]$b$3462 [2:0] } = { 4'0000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][1][1]$b$3462 [3] 3'000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][1][1]$b$3462 [3] 5'00000 }
    Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][2]$3469:
      Old ports: A=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][2]$a$3470, B=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][2]$b$3471, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][1][1]$a$3461
      New ports: A={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][2]$a$3470 [2] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][2]$a$3470 [0] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][2]$a$3470 [0] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][2]$a$3470 [2] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][2]$a$3470 [0] }, B={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][2]$b$3471 [0] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][2]$b$3471 [5] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][2]$b$3471 [5] 1'1 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][2]$b$3471 [0] }, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][1][1]$a$3461 [10:8] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][1][1]$a$3461 [5] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][1][1]$a$3461 [2] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][1][1]$a$3461 [0] }
      New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][1][1]$a$3461 [17:11] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][1][1]$a$3461 [7:6] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][1][1]$a$3461 [4:3] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][1][1]$a$3461 [1] } = { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][1][1]$a$3461 [10] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][1][1]$a$3461 [8] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][1][1]$a$3461 [10] 4'0000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][1][1]$a$3461 [5] 4'0000 }
    Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][1]$3466:
      Old ports: A=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][1]$a$3467, B=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][1]$b$3468, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][1][0]$b$3459
      New ports: A={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][1]$a$3467 [3] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][1]$a$3467 [3] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][1]$a$3467 [1] }, B={ 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][1]$b$3468 [8] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][1]$b$3468 [3] 1'0 }, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][1][0]$b$3459 [11] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][1][0]$b$3459 [8] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][1][0]$b$3459 [3] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][1][0]$b$3459 [1] }
      New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][1][0]$b$3459 [17:12] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][1][0]$b$3459 [10:9] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][1][0]$b$3459 [7:4] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][1][0]$b$3459 [2] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][1][0]$b$3459 [0] } = { 7'0000000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][1][0]$b$3459 [8] 3'000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][1][0]$b$3459 [1] 2'00 }
    Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][0]$3463:
      Old ports: A=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][0]$a$3464, B=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][0]$b$3465, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][1][0]$a$3458
      New ports: A={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][0]$a$3464 [10] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][0]$a$3464 [13] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][0]$a$3464 [13] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][0]$a$3464 [10] 2'00 }, B={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][0]$b$3465 [9] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][0]$b$3465 [1] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][0]$b$3465 [9] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][2][0]$b$3465 [1] }, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][1][0]$a$3458 [16] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][1][0]$a$3458 [14:13] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][1][0]$a$3458 [10:9] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][1][0]$a$3458 [1] }
      New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][1][0]$a$3458 [17] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][1][0]$a$3458 [15] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][1][0]$a$3458 [12:11] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][1][0]$a$3458 [8:2] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][1][0]$a$3458 [0] } = { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][1][0]$a$3458 [14] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][1][0]$a$3458 [14] 10'0000000000 }
    Consolidated identical input bits for $mux cell $auto$memory_share.cc:273:consolidate_wr_by_addr$2647:
      Old ports: A=$auto$rtlil.cc:2582:Mux$2644, B={ \SOC.Memory.buffer [31:8] \SOC.Memory.write_data [7:0] }, Y=$auto$rtlil.cc:2582:Mux$2648
      New ports: A={ $auto$rtlil.cc:2582:Mux$2644 [31:16] \SOC.Memory.write_data [15:8] }, B=\SOC.Memory.buffer [31:8], Y=$auto$rtlil.cc:2582:Mux$2648 [31:8]
      New connections: $auto$rtlil.cc:2582:Mux$2648 [7:0] = \SOC.Memory.write_data [7:0]
    Consolidated identical input bits for $mux cell $flatten\ResetBootSystem.$procmux$1824:
      Old ports: A=2'00, B=$flatten\ResetBootSystem.$procmux$1818_Y, Y=$flatten\ResetBootSystem.$procmux$1824_Y
      New ports: A=1'0, B=$flatten\ResetBootSystem.$procmux$1818_Y [1], Y=$flatten\ResetBootSystem.$procmux$1824_Y [1]
      New connections: $flatten\ResetBootSystem.$procmux$1824_Y [0] = 1'0
    Consolidated identical input bits for $pmux cell $flatten\SOC.\Core.\Immediate_Generator.$procmux$1537:
      Old ports: A={ \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31:20] }, B={ \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24:20] 20'00000000000000000000 \SOC.Core.instruction_register [31:20] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] }, Y=$flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0]
      New ports: A={ \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31:25] }, B={ \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] 1'0 \SOC.Core.instruction_register [31:25] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] }, Y=$flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12:5]
      New connections: { $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [31:13] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [4:0] } = { $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] \SOC.Core.instruction_register [24:20] }
  Optimizing cells in module \top.
    Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][1][1]$3460:
      Old ports: A=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][1][1]$a$3461, B=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][1][1]$b$3462, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][0][0]$b$3456
      New ports: A={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][1][1]$a$3461 [8] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][1][1]$a$3461 [10] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][1][1]$a$3461 [10:8] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][1][1]$a$3461 [5] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][1][1]$a$3461 [2] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][1][1]$a$3461 [0] }, B={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][1][1]$b$3462 [16] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][1][1]$b$3462 [10:9] 2'00 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][1][1]$b$3462 [3] 2'00 }, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][0][0]$b$3456 [16:15] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][0][0]$b$3456 [10:8] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][0][0]$b$3456 [5] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][0][0]$b$3456 [3:2] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][0][0]$b$3456 [0] }
      New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][0][0]$b$3456 [17] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][0][0]$b$3456 [14:11] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][0][0]$b$3456 [7:6] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][0][0]$b$3456 [4] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][0][0]$b$3456 [1] } = { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][0][0]$b$3456 [15] 2'00 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][0][0]$b$3456 [3] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][0][0]$b$3456 [5] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][0][0]$b$3456 [3] 2'00 }
    Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][1][0]$3457:
      Old ports: A=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][1][0]$a$3458, B=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][1][0]$b$3459, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][0][0]$a$3455
      New ports: A={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][1][0]$a$3458 [16] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][1][0]$a$3458 [14:13] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][1][0]$a$3458 [10:9] 3'000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][1][0]$a$3458 [1] }, B={ 3'000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][1][0]$b$3459 [11] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][1][0]$b$3459 [8] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][1][0]$b$3459 [8] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][1][0]$b$3459 [1] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][1][0]$b$3459 [3] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][1][0]$b$3459 [1] }, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][0][0]$a$3455 [16] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][0][0]$a$3455 [14:13] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][0][0]$a$3455 [11:8] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][0][0]$a$3455 [4:3] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][0][0]$a$3455 [1] }
      New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][0][0]$a$3455 [17] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][0][0]$a$3455 [15] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][0][0]$a$3455 [12] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][0][0]$a$3455 [7:5] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][0][0]$a$3455 [2] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][0][0]$a$3455 [0] } = { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][0][0]$a$3455 [14] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][0][0]$a$3455 [14] 6'000000 }
  Optimizing cells in module \top.
    Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][0][0]$3454:
      Old ports: A=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][0][0]$a$3455, B=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][0][0]$b$3456, Y={ \SOC.Core.pc_write \SOC.Core.AluInputBMUX.option \SOC.Core.Control_Unit.ir_write \SOC.Bus.read \SOC.Core.MemoryDataMUX.option \SOC.Core.AluInputAMUX.option \SOC.Core.ALU_Control.aluop_in \SOC.Core.CSR_Unit.csr_write_enable \SOC.Core.pc_write_cond \SOC.Bus.write \SOC.Core.Control_Unit.reg_write \SOC.Core.PCSourceMUX.option [0] \SOC.Core.MemoryAddressMUX.option [0] \SOC.Core.ALU_Control.is_immediate }
      New ports: A={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][0][0]$a$3455 [16] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][0][0]$a$3455 [14] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][0][0]$a$3455 [14:13] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][0][0]$a$3455 [11:8] 2'00 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][0][0]$a$3455 [4:3] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][0][0]$a$3455 [1] 1'0 }, B={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][0][0]$b$3456 [16:15] 3'000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][0][0]$b$3456 [10:8] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][0][0]$b$3456 [3] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][0][0]$b$3456 [5] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][0][0]$b$3456 [3:2] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$895$rdmux[0][0][0]$b$3456 [0] }, Y={ \SOC.Core.AluInputBMUX.option \SOC.Core.Control_Unit.ir_write \SOC.Bus.read \SOC.Core.MemoryDataMUX.option [0] \SOC.Core.AluInputAMUX.option \SOC.Core.ALU_Control.aluop_in [1] \SOC.Core.CSR_Unit.csr_write_enable \SOC.Core.pc_write_cond \SOC.Bus.write \SOC.Core.Control_Unit.reg_write \SOC.Core.PCSourceMUX.option [0] \SOC.Core.MemoryAddressMUX.option [0] \SOC.Core.ALU_Control.is_immediate }
      New connections: { \SOC.Core.pc_write \SOC.Core.MemoryDataMUX.option [1] \SOC.Core.ALU_Control.aluop_in [0] } = { \SOC.Core.AluInputBMUX.option [0] \SOC.Core.CSR_Unit.csr_write_enable \SOC.Core.pc_write_cond }
  Optimizing cells in module \top.
Performed a total of 34 changes.

23.30.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~15 debug messages>
Removed a total of 5 cells.

23.30.6. Executing OPT_DFF pass (perform DFF optimizations).

23.30.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 1 unused cells and 22 unused wires.
<suppressed ~2 debug messages>

23.30.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~1 debug messages>

23.30.9. Rerunning OPT passes. (Maybe there is more to do..)

23.30.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~61 debug messages>

23.30.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

23.30.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

23.30.13. Executing OPT_DFF pass (perform DFF optimizations).
Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$2204 ($sdff) from module top.

23.30.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

23.30.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~2 debug messages>

23.30.16. Rerunning OPT passes. (Maybe there is more to do..)

23.30.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~61 debug messages>

23.30.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

23.30.19. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

23.30.20. Executing OPT_DFF pass (perform DFF optimizations).

23.30.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

23.30.22. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

23.30.23. Finished OPT passes. (There is nothing left to do.)

23.31. Executing TECHMAP pass (map to technology primitives).

23.31.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/techmap.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

23.31.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v' to AST representation.
Generating RTLIL representation for module `\_80_ecp5_alu'.
Successfully finished Verilog frontend.

23.31.3. Continuing TECHMAP pass.
Using extmapper simplemap for cells of type $mux.
Using extmapper simplemap for cells of type $reduce_or.
Using extmapper simplemap for cells of type $not.
Using extmapper simplemap for cells of type $sdffce.
Using extmapper simplemap for cells of type $reduce_bool.
Using extmapper simplemap for cells of type $dffe.
Using template $paramod$521ce43182eecb9f60c72393a788160d2c356bf5\_90_pmux for cells of type $pmux.
Using extmapper simplemap for cells of type $eq.
Using extmapper simplemap for cells of type $logic_not.
Using template $paramod$32efbfac1c4dc57230cf86180788fdfd12e3b511\_80_ecp5_alu for cells of type $alu.
Using template $paramod$54d740639e1393b22262823179ff783ea9f17a35\_90_pmux for cells of type $pmux.
Using template $paramod$645fe0cc96ae5edb83bff90cc2c78f4a20ca3e3c\_90_pmux for cells of type $pmux.
Using template $paramod$49f1dc3dcd6d2c748486fe94c6744a34a19bbafe\_90_pmux for cells of type $pmux.
Using template $paramod$8fabc56b80a569262acfc42757a02ca0b8e91278\_90_pmux for cells of type $pmux.
Using template $paramod$fbc7873bff55778c0b3173955b7e4bce1d9d6834\_80_ecp5_alu for cells of type $alu.
Using extmapper simplemap for cells of type $reduce_and.
Using extmapper simplemap for cells of type $or.
Using extmapper simplemap for cells of type $dff.
Using extmapper simplemap for cells of type $and.
Using extmapper simplemap for cells of type $sdffe.
Using template $paramod$3111a1a8e90c88cc8c163ba5aed0203d96ddc46d\_80_ecp5_alu for cells of type $alu.
Using extmapper simplemap for cells of type $ne.
Using extmapper simplemap for cells of type $tribuf.
Using extmapper simplemap for cells of type $logic_and.
Using extmapper simplemap for cells of type $sdff.
Using template $paramod$32a7b7b86c07519b7537abc18e96f0331f97914d\_90_alu for cells of type $alu.
Using extmapper simplemap for cells of type $logic_or.
Using template $paramod$068ad458e7761d78e5eed8238508872e7b0aef95\_90_pmux for cells of type $pmux.
Using template $paramod$215440792383f7884e57d9c95f84e9552d0bf4ac\_80_ecp5_alu for cells of type $alu.
Using template $paramod$41ef080258eed1ff8fcfbb7776f540ab469a3d7b\_80_ecp5_alu for cells of type $alu.
Using template $paramod$6a42b6fefed750f8a1c58eab59479d960557103c\_80_ecp5_alu for cells of type $alu.
Using template $paramod$c4ef20b21801b37ea2d65c32a05dfe56e84a870d\_80_ecp5_alu for cells of type $alu.
Using template $paramod$ad3b00a3808c9aa98afd971fabdc5fb6557b30ff\_80_ecp5_alu for cells of type $alu.
Using template $paramod$2407ada40cc3dda6c6015be2b49b748cddb5a800\_90_demux for cells of type $demux.
Using template $paramod$cc1e387d9d5ac1d3f6e6bed180038d9c0ac48d0c\_90_pmux for cells of type $pmux.
Using extmapper simplemap for cells of type $bmux.
Using template $paramod$824a2ca00d29d886599434cf8ea60471635f2955\_90_demux for cells of type $demux.
Using template $paramod$f1fc4bc1d42e857fca43ce0fdd0da6ff25c612c4\_90_pmux for cells of type $pmux.
Using template $paramod$4d45682f6d5f8751d24fc75184ef72226da353f7\_90_pmux for cells of type $pmux.
Using template $paramod$a13703aa027da371a1931fc542d213d7de559b19\_90_pmux for cells of type $pmux.
Using template $paramod$85df5dc01c7df96a7d8e5f1fdf76ce9ac452af63\_90_pmux for cells of type $pmux.
Using template $paramod$bf2533632d512eac76dd186c0da49367e29b8e98\_90_pmux for cells of type $pmux.
Using extmapper simplemap for cells of type $dlatch.
Using template $paramod$constmap:b9a86d073741c2a0f7bb241e73c2dd11747f3288$paramod$56955d0f36f77738c952d3505dc563df3ee11b94\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shr.
Using template $paramod$constmap:b9a86d073741c2a0f7bb241e73c2dd11747f3288$paramod$dce7c1188cb25d2520d170426d59301c3b73f9e7\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl.
Using template $paramod$a5f0941832cc861549e29ccafffe20bfdf2e5528\_90_pmux for cells of type $pmux.
Using extmapper simplemap for cells of type $xor.
Using template $paramod$cc80a4e89b0341cb117f5d28b0e7244620640141\_80_ecp5_alu for cells of type $alu.
Using template $paramod$e04283ca12514baf3d204c6994bec8f178dd89f8\_80_ecp5_alu for cells of type $alu.
Using extmapper simplemap for cells of type $pos.
Using template $paramod$63301a5e78ceb1f2c17a4ac1894f292ed5701c1f\_90_demux for cells of type $demux.
Using template $paramod$46c272b461898a6a76adeeeedb0917ce1a81b478\_90_demux for cells of type $demux.
Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000000100 for cells of type $lcu.
No more expansions possible.
<suppressed ~4300 debug messages>

23.32. Executing OPT pass (performing simple optimizations).

23.32.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~6142 debug messages>

23.32.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~4116 debug messages>
Removed a total of 1372 cells.

23.32.3. Executing OPT_DFF pass (perform DFF optimizations).

23.32.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 767 unused cells and 4073 unused wires.
<suppressed ~768 debug messages>

23.32.5. Finished fast OPT passes.

23.33. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

23.34. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).

23.35. Executing TECHMAP pass (map to technology primitives).

23.35.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v' to AST representation.
Generating RTLIL representation for module `\$_DFF_N_'.
Generating RTLIL representation for module `\$_DFF_P_'.
Generating RTLIL representation for module `\$_DFFE_NN_'.
Generating RTLIL representation for module `\$_DFFE_PN_'.
Generating RTLIL representation for module `\$_DFFE_NP_'.
Generating RTLIL representation for module `\$_DFFE_PP_'.
Generating RTLIL representation for module `\$_DFF_NP0_'.
Generating RTLIL representation for module `\$_DFF_NP1_'.
Generating RTLIL representation for module `\$_DFF_PP0_'.
Generating RTLIL representation for module `\$_DFF_PP1_'.
Generating RTLIL representation for module `\$_SDFF_NP0_'.
Generating RTLIL representation for module `\$_SDFF_NP1_'.
Generating RTLIL representation for module `\$_SDFF_PP0_'.
Generating RTLIL representation for module `\$_SDFF_PP1_'.
Generating RTLIL representation for module `\$_DFFE_NP0P_'.
Generating RTLIL representation for module `\$_DFFE_NP1P_'.
Generating RTLIL representation for module `\$_DFFE_PP0P_'.
Generating RTLIL representation for module `\$_DFFE_PP1P_'.
Generating RTLIL representation for module `\$_DFFE_NP0N_'.
Generating RTLIL representation for module `\$_DFFE_NP1N_'.
Generating RTLIL representation for module `\$_DFFE_PP0N_'.
Generating RTLIL representation for module `\$_DFFE_PP1N_'.
Generating RTLIL representation for module `\$_SDFFE_NP0P_'.
Generating RTLIL representation for module `\$_SDFFE_NP1P_'.
Generating RTLIL representation for module `\$_SDFFE_PP0P_'.
Generating RTLIL representation for module `\$_SDFFE_PP1P_'.
Generating RTLIL representation for module `\$_SDFFE_NP0N_'.
Generating RTLIL representation for module `\$_SDFFE_NP1N_'.
Generating RTLIL representation for module `\$_SDFFE_PP0N_'.
Generating RTLIL representation for module `\$_SDFFE_PP1N_'.
Generating RTLIL representation for module `\$_ALDFF_NP_'.
Generating RTLIL representation for module `\$_ALDFF_PP_'.
Generating RTLIL representation for module `\$_ALDFFE_NPN_'.
Generating RTLIL representation for module `\$_ALDFFE_NPP_'.
Generating RTLIL representation for module `\$_ALDFFE_PPN_'.
Generating RTLIL representation for module `\$_ALDFFE_PPP_'.
Generating RTLIL representation for module `\FD1P3AX'.
Generating RTLIL representation for module `\FD1P3AY'.
Generating RTLIL representation for module `\FD1P3BX'.
Generating RTLIL representation for module `\FD1P3DX'.
Generating RTLIL representation for module `\FD1P3IX'.
Generating RTLIL representation for module `\FD1P3JX'.
Generating RTLIL representation for module `\FD1S3AX'.
Generating RTLIL representation for module `\FD1S3AY'.
Generating RTLIL representation for module `\FD1S3BX'.
Generating RTLIL representation for module `\FD1S3DX'.
Generating RTLIL representation for module `\FD1S3IX'.
Generating RTLIL representation for module `\FD1S3JX'.
Generating RTLIL representation for module `\IFS1P3BX'.
Generating RTLIL representation for module `\IFS1P3DX'.
Generating RTLIL representation for module `\IFS1P3IX'.
Generating RTLIL representation for module `\IFS1P3JX'.
Generating RTLIL representation for module `\OFS1P3BX'.
Generating RTLIL representation for module `\OFS1P3DX'.
Generating RTLIL representation for module `\OFS1P3IX'.
Generating RTLIL representation for module `\OFS1P3JX'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\IBPU'.
Generating RTLIL representation for module `\IBPD'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\OBZPU'.
Generating RTLIL representation for module `\OBZPD'.
Generating RTLIL representation for module `\OBCO'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\BBPU'.
Generating RTLIL representation for module `\BBPD'.
Generating RTLIL representation for module `\ILVDS'.
Generating RTLIL representation for module `\OLVDS'.
Successfully finished Verilog frontend.

23.35.2. Continuing TECHMAP pass.
Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'0 for cells of type $_DFFE_PP_.
Using template \$_SDFFE_PP0P_ for cells of type $_SDFFE_PP0P_.
Using template \$_SDFF_PP0_ for cells of type $_SDFF_PP0_.
Using template \$_SDFF_PP1_ for cells of type $_SDFF_PP1_.
Using template \$_SDFFE_PP0N_ for cells of type $_SDFFE_PP0N_.
Using template $paramod\$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_.
Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'1 for cells of type $_DFFE_PP_.
Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFFE_PP_.
Using template \$_SDFFE_PP1P_ for cells of type $_SDFFE_PP1P_.
Using template $paramod\$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'0 for cells of type $_DFF_P_.
No more expansions possible.
<suppressed ~858 debug messages>

23.36. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~29 debug messages>

23.37. Executing SIMPLEMAP pass (map simple cells to gate primitives).

23.38. Executing LATTICE_GSR pass (implement FF init values).
Handling GSR in top.

23.39. Executing ATTRMVCP pass (move or copy attributes).

23.40. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 4162 unused wires.
<suppressed ~1 debug messages>

23.41. Executing TECHMAP pass (map to technology primitives).

23.41.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/latches_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/latches_map.v' to AST representation.
Generating RTLIL representation for module `\$_DLATCH_N_'.
Generating RTLIL representation for module `\$_DLATCH_P_'.
Successfully finished Verilog frontend.

23.41.2. Continuing TECHMAP pass.

23.41.3. Executing SIMPLEMAP pass (map simple cells to gate primitives).
Mapping \$_DLATCH_N_.$ternary$/eda/oss-cad-suite/lib/../share/yosys/ecp5/latches_map.v:4$22460 ($mux).
Mapping \$_DLATCH_N_.$logic_not$/eda/oss-cad-suite/lib/../share/yosys/ecp5/latches_map.v:4$22459 ($logic_not).
<suppressed ~4 debug messages>

23.41.4. Executing OPT pass (performing simple optimizations).

23.41.4.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module \$_DLATCH_N_.
<suppressed ~1 debug messages>

23.41.4.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\$_DLATCH_N_'.
Removed a total of 0 cells.

23.41.4.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \$_DLATCH_N_..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

23.41.4.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \$_DLATCH_N_.
Performed a total of 0 changes.

23.41.4.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\$_DLATCH_N_'.
Removed a total of 0 cells.

23.41.4.6. Executing OPT_DFF pass (perform DFF optimizations).

23.41.4.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \$_DLATCH_N_..
Removed 1 unused cells and 2 unused wires.
<suppressed ~2 debug messages>

23.41.4.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module \$_DLATCH_N_.

23.41.4.9. Rerunning OPT passes. (Maybe there is more to do..)

23.41.4.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \$_DLATCH_N_..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

23.41.4.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \$_DLATCH_N_.
Performed a total of 0 changes.

23.41.4.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\$_DLATCH_N_'.
Removed a total of 0 cells.

23.41.4.13. Executing OPT_DFF pass (perform DFF optimizations).

23.41.4.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \$_DLATCH_N_..

23.41.4.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module \$_DLATCH_N_.

23.41.4.16. Finished OPT passes. (There is nothing left to do.)
Using template \$_DLATCH_N_ for cells of type $_DLATCH_N_.
No more expansions possible.
<suppressed ~4 debug messages>

23.42. Executing ABC9 pass.

23.42.1. Executing ABC9_OPS pass (helper functions for ABC9).

23.42.2. Executing ABC9_OPS pass (helper functions for ABC9).

23.42.3. Executing PROC pass (convert processes to netlists).

23.42.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22564'.
Cleaned up 1 empty switch.

23.42.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22565 in module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

23.42.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

23.42.3.4. Executing PROC_INIT pass (extract init attributes).

23.42.3.5. Executing PROC_ARST pass (detect async resets in processes).

23.42.3.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

23.42.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22589'.
Creating decoders for process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22565'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22563_EN[3:0]$22571
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22563_DATA[3:0]$22570
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22563_ADDR[3:0]$22569
Creating decoders for process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22564'.

23.42.3.8. Executing PROC_DLATCH pass (convert process syncs to latches).

23.42.3.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.\i' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22589'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22548_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22589'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22549_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22589'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22553_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22589'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22558_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22589'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22550_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22589'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22559_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22589'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22555_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22589'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22551_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22589'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22560_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22589'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22556_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22589'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22554_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22589'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22561_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22589'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22562_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22589'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22557_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22589'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22552_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22589'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22547_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22589'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22563_ADDR' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22565'.
  created $dff cell `$procdff$22615' with positive edge clock.
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22563_DATA' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22565'.
  created $dff cell `$procdff$22616' with positive edge clock.
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22563_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22565'.
  created $dff cell `$procdff$22617' with positive edge clock.
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.\muxwre' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22564'.
  created direct connection (no actual register cell created).

23.42.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

23.42.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22589'.
Found and cleaned up 1 empty switch in `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22565'.
Removing empty process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22564'.
Cleaned up 1 empty switch.

23.42.3.12. Executing OPT_EXPR pass (perform const folding).

23.42.4. Executing PROC pass (convert processes to netlists).

23.42.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22635'.
Cleaned up 1 empty switch.

23.42.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22636 in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

23.42.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

23.42.4.4. Executing PROC_INIT pass (extract init attributes).

23.42.4.5. Executing PROC_ARST pass (detect async resets in processes).

23.42.4.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

23.42.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22660'.
Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22636'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22634_EN[3:0]$22640
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22634_DATA[3:0]$22642
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22634_ADDR[3:0]$22641
Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22635'.

23.42.4.8. Executing PROC_DLATCH pass (convert process syncs to latches).

23.42.4.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.\i' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22660'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22628_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22660'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22624_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22660'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22633_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22660'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22631_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22660'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22623_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22660'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22621_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22660'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22622_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22660'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22626_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22660'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22627_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22660'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22632_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22660'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22619_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22660'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22629_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22660'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22630_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22660'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22625_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22660'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22620_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22660'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22618_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22660'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22634_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22636'.
  created $dff cell `$procdff$22686' with positive edge clock.
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22634_ADDR' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22636'.
  created $dff cell `$procdff$22687' with positive edge clock.
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22634_DATA' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22636'.
  created $dff cell `$procdff$22688' with positive edge clock.
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.\muxwre' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22635'.
  created direct connection (no actual register cell created).

23.42.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

23.42.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22660'.
Found and cleaned up 1 empty switch in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22636'.
Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22635'.
Cleaned up 1 empty switch.

23.42.4.12. Executing OPT_EXPR pass (perform const folding).

23.42.5. Executing PROC pass (convert processes to netlists).

23.42.5.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22706'.
Cleaned up 1 empty switch.

23.42.5.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22707 in module $paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

23.42.5.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

23.42.5.4. Executing PROC_INIT pass (extract init attributes).

23.42.5.5. Executing PROC_ARST pass (detect async resets in processes).

23.42.5.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

23.42.5.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22731'.
Creating decoders for process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22707'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22705_EN[3:0]$22713
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22705_DATA[3:0]$22711
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22705_ADDR[3:0]$22712
Creating decoders for process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22706'.

23.42.5.8. Executing PROC_DLATCH pass (convert process syncs to latches).

23.42.5.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.\i' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22731'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22690_EN' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22731'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22702_EN' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22731'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22695_EN' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22731'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22704_EN' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22731'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22696_EN' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22731'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22692_EN' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22731'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22700_EN' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22731'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22701_EN' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22731'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22697_EN' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22731'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22699_EN' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22731'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22691_EN' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22731'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22694_EN' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22731'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22689_EN' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22731'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22703_EN' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22731'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22698_EN' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22731'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22693_EN' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22731'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22705_DATA' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22707'.
  created $dff cell `$procdff$22757' with positive edge clock.
Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22705_ADDR' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22707'.
  created $dff cell `$procdff$22758' with positive edge clock.
Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22705_EN' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22707'.
  created $dff cell `$procdff$22759' with positive edge clock.
Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.\muxwre' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22706'.
  created direct connection (no actual register cell created).

23.42.5.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

23.42.5.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22731'.
Found and cleaned up 1 empty switch in `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22707'.
Removing empty process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22706'.
Cleaned up 1 empty switch.

23.42.5.12. Executing OPT_EXPR pass (perform const folding).

23.42.6. Executing PROC pass (convert processes to netlists).

23.42.6.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22777'.
Cleaned up 1 empty switch.

23.42.6.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22778 in module $paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

23.42.6.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

23.42.6.4. Executing PROC_INIT pass (extract init attributes).

23.42.6.5. Executing PROC_ARST pass (detect async resets in processes).

23.42.6.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

23.42.6.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22802'.
Creating decoders for process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22778'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22776_EN[3:0]$22783
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22776_DATA[3:0]$22782
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22776_ADDR[3:0]$22784
Creating decoders for process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22777'.

23.42.6.8. Executing PROC_DLATCH pass (convert process syncs to latches).

23.42.6.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.\i' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22802'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22765_EN' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22802'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22766_EN' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22802'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22771_EN' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22802'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22773_EN' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22802'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22772_EN' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22802'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22768_EN' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22802'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22763_EN' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22802'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22769_EN' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22802'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22775_EN' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22802'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22774_EN' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22802'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22760_EN' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22802'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22762_EN' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22802'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22767_EN' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22802'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22761_EN' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22802'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22770_EN' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22802'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22764_EN' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22802'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22776_DATA' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22778'.
  created $dff cell `$procdff$22828' with positive edge clock.
Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22776_EN' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22778'.
  created $dff cell `$procdff$22829' with positive edge clock.
Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22776_ADDR' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22778'.
  created $dff cell `$procdff$22830' with positive edge clock.
Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.\muxwre' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22777'.
  created direct connection (no actual register cell created).

23.42.6.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

23.42.6.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22802'.
Found and cleaned up 1 empty switch in `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22778'.
Removing empty process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22777'.
Cleaned up 1 empty switch.

23.42.6.12. Executing OPT_EXPR pass (perform const folding).

23.42.7. Executing PROC pass (convert processes to netlists).

23.42.7.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22848'.
Cleaned up 1 empty switch.

23.42.7.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22849 in module $paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

23.42.7.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

23.42.7.4. Executing PROC_INIT pass (extract init attributes).

23.42.7.5. Executing PROC_ARST pass (detect async resets in processes).

23.42.7.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

23.42.7.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22873'.
Creating decoders for process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22849'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22847_EN[3:0]$22855
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22847_DATA[3:0]$22854
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22847_ADDR[3:0]$22853
Creating decoders for process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22848'.

23.42.7.8. Executing PROC_DLATCH pass (convert process syncs to latches).

23.42.7.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.\i' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22873'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22837_EN' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22873'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22841_EN' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22873'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22835_EN' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22873'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22843_EN' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22873'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22832_EN' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22873'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22836_EN' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22873'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22833_EN' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22873'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22838_EN' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22873'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22844_EN' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22873'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22845_EN' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22873'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22839_EN' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22873'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22842_EN' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22873'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22831_EN' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22873'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22846_EN' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22873'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22840_EN' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22873'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22834_EN' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22873'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22847_ADDR' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22849'.
  created $dff cell `$procdff$22899' with positive edge clock.
Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22847_DATA' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22849'.
  created $dff cell `$procdff$22900' with positive edge clock.
Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22847_EN' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22849'.
  created $dff cell `$procdff$22901' with positive edge clock.
Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.\muxwre' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22848'.
  created direct connection (no actual register cell created).

23.42.7.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

23.42.7.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22873'.
Found and cleaned up 1 empty switch in `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22849'.
Removing empty process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22848'.
Cleaned up 1 empty switch.

23.42.7.12. Executing OPT_EXPR pass (perform const folding).

23.42.8. Executing PROC pass (convert processes to netlists).

23.42.8.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22919'.
Cleaned up 1 empty switch.

23.42.8.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22920 in module $paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

23.42.8.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

23.42.8.4. Executing PROC_INIT pass (extract init attributes).

23.42.8.5. Executing PROC_ARST pass (detect async resets in processes).

23.42.8.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

23.42.8.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22944'.
Creating decoders for process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22920'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22918_EN[3:0]$22925
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22918_DATA[3:0]$22924
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22918_ADDR[3:0]$22926
Creating decoders for process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22919'.

23.42.8.8. Executing PROC_DLATCH pass (convert process syncs to latches).

23.42.8.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.\i' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22944'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22905_EN' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22944'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22907_EN' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22944'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22911_EN' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22944'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22913_EN' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22944'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22917_EN' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22944'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22908_EN' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22944'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22914_EN' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22944'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22912_EN' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22944'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22915_EN' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22944'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22909_EN' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22944'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22903_EN' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22944'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22906_EN' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22944'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22916_EN' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22944'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22910_EN' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22944'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22904_EN' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22944'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22902_EN' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22944'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22918_DATA' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22920'.
  created $dff cell `$procdff$22970' with positive edge clock.
Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22918_EN' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22920'.
  created $dff cell `$procdff$22971' with positive edge clock.
Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22918_ADDR' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22920'.
  created $dff cell `$procdff$22972' with positive edge clock.
Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.\muxwre' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22919'.
  created direct connection (no actual register cell created).

23.42.8.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

23.42.8.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22944'.
Found and cleaned up 1 empty switch in `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22920'.
Removing empty process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22919'.
Cleaned up 1 empty switch.

23.42.8.12. Executing OPT_EXPR pass (perform const folding).

23.42.9. Executing PROC pass (convert processes to netlists).

23.42.9.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22990'.
Cleaned up 1 empty switch.

23.42.9.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22991 in module $paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

23.42.9.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

23.42.9.4. Executing PROC_INIT pass (extract init attributes).

23.42.9.5. Executing PROC_ARST pass (detect async resets in processes).

23.42.9.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

23.42.9.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23015'.
Creating decoders for process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22991'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22989_EN[3:0]$22995
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22989_DATA[3:0]$22997
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22989_ADDR[3:0]$22996
Creating decoders for process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22990'.

23.42.9.8. Executing PROC_DLATCH pass (convert process syncs to latches).

23.42.9.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.\i' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23015'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22973_EN' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23015'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22975_EN' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23015'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22976_EN' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23015'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22981_EN' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23015'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22982_EN' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23015'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22987_EN' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23015'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22988_EN' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23015'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22979_EN' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23015'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22985_EN' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23015'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22977_EN' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23015'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22983_EN' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23015'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22984_EN' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23015'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22978_EN' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23015'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22986_EN' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23015'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22980_EN' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23015'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22974_EN' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23015'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22989_EN' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22991'.
  created $dff cell `$procdff$23041' with positive edge clock.
Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22989_ADDR' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22991'.
  created $dff cell `$procdff$23042' with positive edge clock.
Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22989_DATA' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22991'.
  created $dff cell `$procdff$23043' with positive edge clock.
Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.\muxwre' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22990'.
  created direct connection (no actual register cell created).

23.42.9.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

23.42.9.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23015'.
Found and cleaned up 1 empty switch in `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22991'.
Removing empty process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22990'.
Cleaned up 1 empty switch.

23.42.9.12. Executing OPT_EXPR pass (perform const folding).

23.42.10. Executing PROC pass (convert processes to netlists).

23.42.10.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23061'.
Cleaned up 1 empty switch.

23.42.10.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23062 in module $paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

23.42.10.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

23.42.10.4. Executing PROC_INIT pass (extract init attributes).

23.42.10.5. Executing PROC_ARST pass (detect async resets in processes).

23.42.10.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

23.42.10.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23086'.
Creating decoders for process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23062'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23060_EN[3:0]$23068
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23060_DATA[3:0]$23067
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23060_ADDR[3:0]$23066
Creating decoders for process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23061'.

23.42.10.8. Executing PROC_DLATCH pass (convert process syncs to latches).

23.42.10.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.\i' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23086'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23044_EN' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23086'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23054_EN' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23086'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23048_EN' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23086'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23045_EN' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23086'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23046_EN' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23086'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23051_EN' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23086'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23052_EN' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23086'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23057_EN' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23086'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23058_EN' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23086'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23049_EN' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23086'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23055_EN' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23086'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23047_EN' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23086'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23053_EN' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23086'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23059_EN' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23086'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23056_EN' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23086'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23050_EN' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23086'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23060_ADDR' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23062'.
  created $dff cell `$procdff$23112' with positive edge clock.
Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23060_DATA' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23062'.
  created $dff cell `$procdff$23113' with positive edge clock.
Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23060_EN' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23062'.
  created $dff cell `$procdff$23114' with positive edge clock.
Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.\muxwre' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23061'.
  created direct connection (no actual register cell created).

23.42.10.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

23.42.10.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23086'.
Found and cleaned up 1 empty switch in `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23062'.
Removing empty process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23061'.
Cleaned up 1 empty switch.

23.42.10.12. Executing OPT_EXPR pass (perform const folding).

23.42.11. Executing PROC pass (convert processes to netlists).

23.42.11.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23132'.
Cleaned up 1 empty switch.

23.42.11.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23133 in module $paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

23.42.11.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

23.42.11.4. Executing PROC_INIT pass (extract init attributes).

23.42.11.5. Executing PROC_ARST pass (detect async resets in processes).

23.42.11.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

23.42.11.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23157'.
Creating decoders for process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23133'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23131_EN[3:0]$23137
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23131_DATA[3:0]$23139
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23131_ADDR[3:0]$23138
Creating decoders for process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23132'.

23.42.11.8. Executing PROC_DLATCH pass (convert process syncs to latches).

23.42.11.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.\i' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23157'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23115_EN' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23157'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23116_EN' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23157'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23121_EN' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23157'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23122_EN' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23157'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23117_EN' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23157'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23123_EN' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23157'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23127_EN' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23157'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23128_EN' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23157'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23118_EN' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23157'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23129_EN' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23157'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23119_EN' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23157'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23124_EN' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23157'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23125_EN' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23157'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23130_EN' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23157'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23126_EN' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23157'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23120_EN' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23157'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23131_EN' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23133'.
  created $dff cell `$procdff$23183' with positive edge clock.
Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23131_ADDR' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23133'.
  created $dff cell `$procdff$23184' with positive edge clock.
Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23131_DATA' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23133'.
  created $dff cell `$procdff$23185' with positive edge clock.
Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.\muxwre' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23132'.
  created direct connection (no actual register cell created).

23.42.11.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

23.42.11.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23157'.
Found and cleaned up 1 empty switch in `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23133'.
Removing empty process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23132'.
Cleaned up 1 empty switch.

23.42.11.12. Executing OPT_EXPR pass (perform const folding).

23.42.12. Executing PROC pass (convert processes to netlists).

23.42.12.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23203'.
Cleaned up 1 empty switch.

23.42.12.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23204 in module $paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

23.42.12.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

23.42.12.4. Executing PROC_INIT pass (extract init attributes).

23.42.12.5. Executing PROC_ARST pass (detect async resets in processes).

23.42.12.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

23.42.12.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23228'.
Creating decoders for process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23204'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23202_EN[3:0]$23208
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23202_DATA[3:0]$23209
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23202_ADDR[3:0]$23210
Creating decoders for process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23203'.

23.42.12.8. Executing PROC_DLATCH pass (convert process syncs to latches).

23.42.12.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.\i' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23228'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23195_EN' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23228'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23192_EN' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23228'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23193_EN' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23228'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23197_EN' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23228'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23200_EN' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23228'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23199_EN' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23228'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23186_EN' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23228'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23189_EN' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23228'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23194_EN' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23228'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23187_EN' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23228'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23191_EN' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23228'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23201_EN' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23228'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23198_EN' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23228'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23188_EN' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23228'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23196_EN' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23228'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23190_EN' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23228'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23202_EN' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23204'.
  created $dff cell `$procdff$23254' with positive edge clock.
Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23202_DATA' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23204'.
  created $dff cell `$procdff$23255' with positive edge clock.
Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23202_ADDR' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23204'.
  created $dff cell `$procdff$23256' with positive edge clock.
Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.\muxwre' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23203'.
  created direct connection (no actual register cell created).

23.42.12.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

23.42.12.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23228'.
Found and cleaned up 1 empty switch in `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23204'.
Removing empty process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23203'.
Cleaned up 1 empty switch.

23.42.12.12. Executing OPT_EXPR pass (perform const folding).

23.42.13. Executing PROC pass (convert processes to netlists).

23.42.13.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23274'.
Cleaned up 1 empty switch.

23.42.13.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23275 in module $paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

23.42.13.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

23.42.13.4. Executing PROC_INIT pass (extract init attributes).

23.42.13.5. Executing PROC_ARST pass (detect async resets in processes).

23.42.13.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

23.42.13.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23299'.
Creating decoders for process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23275'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23273_EN[3:0]$23280
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23273_DATA[3:0]$23281
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23273_ADDR[3:0]$23279
Creating decoders for process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23274'.

23.42.13.8. Executing PROC_DLATCH pass (convert process syncs to latches).

23.42.13.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.\i' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23299'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23271_EN' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23299'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23270_EN' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23299'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23265_EN' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23299'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23259_EN' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23299'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23269_EN' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23299'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23264_EN' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23299'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23258_EN' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23299'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23268_EN' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23299'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23267_EN' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23299'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23263_EN' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23299'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23262_EN' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23299'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23257_EN' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23299'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23261_EN' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23299'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23272_EN' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23299'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23266_EN' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23299'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23260_EN' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23299'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23273_ADDR' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23275'.
  created $dff cell `$procdff$23325' with positive edge clock.
Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23273_EN' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23275'.
  created $dff cell `$procdff$23326' with positive edge clock.
Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23273_DATA' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23275'.
  created $dff cell `$procdff$23327' with positive edge clock.
Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.\muxwre' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23274'.
  created direct connection (no actual register cell created).

23.42.13.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

23.42.13.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23299'.
Found and cleaned up 1 empty switch in `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23275'.
Removing empty process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23274'.
Cleaned up 1 empty switch.

23.42.13.12. Executing OPT_EXPR pass (perform const folding).

23.42.14. Executing PROC pass (convert processes to netlists).

23.42.14.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23345'.
Cleaned up 1 empty switch.

23.42.14.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23346 in module $paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

23.42.14.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

23.42.14.4. Executing PROC_INIT pass (extract init attributes).

23.42.14.5. Executing PROC_ARST pass (detect async resets in processes).

23.42.14.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

23.42.14.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23370'.
Creating decoders for process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23346'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23344_EN[3:0]$23352
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23344_DATA[3:0]$23350
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23344_ADDR[3:0]$23351
Creating decoders for process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23345'.

23.42.14.8. Executing PROC_DLATCH pass (convert process syncs to latches).

23.42.14.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23334_EN' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23370'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.\i' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23370'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23329_EN' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23370'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23343_EN' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23370'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23339_EN' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23370'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23338_EN' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23370'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23337_EN' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23370'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23331_EN' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23370'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23341_EN' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23370'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23340_EN' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23370'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23335_EN' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23370'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23333_EN' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23370'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23332_EN' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23370'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23342_EN' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23370'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23336_EN' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23370'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23330_EN' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23370'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23328_EN' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23370'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23344_DATA' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23346'.
  created $dff cell `$procdff$23396' with positive edge clock.
Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23344_ADDR' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23346'.
  created $dff cell `$procdff$23397' with positive edge clock.
Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23344_EN' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23346'.
  created $dff cell `$procdff$23398' with positive edge clock.
Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.\muxwre' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23345'.
  created direct connection (no actual register cell created).

23.42.14.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

23.42.14.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23370'.
Found and cleaned up 1 empty switch in `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23346'.
Removing empty process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23345'.
Cleaned up 1 empty switch.

23.42.14.12. Executing OPT_EXPR pass (perform const folding).

23.42.15. Executing PROC pass (convert processes to netlists).

23.42.15.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23416'.
Cleaned up 1 empty switch.

23.42.15.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23417 in module $paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

23.42.15.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

23.42.15.4. Executing PROC_INIT pass (extract init attributes).

23.42.15.5. Executing PROC_ARST pass (detect async resets in processes).

23.42.15.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

23.42.15.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23441'.
Creating decoders for process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23417'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23415_EN[3:0]$23421
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23415_DATA[3:0]$23422
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23415_ADDR[3:0]$23423
Creating decoders for process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23416'.

23.42.15.8. Executing PROC_DLATCH pass (convert process syncs to latches).

23.42.15.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.\i' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23441'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23411_EN' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23441'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23410_EN' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23441'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23405_EN' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23441'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23404_EN' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23441'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23414_EN' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23441'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23413_EN' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23441'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23409_EN' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23441'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23408_EN' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23441'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23407_EN' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23441'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23403_EN' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23441'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23402_EN' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23441'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23401_EN' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23441'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23399_EN' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23441'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23412_EN' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23441'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23406_EN' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23441'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23400_EN' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23441'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23415_EN' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23417'.
  created $dff cell `$procdff$23467' with positive edge clock.
Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23415_DATA' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23417'.
  created $dff cell `$procdff$23468' with positive edge clock.
Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23415_ADDR' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23417'.
  created $dff cell `$procdff$23469' with positive edge clock.
Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.\muxwre' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23416'.
  created direct connection (no actual register cell created).

23.42.15.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

23.42.15.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23441'.
Found and cleaned up 1 empty switch in `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23417'.
Removing empty process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23416'.
Cleaned up 1 empty switch.

23.42.15.12. Executing OPT_EXPR pass (perform const folding).

23.42.16. Executing PROC pass (convert processes to netlists).

23.42.16.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23487'.
Cleaned up 1 empty switch.

23.42.16.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23488 in module $paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

23.42.16.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

23.42.16.4. Executing PROC_INIT pass (extract init attributes).

23.42.16.5. Executing PROC_ARST pass (detect async resets in processes).

23.42.16.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

23.42.16.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23512'.
Creating decoders for process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23488'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23486_EN[3:0]$23494
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23486_DATA[3:0]$23493
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23486_ADDR[3:0]$23492
Creating decoders for process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23487'.

23.42.16.8. Executing PROC_DLATCH pass (convert process syncs to latches).

23.42.16.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.\i' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23512'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23481_EN' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23512'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23480_EN' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23512'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23475_EN' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23512'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23485_EN' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23512'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23474_EN' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23512'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23484_EN' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23512'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23483_EN' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23512'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23479_EN' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23512'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23478_EN' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23512'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23477_EN' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23512'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23473_EN' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23512'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23472_EN' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23512'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23471_EN' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23512'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23470_EN' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23512'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23482_EN' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23512'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23476_EN' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23512'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23486_ADDR' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23488'.
  created $dff cell `$procdff$23538' with positive edge clock.
Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23486_DATA' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23488'.
  created $dff cell `$procdff$23539' with positive edge clock.
Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23486_EN' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23488'.
  created $dff cell `$procdff$23540' with positive edge clock.
Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.\muxwre' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23487'.
  created direct connection (no actual register cell created).

23.42.16.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

23.42.16.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23512'.
Found and cleaned up 1 empty switch in `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23488'.
Removing empty process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23487'.
Cleaned up 1 empty switch.

23.42.16.12. Executing OPT_EXPR pass (perform const folding).

23.42.17. Executing PROC pass (convert processes to netlists).

23.42.17.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23558'.
Cleaned up 1 empty switch.

23.42.17.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23559 in module $paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

23.42.17.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

23.42.17.4. Executing PROC_INIT pass (extract init attributes).

23.42.17.5. Executing PROC_ARST pass (detect async resets in processes).

23.42.17.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

23.42.17.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23583'.
Creating decoders for process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23559'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23557_EN[3:0]$23564
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23557_DATA[3:0]$23565
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23557_ADDR[3:0]$23563
Creating decoders for process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23558'.

23.42.17.8. Executing PROC_DLATCH pass (convert process syncs to latches).

23.42.17.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23556_EN' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23583'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23551_EN' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23583'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23550_EN' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23583'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23545_EN' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23583'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.\i' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23583'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23555_EN' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23583'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23544_EN' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23583'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23554_EN' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23583'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23553_EN' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23583'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23549_EN' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23583'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23548_EN' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23583'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23547_EN' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23583'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23543_EN' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23583'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23541_EN' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23583'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23542_EN' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23583'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23552_EN' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23583'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23546_EN' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23583'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23557_ADDR' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23559'.
  created $dff cell `$procdff$23609' with positive edge clock.
Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23557_EN' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23559'.
  created $dff cell `$procdff$23610' with positive edge clock.
Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23557_DATA' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23559'.
  created $dff cell `$procdff$23611' with positive edge clock.
Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.\muxwre' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23558'.
  created direct connection (no actual register cell created).

23.42.17.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

23.42.17.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23583'.
Found and cleaned up 1 empty switch in `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23559'.
Removing empty process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23558'.
Cleaned up 1 empty switch.

23.42.17.12. Executing OPT_EXPR pass (perform const folding).

23.42.18. Executing PROC pass (convert processes to netlists).

23.42.18.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23629'.
Cleaned up 1 empty switch.

23.42.18.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23630 in module $paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

23.42.18.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

23.42.18.4. Executing PROC_INIT pass (extract init attributes).

23.42.18.5. Executing PROC_ARST pass (detect async resets in processes).

23.42.18.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

23.42.18.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23654'.
Creating decoders for process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23630'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23628_EN[3:0]$23634
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23628_DATA[3:0]$23635
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23628_ADDR[3:0]$23636
Creating decoders for process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23629'.

23.42.18.8. Executing PROC_DLATCH pass (convert process syncs to latches).

23.42.18.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23613_EN' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23654'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23617_EN' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23654'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.\i' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23654'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23627_EN' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23654'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23626_EN' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23654'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23621_EN' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23654'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23620_EN' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23654'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23615_EN' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23654'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23625_EN' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23654'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23614_EN' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23654'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23624_EN' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23654'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23623_EN' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23654'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23619_EN' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23654'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23618_EN' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23654'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23612_EN' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23654'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23622_EN' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23654'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23616_EN' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23654'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23628_EN' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23630'.
  created $dff cell `$procdff$23680' with positive edge clock.
Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23628_DATA' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23630'.
  created $dff cell `$procdff$23681' with positive edge clock.
Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23628_ADDR' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23630'.
  created $dff cell `$procdff$23682' with positive edge clock.
Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.\muxwre' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23629'.
  created direct connection (no actual register cell created).

23.42.18.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

23.42.18.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23654'.
Found and cleaned up 1 empty switch in `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23630'.
Removing empty process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23629'.
Cleaned up 1 empty switch.

23.42.18.12. Executing OPT_EXPR pass (perform const folding).

23.42.19. Executing PROC pass (convert processes to netlists).

23.42.19.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23700'.
Cleaned up 1 empty switch.

23.42.19.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23701 in module $paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

23.42.19.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

23.42.19.4. Executing PROC_INIT pass (extract init attributes).

23.42.19.5. Executing PROC_ARST pass (detect async resets in processes).

23.42.19.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

23.42.19.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23725'.
Creating decoders for process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23701'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23699_EN[3:0]$23705
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23699_DATA[3:0]$23706
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23699_ADDR[3:0]$23707
Creating decoders for process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23700'.

23.42.19.8. Executing PROC_DLATCH pass (convert process syncs to latches).

23.42.19.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23697_EN' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23725'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23696_EN' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23725'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23691_EN' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23725'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23690_EN' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23725'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23685_EN' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23725'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23695_EN' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23725'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23684_EN' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23725'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23694_EN' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23725'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23693_EN' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23725'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23689_EN' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23725'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23688_EN' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23725'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23687_EN' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23725'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23683_EN' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23725'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.\i' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23725'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23698_EN' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23725'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23692_EN' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23725'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23686_EN' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23725'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23699_EN' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23701'.
  created $dff cell `$procdff$23751' with positive edge clock.
Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23699_DATA' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23701'.
  created $dff cell `$procdff$23752' with positive edge clock.
Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23699_ADDR' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23701'.
  created $dff cell `$procdff$23753' with positive edge clock.
Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.\muxwre' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23700'.
  created direct connection (no actual register cell created).

23.42.19.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

23.42.19.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23725'.
Found and cleaned up 1 empty switch in `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23701'.
Removing empty process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23700'.
Cleaned up 1 empty switch.

23.42.19.12. Executing OPT_EXPR pass (perform const folding).

23.42.20. Executing PROC pass (convert processes to netlists).

23.42.20.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23771'.
Cleaned up 1 empty switch.

23.42.20.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23772 in module $paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

23.42.20.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

23.42.20.4. Executing PROC_INIT pass (extract init attributes).

23.42.20.5. Executing PROC_ARST pass (detect async resets in processes).

23.42.20.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

23.42.20.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23796'.
Creating decoders for process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23772'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23770_EN[3:0]$23776
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23770_DATA[3:0]$23777
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23770_ADDR[3:0]$23778
Creating decoders for process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23771'.

23.42.20.8. Executing PROC_DLATCH pass (convert process syncs to latches).

23.42.20.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23763_EN' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23796'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23759_EN' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23796'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23758_EN' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23796'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.\i' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23796'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23767_EN' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23796'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23766_EN' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23796'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23761_EN' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23796'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23760_EN' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23796'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23755_EN' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23796'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23769_EN' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23796'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23765_EN' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23796'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23757_EN' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23796'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23764_EN' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23796'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23768_EN' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23796'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23762_EN' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23796'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23756_EN' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23796'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23754_EN' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23796'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23770_EN' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23772'.
  created $dff cell `$procdff$23822' with positive edge clock.
Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23770_DATA' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23772'.
  created $dff cell `$procdff$23823' with positive edge clock.
Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23770_ADDR' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23772'.
  created $dff cell `$procdff$23824' with positive edge clock.
Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.\muxwre' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23771'.
  created direct connection (no actual register cell created).

23.42.20.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

23.42.20.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23796'.
Found and cleaned up 1 empty switch in `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23772'.
Removing empty process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23771'.
Cleaned up 1 empty switch.

23.42.20.12. Executing OPT_EXPR pass (perform const folding).

23.42.21. Executing PROC pass (convert processes to netlists).

23.42.21.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23842'.
Cleaned up 1 empty switch.

23.42.21.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23843 in module $paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

23.42.21.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

23.42.21.4. Executing PROC_INIT pass (extract init attributes).

23.42.21.5. Executing PROC_ARST pass (detect async resets in processes).

23.42.21.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

23.42.21.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23867'.
Creating decoders for process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23843'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23841_EN[3:0]$23847
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23841_DATA[3:0]$23848
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23841_ADDR[3:0]$23849
Creating decoders for process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23842'.

23.42.21.8. Executing PROC_DLATCH pass (convert process syncs to latches).

23.42.21.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23836_EN' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23867'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23837_EN' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23867'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.\i' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23867'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23830_EN' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23867'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23840_EN' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23867'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23839_EN' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23867'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23835_EN' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23867'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23834_EN' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23867'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23833_EN' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23867'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23825_EN' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23867'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23829_EN' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23867'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23828_EN' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23867'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23827_EN' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23867'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23831_EN' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23867'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23838_EN' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23867'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23832_EN' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23867'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23826_EN' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23867'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23841_EN' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23843'.
  created $dff cell `$procdff$23893' with positive edge clock.
Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23841_DATA' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23843'.
  created $dff cell `$procdff$23894' with positive edge clock.
Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23841_ADDR' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23843'.
  created $dff cell `$procdff$23895' with positive edge clock.
Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.\muxwre' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23842'.
  created direct connection (no actual register cell created).

23.42.21.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

23.42.21.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23867'.
Found and cleaned up 1 empty switch in `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23843'.
Removing empty process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23842'.
Cleaned up 1 empty switch.

23.42.21.12. Executing OPT_EXPR pass (perform const folding).

23.42.22. Executing PROC pass (convert processes to netlists).

23.42.22.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23913'.
Cleaned up 1 empty switch.

23.42.22.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23914 in module $paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

23.42.22.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

23.42.22.4. Executing PROC_INIT pass (extract init attributes).

23.42.22.5. Executing PROC_ARST pass (detect async resets in processes).

23.42.22.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

23.42.22.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23938'.
Creating decoders for process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23914'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23912_EN[3:0]$23920
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23912_DATA[3:0]$23918
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23912_ADDR[3:0]$23919
Creating decoders for process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23913'.

23.42.22.8. Executing PROC_DLATCH pass (convert process syncs to latches).

23.42.22.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23896_EN' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23938'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23903_EN' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23938'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23897_EN' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23938'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.\i' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23938'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23900_EN' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23938'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23910_EN' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23938'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23909_EN' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23938'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23905_EN' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23938'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23907_EN' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23938'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23904_EN' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23938'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23906_EN' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23938'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23899_EN' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23938'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23898_EN' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23938'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23901_EN' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23938'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23911_EN' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23938'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23908_EN' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23938'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23902_EN' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23938'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23912_DATA' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23914'.
  created $dff cell `$procdff$23964' with positive edge clock.
Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23912_ADDR' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23914'.
  created $dff cell `$procdff$23965' with positive edge clock.
Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23912_EN' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23914'.
  created $dff cell `$procdff$23966' with positive edge clock.
Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.\muxwre' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23913'.
  created direct connection (no actual register cell created).

23.42.22.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

23.42.22.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23938'.
Found and cleaned up 1 empty switch in `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23914'.
Removing empty process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23913'.
Cleaned up 1 empty switch.

23.42.22.12. Executing OPT_EXPR pass (perform const folding).

23.42.23. Executing PROC pass (convert processes to netlists).

23.42.23.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23984'.
Cleaned up 1 empty switch.

23.42.23.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23985 in module $paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

23.42.23.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

23.42.23.4. Executing PROC_INIT pass (extract init attributes).

23.42.23.5. Executing PROC_ARST pass (detect async resets in processes).

23.42.23.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

23.42.23.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24009'.
Creating decoders for process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23985'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23983_EN[3:0]$23990
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23983_DATA[3:0]$23991
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23983_ADDR[3:0]$23989
Creating decoders for process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23984'.

23.42.23.8. Executing PROC_DLATCH pass (convert process syncs to latches).

23.42.23.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.\i' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24009'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23982_EN' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24009'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23977_EN' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24009'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23976_EN' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24009'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23971_EN' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24009'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23981_EN' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24009'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23970_EN' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24009'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23980_EN' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24009'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23979_EN' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24009'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23975_EN' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24009'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23974_EN' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24009'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23973_EN' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24009'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23969_EN' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24009'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23968_EN' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24009'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23967_EN' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24009'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23978_EN' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24009'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23972_EN' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24009'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23983_ADDR' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23985'.
  created $dff cell `$procdff$24035' with positive edge clock.
Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23983_EN' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23985'.
  created $dff cell `$procdff$24036' with positive edge clock.
Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23983_DATA' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23985'.
  created $dff cell `$procdff$24037' with positive edge clock.
Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.\muxwre' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23984'.
  created direct connection (no actual register cell created).

23.42.23.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

23.42.23.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24009'.
Found and cleaned up 1 empty switch in `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23985'.
Removing empty process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23984'.
Cleaned up 1 empty switch.

23.42.23.12. Executing OPT_EXPR pass (perform const folding).

23.42.24. Executing PROC pass (convert processes to netlists).

23.42.24.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24055'.
Cleaned up 1 empty switch.

23.42.24.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24056 in module $paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

23.42.24.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

23.42.24.4. Executing PROC_INIT pass (extract init attributes).

23.42.24.5. Executing PROC_ARST pass (detect async resets in processes).

23.42.24.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

23.42.24.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24080'.
Creating decoders for process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24056'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24054_EN[3:0]$24060
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24054_DATA[3:0]$24061
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24054_ADDR[3:0]$24062
Creating decoders for process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24055'.

23.42.24.8. Executing PROC_DLATCH pass (convert process syncs to latches).

23.42.24.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.\i' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24080'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24053_EN' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24080'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24052_EN' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24080'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24047_EN' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24080'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24046_EN' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24080'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24041_EN' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24080'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24051_EN' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24080'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24040_EN' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24080'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24050_EN' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24080'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24049_EN' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24080'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24045_EN' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24080'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24044_EN' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24080'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24043_EN' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24080'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24039_EN' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24080'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24038_EN' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24080'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24048_EN' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24080'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24042_EN' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24080'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24054_EN' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24056'.
  created $dff cell `$procdff$24106' with positive edge clock.
Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24054_DATA' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24056'.
  created $dff cell `$procdff$24107' with positive edge clock.
Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24054_ADDR' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24056'.
  created $dff cell `$procdff$24108' with positive edge clock.
Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.\muxwre' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24055'.
  created direct connection (no actual register cell created).

23.42.24.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

23.42.24.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24080'.
Found and cleaned up 1 empty switch in `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24056'.
Removing empty process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24055'.
Cleaned up 1 empty switch.

23.42.24.12. Executing OPT_EXPR pass (perform const folding).

23.42.25. Executing PROC pass (convert processes to netlists).

23.42.25.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24126'.
Cleaned up 1 empty switch.

23.42.25.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24127 in module $paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

23.42.25.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

23.42.25.4. Executing PROC_INIT pass (extract init attributes).

23.42.25.5. Executing PROC_ARST pass (detect async resets in processes).

23.42.25.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

23.42.25.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24151'.
Creating decoders for process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24127'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24125_EN[3:0]$24133
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24125_DATA[3:0]$24132
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24125_ADDR[3:0]$24131
Creating decoders for process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24126'.

23.42.25.8. Executing PROC_DLATCH pass (convert process syncs to latches).

23.42.25.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.\i' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24151'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24109_EN' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24151'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24119_EN' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24151'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24120_EN' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24151'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24110_EN' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24151'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24121_EN' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24151'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24117_EN' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24151'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24114_EN' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24151'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24111_EN' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24151'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24123_EN' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24151'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24122_EN' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24151'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24116_EN' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24151'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24115_EN' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24151'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24113_EN' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24151'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24124_EN' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24151'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24118_EN' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24151'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24112_EN' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24151'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24125_ADDR' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24127'.
  created $dff cell `$procdff$24177' with positive edge clock.
Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24125_DATA' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24127'.
  created $dff cell `$procdff$24178' with positive edge clock.
Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24125_EN' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24127'.
  created $dff cell `$procdff$24179' with positive edge clock.
Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.\muxwre' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24126'.
  created direct connection (no actual register cell created).

23.42.25.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

23.42.25.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24151'.
Found and cleaned up 1 empty switch in `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24127'.
Removing empty process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24126'.
Cleaned up 1 empty switch.

23.42.25.12. Executing OPT_EXPR pass (perform const folding).

23.42.26. Executing PROC pass (convert processes to netlists).

23.42.26.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24197'.
Cleaned up 1 empty switch.

23.42.26.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24198 in module $paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

23.42.26.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

23.42.26.4. Executing PROC_INIT pass (extract init attributes).

23.42.26.5. Executing PROC_ARST pass (detect async resets in processes).

23.42.26.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

23.42.26.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24222'.
Creating decoders for process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24198'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24196_EN[3:0]$24203
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24196_DATA[3:0]$24204
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24196_ADDR[3:0]$24202
Creating decoders for process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24197'.

23.42.26.8. Executing PROC_DLATCH pass (convert process syncs to latches).

23.42.26.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24189_EN' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24222'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24193_EN' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24222'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24184_EN' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24222'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24183_EN' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24222'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24194_EN' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24222'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24190_EN' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24222'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24195_EN' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24222'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.\i' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24222'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24181_EN' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24222'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24182_EN' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24222'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24186_EN' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24222'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24187_EN' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24222'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24188_EN' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24222'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24192_EN' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24222'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24180_EN' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24222'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24191_EN' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24222'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24185_EN' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24222'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24196_ADDR' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24198'.
  created $dff cell `$procdff$24248' with positive edge clock.
Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24196_EN' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24198'.
  created $dff cell `$procdff$24249' with positive edge clock.
Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24196_DATA' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24198'.
  created $dff cell `$procdff$24250' with positive edge clock.
Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.\muxwre' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24197'.
  created direct connection (no actual register cell created).

23.42.26.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

23.42.26.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24222'.
Found and cleaned up 1 empty switch in `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24198'.
Removing empty process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24197'.
Cleaned up 1 empty switch.

23.42.26.12. Executing OPT_EXPR pass (perform const folding).

23.42.27. Executing PROC pass (convert processes to netlists).

23.42.27.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24268'.
Cleaned up 1 empty switch.

23.42.27.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24269 in module $paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

23.42.27.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

23.42.27.4. Executing PROC_INIT pass (extract init attributes).

23.42.27.5. Executing PROC_ARST pass (detect async resets in processes).

23.42.27.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

23.42.27.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24293'.
Creating decoders for process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24269'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24267_EN[3:0]$24274
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24267_DATA[3:0]$24275
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24267_ADDR[3:0]$24273
Creating decoders for process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24268'.

23.42.27.8. Executing PROC_DLATCH pass (convert process syncs to latches).

23.42.27.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24255_EN' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24293'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24259_EN' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24293'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24263_EN' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24293'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24261_EN' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24293'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.\i' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24293'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24254_EN' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24293'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24260_EN' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24293'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24253_EN' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24293'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24251_EN' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24293'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24262_EN' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24293'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24257_EN' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24293'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24256_EN' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24293'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24266_EN' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24293'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24265_EN' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24293'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24264_EN' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24293'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24258_EN' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24293'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24252_EN' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24293'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24267_ADDR' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24269'.
  created $dff cell `$procdff$24319' with positive edge clock.
Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24267_EN' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24269'.
  created $dff cell `$procdff$24320' with positive edge clock.
Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24267_DATA' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24269'.
  created $dff cell `$procdff$24321' with positive edge clock.
Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.\muxwre' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24268'.
  created direct connection (no actual register cell created).

23.42.27.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

23.42.27.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24293'.
Found and cleaned up 1 empty switch in `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24269'.
Removing empty process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24268'.
Cleaned up 1 empty switch.

23.42.27.12. Executing OPT_EXPR pass (perform const folding).

23.42.28. Executing PROC pass (convert processes to netlists).

23.42.28.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24339'.
Cleaned up 1 empty switch.

23.42.28.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24340 in module $paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

23.42.28.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

23.42.28.4. Executing PROC_INIT pass (extract init attributes).

23.42.28.5. Executing PROC_ARST pass (detect async resets in processes).

23.42.28.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

23.42.28.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24364'.
Creating decoders for process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24340'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24338_EN[3:0]$24346
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24338_DATA[3:0]$24345
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24338_ADDR[3:0]$24344
Creating decoders for process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24339'.

23.42.28.8. Executing PROC_DLATCH pass (convert process syncs to latches).

23.42.28.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24322_EN' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24364'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.\i' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24364'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24333_EN' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24364'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24327_EN' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24364'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24328_EN' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24364'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24329_EN' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24364'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24330_EN' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24364'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24331_EN' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24364'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24323_EN' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24364'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24324_EN' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24364'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24326_EN' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24364'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24334_EN' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24364'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24335_EN' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24364'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24325_EN' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24364'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24336_EN' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24364'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24337_EN' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24364'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24332_EN' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24364'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24338_ADDR' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24340'.
  created $dff cell `$procdff$24390' with positive edge clock.
Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24338_DATA' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24340'.
  created $dff cell `$procdff$24391' with positive edge clock.
Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24338_EN' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24340'.
  created $dff cell `$procdff$24392' with positive edge clock.
Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.\muxwre' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24339'.
  created direct connection (no actual register cell created).

23.42.28.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

23.42.28.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24364'.
Found and cleaned up 1 empty switch in `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24340'.
Removing empty process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24339'.
Cleaned up 1 empty switch.

23.42.28.12. Executing OPT_EXPR pass (perform const folding).

23.42.29. Executing SCC pass (detecting logic loops).
Found an SCC: $techmap$auto$ff.cc:266:slice$8117.$auto$simplemap.cc:267:simplemap_mux$22462
Found an SCC: $techmap$auto$ff.cc:266:slice$8116.$auto$simplemap.cc:267:simplemap_mux$22462
Found an SCC: $techmap$auto$ff.cc:266:slice$8115.$auto$simplemap.cc:267:simplemap_mux$22462
Found an SCC: $techmap$auto$ff.cc:266:slice$8114.$auto$simplemap.cc:267:simplemap_mux$22462
Found an SCC: $auto$opt_expr.cc:613:replace_const_cells$21633 $auto$ff.cc:266:slice$5132 $auto$simplemap.cc:126:simplemap_reduce$5258 $auto$simplemap.cc:126:simplemap_reduce$5243 $auto$ff.cc:266:slice$5133 $auto$ff.cc:266:slice$5134 $auto$opt_expr.cc:613:replace_const_cells$21601 $auto$simplemap.cc:267:simplemap_mux$14861 $auto$simplemap.cc:126:simplemap_reduce$14879 $auto$simplemap.cc:126:simplemap_reduce$14876 $auto$simplemap.cc:75:simplemap_bitop$14862 $auto$simplemap.cc:267:simplemap_mux$5224 $auto$simplemap.cc:225:simplemap_logbin$5233 $auto$simplemap.cc:196:simplemap_lognot$5248 $auto$simplemap.cc:126:simplemap_reduce$5246 $auto$simplemap.cc:126:simplemap_reduce$5244 $auto$simplemap.cc:196:simplemap_lognot$5263 $auto$simplemap.cc:126:simplemap_reduce$5261 $auto$simplemap.cc:126:simplemap_reduce$5259 $auto$opt_expr.cc:613:replace_const_cells$21585 $auto$ff.cc:266:slice$5135 $auto$simplemap.cc:126:simplemap_reduce$4131 $auto$simplemap.cc:126:simplemap_reduce$4129 $auto$simplemap.cc:225:simplemap_logbin$5183 $auto$simplemap.cc:196:simplemap_lognot$5193 $auto$simplemap.cc:126:simplemap_reduce$5191 $auto$opt_expr.cc:613:replace_const_cells$21603 $auto$simplemap.cc:267:simplemap_mux$14860 $auto$simplemap.cc:126:simplemap_reduce$14874 $auto$simplemap.cc:126:simplemap_reduce$14871 $auto$simplemap.cc:75:simplemap_bitop$14864
Found an SCC: $auto$simplemap.cc:126:simplemap_reduce$4351 $auto$simplemap.cc:38:simplemap_not$4006 $auto$simplemap.cc:38:simplemap_not$14843 $auto$ff.cc:266:slice$3602 $auto$ff.cc:479:convert_ce_over_srst$21717 $auto$ff.cc:266:slice$3603 $auto$ff.cc:479:convert_ce_over_srst$21719 $auto$simplemap.cc:126:simplemap_reduce$4012 $auto$ff.cc:266:slice$3601 $auto$ff.cc:479:convert_ce_over_srst$21715 $auto$simplemap.cc:38:simplemap_not$14841 $auto$ff.cc:266:slice$3600 $auto$ff.cc:479:convert_ce_over_srst$21713 $auto$simplemap.cc:126:simplemap_reduce$4015 $auto$simplemap.cc:126:simplemap_reduce$4011 $auto$simplemap.cc:38:simplemap_not$14840 $auto$alumacc.cc:485:replace_alu$2501.slice[2].ccu2c_i $auto$alumacc.cc:485:replace_alu$2501.slice[0].ccu2c_i $auto$ff.cc:266:slice$3599 $auto$ff.cc:479:convert_ce_over_srst$21711 $auto$simplemap.cc:126:simplemap_reduce$4252 $auto$simplemap.cc:75:simplemap_bitop$4009 $auto$simplemap.cc:38:simplemap_not$3965 $auto$alumacc.cc:485:replace_alu$2501.slice[4].ccu2c_i $auto$ff.cc:266:slice$3604 $auto$ff.cc:479:convert_ce_over_srst$21721 $auto$simplemap.cc:126:simplemap_reduce$4237 $auto$simplemap.cc:126:simplemap_reduce$4353 $auto$simplemap.cc:126:simplemap_reduce$4350 $auto$simplemap.cc:126:simplemap_reduce$4017 $auto$simplemap.cc:126:simplemap_reduce$4013 $auto$simplemap.cc:38:simplemap_not$20244
Found an SCC: $auto$ff.cc:266:slice$5136 $auto$simplemap.cc:126:simplemap_reduce$5282 $auto$ff.cc:266:slice$5137 $auto$simplemap.cc:38:simplemap_not$14756 $auto$ff.cc:266:slice$5138 $auto$ff.cc:266:slice$5139 $auto$ff.cc:266:slice$5140 $auto$simplemap.cc:126:simplemap_reduce$5284 $auto$simplemap.cc:38:simplemap_not$14759 $auto$ff.cc:266:slice$5141 $auto$ff.cc:266:slice$5142 $auto$simplemap.cc:126:simplemap_reduce$5290 $auto$simplemap.cc:126:simplemap_reduce$5285 $auto$ff.cc:266:slice$5143 $auto$ff.cc:266:slice$5144 $auto$simplemap.cc:126:simplemap_reduce$5286 $auto$simplemap.cc:38:simplemap_not$14763 $auto$ff.cc:266:slice$5145 $auto$ff.cc:266:slice$5146 $auto$simplemap.cc:126:simplemap_reduce$5291 $auto$simplemap.cc:126:simplemap_reduce$5287 $auto$simplemap.cc:38:simplemap_not$14765 $auto$ff.cc:266:slice$5147 $auto$simplemap.cc:126:simplemap_reduce$5294 $auto$ff.cc:266:slice$5148 $auto$simplemap.cc:126:simplemap_reduce$4158 $auto$simplemap.cc:196:simplemap_lognot$5298 $auto$simplemap.cc:126:simplemap_reduce$5296 $auto$simplemap.cc:126:simplemap_reduce$5293 $auto$simplemap.cc:126:simplemap_reduce$5289 $auto$simplemap.cc:126:simplemap_reduce$5283 $auto$simplemap.cc:38:simplemap_not$14757
Found an SCC: $auto$simplemap.cc:38:simplemap_not$4614 $auto$ff.cc:266:slice$4719 $auto$simplemap.cc:126:simplemap_reduce$4468 $auto$simplemap.cc:225:simplemap_logbin$4624
Found an SCC: $auto$ff.cc:266:slice$4965 $auto$simplemap.cc:126:simplemap_reduce$5110 $auto$simplemap.cc:126:simplemap_reduce$5075 $auto$simplemap.cc:38:simplemap_not$15709 $auto$ff.cc:266:slice$4966 $auto$simplemap.cc:38:simplemap_not$15710 $auto$ff.cc:266:slice$4967 $auto$simplemap.cc:126:simplemap_reduce$5082 $auto$simplemap.cc:126:simplemap_reduce$5076 $auto$simplemap.cc:126:simplemap_reduce$5117 $auto$simplemap.cc:126:simplemap_reduce$5111 $auto$simplemap.cc:38:simplemap_not$15711 $auto$ff.cc:266:slice$4968 $auto$simplemap.cc:38:simplemap_not$15712 $auto$ff.cc:266:slice$4969 $auto$simplemap.cc:126:simplemap_reduce$5112 $auto$simplemap.cc:38:simplemap_not$15713 $auto$ff.cc:266:slice$4970 $auto$ff.cc:266:slice$4971 $auto$simplemap.cc:126:simplemap_reduce$5121 $auto$simplemap.cc:126:simplemap_reduce$5118 $auto$simplemap.cc:126:simplemap_reduce$5113 $auto$ff.cc:266:slice$4972 $auto$simplemap.cc:38:simplemap_not$15716 $auto$ff.cc:266:slice$4973 $auto$simplemap.cc:126:simplemap_reduce$5079 $auto$simplemap.cc:126:simplemap_reduce$5114 $auto$simplemap.cc:38:simplemap_not$15717 $auto$ff.cc:266:slice$4974 $auto$simplemap.cc:38:simplemap_not$15718 $auto$ff.cc:266:slice$4975 $auto$simplemap.cc:126:simplemap_reduce$5084 $auto$simplemap.cc:126:simplemap_reduce$5080 $auto$simplemap.cc:126:simplemap_reduce$5119 $auto$simplemap.cc:126:simplemap_reduce$5115 $auto$simplemap.cc:38:simplemap_not$15719 $auto$ff.cc:266:slice$4976 $auto$simplemap.cc:196:simplemap_lognot$5126 $auto$simplemap.cc:126:simplemap_reduce$5124 $auto$simplemap.cc:126:simplemap_reduce$5122 $auto$simplemap.cc:126:simplemap_reduce$5087 $auto$ff.cc:266:slice$4977 $auto$simplemap.cc:167:logic_reduce$4110 $auto$simplemap.cc:225:simplemap_logbin$5055 $auto$simplemap.cc:225:simplemap_logbin$5056 $auto$simplemap.cc:196:simplemap_lognot$5091 $auto$simplemap.cc:126:simplemap_reduce$5089 $auto$simplemap.cc:126:simplemap_reduce$5086 $auto$simplemap.cc:126:simplemap_reduce$5083 $auto$simplemap.cc:126:simplemap_reduce$5077
Found 9 SCCs in module top.
Found 9 SCCs.

23.42.30. Executing ABC9_OPS pass (helper functions for ABC9).

23.42.31. Executing PROC pass (convert processes to netlists).

23.42.31.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

23.42.31.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

23.42.31.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 0 assignments to connections.

23.42.31.4. Executing PROC_INIT pass (extract init attributes).

23.42.31.5. Executing PROC_ARST pass (detect async resets in processes).

23.42.31.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

23.42.31.7. Executing PROC_MUX pass (convert decision trees to multiplexers).

23.42.31.8. Executing PROC_DLATCH pass (convert process syncs to latches).

23.42.31.9. Executing PROC_DFF pass (convert process syncs to FFs).

23.42.31.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

23.42.31.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

23.42.31.12. Executing OPT_EXPR pass (perform const folding).

23.42.32. Executing TECHMAP pass (map to technology primitives).

23.42.32.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/techmap.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

23.42.32.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~212 debug messages>

23.42.33. Executing OPT pass (performing simple optimizations).

23.42.33.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.
Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Optimizing module $paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.
Optimizing module $paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.
Optimizing module $paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.
Optimizing module $paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.
Optimizing module $paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.
Optimizing module $paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.
Optimizing module $paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.
Optimizing module $paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.
Optimizing module $paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.
Optimizing module $paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.
Optimizing module $paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.
Optimizing module $paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.
Optimizing module $paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.
Optimizing module $paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.
Optimizing module $paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.
Optimizing module $paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.
Optimizing module $paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.
Optimizing module $paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.
Optimizing module $paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.
Optimizing module $paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.
Optimizing module $paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.
Optimizing module $paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.
Optimizing module $paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.
Optimizing module $paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.

23.42.33.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4'.
Removed a total of 0 cells.

23.42.33.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

23.42.33.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.
Performed a total of 0 changes.

23.42.33.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4'.
Removed a total of 0 cells.

23.42.33.6. Executing OPT_DFF pass (perform DFF optimizations).

23.42.33.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4..

23.42.33.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module $paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.
Optimizing module $paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.
Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Optimizing module $paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.
Optimizing module $paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.
Optimizing module $paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.
Optimizing module $paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.
Optimizing module $paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.
Optimizing module $paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.
Optimizing module $paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.
Optimizing module $paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.
Optimizing module $paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.
Optimizing module $paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.
Optimizing module $paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.
Optimizing module $paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.
Optimizing module $paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.
Optimizing module $paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.
Optimizing module $paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.
Optimizing module $paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.
Optimizing module $paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.
Optimizing module $paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.
Optimizing module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.
Optimizing module $paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.
Optimizing module $paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.
Optimizing module $paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.
Optimizing module $paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.

23.42.33.9. Finished OPT passes. (There is nothing left to do.)

23.42.34. Executing TECHMAP pass (map to technology primitives).

23.42.34.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/abc9_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/abc9_map.v' to AST representation.
Successfully finished Verilog frontend.

23.42.34.2. Continuing TECHMAP pass.
Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Using template $paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4 for cells of type $paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.
Using template $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4 for cells of type $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.
Using template $paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4 for cells of type $paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.
Using template $paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4 for cells of type $paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.
Using template $paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4 for cells of type $paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.
Using template $paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4 for cells of type $paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.
Using template $paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4 for cells of type $paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.
Using template $paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4 for cells of type $paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.
Using template $paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4 for cells of type $paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.
Using template $paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4 for cells of type $paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.
Using template $paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4 for cells of type $paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.
Using template $paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4 for cells of type $paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.
Using template $paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4 for cells of type $paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.
Using template $paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4 for cells of type $paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.
Using template $paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4 for cells of type $paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.
Using template $paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4 for cells of type $paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.
Using template $paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4 for cells of type $paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.
Using template $paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4 for cells of type $paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.
Using template $paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4 for cells of type $paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.
Using template $paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4 for cells of type $paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.
Using template $paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4 for cells of type $paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.
Using template $paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4 for cells of type $paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.
Using template $paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4 for cells of type $paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.
Using template $paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4 for cells of type $paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.
Using template $paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4 for cells of type $paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.
No more expansions possible.
<suppressed ~320 debug messages>

23.42.35. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/abc9_model.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/abc9_model.v' to AST representation.
Generating RTLIL representation for module `$__ABC9_DELAY'.
Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'.
Generating RTLIL representation for module `$__DFF_N__$abc9_flop'.
Generating RTLIL representation for module `$__DFF_P__$abc9_flop'.
Successfully finished Verilog frontend.

23.42.36. Executing ABC9_OPS pass (helper functions for ABC9).
<suppressed ~2 debug messages>

23.42.37. Executing ABC9_OPS pass (helper functions for ABC9).

23.42.38. Executing ABC9_OPS pass (helper functions for ABC9).
<suppressed ~2 debug messages>

23.42.39. Executing TECHMAP pass (map to technology primitives).

23.42.39.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/techmap.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

23.42.39.2. Continuing TECHMAP pass.
Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C.
Using extmapper simplemap for cells of type $or.
Using extmapper simplemap for cells of type $and.
Using extmapper simplemap for cells of type $not.
Using extmapper simplemap for cells of type $xor.
Using template $paramod\LUT2\INIT=4'1010 for cells of type LUT2.
Using template $paramod\LUT4\INIT=16'1001011010101010 for cells of type LUT4.
Using extmapper simplemap for cells of type $mux.
No more expansions possible.
<suppressed ~251 debug messages>

23.42.40. Executing OPT pass (performing simple optimizations).

23.42.40.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~18 debug messages>

23.42.40.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~6 debug messages>
Removed a total of 2 cells.

23.42.40.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

23.42.40.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

23.42.40.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

23.42.40.6. Executing OPT_DFF pass (perform DFF optimizations).

23.42.40.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 55 unused wires.
<suppressed ~1 debug messages>

23.42.40.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

23.42.40.9. Rerunning OPT passes. (Maybe there is more to do..)

23.42.40.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

23.42.40.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

23.42.40.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

23.42.40.13. Executing OPT_DFF pass (perform DFF optimizations).

23.42.40.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

23.42.40.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

23.42.40.16. Finished OPT passes. (There is nothing left to do.)

23.42.41. Executing AIGMAP pass (map logic to AIG).
Module top: replaced 18 cells with 120 new cells, skipped 39 cells.
  replaced 3 cell types:
       2 $_OR_
       2 $_XOR_
      14 $_MUX_
  not replaced 3 cell types:
      31 $specify2
       4 $_NOT_
       4 $_AND_

23.42.42. Executing AIGMAP pass (map logic to AIG).
Module top: replaced 3999 cells with 23955 new cells, skipped 3368 cells.
  replaced 3 cell types:
    1346 $_OR_
      94 $_XOR_
    2559 $_MUX_
  not replaced 59 cell types:
      30 $scopeinfo
     363 $_NOT_
    1260 $_AND_
       6 $_TBUF_
       1 $paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4
       1 $paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4
       1 $paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4
       1 $paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4
     732 TRELLIS_FF
       1 $paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4
       1 $paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4
       1 $paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4
       1 $paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4
       1 $paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4
       1 $paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4
       1 $paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4
       1 $paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4
       1 $paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4
       1 $paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4
      16 $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4
      16 $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4
       1 $paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4
     252 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4
       1 $paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4
       1 $paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4
       1 $paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4
       1 $paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4
       1 $paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4
       1 $paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4
       1 $paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4
       1 $paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4
       1 $paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4_$abc9_byp
     252 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4_$abc9_byp
     392 $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C
       1 $paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4_$abc9_byp
       1 $__ABC9_SCC_BREAKER
       1 $paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4_$abc9_byp

23.42.42.1. Executing ABC9_OPS pass (helper functions for ABC9).

23.42.42.2. Executing ABC9_OPS pass (helper functions for ABC9).

23.42.42.3. Executing XAIGER backend.
<suppressed ~11 debug messages>
Extracted 10565 AND gates and 30512 wires from module `top' to a netlist network with 1918 inputs and 766 outputs.

23.42.42.4. Executing ABC9_EXE pass (technology mapping using ABC9).

23.42.42.5. Executing ABC9.
Running ABC command: "<yosys-exe-dir>/yosys-abc" -s -f <abc-temp-dir>/abc.script 2>&1
ABC: ABC command line: "source <abc-temp-dir>/abc.script".
ABC: 
ABC: + read_lut <abc-temp-dir>/input.lut 
ABC: + read_box <abc-temp-dir>/input.box 
ABC: + &read <abc-temp-dir>/input.xaig 
ABC: + &ps 
ABC: <abc-temp-dir>/input : i/o =   1918/    766  and =    9154  lev =   46 (5.11)  mem = 0.27 MB  box = 684  bb = 292
ABC: + &scorr 
ABC: Warning: The network is combinational.
ABC: + &sweep 
ABC: + &dc2 
ABC: + &dch -f 
ABC: + &ps 
ABC: <abc-temp-dir>/input : i/o =   1918/    766  and =   11975  lev =   62 (3.11)  mem = 0.30 MB  ch = 1318  box = 637  bb = 292
ABC: + &if -W 300 -v 
ABC: K = 7. Memory (bytes): Truth =    0. Cut =   60. Obj =  140. Set =  636. CutMin = no
ABC: Node =   11975.  Ch =  1145.  Total mem =    3.32 MB. Peak cut mem =    0.25 MB.
ABC: P:  Del = 6847.00.  Ar =   11642.0.  Edge =    14127.  Cut =   173001.  T =     0.04 sec
ABC: P:  Del = 6807.00.  Ar =   11934.0.  Edge =    14255.  Cut =   167805.  T =     0.04 sec
ABC: P:  Del = 6807.00.  Ar =    6980.0.  Edge =    12983.  Cut =   364445.  T =     0.08 sec
ABC: F:  Del = 6807.00.  Ar =    4729.0.  Edge =    11390.  Cut =   325328.  T =     0.08 sec
ABC: A:  Del = 6807.00.  Ar =    4073.0.  Edge =     9941.  Cut =   294943.  T =     0.11 sec
ABC: A:  Del = 6807.00.  Ar =    4011.0.  Edge =     9883.  Cut =   288586.  T =     0.11 sec
ABC: Total time =     0.48 sec
ABC: + &write -n <abc-temp-dir>/output.aig 
ABC: + &mfs 
ABC: + &ps -l 
ABC: <abc-temp-dir>/input : i/o =   1918/    766  and =    8496  lev =   40 (3.33)  mem = 0.26 MB  box = 637  bb = 292
ABC: Mapping (K=7)  :  lut =   2504  edge =    9807  lev =   14 (1.39)  levB =   41  mem = 0.13 MB
ABC: LUT = 2504 : 2=253 10.1 %  3=589 23.5 %  4=1118 44.6 %  5=326 13.0 %  6=94 3.8 %  7=124 5.0 %  Ave = 3.92
ABC: + &write -n <abc-temp-dir>/output.aig 
ABC: + time 
ABC: elapse: 5.56 seconds, total: 5.56 seconds

23.42.42.6. Executing AIGER frontend.
<suppressed ~5427 debug messages>
Removed 11772 unused cells and 23544 unused wires.

23.42.42.7. Executing ABC9_OPS pass (helper functions for ABC9).
ABC RESULTS:              $lut cells:     2530
ABC RESULTS:   $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4_$abc9_byp cells:       16
ABC RESULTS:   $paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp cells:      252
ABC RESULTS:   $paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C cells:      345
ABC RESULTS:   $paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:           input signals:      341
ABC RESULTS:          output signals:      137
Removing temp directory.

23.42.43. Executing TECHMAP pass (map to technology primitives).

23.42.43.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/abc9_unmap.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/abc9_unmap.v' to AST representation.
Generating RTLIL representation for module `\$__DFF_x__$abc9_flop'.
Generating RTLIL representation for module `\$__ABC9_SCC_BREAKER'.
Successfully finished Verilog frontend.

23.42.43.2. Continuing TECHMAP pass.
Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C.
Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4 for cells of type $paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.
Using template $paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4 for cells of type $paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.
Using template $paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4 for cells of type $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.
Using template $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4 for cells of type $paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.
Using template $paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4 for cells of type $paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.
Using template $paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4 for cells of type $paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.
Using template $paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4 for cells of type $paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.
Using template $paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4 for cells of type $paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.
Using template $paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4 for cells of type $paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.
Using template $paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4 for cells of type $paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.
Using template $paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4 for cells of type $paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.
Using template $paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4 for cells of type $paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.
Using template $paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4 for cells of type $paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.
Using template $paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4 for cells of type $paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.
Using template $paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4 for cells of type $paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.
Using template $paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4 for cells of type $paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.
Using template $paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4 for cells of type $paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.
Using template $paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4 for cells of type $paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.
Using template $paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4 for cells of type $paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.
Using template $paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4 for cells of type $paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.
Using template $paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4 for cells of type $paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.
Using template $paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4 for cells of type $paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.
Using template $paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4 for cells of type $paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.
Using template $paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4 for cells of type $paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.
Using template $paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4 for cells of type $paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.
Using template $paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod\$__ABC9_SCC_BREAKER\WIDTH=32'00000000000000000000000000001001 for cells of type $__ABC9_SCC_BREAKER.
No more expansions possible.
<suppressed ~999 debug messages>
Removed 320 unused cells and 36958 unused wires.

23.43. Executing TECHMAP pass (map to technology primitives).

23.43.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v' to AST representation.
Generating RTLIL representation for module `\$_DFF_N_'.
Generating RTLIL representation for module `\$_DFF_P_'.
Generating RTLIL representation for module `\$_DFFE_NN_'.
Generating RTLIL representation for module `\$_DFFE_PN_'.
Generating RTLIL representation for module `\$_DFFE_NP_'.
Generating RTLIL representation for module `\$_DFFE_PP_'.
Generating RTLIL representation for module `\$_DFF_NP0_'.
Generating RTLIL representation for module `\$_DFF_NP1_'.
Generating RTLIL representation for module `\$_DFF_PP0_'.
Generating RTLIL representation for module `\$_DFF_PP1_'.
Generating RTLIL representation for module `\$_SDFF_NP0_'.
Generating RTLIL representation for module `\$_SDFF_NP1_'.
Generating RTLIL representation for module `\$_SDFF_PP0_'.
Generating RTLIL representation for module `\$_SDFF_PP1_'.
Generating RTLIL representation for module `\$_DFFE_NP0P_'.
Generating RTLIL representation for module `\$_DFFE_NP1P_'.
Generating RTLIL representation for module `\$_DFFE_PP0P_'.
Generating RTLIL representation for module `\$_DFFE_PP1P_'.
Generating RTLIL representation for module `\$_DFFE_NP0N_'.
Generating RTLIL representation for module `\$_DFFE_NP1N_'.
Generating RTLIL representation for module `\$_DFFE_PP0N_'.
Generating RTLIL representation for module `\$_DFFE_PP1N_'.
Generating RTLIL representation for module `\$_SDFFE_NP0P_'.
Generating RTLIL representation for module `\$_SDFFE_NP1P_'.
Generating RTLIL representation for module `\$_SDFFE_PP0P_'.
Generating RTLIL representation for module `\$_SDFFE_PP1P_'.
Generating RTLIL representation for module `\$_SDFFE_NP0N_'.
Generating RTLIL representation for module `\$_SDFFE_NP1N_'.
Generating RTLIL representation for module `\$_SDFFE_PP0N_'.
Generating RTLIL representation for module `\$_SDFFE_PP1N_'.
Generating RTLIL representation for module `\$_ALDFF_NP_'.
Generating RTLIL representation for module `\$_ALDFF_PP_'.
Generating RTLIL representation for module `\$_ALDFFE_NPN_'.
Generating RTLIL representation for module `\$_ALDFFE_NPP_'.
Generating RTLIL representation for module `\$_ALDFFE_PPN_'.
Generating RTLIL representation for module `\$_ALDFFE_PPP_'.
Generating RTLIL representation for module `\FD1P3AX'.
Generating RTLIL representation for module `\FD1P3AY'.
Generating RTLIL representation for module `\FD1P3BX'.
Generating RTLIL representation for module `\FD1P3DX'.
Generating RTLIL representation for module `\FD1P3IX'.
Generating RTLIL representation for module `\FD1P3JX'.
Generating RTLIL representation for module `\FD1S3AX'.
Generating RTLIL representation for module `\FD1S3AY'.
Generating RTLIL representation for module `\FD1S3BX'.
Generating RTLIL representation for module `\FD1S3DX'.
Generating RTLIL representation for module `\FD1S3IX'.
Generating RTLIL representation for module `\FD1S3JX'.
Generating RTLIL representation for module `\IFS1P3BX'.
Generating RTLIL representation for module `\IFS1P3DX'.
Generating RTLIL representation for module `\IFS1P3IX'.
Generating RTLIL representation for module `\IFS1P3JX'.
Generating RTLIL representation for module `\OFS1P3BX'.
Generating RTLIL representation for module `\OFS1P3DX'.
Generating RTLIL representation for module `\OFS1P3IX'.
Generating RTLIL representation for module `\OFS1P3JX'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\IBPU'.
Generating RTLIL representation for module `\IBPD'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\OBZPU'.
Generating RTLIL representation for module `\OBZPD'.
Generating RTLIL representation for module `\OBCO'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\BBPU'.
Generating RTLIL representation for module `\BBPD'.
Generating RTLIL representation for module `\ILVDS'.
Generating RTLIL representation for module `\OLVDS'.
Generating RTLIL representation for module `\$lut'.
Successfully finished Verilog frontend.

23.43.2. Continuing TECHMAP pass.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101100 for cells of type $lut.
Using template $paramod$c28a8b7ce0535d090c4cfb52e9c74affd52b110c\$lut for cells of type $lut.
Using template $paramod$a8b2b0f3a3fd7b01c99e8d61bb72f602bd41af54\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000000 for cells of type $lut.
Using template $paramod$272652f6c6fbe9a75eff76e45cc7e2788835518b\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000000 for cells of type $lut.
Using template $paramod$ccd3e15dc00d71b9284dff48e88ccef5be7362c8\$lut for cells of type $lut.
Using template $paramod$37c9af120c85145419565a9ccf4ceb7397fbbe92\$lut for cells of type $lut.
Using template $paramod$fb7bbfbe62f17d1abd6f8eaee546f5a966c46c29\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0010 for cells of type $lut.
Using template $paramod$de8f8bba29d56316e95e77d4f2a0bc9ef73137bb\$lut for cells of type $lut.
Using template $paramod$5c3294d2efb88caf0474e72690e5c12ab871a3e8\$lut for cells of type $lut.
Using template $paramod$73168779d124d0e86f3f4da4f351086f6646bb40\$lut for cells of type $lut.
Using template $paramod$5980ba3a5eca9061be62335d773e796254ed1b94\$lut for cells of type $lut.
Using template $paramod$e51a8a571bee774247b38f52d6e85fd62ae52cea\$lut for cells of type $lut.
Using template $paramod$df5c8730c0a53792c3f54c2192a2221c27162fb5\$lut for cells of type $lut.
Using template $paramod$873c285bdccf0ac2b60d2304ea5cd14bf211d2a6\$lut for cells of type $lut.
Using template $paramod$b97ff285770a798ba31d840db2ce52fdc36910ae\$lut for cells of type $lut.
Using template $paramod$a8f200f2806e23893fd75a1574871ecd897f762e\$lut for cells of type $lut.
Using template $paramod$84bef48419505c45080a829b4c4b6379a157eb8b\$lut for cells of type $lut.
Using template $paramod$6d6beead1425af15cf78b27fd9b11b41b5d4bce8\$lut for cells of type $lut.
Using template $paramod$b18a3edb490ff3a49fefc94182a05f36efbdbba2\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000111 for cells of type $lut.
Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0001 for cells of type $lut.
Using template $paramod$332530260df33f1e6567b344a898a29636fd4f0f\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000001 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000010 for cells of type $lut.
Using template $paramod$f8f63b209b7230e81958663ff24fef1613156af7\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001000 for cells of type $lut.
Using template $paramod$251994398653c4cf8de320f1e306e535d5d2d624\$lut for cells of type $lut.
Using template $paramod$a5dd9ee10fc2202a29791f7d68d4afcce241aee5\$lut for cells of type $lut.
Using template $paramod$4a4e8242f8f2e0e44388e42a12a5ef5e2b8bb93f\$lut for cells of type $lut.
Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100000 for cells of type $lut.
Using template $paramod$59f2a3e232df3029c8bc36978b9bbe72a71dfb5a\$lut for cells of type $lut.
Using template $paramod$e85b6eba0dacefc5f73f8748159b8b9599212afc\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101010 for cells of type $lut.
Using template $paramod$5e9374f44a27c3f8a1c38af244ec43ceb4fb8d4f\$lut for cells of type $lut.
Using template $paramod$723be7177967d6866729df0ff463a602326a012e\$lut for cells of type $lut.
Using template $paramod$58d49ffbb43fac74e1430ef7dfa6e760bbd204ab\$lut for cells of type $lut.
Using template $paramod$f7a897257decedfb6cc642e53d65fef7fc0df390\$lut for cells of type $lut.
Using template $paramod$c07d61aaf1d93e15249de987e8fd0ca391dbd52a\$lut for cells of type $lut.
Using template $paramod$f405ee362848dd1a47c58160f854302f6ecf95ff\$lut for cells of type $lut.
Using template $paramod$a5516fc31d1e552de2435200bb732b4d4ad63a9c\$lut for cells of type $lut.
Using template $paramod$6c51c1ba6c39f0c09b896d52432b366f116bd3c1\$lut for cells of type $lut.
Using template $paramod$a50be0e6fa3a01511bb234559cb74fb8bd3e2061\$lut for cells of type $lut.
Using template $paramod$ce44877a8aba311086973ef3ef648b154684306e\$lut for cells of type $lut.
Using template $paramod$f28a4401e00366386f5c9da01093cb438d2ef37a\$lut for cells of type $lut.
Using template $paramod$88a106be73851c7a5d1740739afdb4dbd65330dc\$lut for cells of type $lut.
Using template $paramod$faba0cf60f1c89602d59ba2d491152c8f0d36384\$lut for cells of type $lut.
Using template $paramod$bde6c96e44b0f8e6d9db97eafdf28d77ceaa9a96\$lut for cells of type $lut.
Using template $paramod$33e58adf67c6b686a154c9ce8ebbc4b04b8cabc5\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001010 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1110 for cells of type $lut.
Using template $paramod$c79aec6bf66334ca918f85c196e004c918c371ef\$lut for cells of type $lut.
Using template $paramod$db8547c0ce3f404162c765a55df5db805b4e10bc\$lut for cells of type $lut.
Using template $paramod$7aa8140c7d6de3160b21e7ff84e0f93f69f7fcc6\$lut for cells of type $lut.
Using template $paramod$2e6f7636c4430e71acfafacf89034290c19a68d2\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101111 for cells of type $lut.
Using template $paramod$7bb6a37e65823eeb4b38c370fec30ab082759a14\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001110 for cells of type $lut.
Using template $paramod$d21d214a5aa271f2d9da3f90f22432c0ecee130f\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001111 for cells of type $lut.
Using template $paramod$f20ce4917fd5b3c1bb5c623666c4e99ee36747d1\$lut for cells of type $lut.
Using template $paramod$a81cf453a316218febe7a33c0cf3157f69dfa7dc\$lut for cells of type $lut.
Using template $paramod$f3ada871809f362efd8eb0c4fb952bb5c98f0750\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100100 for cells of type $lut.
Using template $paramod$492eaf0a536adc9996cc1bdb46e9f2144885c0ab\$lut for cells of type $lut.
Using template $paramod$eaea85d27cc0950ed001348e061727a194f5cf9c\$lut for cells of type $lut.
Using template $paramod$e5759512db67494ff77fbdfc66dff4006376568f\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10110000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010101 for cells of type $lut.
Using template $paramod$ddace04fba544e6adc4cdda6a50048ddd7c111af\$lut for cells of type $lut.
Using template $paramod$81d8a60fd95b1a9f9ef71c12a774ae6988cb9fd5\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10010000 for cells of type $lut.
Using template $paramod$feac1814a13647ff95d85e23385825c648d6c2ee\$lut for cells of type $lut.
Using template $paramod$ea9f0804ffa1047d479d3e00429394419ff5856b\$lut for cells of type $lut.
Using template $paramod$7ccb46ee9b56c39e0a7d82a185b08cb026e04fbc\$lut for cells of type $lut.
Using template $paramod$173257c402a3003de28bff8c2a49d358e5f4004c\$lut for cells of type $lut.
Using template $paramod$f9813472aa48e533b3838c6f2316dc2e78c66111\$lut for cells of type $lut.
Using template $paramod$63114da772fb28945ba24699e32f1e30ca7142f4\$lut for cells of type $lut.
Using template $paramod$2c1875de701f39453798b76f5b327fe456cc0991\$lut for cells of type $lut.
Using template $paramod$394086530b97e2ede4325cfef07483589916f736\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000100 for cells of type $lut.
Using template $paramod$23ba03b3f106a8b0f20f18bfebd862b419996ddc\$lut for cells of type $lut.
Using template $paramod$7202672b7332febf25cdbe5424cf24593f5449be\$lut for cells of type $lut.
Using template $paramod$f28c2e49975958241d4d835ef97e799ed72256e5\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010011 for cells of type $lut.
Using template $paramod$b2e8d279775d333b39e310bd45fd5952acdde290\$lut for cells of type $lut.
Using template $paramod$9a8855b22366cbd3367af17a25fe0def507b1d15\$lut for cells of type $lut.
Using template $paramod$b2b8f14c1dc45737f0261c4484079d734f30d41f\$lut for cells of type $lut.
Using template $paramod$1221ecddf806ed98cf6cee2f2b5a80f38aeb4bee\$lut for cells of type $lut.
Using template $paramod$08466811901d5e03ed77c75ae1ee4f324a7c22b7\$lut for cells of type $lut.
Using template $paramod$670adfc2251aa7379d959d0bae22433a43e8d85a\$lut for cells of type $lut.
Using template $paramod$c19ac226b2328a9dc00b76bc0a6d1e025c6f4fca\$lut for cells of type $lut.
Using template $paramod$05402c79be82cc63a2eaed19f98c2af9df54d241\$lut for cells of type $lut.
Using template $paramod$d7a87ca2ecbda1d431eb014d7af4b3bc1067b28d\$lut for cells of type $lut.
Using template $paramod$38e18d818042e7be412a935b1fcbd89ce659b02d\$lut for cells of type $lut.
Using template $paramod$3cc80e2a63856e1f46075e358d1c072c35cc4ca8\$lut for cells of type $lut.
Using template $paramod$83c1b6108170249166239e09804c5f4542556524\$lut for cells of type $lut.
Using template $paramod$c441dbd41fa7b52ce609b1fb3e8a706905598601\$lut for cells of type $lut.
Using template $paramod$043a5a6e44cd8aa3c9e716e2f57f2e4f94d6e7b4\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11110010 for cells of type $lut.
Using template $paramod$4a9f20a18e16e687c50b1afb238d77d575a68f2d\$lut for cells of type $lut.
Using template $paramod$38400b76de2b00d7d5f8f09de118b82fd1b8be0a\$lut for cells of type $lut.
Using template $paramod$43b222efc278812f84aae21629319c00666b72b2\$lut for cells of type $lut.
Using template $paramod$b45308ffeb4031bc5d55ef31b149afd94d3d7565\$lut for cells of type $lut.
Using template $paramod$e25c199a439e39b844272fa7d6225073bca7d3a4\$lut for cells of type $lut.
Using template $paramod$48f2db66c872c1f64faeb797c1719c912a15a86f\$lut for cells of type $lut.
Using template $paramod$35e780f9333f3666b86f6bdeb5e6c5f65477f87e\$lut for cells of type $lut.
Using template $paramod$3b374b0454c507d1efadee363d480c52c3b3f58f\$lut for cells of type $lut.
Using template $paramod$09312832496e3ee8317d1ddf4e4ce05d551d0a6d\$lut for cells of type $lut.
Using template $paramod$b8113752b08bd47f69a1c8c2bca1cfb157e800c9\$lut for cells of type $lut.
Using template $paramod$a05170b3f2d3fcb0bf88d37e810984e864962880\$lut for cells of type $lut.
Using template $paramod$5637f6366c0fa622e75f886ee59706323e5fe6fc\$lut for cells of type $lut.
Using template $paramod$4db3f0d067a6794efd5979ea33ffc0ce06e2e75c\$lut for cells of type $lut.
Using template $paramod$47a8214374025465e226fa66bee690ff33268a25\$lut for cells of type $lut.
Using template $paramod$e01a027fedb28671a20c130493a89c7afd4e87d3\$lut for cells of type $lut.
Using template $paramod$af2687fd5fb9a9e3acf03acbf02c6dad53202781\$lut for cells of type $lut.
Using template $paramod$9867a3e9570c7eb867a9d3eb01fe3cf6a96fe544\$lut for cells of type $lut.
Using template $paramod$c1a19a87ccbbb03d43a72335db63f692ddf82cc1\$lut for cells of type $lut.
Using template $paramod$f109125ffdede8321ac65719b1066c75ff1eaef0\$lut for cells of type $lut.
Using template $paramod$4c274551372e5e846c5a80986ee03383a4d3b57e\$lut for cells of type $lut.
Using template $paramod$efd9db50f639c84b61057002b4119366b96c7abc\$lut for cells of type $lut.
Using template $paramod$6fc23ce09f2013cb9de2228dbcdda21841008f92\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010000 for cells of type $lut.
Using template $paramod$89ca3723ebb4dfdb3c4024f3f04b784a3e88f188\$lut for cells of type $lut.
Using template $paramod$6e238df02989b317f10820a22773676e71120644\$lut for cells of type $lut.
Using template $paramod$3416dacc8eaab1f89b3d6b7398df3da766d29ef2\$lut for cells of type $lut.
Using template $paramod$b93d1ea7a612a32c185108f67a153d44ffb9aac2\$lut for cells of type $lut.
Using template $paramod$6fc2d22b16acbc3c0d1ab4810a22084b2df32ef5\$lut for cells of type $lut.
Using template $paramod$93607e2cc65b766bf77d3fc876fc0a60461b4743\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00111011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111000 for cells of type $lut.
Using template $paramod$75ae9627805e0c99d176bdce0ae8ff0c02687aab\$lut for cells of type $lut.
Using template $paramod$ba40e4d7d6c53d51f2af05243b27d05d1f6ccae3\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10100010 for cells of type $lut.
Using template $paramod$6e46ec5a196ba1a24b8e69ab094cadc07c13ac1f\$lut for cells of type $lut.
Using template $paramod$373d637619c29cb9150902df9528107e5f3b8288\$lut for cells of type $lut.
Using template $paramod$0d26e42822227428593a6f2ed183ae9b22d4b575\$lut for cells of type $lut.
Using template $paramod$758d9e8729b283bb3651b0fa835584bea2e26299\$lut for cells of type $lut.
Using template $paramod$70a934594406e8042bf2854c778fef542ef3ea5f\$lut for cells of type $lut.
Using template $paramod$4b2297966ddb718657b80566604f97685ffc0120\$lut for cells of type $lut.
Using template $paramod$64036e71871a4e1b268136afcadb37a975c7f3f3\$lut for cells of type $lut.
Using template $paramod$f85f1073c412d406200a6a72283f918c8b751314\$lut for cells of type $lut.
Using template $paramod$364c9ffbffac467d60dfec81bba4e18476c15602\$lut for cells of type $lut.
Using template $paramod$e2922126afb3c6df9be8375bf6f36b929cdc98c3\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110000 for cells of type $lut.
Using template $paramod$240e171f8bae87a2fe4bee672a3055fa35afe320\$lut for cells of type $lut.
Using template $paramod$c0e395c2d0dfbafa147a6aae7cfc1897ce26affb\$lut for cells of type $lut.
Using template $paramod$2a95589caada067659f6880a072dbb51c724ba2f\$lut for cells of type $lut.
Using template $paramod$3dc8df1b07971bda7726ddf94f6377e60804ab64\$lut for cells of type $lut.
Using template $paramod$56e6d8a28a52006bb4e50e077743f0a2163235af\$lut for cells of type $lut.
Using template $paramod$6d05ee5be4fbc817e6482b590e1831ddde15ffbe\$lut for cells of type $lut.
Using template $paramod$2d70e360329f2b83357618532825d0cf30a325f3\$lut for cells of type $lut.
Using template $paramod$58df2c605746858c7e53492c8f57d6f1fafa12d2\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1001 for cells of type $lut.
Using template $paramod$a4640096cbef09c4ef8613155a589c40164ac034\$lut for cells of type $lut.
Using template $paramod$be95f3a2132281eadd1adcfe6229e43dbc3353c9\$lut for cells of type $lut.
Using template $paramod$81f38dbe34c0131668a5f4192c3c2c07e8338073\$lut for cells of type $lut.
Using template $paramod$4541c098116f7292d10d7d30a0922be20fa68a41\$lut for cells of type $lut.
Using template $paramod$9fc14cb0ba5120a1da0c687a9fb19472f206fdfe\$lut for cells of type $lut.
Using template $paramod$66caeb00a39d236782a97659e3bd99621b74681b\$lut for cells of type $lut.
Using template $paramod$8e55a9cca77fc533dfed315558bf3940f6a7ff6b\$lut for cells of type $lut.
Using template $paramod$7ffc04c088a4897014506d1e561a14b627924059\$lut for cells of type $lut.
Using template $paramod$0331e023d83b8009e60defb446ce9fa640b122c7\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101000 for cells of type $lut.
Using template $paramod$238ce1c123ccd5620a61157a2c5350ee6fc4d4ff\$lut for cells of type $lut.
Using template $paramod$1dbc005c3ca46176ed5f71d3318762a2498d170f\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11010000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00110001 for cells of type $lut.
Using template $paramod$d2a1a3b18350dd0754abc41ae3ec8d880a85d26a\$lut for cells of type $lut.
Using template $paramod$47a326ee296feaca60c97add5a2f7670de259bd9\$lut for cells of type $lut.
Using template $paramod$7a73f9756d5c153bcd3667a54c2eeb22386fe779\$lut for cells of type $lut.
Using template $paramod$dafa5d77005060eef9df3a9c17558a81d6d31f4d\$lut for cells of type $lut.
Using template $paramod$de07eb062963514b9c819aacc3e74a1253bffd53\$lut for cells of type $lut.
Using template $paramod$8c11a155773d2e4aba9b1022fc059160b55313e8\$lut for cells of type $lut.
Using template $paramod$6b0849254d6c87461fb93e37cc18f089f61eb912\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01011101 for cells of type $lut.
Using template $paramod$f546bd96bcec6e3bf1b78bdea64b0f5bbbaff6df\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0110 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11000100 for cells of type $lut.
Using template $paramod$a50bbaf70b48eb6d78317eddf4f7e11e8988acec\$lut for cells of type $lut.
Using template $paramod$d646cd5cb36fb1f9dd2b06f584b3b88b2dec1d24\$lut for cells of type $lut.
Using template $paramod$8adf7fbd410d2cc654c288d5be5f7508ee8809b0\$lut for cells of type $lut.
Using template $paramod$018d71a0fe325d6362687fe53ac13dd6340e400d\$lut for cells of type $lut.
Using template $paramod$26d876869d6ab003366d0470e095daef2ccfcbd7\$lut for cells of type $lut.
Using template $paramod$440c55e9b86a4d19d2d9af4513ac1f3c626292af\$lut for cells of type $lut.
Using template $paramod$31387621d1610a0290872bbf4d90a41c51f62d2e\$lut for cells of type $lut.
Using template $paramod$e0a16b39d62021fbd2d1c105eda1b9c3b86f8b30\$lut for cells of type $lut.
Using template $paramod$17d8db5e0049209af1b683c163ab6882816960dc\$lut for cells of type $lut.
Using template $paramod$3a0a392069bc969f34c65c546a8c56fbbb67e282\$lut for cells of type $lut.
Using template $paramod$3702268f692b8bf258e428f65d3bca4e1f76d98b\$lut for cells of type $lut.
Using template $paramod$c8f16510db975553c8b0be1064e8f5234175f8a8\$lut for cells of type $lut.
Using template $paramod$b698dd2b885039c9e1d53e243fc4e0191632dfd9\$lut for cells of type $lut.
Using template $paramod$51307cdec77060d17363ea3d60427c9afef1ddc2\$lut for cells of type $lut.
Using template $paramod$1d8da67e55226ee6f849b82c7c3ba5690a649089\$lut for cells of type $lut.
Using template $paramod$f4924b9d1c382d0cb922de70d1eb4371b36c168b\$lut for cells of type $lut.
Using template $paramod$ca009e911508f27903ef81bdd82bfd594b87e190\$lut for cells of type $lut.
Using template $paramod$a760bb0c868463583597b74627bb191c230e84d6\$lut for cells of type $lut.
Using template $paramod$d08ae3e2fee668f1a68bd32fd012d46d229cb782\$lut for cells of type $lut.
Using template $paramod$be7b9b4fe304f35e2a126a3893cf799cf6d216a8\$lut for cells of type $lut.
Using template $paramod$865395c0228487a64a8e4011cecafc2c64b79f2b\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1101 for cells of type $lut.
Using template $paramod$df29fe9e6d6d694a9cc5697e4251bf7d8cd4d8e4\$lut for cells of type $lut.
Using template $paramod$e49f6e3576ef1a6d2f58c54414dbb786af8cc869\$lut for cells of type $lut.
Using template $paramod$682dcf7a44e09cdf417bc55247ac658426f4c8e6\$lut for cells of type $lut.
Using template $paramod$baa9d2fb2d21010939721b85aa9f11effe0b53c4\$lut for cells of type $lut.
Using template $paramod$63ad113d539ca3e933806bc7a6f9822dafc59f3e\$lut for cells of type $lut.
Using template $paramod$bba54c1ef87367812b4c15f4aed5ac70773df775\$lut for cells of type $lut.
Using template $paramod$068092ddede495d8462ffe530e6d91711913edbc\$lut for cells of type $lut.
Using template $paramod$2ec6422db00d358fc7469efce6208bffbc8521cd\$lut for cells of type $lut.
Using template $paramod$712505941a295086314c22735153725461a87f4a\$lut for cells of type $lut.
Using template $paramod$653ed1fca2cbea6092fc92115114dddd9158d22d\$lut for cells of type $lut.
Using template $paramod$98c377328f303d3ed9039ca0db26b18f36e929b2\$lut for cells of type $lut.
Using template $paramod$8d34a5a71d627316427f29a4a50d78b9c600fe42\$lut for cells of type $lut.
Using template $paramod$302ba22a83dfb50189674147c5c2626b9e9dab7e\$lut for cells of type $lut.
Using template $paramod$f7744fc299c4b6dc315f22eb6110994661b48d3f\$lut for cells of type $lut.
Using template $paramod$c1bc0fac7ee4f636a7acbb8be0f7ebafcf4fd3c8\$lut for cells of type $lut.
Using template $paramod$11bc766f7154baa3cc5851153bc4dab883f3cff9\$lut for cells of type $lut.
Using template $paramod$f24ba3ced4b870f8e829f5ac5a8af88573350e6f\$lut for cells of type $lut.
Using template $paramod$ffc2ea81a65101fbef8a332deddf112494d27163\$lut for cells of type $lut.
Using template $paramod$f8b5a2092e0c5e20cb9d3c609617b439b0653eaf\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001010 for cells of type $lut.
Using template $paramod$60b99ddfae8ffcebbb1fe7f9e676a60f7472edd5\$lut for cells of type $lut.
Using template $paramod$4d91d432f89d9d781957f1bb7c532aaf3de07096\$lut for cells of type $lut.
Using template $paramod$f462624619cf0a2d6f0c31648d390037e6d23d7c\$lut for cells of type $lut.
Using template $paramod$8d8a6111e2a82db0bfbd78666fa69c753d8df004\$lut for cells of type $lut.
Using template $paramod$b4410865e8124402796f9dfbf73ef8d279fdbd08\$lut for cells of type $lut.
Using template $paramod$18b66a2dc66be2a0d172c3d50ba03932f5924e22\$lut for cells of type $lut.
Using template $paramod$9cc51547ab44a72dd506ee5bb84a864365a103da\$lut for cells of type $lut.
Using template $paramod$3f9a3800e34bd795630a4eaf44b2e1d4a7f48a74\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100011 for cells of type $lut.
Using template $paramod$e6a488add0b5a2d742e2ae29f62ce7616e04271d\$lut for cells of type $lut.
Using template $paramod$d9922e15eb5da1acc26e937540cc16b16c2ad42c\$lut for cells of type $lut.
Using template $paramod$21a1ca6f9f5c15b304c8c46ce6cda8b91e063cf1\$lut for cells of type $lut.
Using template $paramod$6e3a03c79073e44642e8ed2dab4ee82dfd40dfba\$lut for cells of type $lut.
Using template $paramod$3751cff910103888107374559f35d9f1f2f94946\$lut for cells of type $lut.
Using template $paramod$9f9f23a6a1a433c444d9411b274e8c232c6fbcb3\$lut for cells of type $lut.
Using template $paramod$17fd36fab32bce162e5828682c2ba9fa7f9e273b\$lut for cells of type $lut.
Using template $paramod$9cf976b4f3a576aa2cd6b51304cf5de7fc836fbd\$lut for cells of type $lut.
Using template $paramod$c63efa97e6cbc8132d15a22fbd0c7fc96068748a\$lut for cells of type $lut.
Using template $paramod$f672f1e5ea7eaf40630014635549af40fc023a51\$lut for cells of type $lut.
Using template $paramod$ba7f31f246a278c41fa0648a6e0512f63185dec0\$lut for cells of type $lut.
Using template $paramod$8504d86f1088c038cefc453338e6ce07c755faf4\$lut for cells of type $lut.
Using template $paramod$3e169cec6f369077a59a80fe281a083ba6809078\$lut for cells of type $lut.
Using template $paramod$985f4a39445dc8a19b2aa35fe53dc5ac282e20d6\$lut for cells of type $lut.
Using template $paramod$eabde4761c91679426ef5401ae1b2c95bf56e107\$lut for cells of type $lut.
Using template $paramod$04378ff5de74dcc5e8256236add5995200f72e4d\$lut for cells of type $lut.
Using template $paramod$e332cff882edd417f410bab5fe07a0f88572cce3\$lut for cells of type $lut.
Using template $paramod$993b4f1762899d4359410690d334eafca84b9285\$lut for cells of type $lut.
Using template $paramod$4385b611926e5c0509dba4de58311d325da0ff0d\$lut for cells of type $lut.
Using template $paramod$02750f8d568bd99efbda01449a05e084a3143ca8\$lut for cells of type $lut.
Using template $paramod$ec77ef2f39e0c5347eaada9711f26fca6a276050\$lut for cells of type $lut.
Using template $paramod$097592bb16245531f0716c5ddb18d7090f9c7d9d\$lut for cells of type $lut.
Using template $paramod$e4028dbef8bf09e426c35a5ead7da0bbf24c7433\$lut for cells of type $lut.
Using template $paramod$0f891ee84fac320f890afcf9c994c53a24cd31f9\$lut for cells of type $lut.
Using template $paramod$b9305c669fd883d24574655b402c7ff9f28efb1a\$lut for cells of type $lut.
Using template $paramod$1286a3d975c594752b534a4722a03c9fb6e30920\$lut for cells of type $lut.
Using template $paramod$ac9e3968766d438b96ef7a04264cc79d386f7658\$lut for cells of type $lut.
Using template $paramod$b587e1dcd8f8a9800d395e4aeecac52c55d6f585\$lut for cells of type $lut.
Using template $paramod$6d6aab6ca80aca5ae70889822a914b9498798ab4\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001000 for cells of type $lut.
Using template $paramod$5416c1fb57d2673f981291c837d3bd2b1a12648f\$lut for cells of type $lut.
Using template $paramod$c284ff54f56770afea639d8dc3d5a680938d3638\$lut for cells of type $lut.
Using template $paramod$b03659edff45c1f1bd958c0a9c302348801cbbe0\$lut for cells of type $lut.
Using template $paramod$cb63a6e25879a415b84a2418577cc471d6e8d208\$lut for cells of type $lut.
Using template $paramod$0c9cc7bd3818da14b349d2e49e8c15965761a225\$lut for cells of type $lut.
Using template $paramod$83f0056a7fc78775b1c0d1b0c8a0d332bd1c5778\$lut for cells of type $lut.
Using template $paramod$b8f75cf9c6c06c079da053f4aa60c4d5363c32b3\$lut for cells of type $lut.
Using template $paramod$43779580bfffd5d5a9f321249a174febf1dac288\$lut for cells of type $lut.
Using template $paramod$2d07c1a6c53c7b878509360922c4fa5ebedc3011\$lut for cells of type $lut.
Using template $paramod$df196ed0a1da5c4a58c5e08a1dac304fd3fccaab\$lut for cells of type $lut.
Using template $paramod$65d5d5c1e01bf41ee659754efba932f3d99198e5\$lut for cells of type $lut.
Using template $paramod$c217e185eb8e6463ca272982ba8c5940fa90d81f\$lut for cells of type $lut.
Using template $paramod$517625bf4a7b846fd553901d881a35fcc8afe4c4\$lut for cells of type $lut.
Using template $paramod$8512f4fb47fa9596f76cdbe5b407a5b54df368e7\$lut for cells of type $lut.
Using template $paramod$edc5a73130589b9210f4bdf92e14bdcacac8945d\$lut for cells of type $lut.
Using template $paramod$82b4a585d1edcb5c6e755dc9bd3392228a1c1304\$lut for cells of type $lut.
Using template $paramod$be48d952fcad8a16b8d84daa4c48a3065f343e5e\$lut for cells of type $lut.
Using template $paramod$40f50322426372d948aaadc2f14dc77fbf5a9200\$lut for cells of type $lut.
Using template $paramod$150ee00bee81b2fcb159e621f4ef27bccb5ede20\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut.
Using template $paramod$7d813eb49700f971f2635a434700eafdfa816bc3\$lut for cells of type $lut.
Using template $paramod$4cab3b31c601551ff65536bf4f533afa0b2094ee\$lut for cells of type $lut.
Using template $paramod$7d35f3eb4056e6484203c99fe42cfcf1dfaba704\$lut for cells of type $lut.
Using template $paramod$22641603d8fa727856e499ecf3ff9bfa826a5891\$lut for cells of type $lut.
Using template $paramod$498daa9936ffa1c0b12d774cacc95a35d14b818e\$lut for cells of type $lut.
Using template $paramod$00da6ee835349555028231ae835c9b401a5c1dee\$lut for cells of type $lut.
Using template $paramod$8e44661def013b6bf9fe6f8b049ef2c838d749f9\$lut for cells of type $lut.
Using template $paramod$181733d3e31dcdcea8c52d0a4fc252b3aa453564\$lut for cells of type $lut.
Using template $paramod$7cd2eb6a7d66e3dc32689a836e66ef851f6abf28\$lut for cells of type $lut.
Using template $paramod$f4257f9b9dfe762de25d0a149f2ea6e405c888f2\$lut for cells of type $lut.
Using template $paramod$d600a497251a1b488524ff8c469b2bb2309f570b\$lut for cells of type $lut.
Using template $paramod$b6ebb0ea1200440e9f4d8451077c5efc796eb6bd\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000100 for cells of type $lut.
Using template $paramod$8d7a8d6e3356de09670738ba85f2c6b874f6b06d\$lut for cells of type $lut.
Using template $paramod$f45429e380905f064bb0bad3a8bdb941708e63a7\$lut for cells of type $lut.
Using template $paramod$14d4ecb35d1ed77a073faf7c00fef16843b49ef7\$lut for cells of type $lut.
Using template $paramod$e3e4230bb990723642112b292aa705ee0cbad0d4\$lut for cells of type $lut.
Using template $paramod$b26fbfdb68e98cf016d61a8611b449e9f4a30f3c\$lut for cells of type $lut.
Using template $paramod$6bf74d43098222579e639c5a64a5885252736467\$lut for cells of type $lut.
Using template $paramod$655e7cdf1fce9923e771969f28446489197085e2\$lut for cells of type $lut.
Using template $paramod$cf652acbfbf67d2248e3045cd0f09c58ca55886c\$lut for cells of type $lut.
Using template $paramod$973394a6f8c13a435c2fa950b3fc699e041032a1\$lut for cells of type $lut.
Using template $paramod$8ce3bb5281756031c29296f5408ac54526962f46\$lut for cells of type $lut.
Using template $paramod$e234b33fd72932ba3f0d727e277c697708f63208\$lut for cells of type $lut.
Using template $paramod$256f3f936b752cf569dca900ae92c3ac452c7e57\$lut for cells of type $lut.
Using template $paramod$757c055b2d591f99a56beeb4bd1bdff266f67334\$lut for cells of type $lut.
Using template $paramod$0a85ef24bbe0af4c0a398eda4c9c483e3a950ffc\$lut for cells of type $lut.
Using template $paramod$9d7cb07dac3530494de4bfa055f16a7657afbcb4\$lut for cells of type $lut.
Using template $paramod$83cb19296515f545f4c69bf6713ff705a6b55de0\$lut for cells of type $lut.
Using template $paramod$5b5755730b9a53f6c50cca29ba2f99d7e0bc0fe6\$lut for cells of type $lut.
Using template $paramod$41b777a122fa6162fe05e453fac63a5bd726825e\$lut for cells of type $lut.
Using template $paramod$8fc5d3ca06d4a86c278b2fcd889e8bb36c71cda0\$lut for cells of type $lut.
Using template $paramod$179512a187da069f3b79ef6612a41e494e7d54b6\$lut for cells of type $lut.
Using template $paramod$3a313ff02d51d1203c8a57fd50d2cde2804e4da1\$lut for cells of type $lut.
Using template $paramod$f90e2ec6b7a4c6db6f7a3682dfa870e7c33a78da\$lut for cells of type $lut.
Using template $paramod$bef7fff73d7847e500891f20145b83b119b2bb41\$lut for cells of type $lut.
Using template $paramod$5f99aa1a31b4f0c356281a67e16706e1e689d29f\$lut for cells of type $lut.
Using template $paramod$766f851776a2d25e13728c9147ddfe7ff70917a3\$lut for cells of type $lut.
Using template $paramod$a18efd9245448b0a198b87f7e710a6a1c17ab9de\$lut for cells of type $lut.
Using template $paramod$7910dd2b5f1d6963b04c4c488a8305218816b998\$lut for cells of type $lut.
Using template $paramod$8f7210088a40da1859d27e900c288fd298d68bed\$lut for cells of type $lut.
Using template $paramod$fffed37ec5aab9b071d5d6a875571939891d8a2e\$lut for cells of type $lut.
Using template $paramod$425da8bbf32ad83dea76dd417944f9ef98f2525c\$lut for cells of type $lut.
Using template $paramod$bb0607774756a7cf4db332b8ee3601a9f01f0cec\$lut for cells of type $lut.
Using template $paramod$97bfd0f207e3cd11e81dc81c48f8e4fa7fc28966\$lut for cells of type $lut.
Using template $paramod$91c597fdd01f1a36fd1300f0b1a352645aeb6e2f\$lut for cells of type $lut.
Using template $paramod$f2a45de84ab104b36698aefae5956dc025e5c717\$lut for cells of type $lut.
Using template $paramod$6c79511ccb6cb7e0854720379cad028a570f2e37\$lut for cells of type $lut.
Using template $paramod$f34999160a5c14d7bdd27e994783f035df17f5bc\$lut for cells of type $lut.
Using template $paramod$a9838c90d971b33a783e2ac891a278c41ba26ad3\$lut for cells of type $lut.
Using template $paramod$a29dc9226a883358910d3758606f48686bda2689\$lut for cells of type $lut.
Using template $paramod$b4f85a6321a00b090afc4e21d68e7b99eb94d149\$lut for cells of type $lut.
Using template $paramod$ade97056e03d3c65f105329ccff6749f3645e1a9\$lut for cells of type $lut.
Using template $paramod$ebc2bffeb14d72cac79dd0d6e85ade2c5c402e42\$lut for cells of type $lut.
Using template $paramod$aebfd6dc7069289f10bac1debe2efe61f7608c7f\$lut for cells of type $lut.
Using template $paramod$c362ad8dedc7d166ed978091aca319ab1e81a2d4\$lut for cells of type $lut.
Using template $paramod$280035305b2faefe3e035f896034d2f4cfc7680f\$lut for cells of type $lut.
Using template $paramod$085cb83d0db09780ae5aa544a0f286ba9445143f\$lut for cells of type $lut.
Using template $paramod$47d363ae7b1a0e81207e02fe31af85b6bf36a2ac\$lut for cells of type $lut.
Using template $paramod$bb7e7a621b60502914abfe85162d215ad010143b\$lut for cells of type $lut.
Using template $paramod$7456623269e725777894300dcddb27d8903aa69a\$lut for cells of type $lut.
Using template $paramod$e2d96f36ef28053ecd27167cd95b944485ac3146\$lut for cells of type $lut.
Using template $paramod$f31b051e85a2bc96a5cf3eaf7f86a4f418c293dc\$lut for cells of type $lut.
Using template $paramod$4d1533dad4814c51bde53f9a378e78c03dd47a9f\$lut for cells of type $lut.
Using template $paramod$af6bfc66edfa832be553173935a94fd15de7c168\$lut for cells of type $lut.
Using template $paramod$c5e227af307b9c53329a9bcea914f98030ca9bc6\$lut for cells of type $lut.
Using template $paramod$2600c76ca5fc8e4e0cd2721244c32184874b6439\$lut for cells of type $lut.
Using template $paramod$a48d96b3084901aac1f541d9be59ab6aad37df36\$lut for cells of type $lut.
Using template $paramod$318e655f028abd6c26dfa0bd6ca4aae49ecd6bb2\$lut for cells of type $lut.
Using template $paramod$d491a266f9662a297987d35d4b16957a59e4712a\$lut for cells of type $lut.
Using template $paramod$98da953dac84989c1dec711ba4d909885d65c4dd\$lut for cells of type $lut.
Using template $paramod$ad8a8c8c3362de58b4d368e2772ebe76c9e0aa7a\$lut for cells of type $lut.
Using template $paramod$16894c241be5ea1f024e9339dea788b4dbe184ae\$lut for cells of type $lut.
Using template $paramod$13db89d803fba2c388a0746a896148ea18b92b01\$lut for cells of type $lut.
Using template $paramod$f23107923150e607001e5d808d357fcd051b5344\$lut for cells of type $lut.
Using template $paramod$72148f3545efac6f48701d6c21ae5eeb7a5f865b\$lut for cells of type $lut.
Using template $paramod$e9c77024ca501b890c641f9c0b10e27242db8730\$lut for cells of type $lut.
Using template $paramod$059968be1ef12c596bb5d360a749040b6777bf4a\$lut for cells of type $lut.
Using template $paramod$ba4b1c9b57f942a38af35848615a2f06189d3bfe\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111001 for cells of type $lut.
Using template $paramod$7e9df0afb32b76fe5fce0691b8752aca650057fa\$lut for cells of type $lut.
Using template $paramod$e03a085a6f62957990465e57c27110fc0ca3a44f\$lut for cells of type $lut.
Using template $paramod$9e1755e3954600257bb9b9ab192e2c0243b0f35a\$lut for cells of type $lut.
Using template $paramod$84c5cfa8d7481774250caab0fcdd6d249a376a31\$lut for cells of type $lut.
Using template $paramod$ec6bb3db7c80c492ce6110718f99328a4ab7f019\$lut for cells of type $lut.
Using template $paramod$101238f3d8d49ab12a9b49a2f01cd503b26e9c61\$lut for cells of type $lut.
Using template $paramod$81186628bc8c24a4f1f4f97548486a6e598c757d\$lut for cells of type $lut.
Using template $paramod$e3631d698937358b0cc75c5b282090fead21ade1\$lut for cells of type $lut.
Using template $paramod$d7ec878ecfa8f5f7604d3e91692b5d4c2ee758ad\$lut for cells of type $lut.
Using template $paramod$4ebbf381cf64b08e3304ae8194da41d0cd1eaa92\$lut for cells of type $lut.
Using template $paramod$57400e123f0147f905d2ec980ae5b64230fc0a43\$lut for cells of type $lut.
Using template $paramod$daac9b1e7bb2ac018f7132a3fbe0026ddd7b1a71\$lut for cells of type $lut.
Using template $paramod$7ce7683c590e6b9a2ebd543a8f468551f1af24cf\$lut for cells of type $lut.
Using template $paramod$8075729953f49b6cb1b4d863b2fb20da9818d304\$lut for cells of type $lut.
Using template $paramod$5076a9b521f13af7c5d1c35833cc1b2260625b01\$lut for cells of type $lut.
Using template $paramod$1807eea78e457340167633ea676b60cb92188169\$lut for cells of type $lut.
Using template $paramod$b9fe3aa75b16af887d56dc97666680b6a73cdb4d\$lut for cells of type $lut.
Using template $paramod$023d9d13c9ddd8e6cbda8fa49753038bbbacbfa4\$lut for cells of type $lut.
Using template $paramod$219b71aec9a19e7a27754ed85a7d6cdad9e5ec96\$lut for cells of type $lut.
Using template $paramod$e90c7b49003fd47c4e79ac1db3fd5c8d4f54e2f0\$lut for cells of type $lut.
Using template $paramod$90418f71a1b3e98f36d147df874dd839b0e31579\$lut for cells of type $lut.
Using template $paramod$9bdc414229f06e785dc8fd97a243faa9336e164a\$lut for cells of type $lut.
Using template $paramod$ab8bb87959c5d7cfa27886cee1355b38e054a61a\$lut for cells of type $lut.
Using template $paramod$6de442abe246ff8c0692702d40d84ce1c07479d9\$lut for cells of type $lut.
Using template $paramod$d6826839cb73f8300cfc390fbaaf017a5f543fb6\$lut for cells of type $lut.
Using template $paramod$633ae299df262467973f925d88826d85d4a12fb4\$lut for cells of type $lut.
Using template $paramod$f03663c7f91be924d1e9df8220b895406b3f6489\$lut for cells of type $lut.
Using template $paramod$52fa1b2073b9054923f466bbb768e0ea7c69c9e3\$lut for cells of type $lut.
Using template $paramod$68333ba85565e16101ab8af69fddc9a0d05bfda5\$lut for cells of type $lut.
Using template $paramod$52acd744af558b1acd7f06b0e1d721506b042b9b\$lut for cells of type $lut.
Using template $paramod$000fa2164e1f538c16460571efee2b6209a086cc\$lut for cells of type $lut.
Using template $paramod$fdb7d2f78b1b1d86177579c82e917e4e8af6f77d\$lut for cells of type $lut.
Using template $paramod$2f23ee9496edbb044d48f324aa9a472e448048c6\$lut for cells of type $lut.
Using template $paramod$7ff054bf1849e35157c5493ac1b0fb5805fe014a\$lut for cells of type $lut.
Using template $paramod$d80c9b99dacb354fa564a6fcc23ca30753bf6623\$lut for cells of type $lut.
Using template $paramod$aaf2ef5cf75121bbc717334d538c8a2de3e26e03\$lut for cells of type $lut.
Using template $paramod$87835d39fc38ae5dfbc03e273a9ca43a6431c8e1\$lut for cells of type $lut.
Using template $paramod$09ff6bc38860bc684248b0f5479347794277f7f7\$lut for cells of type $lut.
Using template $paramod$77eba90f08fef1f04e121480501078ac12ffbebb\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100010 for cells of type $lut.
Using template $paramod$4f6ef5838c139220e91b3d9534b74e9d61193cac\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111000 for cells of type $lut.
Using template $paramod$769bdbbde83614df0f4ab5f54e777ded51bb10ce\$lut for cells of type $lut.
Using template $paramod$19f4fa446d94767b8a3977abee599cf6b53b2330\$lut for cells of type $lut.
Using template $paramod$138253370bae6007e6e519350af9f987329e0b68\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00011101 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1011 for cells of type $lut.
Using template $paramod$e934877433e628b9aa4b7cb2bee8957bca3e1db5\$lut for cells of type $lut.
Using template $paramod$432f26b811c14bf54c5e87c8670ec65cbcaf38ac\$lut for cells of type $lut.
Using template $paramod$c5f3c57a6d466a2f42208bafb8985b96ce884440\$lut for cells of type $lut.
Using template $paramod$4d673f44384ebded9d542bceabb0e9271e6f9336\$lut for cells of type $lut.
Using template $paramod$39fecdaa624309b39c1f847c4e14205177fabf73\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111110 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0111 for cells of type $lut.
Using template $paramod$505ca6f83efadae0442899a08af73f5288142a52\$lut for cells of type $lut.
Using template $paramod$717dae7a4b4d98fb824634d546043d165e3cf20a\$lut for cells of type $lut.
Using template $paramod$ead66ba22839f96e739c8f1b5a09bc1717b3be02\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01101010 for cells of type $lut.
Using template $paramod$95f9b81027e0efcb4250de73f2fadc287f9fe7c2\$lut for cells of type $lut.
Using template $paramod$5552b23a89809fed2b1588e8f91bb3893be2e6ce\$lut for cells of type $lut.
Using template $paramod$0e6f7067c2a44b2e3cbef1e1c87513a6042c22b4\$lut for cells of type $lut.
Using template $paramod$619b7c9a4d44585e10b42f7fb79b16304cca97c5\$lut for cells of type $lut.
Using template $paramod$0f19b1c588a47c675d00132b243b5e3308ffab5d\$lut for cells of type $lut.
Using template $paramod$5b4b4ed558983d9f3ab4c896a7a011d129b0db9a\$lut for cells of type $lut.
Using template $paramod$95e069858cb2e42f0b23620675213cfe73b02fff\$lut for cells of type $lut.
Using template $paramod$b574c1df31b19134bcccccd0450f90abe2dd8f26\$lut for cells of type $lut.
Using template $paramod$71b6d833a4170eede1dcc8409c3fc7460c2df8d9\$lut for cells of type $lut.
Using template $paramod$b6fd3dc9372f3dfdc7db31822fae1fe43708b3b8\$lut for cells of type $lut.
Using template $paramod$263b613d26e59958a0d1e36903a2016b82f2f359\$lut for cells of type $lut.
Using template $paramod$d657361b360a152b4018b0283df55e5626273e96\$lut for cells of type $lut.
Using template $paramod$561d2773f8d56e396c30ee941900c9935428585f\$lut for cells of type $lut.
Using template $paramod$f7e977e4ab769956ecac4448595a773db86c44e8\$lut for cells of type $lut.
No more expansions possible.
<suppressed ~8323 debug messages>

23.44. Executing OPT_LUT_INS pass (discard unused LUT inputs).
Optimizing LUTs in top.
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73394.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73394.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73394.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73394.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73394.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73394.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73393.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73393.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73393.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73393.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73393.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73393.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73386.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73385.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73385.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73383.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73383.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73383.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73383.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73383.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73383.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73376.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73379.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73379.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73379.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73379.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73379.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73379.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73380.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73380.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73381.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73381.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73382.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73382.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73392.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73392.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73392.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73392.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73392.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73391.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73391.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73391.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73391.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73391.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73391.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73390.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73390.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73388.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73388.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73387.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73387.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73389.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73215.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73215.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73215.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73215.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73215.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73395.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73395.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73395.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73395.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73395.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$73136$lut\SOC.Core.CSR_Unit.csr_write_data[13].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$9554.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$9518.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$9316.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$9311.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$8500.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$73136$lut$aiger73135$8264.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$8258.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$8258.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$8213.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$8213.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$8205.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$8205.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73136$lut$auto$fsm_map.cc:170:map_fsm$2146[2].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$7930.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$7930.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$7925.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$73136$lut$aiger73135$7925.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$7771.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$73136$lut$aiger73135$7771.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$7581.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$7581.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$7581.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$7581.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$73136$lut$aiger73135$7581.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$73136$lut$aiger73135$7581.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$73136$lut$aiger73135$7536.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$7536.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$7536.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$7536.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$7536.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$7503.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$7483.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$7392.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$7392.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73223.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$7181.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$7133.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$7133.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$7095.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$7095.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$7095.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$7095.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$7095.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$7095.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6894.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6894.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6894.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$73136$lut$aiger73135$6894.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$73136$lut$aiger73135$6854.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$6854.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$6854.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$73136$lut$aiger73135$6846.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6846.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6846.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6846.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$6846.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$6835.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$6835.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$6835.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$6804.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$6804.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6804.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6804.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$6778.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6672.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6672.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73228.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$73136$lut$aiger73135$6628.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$6628.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$6602.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6602.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$73136$lut$aiger73135$6602.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$73136$lut$aiger73135$6602.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$73136$lut$aiger73135$6595.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$6595.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$6595.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$6595.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6595.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6587.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6587.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6587.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6587.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$6587.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$6552.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6552.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$73136$lut$aiger73135$6552.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$73136$lut$aiger73135$6330.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6330.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$6330.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6330.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$6330.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$6285.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$6280.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$73136$lut$aiger73135$6280.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$73136$lut$aiger73135$6280.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$6262.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$6240.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$6240.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$73136$lut$aiger73135$6193.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6193.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6193.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6193.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$6193.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$6193.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$6193.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$6172.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$6172.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$6172.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$73136$lut$aiger73135$6051.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6051.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6051.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6043.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$6032.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$5990.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5990.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5990.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5990.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5990.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5983.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5983.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5983.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5983.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5983.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5983.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5953.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5953.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5953.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73230.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73230.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73230.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73230.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73230.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73230.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73230.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73232.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$5857.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$73136$lut$aiger73135$5857.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$73136$lut$aiger73135$5829.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5829.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5829.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5829.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$5829.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$5829.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$5829.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$5622.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$73136$lut$aiger73135$5622.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5622.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5622.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5622.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5622.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5434.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$5383.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$5383.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$73136$lut$aiger73135$5383.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5383.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5375.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5375.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5375.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5375.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$5375.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$5375.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$5375.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$5345.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$5328.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5328.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5328.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5328.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5328.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5328.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5307.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5307.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5307.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5307.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5307.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5290.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5290.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5290.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5290.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5290.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5290.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5269.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5269.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5269.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5269.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5269.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$4632.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73224.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$7044.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$7044.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$7044.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$7044.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$7044.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$7044.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$7011.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$7011.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$73136$lut$aiger73135$7011.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$73136$lut$aiger73135$7011.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$7011.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$7011.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$7011.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$7005.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$7005.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$7005.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$7005.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$7005.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$7005.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6999.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6999.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6999.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6999.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$6999.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$6999.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$6999.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$6989.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$6989.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$6989.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$6989.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6989.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73218.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73218.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$7283.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$7283.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$7273.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$7273.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$7273.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$7273.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$7273.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$7273.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$7418.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$7418.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$7406.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$7406.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$7406.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$7406.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$7406.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$7406.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$7406.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73226.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73226.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$6904.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6904.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6904.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$6904.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$6904.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$6904.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73227.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73227.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73227.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73227.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73227.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73227.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$6735.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6735.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$6735.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6735.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$6735.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6735.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6718.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$6718.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$6718.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$73136$lut$aiger73135$5735.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5735.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5735.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5735.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$5735.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$5735.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$5735.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$5681.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5681.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5681.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$73136$lut$aiger73135$5681.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6467.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6467.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6467.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6467.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6467.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73136$lut\SOC.Core.CSR_Unit.csr_write_data[24].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$73136$lut\SOC.Core.CSR_Unit.csr_write_data[24].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$73136$lut\SOC.Core.CSR_Unit.csr_write_data[24].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$73136$lut\SOC.Core.CSR_Unit.csr_write_data[24].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$73136$lut\SOC.Core.CSR_Unit.csr_write_data[24].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$5871.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$6418.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6418.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$6418.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6418.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$6418.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6418.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6412.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6412.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6400.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6400.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6400.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6400.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6400.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6400.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6393.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6393.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6393.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6393.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6393.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6393.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6139.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5976.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5695.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5695.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5695.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5695.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5695.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5695.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73136$lut\SOC.Core.CSR_Unit.csr_write_data[22].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$73136$lut\SOC.Core.CSR_Unit.csr_write_data[22].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$73136$lut\SOC.Core.CSR_Unit.csr_write_data[22].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$73136$lut\SOC.Core.CSR_Unit.csr_write_data[22].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$73136$lut\SOC.Core.CSR_Unit.csr_write_data[22].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$10852.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$7078.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$7073.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$7073.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$7073.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$7073.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$7073.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6494.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6494.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6494.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$6494.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$6494.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$6494.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$7053.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$6823.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6823.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6823.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$73136$lut$aiger73135$6823.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5881.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5881.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5881.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$5881.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$5881.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$5881.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73217.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73217.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73217.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73217.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73217.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73217.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$73136$lut$aiger73135$7350.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$73136$lut$aiger73135$7350.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$73136$lut$aiger73135$7350.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$73136$lut$aiger73135$7350.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$73136$lut$aiger73135$7350.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$6386.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6386.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6386.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$6386.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$6386.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$6386.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$6344.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6344.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6344.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6344.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6344.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5812.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$5812.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$73136$lut$aiger73135$7368.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$7368.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5725.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5725.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5725.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5725.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$5725.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$5725.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$5725.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$5712.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5712.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5712.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5712.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5712.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5712.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6484.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6484.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6484.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$6484.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$6484.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$6484.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$5568.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5568.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5568.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5568.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5568.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5568.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5200.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5200.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5200.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5200.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5200.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5200.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5183.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5183.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5183.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5183.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5183.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5183.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5166.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5166.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5166.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5166.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5166.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5166.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5149.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5149.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5149.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5149.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5149.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5149.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5123.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5123.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5123.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5123.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5123.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5123.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5106.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5106.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5106.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5106.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5106.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5106.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5083.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5083.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5083.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5083.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5083.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5066.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5066.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5066.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5066.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5066.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5066.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5673.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5673.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5673.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5673.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5673.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5636.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5636.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5636.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5636.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5636.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5636.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5650.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5650.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5650.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5650.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5650.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5650.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5643.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5643.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5643.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5643.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5643.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5643.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5906.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5906.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5906.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5906.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$5906.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$5906.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$5906.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$5705.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5705.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5705.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5705.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5705.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5705.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5657.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5657.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5657.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5657.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5657.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5657.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73136$lut\SOC.Core.CSR_Unit.csr_write_data[17].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$73136$lut\SOC.Core.CSR_Unit.csr_write_data[17].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$73136$lut\SOC.Core.CSR_Unit.csr_write_data[17].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$73136$lut\SOC.Core.CSR_Unit.csr_write_data[17].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$73136$lut\SOC.Core.CSR_Unit.csr_write_data[17].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$73136$lut\SOC.Core.CSR_Unit.csr_write_data[16].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$73136$lut\SOC.Core.CSR_Unit.csr_write_data[16].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$73136$lut\SOC.Core.CSR_Unit.csr_write_data[16].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$73136$lut\SOC.Core.CSR_Unit.csr_write_data[16].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$73136$lut\SOC.Core.CSR_Unit.csr_write_data[16].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$6095.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6095.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6095.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6095.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6095.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6065.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6065.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6065.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6065.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6065.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6058.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6058.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6058.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6058.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6058.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6004.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6004.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6004.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6004.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6004.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5234.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5234.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5234.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5234.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5234.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5234.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5234.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5228.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5228.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5228.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5228.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5228.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5228.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6114.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6114.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6114.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6114.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6114.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6114.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6107.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6107.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6107.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6107.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6107.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6082.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6082.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6082.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6082.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6082.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6082.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6075.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6075.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6075.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6075.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6075.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6425.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6425.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6425.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6425.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6425.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6425.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6207.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6207.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6207.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6207.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6207.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73452.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6017.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6017.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6017.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6017.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6017.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6432.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6432.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6432.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6432.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6432.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6432.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6361.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6361.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6361.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6361.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6361.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73436.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6354.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6354.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6354.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6354.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6354.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6337.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6337.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6337.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6337.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6337.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5029.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5029.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5029.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5029.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5029.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5029.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73407.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73407.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73407.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73407.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73407.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73407.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73407.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73411.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73411.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73411.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73411.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73411.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73411.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$73136$lut$aiger73135$5017.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5017.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$4980.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$4980.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$4980.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$4980.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$4980.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$4980.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73419.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73419.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73419.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73419.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73419.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73419.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73419.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$4949.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$4949.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$4922.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$4922.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$4915.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$4915.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$4915.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$4915.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$4915.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73422.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73422.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73422.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$73136$lut$aiger73135$4876.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73399.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73399.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73399.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$73136$lut$aiger73135$4904.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$4904.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$4852.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$73136$lut$aiger73135$4852.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$4852.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$4852.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$73136$lut$aiger73135$4852.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$4836.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$4836.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$4836.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$4836.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$4836.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$4836.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73427.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73427.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73427.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73427.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73427.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73427.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$73136$lut$aiger73135$4825.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$4814.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73431.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73431.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73431.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$73136$lut$aiger73135$4944.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$4776.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$4776.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$4776.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$4776.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$4776.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$4776.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$4755.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$4608.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$4608.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$4592.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$4592.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$4592.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$4592.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$4560.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$4555.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$4555.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$4555.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$4545.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$4525.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$4525.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$4520.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$4520.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$4520.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$4513.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$4513.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$4513.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$4513.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$4513.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$4501.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$4501.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$4501.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$4501.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$4501.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$4501.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$4501.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$4483.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$10048.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$10052.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$10126.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut\SOC.Core.CSR_Unit.csr_write_data[16].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$10175.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$10179.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$10340.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$10475.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$10584.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$10589.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$10610.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$10615.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$10802.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$10812.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$10856.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut\SOC.Core.CSR_Unit.csr_write_data[22].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$10932.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$10949.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$10969.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$10976.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$11001.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$11035.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$11072.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$11079.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$11090.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$11097.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$11131.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$11148.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$11165.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$11194.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$11216.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$11221.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut\SOC.Core.CSR_Unit.csr_write_data[24].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$11255.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$11305.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$11342.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$11349.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$11360.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$11367.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$11437.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$11447.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$11595.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$11617.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$11621.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$11632.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$11639.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$11650.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$11657.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$11689.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$11696.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$11725.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$11753.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$11760.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$11807.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$11814.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$11869.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$11924.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$11931.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$11980.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$11987.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$12037.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$12074.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$12081.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$12145.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$12182.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$12189.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$12200.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$12207.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$4755.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$4483.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$4483.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$4492.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$73136$lut$aiger73135$4501.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$4513.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$4520.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$4525.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$4533.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$73136$lut$aiger73135$4545.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$4545.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$4555.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$4560.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$4560.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$4567.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$73136$lut$aiger73135$4574.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$73136$lut$aiger73135$4574.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$73136$lut$aiger73135$4592.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$4600.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$4608.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$4608.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$4592.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$4641.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$4656.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$4692.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$4747.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$4755.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$4759.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$4776.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$4814.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$4814.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$4825.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$4825.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$4836.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73439.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$73136$lut$aiger73135$4852.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$73136$lut$aiger73135$4852.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$4868.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$4876.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$4876.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$4904.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$4908.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$4915.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$4932.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$4944.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$4949.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$4959.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$4944.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$4967.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$4980.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73411.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$73136$lut$aiger73135$5017.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5012.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5021.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5029.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$6095.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5066.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5083.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5083.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5106.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6107.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5123.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5149.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6004.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6075.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5166.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5183.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6058.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5200.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5228.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5238.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6354.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6337.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5269.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5269.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6361.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5290.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6207.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5307.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5307.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5328.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5345.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6017.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5375.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5423.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5444.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5499.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5560.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$73136$lut$aiger73135$5568.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5576.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5636.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5643.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5650.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5657.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5673.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5681.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5681.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5695.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5705.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5712.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5725.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5735.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut\SOC.Core.CSR_Unit.csr_write_data[17].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$5771.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$5779.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5622.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5812.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5829.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5841.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$5852.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5857.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$73136$lut$aiger73135$5871.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5881.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5906.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5916.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$73136$lut$aiger73135$5673.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5942.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$5983.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5990.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5990.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6004.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6017.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6032.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6043.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6051.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6058.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6065.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6065.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6075.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6082.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6095.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6107.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6114.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6125.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$6147.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$6164.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$6193.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6207.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6240.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$6240.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$6262.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$73136$lut$aiger73135$6280.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6285.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$6285.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$73136$lut$aiger73135$6299.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$6313.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6337.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6344.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6344.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6354.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6361.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6386.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6393.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6400.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6412.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6418.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$73136$lut$aiger73135$6425.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6432.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6448.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$6467.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6467.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6484.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6494.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6518.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$6526.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$6535.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$6543.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$6552.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$73136$lut$aiger73135$6552.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$5812.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6587.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6595.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$6609.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6655.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6672.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6707.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6718.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$6726.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$6735.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$73136$lut$aiger73135$6751.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$6762.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6774.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$73136$lut$aiger73135$6823.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6804.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6804.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6823.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6827.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$6835.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$73136$lut$aiger73135$6846.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6854.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$6868.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$6885.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$6894.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$73136$lut$aiger73135$6904.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6904.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6922.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$6930.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$5881.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6963.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$6989.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$6999.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$7005.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$7035.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$7044.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$73136$lut$aiger73135$6494.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$7073.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$7073.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$7086.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$7095.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$7114.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$7142.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$7176.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$7189.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$6484.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$7248.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$7273.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$7273.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$7283.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$73136$lut$aiger73135$7289.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$7297.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$6386.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$7332.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$7343.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$7350.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$73136$lut$aiger73135$7368.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$7406.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$7418.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$7448.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$7454.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$7392.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$7487.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$73136$lut$aiger73135$7518.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$7507.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$7536.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$7546.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$7572.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$7581.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$7676.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$7727.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$73136$lut$aiger73135$7751.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$7758.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$7766.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$7771.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$7775.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$7857.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$7925.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$7930.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$7934.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$7960.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$8146.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$8187.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$73136$lut$aiger73135$8200.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$8205.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$8213.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$8235.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$8242.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$8249.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$8258.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$8264.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$8264.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$8288.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$8346.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$8387.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$73136$lut$aiger73135$8427.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$8459.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$8472.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$8495.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$8500.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$8500.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$8507.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$8536.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$8619.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$73136$lut$aiger73135$8703.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$73136$lut$aiger73135$8754.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$8763.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$8822.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$8960.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$8998.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$9009.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$9029.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$9036.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$9096.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$9267.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$9305.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$9316.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$73136$lut$aiger73135$9316.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$9363.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$9518.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$73136$lut$aiger73135$9518.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$9528.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$9554.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$9554.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$9663.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$aiger73135$9786.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$4628.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$9829.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$9886.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73136$lut$auto$fsm_map.cc:170:map_fsm$2146[1].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$7815.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73136$lut$auto$rtlil.cc:2582:Mux$2656[25].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$73136$lut$auto$rtlil.cc:2582:Mux$2656[30].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$73136$lut\SOC.Core.CSR_Unit.csr_write_data[13].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$73136$lut\SOC.Core.CSR_Unit.csr_write_data[13].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$73136$lut\SOC.Core.CSR_Unit.csr_write_data[16].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$73136$lut\SOC.Core.CSR_Unit.csr_write_data[17].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$73136$lut\SOC.Core.CSR_Unit.csr_write_data[22].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$73136$lut\SOC.Core.CSR_Unit.csr_write_data[24].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$73136$lut\SOC.Core.CSR_Unit.csr_write_data[25].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$73136$lut\SOC.Core.CSR_Unit.csr_write_data[26].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$73136$lut\SOC.Core.CSR_Unit.csr_write_data[27].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$73136$lut\SOC.Core.CSR_Unit.csr_write_data[28].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$73136$lut\SOC.Core.CSR_Unit.csr_write_data[29].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$73136$lut\SOC.Core.CSR_Unit.csr_write_data[30].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$73136$lut\SOC.Core.CSR_Unit.csr_write_data[31].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73217.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73231.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73227.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73226.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73216.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73218.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73224.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$12106.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73386.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$73136$lut$aiger73135$7558.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73189.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73198.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73204.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73389.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73215.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73215.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73219.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73222.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73224.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73229.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73237.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73395.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73392.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73376.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73376.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73377.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73378.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73379.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73380.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73381.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73382.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73383.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73384.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73385.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73386.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73387.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73388.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73389.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73390.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73391.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73392.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73393.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73394.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73395.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73427.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$73136$lut$aiger73135$4922.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$73136$lut$aiger73135$4915.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Removed 0 unused cells and 6974 unused wires.

23.45. Executing AUTONAME pass.
Renamed 309167 objects in module top (311 iterations).
<suppressed ~11783 debug messages>

23.46. Executing HIERARCHY pass (managing design hierarchy).

23.46.1. Analyzing design hierarchy..
Top module:  \top

23.46.2. Analyzing design hierarchy..
Top module:  \top
Removed 0 unused modules.

23.47. Printing statistics.

=== top ===

   Number of wires:               5439
   Number of wire bits:          13284
   Number of public wires:        5439
   Number of public wire bits:   13284
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:               6888
     $_TBUF_                         6
     $scopeinfo                     30
     CCU2C                         345
     L6MUX21                       466
     LUT4                         4007
     PFUMX                        1010
     TRELLIS_DPR16X4               292
     TRELLIS_FF                    732

23.48. Executing CHECK pass (checking for obvious problems).
Checking module top...
Found and reported 0 problems.

23.49. Executing JSON backend.

Warnings: 213 unique messages, 214 total
End of script. Logfile hash: 3f888f8b63, CPU: user 7.99s system 0.08s, MEM: 222.99 MB peak
Yosys 0.38+120 (git sha1 1e42b4f0f, clang++ 14.0.0-1ubuntu1.1 -fPIC -Os)
Time spent: 40% 1x abc9_exe (5 sec), 11% 11x techmap (1 sec), ...
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (NextPNR)
[Pipeline] sh
+ /eda/oss-cad-suite/bin/nextpnr-ecp5 --json ./build/out.json --write ./build/out_pnr.json --45k --lpf Risco-5/fpga/ecp5/pinout.lpf --textcfg ./build/out.config --package CABGA381 --speed 6 --ignore-loops --lpf-allow-unconstrained
Info: constraining clock net 'clk' to 25.00 MHz

Info: Logic utilisation before packing:
Info:     Total LUT4s:      6449/43848    14%
Info:         logic LUTs:   4007/43848     9%
Info:         carry LUTs:    690/43848     1%
Info:           RAM LUTs:   1168/ 5481    21%
Info:          RAMW LUTs:    584/10962     5%

Info:      Total DFFs:       732/43848     1%

Info: Packing IOs..
Info: $gpios[5]$iobuf_i: gpios_$_TBUF__Y.Y
Info: pin 'gpios[5]$tr_io' constrained to Bel 'X0/Y23/PIOC'.
Info: $gpios[4]$iobuf_i: gpios_$_TBUF__Y_1.Y
Info: pin 'gpios[4]$tr_io' constrained to Bel 'X0/Y44/PIOA'.
Info: $gpios[3]$iobuf_i: gpios_$_TBUF__Y_2.Y
Info: pin 'gpios[3]$tr_io' constrained to Bel 'X0/Y23/PIOA'.
Info: $gpios[2]$iobuf_i: gpios_$_TBUF__Y_3.Y
Info: pin 'gpios[2]$tr_io' constrained to Bel 'X90/Y23/PIOD'.
Info: $gpios[1]$iobuf_i: gpios_$_TBUF__Y_4.Y
Info: pin 'gpios[1]$tr_io' constrained to Bel 'X0/Y14/PIOD'.
Info: $gpios[0]$iobuf_i: gpios_$_TBUF__Y_5.Y
Info: pin 'gpios[0]$tr_io' constrained to Bel 'X0/Y44/PIOB'.
Info: pin 'tx$tr_io' constrained to Bel 'X90/Y20/PIOC'.
Info: pin 'rx$tr_io' constrained to Bel 'X90/Y20/PIOA'.
Info: pin 'reset$tr_io' constrained to Bel 'X0/Y29/PIOA'.
Info: pin 'led[7]$tr_io' constrained to Bel 'X90/Y20/PIOD'.
Info: pin 'led[6]$tr_io' constrained to Bel 'X0/Y44/PIOD'.
Info: pin 'led[5]$tr_io' constrained to Bel 'X0/Y59/PIOA'.
Info: pin 'led[4]$tr_io' constrained to Bel 'X15/Y71/PIOB'.
Info: pin 'led[3]$tr_io' constrained to Bel 'X90/Y29/PIOC'.
Info: pin 'led[2]$tr_io' constrained to Bel 'X90/Y44/PIOB'.
Info: pin 'led[1]$tr_io' constrained to Bel 'X0/Y44/PIOC'.
Info: pin 'led[0]$tr_io' constrained to Bel 'X0/Y59/PIOC'.
Info: pin 'clk$tr_io' constrained to Bel 'X0/Y68/PIOC'.
Info: Packing constants..
Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info:     357 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info: Promoting globals...
Info:     promoting clock net clk$TRELLIS_IO_IN to global network
Info: Checksum: 0x4d5d563a

Info: Device utilisation:
Info: 	          TRELLIS_IO:    18/  245     7%
Info: 	                DCCA:     1/   56     1%
Info: 	              DP16KD:     0/  108     0%
Info: 	          MULT18X18D:     0/   72     0%
Info: 	              ALU54B:     0/   36     0%
Info: 	             EHXPLLL:     0/    4     0%
Info: 	             EXTREFB:     0/    2     0%
Info: 	                DCUA:     0/    2     0%
Info: 	           PCSCLKDIV:     0/    2     0%
Info: 	             IOLOGIC:     0/  160     0%
Info: 	            SIOLOGIC:     0/   85     0%
Info: 	                 GSR:     0/    1     0%
Info: 	               JTAGG:     0/    1     0%
Info: 	                OSCG:     0/    1     0%
Info: 	               SEDGA:     0/    1     0%
Info: 	                 DTR:     0/    1     0%
Info: 	             USRMCLK:     0/    1     0%
Info: 	             CLKDIVF:     0/    4     0%
Info: 	           ECLKSYNCB:     0/   10     0%
Info: 	             DLLDELD:     0/    8     0%
Info: 	              DDRDLL:     0/    4     0%
Info: 	             DQSBUFM:     0/   10     0%
Info: 	     TRELLIS_ECLKBUF:     0/    8     0%
Info: 	        ECLKBRIDGECS:     0/    2     0%
Info: 	                DCSC:     0/    2     0%
Info: 	          TRELLIS_FF:   732/43848     1%
Info: 	        TRELLIS_COMB:  6545/43848    14%
Info: 	        TRELLIS_RAMW:   292/ 5481     5%

Info: Placed 18 cells based on constraints.
Info: Creating initial analytic placement for 3228 cells, random placement wirelen = 301690.
Info:     at initial placer iter 0, wirelen = 3238
Info:     at initial placer iter 1, wirelen = 2353
Info:     at initial placer iter 2, wirelen = 2259
Info:     at initial placer iter 3, wirelen = 2808
Info: Running main analytical placer, max placement attempts per cell = 7197218.
Info:     at iteration #1, type ALL: wirelen solved = 3010, spread = 46535, legal = 46993; time = 0.17s
Info:     at iteration #2, type ALL: wirelen solved = 4710, spread = 39349, legal = 39998; time = 0.17s
Info:     at iteration #3, type ALL: wirelen solved = 6322, spread = 36713, legal = 37375; time = 0.17s
Info:     at iteration #4, type ALL: wirelen solved = 7805, spread = 39014, legal = 39597; time = 0.18s
Info:     at iteration #5, type ALL: wirelen solved = 8868, spread = 39429, legal = 39853; time = 0.16s
Info:     at iteration #6, type ALL: wirelen solved = 10935, spread = 36592, legal = 37163; time = 0.16s
Info:     at iteration #7, type ALL: wirelen solved = 11986, spread = 35279, legal = 36031; time = 0.16s
Info:     at iteration #8, type ALL: wirelen solved = 13152, spread = 32968, legal = 33871; time = 0.16s
Info:     at iteration #9, type ALL: wirelen solved = 13801, spread = 30919, legal = 32074; time = 0.16s
Info:     at iteration #10, type ALL: wirelen solved = 14539, spread = 30192, legal = 31282; time = 0.16s
Info:     at iteration #11, type ALL: wirelen solved = 15276, spread = 30852, legal = 31927; time = 0.16s
Info:     at iteration #12, type ALL: wirelen solved = 16617, spread = 30876, legal = 31611; time = 0.16s
Info:     at iteration #13, type ALL: wirelen solved = 16911, spread = 30331, legal = 31095; time = 0.16s
Info:     at iteration #14, type ALL: wirelen solved = 17423, spread = 29893, legal = 30604; time = 0.16s
Info:     at iteration #15, type ALL: wirelen solved = 18341, spread = 28740, legal = 29465; time = 0.15s
Info:     at iteration #16, type ALL: wirelen solved = 17235, spread = 28877, legal = 29767; time = 0.15s
Info:     at iteration #17, type ALL: wirelen solved = 18159, spread = 28851, legal = 29642; time = 0.15s
Info:     at iteration #18, type ALL: wirelen solved = 18107, spread = 28081, legal = 29074; time = 0.15s
Info:     at iteration #19, type ALL: wirelen solved = 18384, spread = 26825, legal = 28247; time = 0.15s
Info:     at iteration #20, type ALL: wirelen solved = 17749, spread = 25922, legal = 28327; time = 0.16s
Info:     at iteration #21, type ALL: wirelen solved = 17690, spread = 27825, legal = 28805; time = 0.16s
Info:     at iteration #22, type ALL: wirelen solved = 18457, spread = 26038, legal = 27516; time = 0.15s
Info:     at iteration #23, type ALL: wirelen solved = 18800, spread = 27089, legal = 28386; time = 0.15s
Info:     at iteration #24, type ALL: wirelen solved = 18714, spread = 28114, legal = 29063; time = 0.14s
Info:     at iteration #25, type ALL: wirelen solved = 19601, spread = 27938, legal = 29054; time = 0.14s
Info:     at iteration #26, type ALL: wirelen solved = 19295, spread = 27413, legal = 28546; time = 0.15s
Info:     at iteration #27, type ALL: wirelen solved = 19706, spread = 27644, legal = 28555; time = 0.14s
Info: HeAP Placer Time: 6.67s
Info:   of which solving equations: 3.79s
Info:   of which spreading cells: 0.56s
Info:   of which strict legalisation: 0.21s

Info: Running simulated annealing placer for refinement.
Info:   at iteration #1: temp = 0.000000, timing cost = 4891, wirelen = 27516
Info:   at iteration #5: temp = 0.000000, timing cost = 3343, wirelen = 24086
Info:   at iteration #10: temp = 0.000000, timing cost = 3452, wirelen = 23270
Info:   at iteration #15: temp = 0.000000, timing cost = 3432, wirelen = 22920
Info:   at iteration #20: temp = 0.000000, timing cost = 3345, wirelen = 22807
Info:   at iteration #25: temp = 0.000000, timing cost = 3521, wirelen = 22781
Info:   at iteration #26: temp = 0.000000, timing cost = 3209, wirelen = 22772 
Info: SA placement time 19.38s

Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 38.47 MHz (PASS at 25.00 MHz)

Info: Max delay <async>                           -> posedge $glbnet$clk$TRELLIS_IO_IN: 10.08 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async>                          : 10.92 ns

Info: Slack histogram:
Info:  legend: * represents 54 endpoint(s)
Info:          + represents [1,54) endpoint(s)
Info: [ 14009,  15271) |+
Info: [ 15271,  16533) |+
Info: [ 16533,  17795) |*+
Info: [ 17795,  19057) |**+
Info: [ 19057,  20319) |*******+
Info: [ 20319,  21581) |****+
Info: [ 21581,  22843) |*+
Info: [ 22843,  24105) |****+
Info: [ 24105,  25367) |***********+
Info: [ 25367,  26629) |*************************+
Info: [ 26629,  27891) |************************************************************ 
Info: [ 27891,  29153) |**************+
Info: [ 29153,  30415) |*****+
Info: [ 30415,  31677) |******+
Info: [ 31677,  32939) |+
Info: [ 32939,  34201) |+
Info: [ 34201,  35463) |*******+
Info: [ 35463,  36725) |*****+
Info: [ 36725,  37987) |****+
Info: [ 37987,  39249) |**+
Info: Checksum: 0x48d02b6f
Info: Routing globals...
Info:     routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0

Info: Routing..
Info: Setting up routing queue.
Info: Routing 28993 arcs.
Info:            |   (re-)routed arcs  |   delta    | remaining|       time spent     |
Info:    IterCnt |  w/ripup   wo/ripup |  w/r  wo/r |      arcs| batch(sec) total(sec)|
Info:       1000 |      116        883 |  116   883 |     28164|       0.63       0.63|
Info:       2000 |      220       1779 |  104   896 |     27424|       0.25       0.88|
Info:       3000 |      349       2650 |  129   871 |     26659|       0.25       1.13|
Info:       4000 |      514       3485 |  165   835 |     25913|       0.24       1.37|
Info:       5000 |      640       4359 |  126   874 |     25346|       0.22       1.59|
Info:       6000 |      785       5214 |  145   855 |     24546|       0.24       1.83|
Info:       7000 |      950       6049 |  165   835 |     23864|       0.25       2.08|
Info:       8000 |     1123       6876 |  173   827 |     23110|       0.23       2.30|
Info:       9000 |     1308       7691 |  185   815 |     22485|       0.24       2.55|
Info:      10000 |     1512       8487 |  204   796 |     21878|       0.25       2.80|
Info:      11000 |     1719       9280 |  207   793 |     21179|       0.25       3.05|
Info:      12000 |     1939      10060 |  220   780 |     20533|       0.23       3.28|
Info:      13000 |     2224      10775 |  285   715 |     19967|       0.27       3.56|
Info:      14000 |     2455      11544 |  231   769 |     19332|       0.26       3.82|
Info:      15000 |     2650      12349 |  195   805 |     18941|       0.23       4.05|
Info:      16000 |     2931      13068 |  281   719 |     18369|       0.28       4.33|
Info:      17000 |     3203      13796 |  272   728 |     17820|       0.31       4.65|
Info:      18000 |     3335      14664 |  132   868 |     17541|       0.27       4.92|
Info:      19000 |     3602      15397 |  267   733 |     16930|       0.29       5.20|
Info:      20000 |     3938      16061 |  336   664 |     16451|       0.30       5.51|
Info:      21000 |     4253      16746 |  315   685 |     15904|       0.29       5.80|
Info:      22000 |     4636      17363 |  383   617 |     15378|       0.31       6.11|
Info:      23000 |     5042      17957 |  406   594 |     14915|       0.31       6.42|
Info:      24000 |     5420      18579 |  378   622 |     14437|       0.30       6.72|
Info:      25000 |     5793      19206 |  373   627 |     13860|       0.32       7.04|
Info:      26000 |     6201      19798 |  408   592 |     13369|       0.31       7.34|
Info:      27000 |     6645      20354 |  444   556 |     12950|       0.31       7.66|
Info:      28000 |     7060      20939 |  415   585 |     12557|       0.31       7.96|
Info:      29000 |     7455      21544 |  395   605 |     12075|       0.30       8.27|
Info:      30000 |     7861      22138 |  406   594 |     11727|       0.33       8.60|
Info:      31000 |     8194      22757 |  333   619 |     11202|       0.29       8.89|
Info:      32000 |     8483      23369 |  289   612 |     10566|       0.21       9.10|
Info:      33000 |     8730      23939 |  247   570 |      9843|       0.19       9.29|
Info:      34000 |     9053      24451 |  323   512 |      9256|       0.22       9.52|
Info:      35000 |     9314      25103 |  261   652 |      9020|       0.22       9.74|
Info:      36000 |     9405      25999 |   91   896 |      8525|       0.24       9.98|
Info:      37000 |     9713      26632 |  308   633 |      7928|       0.25      10.23|
Info:      38000 |    10040      27224 |  327   592 |      7336|       0.24      10.46|
Info:      39000 |    10397      27792 |  357   568 |      6720|       0.25      10.72|
Info:      40000 |    10793      28354 |  396   562 |      6177|       0.29      11.00|
Info:      41000 |    10927      29189 |  134   835 |      5522|       0.21      11.21|
Info:      42000 |    10958      30138 |   31   949 |      4555|       0.08      11.29|
Info:      43000 |    10986      31107 |   28   969 |      3583|       0.07      11.36|
Info:      44000 |    11093      31989 |  107   882 |      2722|       0.14      11.50|
Info:      45000 |    11291      32788 |  198   799 |      1952|       0.24      11.75|
Info:      46000 |    11439      33528 |  148   740 |      1164|       0.26      12.01|
Info:      47000 |    11497      34221 |   58   693 |       230|       0.16      12.17|
Info:      47229 |    11497      34333 |    0   112 |         0|       0.07      12.24|
Info: Routing complete.
Info: Router1 time 12.24s
Info: Checksum: 0xb68d19ea

Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
Info: curr total
Info:  0.5  0.5  Source SOC.Core.instruction_register_TRELLIS_FF_Q_1.Q
Info:  1.6  2.1    Net SOC.Core.instruction_register[30] (26,24) -> (16,21)
Info:                Sink SOC.Core.Control_Unit.ir_write_LUT4_Z_D_LUT4_D_Z_PFUMX_Z_C0_PFUMX_C0_Z_LUT4_Z_C_L6MUX21_SD_2_Z_L6MUX21_D0_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.B
Info:                Defined in:
Info:                  Risco-5/src/core/core.v:50.12-50.32
Info:  0.4  2.5  Source SOC.Core.Control_Unit.ir_write_LUT4_Z_D_LUT4_D_Z_PFUMX_Z_C0_PFUMX_C0_Z_LUT4_Z_C_L6MUX21_SD_2_Z_L6MUX21_D0_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.OFX
Info:  0.0  2.5    Net SOC.Core.Control_Unit.ir_write_LUT4_Z_D_LUT4_D_Z_PFUMX_Z_C0_PFUMX_C0_Z_LUT4_Z_C_L6MUX21_SD_2_Z_L6MUX21_D0_Z_L6MUX21_Z_D1 (16,21) -> (16,21)
Info:                Sink SOC.Core.Control_Unit.ir_write_LUT4_Z_D_LUT4_D_Z_PFUMX_Z_C0_PFUMX_C0_Z_LUT4_Z_C_L6MUX21_SD_2_Z_L6MUX21_D0_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.FXB
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:141.38-141.40
Info:  0.2  2.8  Source SOC.Core.Control_Unit.ir_write_LUT4_Z_D_LUT4_D_Z_PFUMX_Z_C0_PFUMX_C0_Z_LUT4_Z_C_L6MUX21_SD_2_Z_L6MUX21_D0_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
Info:  1.0  3.7    Net SOC.Core.Control_Unit.ir_write_LUT4_Z_D_LUT4_D_Z_LUT4_Z_1_B_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_Z_2_D1_PFUMX_Z_ALUT_LUT4_Z_D[5] (16,21) -> (17,17)
Info:                Sink SOC.Core.Control_Unit.ir_write_LUT4_Z_D_LUT4_D_Z_LUT4_Z_1_B_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_Z_2_D1_PFUMX_Z_ALUT_LUT4_Z.M
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.3  4.0  Source SOC.Core.Control_Unit.ir_write_LUT4_Z_D_LUT4_D_Z_LUT4_Z_1_B_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_Z_2_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
Info:  1.0  5.0    Net SOC.Core.Control_Unit.ir_write_LUT4_Z_D_LUT4_D_Z_LUT4_Z_1_B_LUT4_C_Z[5] (17,17) -> (16,14)
Info:                Sink SOC.Core.Control_Unit.nextstate_PFUMX_Z_3_C0_LUT4_Z_B_LUT4_Z_1_D_L6MUX21_SD_2_Z_LUT4_B.D
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2  5.2  Source SOC.Core.Control_Unit.nextstate_PFUMX_Z_3_C0_LUT4_Z_B_LUT4_Z_1_D_L6MUX21_SD_2_Z_LUT4_B.F
Info:  0.7  5.9    Net SOC.Core.Alu.ALU_out_S_PFUMX_Z_2_C0_LUT4_Z_B_LUT4_Z_B_LUT4_Z_D[3] (16,14) -> (16,13)
Info:                Sink SOC.Core.Control_Unit.nextstate_PFUMX_Z_3_C0_LUT4_Z_B_LUT4_Z_1_D_L6MUX21_SD_Z_LUT4_B_Z_LUT4_C_Z_L6MUX21_Z_2_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.M
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.3  6.2  Source SOC.Core.Control_Unit.nextstate_PFUMX_Z_3_C0_LUT4_Z_B_LUT4_Z_1_D_L6MUX21_SD_Z_LUT4_B_Z_LUT4_C_Z_L6MUX21_Z_2_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.OFX
Info:  0.0  6.2    Net SOC.Core.Control_Unit.nextstate_PFUMX_Z_3_C0_LUT4_Z_B_LUT4_Z_1_D_L6MUX21_SD_Z_LUT4_B_Z_LUT4_C_Z_L6MUX21_Z_2_D1_L6MUX21_Z_D1 (16,13) -> (16,13)
Info:                Sink SOC.Core.Control_Unit.nextstate_PFUMX_Z_3_C0_LUT4_Z_B_LUT4_Z_1_D_L6MUX21_SD_Z_LUT4_B_Z_LUT4_C_Z_L6MUX21_Z_2_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.FXB
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:157.62-157.64
Info:  0.2  6.4  Source SOC.Core.Control_Unit.nextstate_PFUMX_Z_3_C0_LUT4_Z_B_LUT4_Z_1_D_L6MUX21_SD_Z_LUT4_B_Z_LUT4_C_Z_L6MUX21_Z_2_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
Info:  0.0  6.4    Net SOC.Core.Control_Unit.nextstate_PFUMX_Z_3_C0_LUT4_Z_B_LUT4_Z_1_D_L6MUX21_SD_Z_LUT4_B_Z_LUT4_C_Z_L6MUX21_Z_2_D1 (16,13) -> (16,13)
Info:                Sink SOC.Core.Control_Unit.nextstate_PFUMX_Z_3_C0_LUT4_Z_B_LUT4_Z_1_D_L6MUX21_SD_Z_LUT4_B_Z_LUT4_C_Z_L6MUX21_Z_2_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.FXB
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:157.70-157.72
Info:  0.2  6.7  Source SOC.Core.Control_Unit.nextstate_PFUMX_Z_3_C0_LUT4_Z_B_LUT4_Z_1_D_L6MUX21_SD_Z_LUT4_B_Z_LUT4_C_Z_L6MUX21_Z_2_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX
Info:  1.2  7.8    Net SOC.Core.Control_Unit.nextstate_PFUMX_Z_3_C0_LUT4_Z_B_LUT4_Z_1_D_L6MUX21_SD_Z_LUT4_B_Z_LUT4_C_Z[6] (16,13) -> (23,14)
Info:                Sink SOC.Core.Control_Unit.ir_write_LUT4_Z_D_LUT4_D_Z_PFUMX_Z_C0_PFUMX_C0_Z_LUT4_D_2_Z_LUT4_D_Z_L6MUX21_Z_2_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.M
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.3  8.1  Source SOC.Core.Control_Unit.ir_write_LUT4_Z_D_LUT4_D_Z_PFUMX_Z_C0_PFUMX_C0_Z_LUT4_D_2_Z_LUT4_D_Z_L6MUX21_Z_2_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX
Info:  1.5  9.6    Net SOC.Core.Alu.ALU_out_S_LUT4_Z_1_B_LUT4_Z_B[6] (23,14) -> (25,5)
Info:                Sink SOC.Core.Alu.ALU_out_S_PFUMX_Z_7_BLUT_LUT4_Z_D_LUT4_Z_C_L6MUX21_Z_1_D0_PFUMX_Z_ALUT_LUT4_Z_C_LUT4_D_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.M
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.3  9.9  Source SOC.Core.Alu.ALU_out_S_PFUMX_Z_7_BLUT_LUT4_Z_D_LUT4_Z_C_L6MUX21_Z_1_D0_PFUMX_Z_ALUT_LUT4_Z_C_LUT4_D_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX
Info:  0.9 10.7    Net SOC.Core.Alu.ALU_out_S_PFUMX_Z_7_BLUT_LUT4_Z_D_LUT4_Z_C_L6MUX21_Z_1_D0_PFUMX_Z_ALUT_LUT4_Z_C[4] (25,5) -> (25,4)
Info:                Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_9_A_LUT4_Z_2_C_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.C
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2 11.0  Source SOC.Core.Alu.ALU_out_S_LUT4_Z_9_A_LUT4_Z_2_C_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.F
Info:  0.0 11.0    Net SOC.Core.Alu.ALU_out_S_LUT4_Z_9_A_LUT4_Z_2_C_L6MUX21_Z_D0_PFUMX_Z_ALUT (25,4) -> (25,4)
Info:                Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_9_A_LUT4_Z_2_C_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z.F1
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:141.22-141.24
Info:  0.2 11.1  Source SOC.Core.Alu.ALU_out_S_LUT4_Z_9_A_LUT4_Z_2_C_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z.OFX
Info:  0.0 11.1    Net SOC.Core.Alu.ALU_out_S_LUT4_Z_9_A_LUT4_Z_2_C_L6MUX21_Z_D0 (25,4) -> (25,4)
Info:                Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_9_A_LUT4_Z_2_C_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.FXA
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:141.34-141.36
Info:  0.2 11.4  Source SOC.Core.Alu.ALU_out_S_LUT4_Z_9_A_LUT4_Z_2_C_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
Info:  0.4 11.8    Net SOC.Core.Alu.ALU_out_S_LUT4_Z_9_A_LUT4_Z_2_C[3] (25,4) -> (25,4)
Info:                Sink SOC.Core.Alu.ALU_out_S_L6MUX21_Z_3_D0_PFUMX_Z_C0_PFUMX_C0_Z_PFUMX_Z_1_C0_L6MUX21_SD_1_Z_LUT4_Z_1.D
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2 12.0  Source SOC.Core.Alu.ALU_out_S_L6MUX21_Z_3_D0_PFUMX_Z_C0_PFUMX_C0_Z_PFUMX_Z_1_C0_L6MUX21_SD_1_Z_LUT4_Z_1.F
Info:  1.4 13.4    Net SOC.Core.Alu.ALU_out_S_L6MUX21_Z_3_D0_PFUMX_Z_C0_PFUMX_C0_Z_PFUMX_Z_1_C0_L6MUX21_SD_1_Z[6] (25,4) -> (29,9)
Info:                Sink SOC.Core.Alu.ALU_out_S_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.M
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.3 13.6  Source SOC.Core.Alu.ALU_out_S_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX
Info:  1.4 15.0    Net SOC.Core.alu_out[27] (29,9) -> (25,21)
Info:                Sink SOC.Core.Alu.ALU_out_S_PFUMX_Z_7_C0_PFUMX_Z_C0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_LUT4_B_Z_PFUMX_Z_BLUT_LUT4_Z.M
Info:                Defined in:
Info:                  Risco-5/src/core/core.v:47.31-47.38
Info:  0.3 15.3  Source SOC.Core.Alu.ALU_out_S_PFUMX_Z_7_C0_PFUMX_Z_C0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_LUT4_B_Z_PFUMX_Z_BLUT_LUT4_Z.OFX
Info:  0.7 16.0    Net SOC.Core.Alu.ALU_out_S_PFUMX_Z_7_C0_PFUMX_Z_C0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_LUT4_B_Z[6] (25,21) -> (25,20)
Info:                Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_1_B_LUT4_A_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.M
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.3 16.2  Source SOC.Core.Alu.ALU_out_S_LUT4_Z_1_B_LUT4_A_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX
Info:  1.3 17.5    Net SOC.Core.Alu.ALU_out_S_LUT4_Z_1_B_LUT4_A_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z[5] (25,20) -> (25,9)
Info:                Sink SOC.Core.Pc.load_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.M
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.3 17.8  Source SOC.Core.Pc.load_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
Info:  0.0 17.8    Net SOC.Core.Pc.load_L6MUX21_Z_D1 (25,9) -> (25,9)
Info:                Sink SOC.Core.Pc.load_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.FXB
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:157.70-157.72
Info:  0.2 18.0  Source SOC.Core.Pc.load_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX
Info:  1.9 19.9    Net SOC.Core.pc_load (25,9) -> (27,25)
Info:                Sink SOC.Core.Pc.Output_TRELLIS_FF_Q_6.CE
Info:                Defined in:
Info:                  Risco-5/src/core/core.v:42.38-42.45
Info:  0.0 19.9  Setup SOC.Core.Pc.Output_TRELLIS_FF_Q_6.CE
Info: 5.1 ns logic, 14.8 ns routing

Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
Info: curr total
Info:  0.0  0.0  Source gpios[2]$tr_io.O
Info:  5.1  5.1    Net gpios[2]$TRELLIS_IO_IN (90,23) -> (13,21)
Info:                Sink SOC.GPIOS.Gpios[2].direction_LUT4_B.A
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:7.16-7.21
Info:  0.2  5.3  Source SOC.GPIOS.Gpios[2].direction_LUT4_B.F
Info:  0.0  5.3    Net SOC.GPIOS.Gpios[2].direction_LUT4_B_Z (13,21) -> (13,21)
Info:                Sink SOC.Core.read_data_LUT4_Z_19_B_PFUMX_Z_BLUT_LUT4_Z.F1
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:133.22-133.24
Info:  0.2  5.5  Source SOC.Core.read_data_LUT4_Z_19_B_PFUMX_Z_BLUT_LUT4_Z.OFX
Info:  1.0  6.5    Net SOC.Core.read_data_LUT4_Z_19_B[1] (13,21) -> (12,18)
Info:                Sink SOC.Core.read_data_LUT4_Z_19.B
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2  6.7  Source SOC.Core.read_data_LUT4_Z_19.F
Info:  0.4  7.1    Net SOC.read_data[2] (12,18) -> (12,18)
Info:                Sink SOC.Core.memory_register_TRELLIS_FF_Q_29.M
Info:                Defined in:
Info:                  Risco-5/src/peripheral/soc.v:21.34-21.43
Info:  0.0  7.1  Setup SOC.Core.memory_register_TRELLIS_FF_Q_29.M
Info: 0.6 ns logic, 6.5 ns routing

Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
Info: curr total
Info:  0.5  0.5  Source SOC.GPIOS.Gpios[2].direction_TRELLIS_FF_Q.Q
Info:  3.5  4.0    Net SOC.GPIOS.gpio_direction[2] (13,21) -> (65,21)
Info:                Sink SOC.GPIOS.Gpios[2].direction_LUT4_D.D
Info:                Defined in:
Info:                  Risco-5/src/peripheral/gpios.v:14.19-14.33
Info:  0.2  4.3  Source SOC.GPIOS.Gpios[2].direction_LUT4_D.F
Info:  1.8  6.1    Net gpios_$_TBUF__Y_3_E (65,21) -> (82,23)
Info:                Sink gpios[2]$tr_io$invert_T.A
Info:  0.2  6.3  Source gpios[2]$tr_io$invert_T.F
Info:  1.0  7.3    Net gpios[2]$tr_io$invert_T$conn$Z (82,23) -> (90,23)
Info:                Sink gpios[2]$tr_io.T
Info: 1.0 ns logic, 6.3 ns routing

Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 50.35 MHz (PASS at 25.00 MHz)

Info: Max delay <async>                           -> posedge $glbnet$clk$TRELLIS_IO_IN: 7.13 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async>                          : 7.31 ns

Info: Slack histogram:
Info:  legend: * represents 47 endpoint(s)
Info:          + represents [1,47) endpoint(s)
Info: [ 20139,  21085) |+
Info: [ 21085,  22031) |*****+
Info: [ 22031,  22977) |******+
Info: [ 22977,  23923) |**+
Info: [ 23923,  24869) |*+
Info: [ 24869,  25815) |*+
Info: [ 25815,  26761) |******+
Info: [ 26761,  27707) |**********+
Info: [ 27707,  28653) |******************+
Info: [ 28653,  29599) |************************************************************ 
Info: [ 29599,  30545) |*************************************+
Info: [ 30545,  31491) |+
Info: [ 31491,  32437) |***+
Info: [ 32437,  33383) |*******+
Info: [ 33383,  34329) |***+
Info: [ 34329,  35275) |**+
Info: [ 35275,  36221) |***+
Info: [ 36221,  37167) |*******+
Info: [ 37167,  38113) |******+
Info: [ 38113,  39059) |***+

Info: Program finished normally.
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (ECPPACK)
[Pipeline] sh
+ /eda/oss-cad-suite/bin/ecppack --compress --input ./build/out.config --bit ./build/out.bit
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (FPGA Flash)
[Pipeline] parallel
[Pipeline] { (Branch: openFPGAloader ECP5)
[Pipeline] { (Branch: openFPGAloader Tangnano 20k)
[Pipeline] stage
[Pipeline] { (openFPGAloader ECP5)
[Pipeline] stage
[Pipeline] { (openFPGAloader Tangnano 20k)
[Pipeline] script
[Pipeline] {
[Pipeline] script
[Pipeline] {
[Pipeline] lock
Trying to acquire lock on [ecp5]
Resource [ecp5] did not exist. Created.
Lock acquired on [ecp5]
[Pipeline] {
[Pipeline] lock
Trying to acquire lock on [tangnano20k]
Resource [tangnano20k] did not exist. Created.
Lock acquired on [tangnano20k]
[Pipeline] {
[Pipeline] echo
FPGA ECP5 Broqueada
[Pipeline] sh
[Pipeline] echo
FPGA TangNano Broqueada
[Pipeline] sh
+ /eda/oss-cad-suite/bin/openFPGALoader -b colorlight-i9 ./build/out.bit
empty
Found 1 compatible device:
	0x0d28 0x0204 0x3 DAPLink CMSIS-DAP
Open file: DONE
b3bdffff
Parse file: DONE
Enable configuration: DONE
SRAM erase: DONE
+ echo gravando na tang nano
gravando na tang nano
[Pipeline] }
Lock released on resource [tangnano20k]
[Pipeline] // lock
[Pipeline] }
[Pipeline] // script
[Pipeline] }
[Pipeline] // stage
[Pipeline] }

Loading: [======                                            ] 11.04%
Loading: [============                                      ] 22.07%
Loading: [=================                                 ] 33.11%
Loading: [=======================                           ] 44.15%
Loading: [============================                      ] 55.19%
Loading: [==================================                ] 66.22%
Loading: [=======================================           ] 77.26%
Loading: [=============================================     ] 88.30%
Loading: [==================================================] 99.33%
Loading: [==================================================] 100.00%
Done
Disable configuration: DONE
[Pipeline] }
Lock released on resource [ecp5]
[Pipeline] // lock
[Pipeline] }
[Pipeline] // script
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Testes)
[Pipeline] parallel
[Pipeline] { (Branch: ECP5 - Testes)
[Pipeline] { (Branch: TangNano - Testes)
[Pipeline] stage
[Pipeline] { (ECP5 - Testes)
[Pipeline] stage
[Pipeline] { (TangNano - Testes)
[Pipeline] script
[Pipeline] {
[Pipeline] script
[Pipeline] {
[Pipeline] echo
Rodando teste na ECP5
[Pipeline] lock
Trying to acquire lock on [ecp5]
Resource [ecp5] did not exist. Created.
Lock acquired on [ecp5]
[Pipeline] {
[Pipeline] echo
Rodando teste na tang nano
[Pipeline] lock
Trying to acquire lock on [tangnano20k]
Resource [tangnano20k] did not exist. Created.
Lock acquired on [tangnano20k]
[Pipeline] {
[Pipeline] echo
FPGA ECP5 Broqueada
[Pipeline] sh
[Pipeline] echo
FPGA TangNano Broqueada
[Pipeline] sh
+ echo testando na ecp5
testando na ecp5
[Pipeline] }
Lock released on resource [ecp5]
+ echo testando na tang nano
testando na tang nano
[Pipeline] // lock
[Pipeline] echo
ECP5 liberada
[Pipeline] }
[Pipeline] }
Lock released on resource [tangnano20k]
[Pipeline] // script
[Pipeline] // lock
[Pipeline] }
[Pipeline] echo
TangNano liberada
[Pipeline] }
[Pipeline] // stage
[Pipeline] // script
[Pipeline] }
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // node
[Pipeline] End of Pipeline
Finished: SUCCESS