Console Output
+ python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p SuperScalar-RISCV-CPU -b digilent_arty_a7_100t
[LOCK] Criado: run.lock
File 'processor_ci_defines.vh' generated for board: 'digilent_arty_a7_100t'.
Final configuration file generated at /var/jenkins_home/workspace/SuperScalar-RISCV-CPU/SuperScalar-RISCV-CPU/build_digilent_arty_a7_100t.tcl
[LOCK] Removido: run.lock
Makefile executed successfully.
Makefile output:
Building the Design...
/eda/vivado/Vivado/2023.2/bin/vivado -mode batch -nolog -nojournal -source /var/jenkins_home/workspace/SuperScalar-RISCV-CPU/SuperScalar-RISCV-CPU/build_digilent_arty_a7_100t.tcl
****** Vivado v2023.2 (64-bit)
**** SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023
**** IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
**** SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023
** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
** Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
source /var/jenkins_home/workspace/SuperScalar-RISCV-CPU/SuperScalar-RISCV-CPU/build_digilent_arty_a7_100t.tcl
# read_verilog -sv /eda/processor_ci/rtl/SuperScalar-RISCV-CPU.sv
read_verilog: Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1320.000 ; gain = 0.023 ; free physical = 1193 ; free virtual = 26976
# read_verilog /var/jenkins_home/workspace/SuperScalar-RISCV-CPU/SuperScalar-RISCV-CPU/rtl/alu.v
# read_verilog /var/jenkins_home/workspace/SuperScalar-RISCV-CPU/SuperScalar-RISCV-CPU/rtl/define.v
# read_verilog /var/jenkins_home/workspace/SuperScalar-RISCV-CPU/SuperScalar-RISCV-CPU/rtl/define_para.v
# read_verilog /var/jenkins_home/workspace/SuperScalar-RISCV-CPU/SuperScalar-RISCV-CPU/rtl/include_func.v
# read_verilog /var/jenkins_home/workspace/SuperScalar-RISCV-CPU/SuperScalar-RISCV-CPU/rtl/instrbits.v
# read_verilog /var/jenkins_home/workspace/SuperScalar-RISCV-CPU/SuperScalar-RISCV-CPU/rtl/instrman.v
# read_verilog /var/jenkins_home/workspace/SuperScalar-RISCV-CPU/SuperScalar-RISCV-CPU/rtl/lsu.v
# read_verilog /var/jenkins_home/workspace/SuperScalar-RISCV-CPU/SuperScalar-RISCV-CPU/rtl/membuf.v
# read_verilog /var/jenkins_home/workspace/SuperScalar-RISCV-CPU/SuperScalar-RISCV-CPU/rtl/mprf.v
# read_verilog /var/jenkins_home/workspace/SuperScalar-RISCV-CPU/SuperScalar-RISCV-CPU/rtl/mul.v
# read_verilog /var/jenkins_home/workspace/SuperScalar-RISCV-CPU/SuperScalar-RISCV-CPU/rtl/predictor.v
# read_verilog /var/jenkins_home/workspace/SuperScalar-RISCV-CPU/SuperScalar-RISCV-CPU/rtl/schedule.v
# read_verilog /var/jenkins_home/workspace/SuperScalar-RISCV-CPU/SuperScalar-RISCV-CPU/rtl/ssrv_top.v
# read_verilog /var/jenkins_home/workspace/SuperScalar-RISCV-CPU/SuperScalar-RISCV-CPU/rtl/sys_csr.v
# set_property include_dirs [list "/var/jenkins_home/workspace/SuperScalar-RISCV-CPU/SuperScalar-RISCV-CPU/rtl/" ] [get_filesets sources_1]
# read_verilog -sv /eda/processor-ci-controller/modules/uart.sv
# read_verilog /eda/processor-ci-controller/modules/UART/rtl/uart_rx.v
# read_verilog /eda/processor-ci-controller/modules/UART/rtl/uart_tx.v
# read_verilog -sv /eda/processor_ci/internal/ahblite_to_wishbone.sv
# read_verilog -sv /eda/processor_ci/internal/axi4_to_wishbone.sv
# read_verilog -sv /eda/processor_ci/internal/axi4lite_to_wishbone.sv
# read_verilog -sv /eda/processor-ci-controller/rtl/fifo.sv
# read_verilog -sv /eda/processor-ci-controller/rtl/reset.sv
# read_verilog -sv /eda/processor-ci-controller/rtl/clk_divider.sv
# read_verilog -sv /eda/processor-ci-controller/rtl/memory.sv
# read_verilog -sv /eda/processor-ci-controller/rtl/interpreter.sv
# read_verilog -sv /eda/processor-ci-controller/rtl/controller.sv
# read_verilog -sv /eda/processor-ci-controller/rtl/timer.sv
# read_verilog -sv /eda/processor_ci/internal/fpga_top.sv
# set_param general.maxThreads 16
# read_xdc "/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc"
# set_property PROCESSING_ORDER EARLY [get_files /eda/processor_ci/constraints/digilent_arty_a7_100t.xdc]
# synth_design -top "fpga_top" -part "xc7a100tcsg324-1"
Command: synth_design -top fpga_top -part xc7a100tcsg324-1
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a100t'
INFO: [Device 21-403] Loading part xc7a100tcsg324-1
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
INFO: [Synth 8-7075] Helper process launched with PID 1682510
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 2032.730 ; gain = 403.660 ; free physical = 233 ; free virtual = 26017
---------------------------------------------------------------------------------
WARNING: [Synth 8-6901] identifier 'wstrb' is used before its declaration [/eda/processor_ci/internal/ahblite_to_wishbone.sv:79]
WARNING: [Synth 8-6901] identifier 'timer_data_out' is used before its declaration [/eda/processor-ci-controller/rtl/controller.sv:149]
WARNING: [Synth 8-9535] ignoring re-definition of command line macro 'SYNTHESIS' [/eda/processor_ci/internal/fpga_top.sv:7]
WARNING: [Synth 8-11145] root scope declaration is not allowed in Verilog 95/2K mode [/var/jenkins_home/workspace/SuperScalar-RISCV-CPU/SuperScalar-RISCV-CPU/rtl/include_func.v:258]
WARNING: [Synth 8-11145] root scope declaration is not allowed in Verilog 95/2K mode [/var/jenkins_home/workspace/SuperScalar-RISCV-CPU/SuperScalar-RISCV-CPU/rtl/include_func.v:268]
WARNING: [Synth 8-11145] root scope declaration is not allowed in Verilog 95/2K mode [/var/jenkins_home/workspace/SuperScalar-RISCV-CPU/SuperScalar-RISCV-CPU/rtl/include_func.v:277]
WARNING: [Synth 8-11145] root scope declaration is not allowed in Verilog 95/2K mode [/var/jenkins_home/workspace/SuperScalar-RISCV-CPU/SuperScalar-RISCV-CPU/rtl/include_func.v:286]
WARNING: [Synth 8-11145] root scope declaration is not allowed in Verilog 95/2K mode [/var/jenkins_home/workspace/SuperScalar-RISCV-CPU/SuperScalar-RISCV-CPU/rtl/include_func.v:292]
WARNING: [Synth 8-11145] root scope declaration is not allowed in Verilog 95/2K mode [/var/jenkins_home/workspace/SuperScalar-RISCV-CPU/SuperScalar-RISCV-CPU/rtl/include_func.v:298]
WARNING: [Synth 8-11145] root scope declaration is not allowed in Verilog 95/2K mode [/var/jenkins_home/workspace/SuperScalar-RISCV-CPU/SuperScalar-RISCV-CPU/rtl/include_func.v:317]
WARNING: [Synth 8-6901] identifier 'PAYLOAD_BITS' is used before its declaration [/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:16]
WARNING: [Synth 8-6901] identifier 'PAYLOAD_BITS' is used before its declaration [/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:16]
INFO: [Synth 8-6157] synthesizing module 'fpga_top' [/eda/processor_ci/internal/fpga_top.sv:8]
INFO: [Synth 8-6157] synthesizing module 'processorci_top' [/eda/processor_ci/rtl/SuperScalar-RISCV-CPU.sv:9]
INFO: [Synth 8-6157] synthesizing module 'Controller' [/eda/processor-ci-controller/rtl/controller.sv:1]
Parameter CLK_FREQ bound to: 50000000 - type: integer
Parameter BIT_RATE bound to: 115200 - type: integer
Parameter PAYLOAD_BITS bound to: 8 - type: integer
Parameter BUFFER_SIZE bound to: 8 - type: integer
Parameter PULSE_CONTROL_BITS bound to: 32 - type: integer
Parameter BUS_WIDTH bound to: 32 - type: integer
Parameter WORD_SIZE_BY bound to: 4 - type: integer
Parameter ID bound to: 1095914585 - type: integer
Parameter RESET_CLK_CYCLES bound to: 20 - type: integer
Parameter MEMORY_FILE bound to: (null) - type: string
Parameter MEMORY_SIZE bound to: 8192 - type: integer
INFO: [Synth 8-6157] synthesizing module 'ClkDivider' [/eda/processor-ci-controller/rtl/clk_divider.sv:1]
Parameter COUNTER_BITS bound to: 32 - type: integer
Parameter PULSE_CONTROL_BITS bound to: 32 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'ClkDivider' (0#1) [/eda/processor-ci-controller/rtl/clk_divider.sv:1]
INFO: [Synth 8-6157] synthesizing module 'Interpreter' [/eda/processor-ci-controller/rtl/interpreter.sv:1]
Parameter CLK_FREQ bound to: 50000000 - type: integer
Parameter PULSE_CONTROL_BITS bound to: 32 - type: integer
Parameter BUS_WIDTH bound to: 32 - type: integer
Parameter ID bound to: 1095914585 - type: integer
Parameter RESET_CLK_CYCLES bound to: 20 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'Interpreter' (0#1) [/eda/processor-ci-controller/rtl/interpreter.sv:1]
INFO: [Synth 8-6157] synthesizing module 'UART' [/eda/processor-ci-controller/modules/uart.sv:1]
Parameter CLK_FREQ bound to: 50000000 - type: integer
Parameter BIT_RATE bound to: 115200 - type: integer
Parameter PAYLOAD_BITS bound to: 8 - type: integer
Parameter BUFFER_SIZE bound to: 8 - type: integer
Parameter WORD_SIZE_BY bound to: 4 - type: integer
INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/eda/processor-ci-controller/modules/uart.sv:66]
INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/eda/processor-ci-controller/modules/uart.sv:125]
INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/eda/processor-ci-controller/modules/uart.sv:199]
INFO: [Synth 8-226] default block is never used [/eda/processor-ci-controller/modules/uart.sv:199]
INFO: [Synth 8-6157] synthesizing module 'FIFO' [/eda/processor-ci-controller/rtl/fifo.sv:1]
Parameter DEPTH bound to: 8 - type: integer
Parameter WIDTH bound to: 8 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'FIFO' (0#1) [/eda/processor-ci-controller/rtl/fifo.sv:1]
INFO: [Synth 8-6157] synthesizing module 'uart_rx' [/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:9]
Parameter BIT_RATE bound to: 115200 - type: integer
Parameter CLK_HZ bound to: 50000000 - type: integer
Parameter PAYLOAD_BITS bound to: 8 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'uart_rx' (0#1) [/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:9]
INFO: [Synth 8-6157] synthesizing module 'uart_tx' [/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:10]
Parameter BIT_RATE bound to: 115200 - type: integer
Parameter CLK_HZ bound to: 50000000 - type: integer
Parameter PAYLOAD_BITS bound to: 8 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'uart_tx' (0#1) [/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:10]
INFO: [Synth 8-6155] done synthesizing module 'UART' (0#1) [/eda/processor-ci-controller/modules/uart.sv:1]
INFO: [Synth 8-6157] synthesizing module 'Memory' [/eda/processor-ci-controller/rtl/memory.sv:1]
Parameter MEMORY_FILE bound to: (null) - type: string
Parameter MEMORY_SIZE bound to: 8192 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'Memory' (0#1) [/eda/processor-ci-controller/rtl/memory.sv:1]
INFO: [Synth 8-6157] synthesizing module 'Timer' [/eda/processor-ci-controller/rtl/timer.sv:1]
INFO: [Synth 8-6155] done synthesizing module 'Timer' (0#1) [/eda/processor-ci-controller/rtl/timer.sv:1]
INFO: [Synth 8-6157] synthesizing module 'Memory__parameterized0' [/eda/processor-ci-controller/rtl/memory.sv:1]
Parameter MEMORY_SIZE bound to: 4096 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'Memory__parameterized0' (0#1) [/eda/processor-ci-controller/rtl/memory.sv:1]
INFO: [Synth 8-6155] done synthesizing module 'Controller' (0#1) [/eda/processor-ci-controller/rtl/controller.sv:1]
INFO: [Synth 8-6157] synthesizing module 'ssrv_top' [/var/jenkins_home/workspace/SuperScalar-RISCV-CPU/SuperScalar-RISCV-CPU/rtl/ssrv_top.v:20]
INFO: [Synth 8-6157] synthesizing module 'alu' [/var/jenkins_home/workspace/SuperScalar-RISCV-CPU/SuperScalar-RISCV-CPU/rtl/alu.v:20]
INFO: [Synth 8-226] default block is never used [/var/jenkins_home/workspace/SuperScalar-RISCV-CPU/SuperScalar-RISCV-CPU/rtl/alu.v:118]
INFO: [Synth 8-6155] done synthesizing module 'alu' (0#1) [/var/jenkins_home/workspace/SuperScalar-RISCV-CPU/SuperScalar-RISCV-CPU/rtl/alu.v:20]
INFO: [Synth 8-6157] synthesizing module 'mul' [/var/jenkins_home/workspace/SuperScalar-RISCV-CPU/SuperScalar-RISCV-CPU/rtl/mul.v:20]
INFO: [Synth 8-6155] done synthesizing module 'mul' (0#1) [/var/jenkins_home/workspace/SuperScalar-RISCV-CPU/SuperScalar-RISCV-CPU/rtl/mul.v:20]
INFO: [Synth 8-6157] synthesizing module 'instrman' [/var/jenkins_home/workspace/SuperScalar-RISCV-CPU/SuperScalar-RISCV-CPU/rtl/instrman.v:25]
INFO: [Synth 8-6155] done synthesizing module 'instrman' (0#1) [/var/jenkins_home/workspace/SuperScalar-RISCV-CPU/SuperScalar-RISCV-CPU/rtl/instrman.v:25]
INFO: [Synth 8-6157] synthesizing module 'predictor' [/var/jenkins_home/workspace/SuperScalar-RISCV-CPU/SuperScalar-RISCV-CPU/rtl/predictor.v:24]
INFO: [Synth 8-6155] done synthesizing module 'predictor' (0#1) [/var/jenkins_home/workspace/SuperScalar-RISCV-CPU/SuperScalar-RISCV-CPU/rtl/predictor.v:24]
INFO: [Synth 8-6157] synthesizing module 'instrbits' [/var/jenkins_home/workspace/SuperScalar-RISCV-CPU/SuperScalar-RISCV-CPU/rtl/instrbits.v:20]
INFO: [Synth 8-6155] done synthesizing module 'instrbits' (0#1) [/var/jenkins_home/workspace/SuperScalar-RISCV-CPU/SuperScalar-RISCV-CPU/rtl/instrbits.v:20]
INFO: [Synth 8-6157] synthesizing module 'schedule' [/var/jenkins_home/workspace/SuperScalar-RISCV-CPU/SuperScalar-RISCV-CPU/rtl/schedule.v:23]
INFO: [Synth 8-6155] done synthesizing module 'schedule' (0#1) [/var/jenkins_home/workspace/SuperScalar-RISCV-CPU/SuperScalar-RISCV-CPU/rtl/schedule.v:23]
INFO: [Synth 8-6157] synthesizing module 'mprf' [/var/jenkins_home/workspace/SuperScalar-RISCV-CPU/SuperScalar-RISCV-CPU/rtl/mprf.v:20]
INFO: [Synth 8-6155] done synthesizing module 'mprf' (0#1) [/var/jenkins_home/workspace/SuperScalar-RISCV-CPU/SuperScalar-RISCV-CPU/rtl/mprf.v:20]
INFO: [Synth 8-6157] synthesizing module 'membuf' [/var/jenkins_home/workspace/SuperScalar-RISCV-CPU/SuperScalar-RISCV-CPU/rtl/membuf.v:20]
INFO: [Synth 8-6155] done synthesizing module 'membuf' (0#1) [/var/jenkins_home/workspace/SuperScalar-RISCV-CPU/SuperScalar-RISCV-CPU/rtl/membuf.v:20]
INFO: [Synth 8-6157] synthesizing module 'lsu' [/var/jenkins_home/workspace/SuperScalar-RISCV-CPU/SuperScalar-RISCV-CPU/rtl/lsu.v:20]
INFO: [Synth 8-6155] done synthesizing module 'lsu' (0#1) [/var/jenkins_home/workspace/SuperScalar-RISCV-CPU/SuperScalar-RISCV-CPU/rtl/lsu.v:20]
INFO: [Synth 8-6157] synthesizing module 'sys_csr' [/var/jenkins_home/workspace/SuperScalar-RISCV-CPU/SuperScalar-RISCV-CPU/rtl/sys_csr.v:20]
INFO: [Synth 8-6155] done synthesizing module 'sys_csr' (0#1) [/var/jenkins_home/workspace/SuperScalar-RISCV-CPU/SuperScalar-RISCV-CPU/rtl/sys_csr.v:20]
INFO: [Synth 8-6155] done synthesizing module 'ssrv_top' (0#1) [/var/jenkins_home/workspace/SuperScalar-RISCV-CPU/SuperScalar-RISCV-CPU/rtl/ssrv_top.v:20]
INFO: [Synth 8-6155] done synthesizing module 'processorci_top' (0#1) [/eda/processor_ci/rtl/SuperScalar-RISCV-CPU.sv:9]
INFO: [Synth 8-6157] synthesizing module 'ResetBootSystem' [/eda/processor-ci-controller/rtl/reset.sv:1]
Parameter CYCLES bound to: 32'sb00000000000000000000000000010100
INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/eda/processor-ci-controller/rtl/reset.sv:32]
INFO: [Synth 8-6155] done synthesizing module 'ResetBootSystem' (0#1) [/eda/processor-ci-controller/rtl/reset.sv:1]
WARNING: [Synth 8-7071] port 'start' of module 'ResetBootSystem' is unconnected for instance 'ResetBootSystem' [/eda/processor_ci/internal/fpga_top.sv:98]
WARNING: [Synth 8-7071] port 'rst_o' of module 'ResetBootSystem' is unconnected for instance 'ResetBootSystem' [/eda/processor_ci/internal/fpga_top.sv:98]
WARNING: [Synth 8-7023] instance 'ResetBootSystem' of module 'ResetBootSystem' has 4 connections declared, but only 2 given [/eda/processor_ci/internal/fpga_top.sv:98]
INFO: [Synth 8-6155] done synthesizing module 'fpga_top' (0#1) [/eda/processor_ci/internal/fpga_top.sv:8]
WARNING: [Synth 8-3848] Net intr_o in module/entity Controller does not have driver. [/eda/processor-ci-controller/rtl/controller.sv:25]
WARNING: [Synth 8-6014] Unused sequential element mmbuf_pc_reg was removed. [/var/jenkins_home/workspace/SuperScalar-RISCV-CPU/SuperScalar-RISCV-CPU/rtl/membuf.v:182]
WARNING: [Synth 8-3848] Net mmbuf_int_pc in module/entity ssrv_top does not have driver. [/var/jenkins_home/workspace/SuperScalar-RISCV-CPU/SuperScalar-RISCV-CPU/rtl/ssrv_top.v:141]
WARNING: [Synth 8-3848] Net miso in module/entity processorci_top does not have driver. [/eda/processor_ci/rtl/SuperScalar-RISCV-CPU.sv:22]
WARNING: [Synth 8-7129] Port csr_instr[11] in module sys_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port csr_instr[10] in module sys_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port csr_instr[9] in module sys_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port csr_instr[8] in module sys_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port csr_instr[7] in module sys_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port csr_instr[6] in module sys_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port csr_instr[5] in module sys_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port csr_instr[4] in module sys_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port csr_instr[3] in module sys_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port csr_instr[2] in module sys_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port csr_instr[1] in module sys_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port csr_instr[0] in module sys_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port dmem_exception[1] in module sys_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port dmem_exception[0] in module sys_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port int_pc[31] in module sys_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port int_pc[30] in module sys_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port int_pc[29] in module sys_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port int_pc[28] in module sys_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port int_pc[27] in module sys_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port int_pc[26] in module sys_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port int_pc[25] in module sys_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port int_pc[24] in module sys_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port int_pc[23] in module sys_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port int_pc[22] in module sys_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port int_pc[21] in module sys_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port int_pc[20] in module sys_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port int_pc[19] in module sys_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port int_pc[18] in module sys_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port int_pc[17] in module sys_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port int_pc[16] in module sys_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port int_pc[15] in module sys_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port int_pc[14] in module sys_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port int_pc[13] in module sys_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port int_pc[12] in module sys_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port int_pc[11] in module sys_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port int_pc[10] in module sys_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port int_pc[9] in module sys_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port int_pc[8] in module sys_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port int_pc[7] in module sys_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port int_pc[6] in module sys_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port int_pc[5] in module sys_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port int_pc[4] in module sys_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port int_pc[3] in module sys_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port int_pc[2] in module sys_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port int_pc[1] in module sys_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port int_pc[0] in module sys_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port mem_busy in module sys_csr is either unconnected or has no load
WARNING: [Synth 8-7129] Port lsu_status in module membuf is either unconnected or has no load
WARNING: [Synth 8-7129] Port mem_pc[95] in module membuf is either unconnected or has no load
WARNING: [Synth 8-7129] Port mem_pc[94] in module membuf is either unconnected or has no load
WARNING: [Synth 8-7129] Port mem_pc[93] in module membuf is either unconnected or has no load
WARNING: [Synth 8-7129] Port mem_pc[92] in module membuf is either unconnected or has no load
WARNING: [Synth 8-7129] Port mem_pc[91] in module membuf is either unconnected or has no load
WARNING: [Synth 8-7129] Port mem_pc[90] in module membuf is either unconnected or has no load
WARNING: [Synth 8-7129] Port mem_pc[89] in module membuf is either unconnected or has no load
WARNING: [Synth 8-7129] Port mem_pc[88] in module membuf is either unconnected or has no load
WARNING: [Synth 8-7129] Port mem_pc[87] in module membuf is either unconnected or has no load
WARNING: [Synth 8-7129] Port mem_pc[86] in module membuf is either unconnected or has no load
WARNING: [Synth 8-7129] Port mem_pc[85] in module membuf is either unconnected or has no load
WARNING: [Synth 8-7129] Port mem_pc[84] in module membuf is either unconnected or has no load
WARNING: [Synth 8-7129] Port mem_pc[83] in module membuf is either unconnected or has no load
WARNING: [Synth 8-7129] Port mem_pc[82] in module membuf is either unconnected or has no load
WARNING: [Synth 8-7129] Port mem_pc[81] in module membuf is either unconnected or has no load
WARNING: [Synth 8-7129] Port mem_pc[80] in module membuf is either unconnected or has no load
WARNING: [Synth 8-7129] Port mem_pc[79] in module membuf is either unconnected or has no load
WARNING: [Synth 8-7129] Port mem_pc[78] in module membuf is either unconnected or has no load
WARNING: [Synth 8-7129] Port mem_pc[77] in module membuf is either unconnected or has no load
WARNING: [Synth 8-7129] Port mem_pc[76] in module membuf is either unconnected or has no load
WARNING: [Synth 8-7129] Port mem_pc[75] in module membuf is either unconnected or has no load
WARNING: [Synth 8-7129] Port mem_pc[74] in module membuf is either unconnected or has no load
WARNING: [Synth 8-7129] Port mem_pc[73] in module membuf is either unconnected or has no load
WARNING: [Synth 8-7129] Port mem_pc[72] in module membuf is either unconnected or has no load
WARNING: [Synth 8-7129] Port mem_pc[71] in module membuf is either unconnected or has no load
WARNING: [Synth 8-7129] Port mem_pc[70] in module membuf is either unconnected or has no load
WARNING: [Synth 8-7129] Port mem_pc[69] in module membuf is either unconnected or has no load
WARNING: [Synth 8-7129] Port mem_pc[68] in module membuf is either unconnected or has no load
WARNING: [Synth 8-7129] Port mem_pc[67] in module membuf is either unconnected or has no load
WARNING: [Synth 8-7129] Port mem_pc[66] in module membuf is either unconnected or has no load
WARNING: [Synth 8-7129] Port mem_pc[65] in module membuf is either unconnected or has no load
WARNING: [Synth 8-7129] Port mem_pc[64] in module membuf is either unconnected or has no load
WARNING: [Synth 8-7129] Port mem_pc[63] in module membuf is either unconnected or has no load
WARNING: [Synth 8-7129] Port mem_pc[62] in module membuf is either unconnected or has no load
WARNING: [Synth 8-7129] Port mem_pc[61] in module membuf is either unconnected or has no load
WARNING: [Synth 8-7129] Port mem_pc[60] in module membuf is either unconnected or has no load
WARNING: [Synth 8-7129] Port mem_pc[59] in module membuf is either unconnected or has no load
WARNING: [Synth 8-7129] Port mem_pc[58] in module membuf is either unconnected or has no load
WARNING: [Synth 8-7129] Port mem_pc[57] in module membuf is either unconnected or has no load
WARNING: [Synth 8-7129] Port mem_pc[56] in module membuf is either unconnected or has no load
WARNING: [Synth 8-7129] Port mem_pc[55] in module membuf is either unconnected or has no load
WARNING: [Synth 8-7129] Port mem_pc[54] in module membuf is either unconnected or has no load
WARNING: [Synth 8-7129] Port mem_pc[53] in module membuf is either unconnected or has no load
WARNING: [Synth 8-7129] Port mem_pc[52] in module membuf is either unconnected or has no load
WARNING: [Synth 8-7129] Port mem_pc[51] in module membuf is either unconnected or has no load
WARNING: [Synth 8-7129] Port mem_pc[50] in module membuf is either unconnected or has no load
WARNING: [Synth 8-7129] Port mem_pc[49] in module membuf is either unconnected or has no load
WARNING: [Synth 8-7129] Port mem_pc[48] in module membuf is either unconnected or has no load
WARNING: [Synth 8-7129] Port mem_pc[47] in module membuf is either unconnected or has no load
WARNING: [Synth 8-7129] Port mem_pc[46] in module membuf is either unconnected or has no load
WARNING: [Synth 8-7129] Port mem_pc[45] in module membuf is either unconnected or has no load
WARNING: [Synth 8-7129] Port mem_pc[44] in module membuf is either unconnected or has no load
INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2216.668 ; gain = 587.598 ; free physical = 175 ; free virtual = 25823
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2234.480 ; gain = 605.410 ; free physical = 175 ; free virtual = 25823
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2234.480 ; gain = 605.410 ; free physical = 175 ; free virtual = 25823
---------------------------------------------------------------------------------
Netlist sorting complete. Time (s): cpu = 00:00:00.22 ; elapsed = 00:00:00.21 . Memory (MB): peak = 2234.480 ; gain = 0.000 ; free physical = 164 ; free virtual = 25813
INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints
Initializing timing engine
Parsing XDC File [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc]
WARNING: [Vivado 12-507] No nets matched 'sck_IBUF'. [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc:112]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc:112]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
Finished Parsing XDC File [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc]
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/fpga_top_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/fpga_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Completed Processing XDC Constraints
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2371.230 ; gain = 0.000 ; free physical = 162 ; free virtual = 25784
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
Constraint Validation Runtime : Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2371.266 ; gain = 0.000 ; free physical = 162 ; free virtual = 25783
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:21 ; elapsed = 00:00:20 . Memory (MB): peak = 2371.266 ; gain = 742.195 ; free physical = 185 ; free virtual = 25779
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7a100tcsg324-1
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:21 ; elapsed = 00:00:20 . Memory (MB): peak = 2371.266 ; gain = 742.195 ; free physical = 185 ; free virtual = 25779
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:21 ; elapsed = 00:00:20 . Memory (MB): peak = 2371.266 ; gain = 742.195 ; free physical = 185 ; free virtual = 25779
---------------------------------------------------------------------------------
INFO: [Synth 8-802] inferred FSM for state register 'fsm_state_reg' in module 'uart_rx'
INFO: [Synth 8-802] inferred FSM for state register 'fsm_state_reg' in module 'uart_tx'
INFO: [Synth 8-802] inferred FSM for state register 'state_read_reg' in module 'UART'
INFO: [Synth 8-802] inferred FSM for state register 'state_write_reg' in module 'UART'
INFO: [Synth 8-802] inferred FSM for state register 'tx_read_fifo_state_reg' in module 'UART'
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'processorci_top'
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'ResetBootSystem'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
FSM_IDLE | 00 | 000
FSM_START | 11 | 001
FSM_RECV | 10 | 010
FSM_STOP | 01 | 011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'fsm_state_reg' using encoding 'sequential' in module 'uart_rx'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
FSM_IDLE | 00 | 000
FSM_START | 11 | 001
FSM_SEND | 10 | 010
FSM_STOP | 01 | 011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'fsm_state_reg' using encoding 'sequential' in module 'uart_tx'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
IDLE | 000 | 0000
READ | 001 | 0001
COPY_READ_BUFFER | 010 | 0100
WB | 011 | 0010
FINISH | 100 | 0011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_read_reg' using encoding 'sequential' in module 'UART'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
IDLE | 000 | 0000
COPY_WRITE_BUFFER | 001 | 0100
WRITE | 010 | 0101
WB | 011 | 0010
FINISH | 100 | 0011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_write_reg' using encoding 'sequential' in module 'UART'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
TX_FIFO_IDLE | 0001 | 00
TX_FIFO_READ_FIFO | 0010 | 01
TX_FIFO_WRITE_TX | 0100 | 10
TX_FIFO_WAIT | 1000 | 11
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'tx_read_fifo_state_reg' using encoding 'one-hot' in module 'UART'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
IDLE | 000000001 | 0000
READ_WB_1 | 000000010 | 0001
READ_NEXT_INSTR | 000000100 | 0010
READ_WB_2 | 000001000 | 0011
READ_NEXT_INSTR_2 | 000010000 | 0100
READ_WB_3 | 000100000 | 0101
READ_NEXT_INSTR_3 | 001000000 | 0110
READ_WB_4 | 010000000 | 0111
WB | 100000000 | 1000
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'processorci_top'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
INIT | 001 | 00
RESET_COUNTER | 010 | 01
IDLE | 100 | 10
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'ResetBootSystem'
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:27 ; elapsed = 00:00:26 . Memory (MB): peak = 2371.266 ; gain = 742.195 ; free physical = 170 ; free virtual = 25768
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Component Statistics
---------------------------------------------------------------------------------
Detailed RTL Component Info :
+---Adders :
2 Input 160 Bit Adders := 2
2 Input 80 Bit Adders := 2
2 Input 64 Bit Adders := 2
3 Input 33 Bit Adders := 3
2 Input 32 Bit Adders := 26
3 Input 32 Bit Adders := 3
4 Input 32 Bit Adders := 3
2 Input 24 Bit Adders := 2
2 Input 16 Bit Adders := 2
2 Input 10 Bit Adders := 2
2 Input 8 Bit Adders := 1
2 Input 7 Bit Adders := 2
65 Input 7 Bit Adders := 3
3 Input 6 Bit Adders := 1
2 Input 5 Bit Adders := 3
4 Input 5 Bit Adders := 1
3 Input 5 Bit Adders := 3
3 Input 4 Bit Adders := 25
11 Input 4 Bit Adders := 1
7 Input 4 Bit Adders := 1
8 Input 4 Bit Adders := 1
4 Input 4 Bit Adders := 4
2 Input 4 Bit Adders := 9
3 Input 3 Bit Adders := 50
4 Input 3 Bit Adders := 2
5 Input 3 Bit Adders := 1
6 Input 3 Bit Adders := 2
2 Input 3 Bit Adders := 15
2 Input 2 Bit Adders := 7
3 Input 2 Bit Adders := 3
4 Input 2 Bit Adders := 3
5 Input 2 Bit Adders := 2
6 Input 2 Bit Adders := 5
7 Input 2 Bit Adders := 1
2 Input 1 Bit Adders := 3
3 Input 1 Bit Adders := 3
+---XORs :
2 Input 32 Bit XORs := 6
2 Input 3 Bit XORs := 1
2 Input 1 Bit XORs := 8
+---Registers :
256 Bit Registers := 4
192 Bit Registers := 2
160 Bit Registers := 3
128 Bit Registers := 4
102 Bit Registers := 1
96 Bit Registers := 2
80 Bit Registers := 2
68 Bit Registers := 1
64 Bit Registers := 3
51 Bit Registers := 1
40 Bit Registers := 1
32 Bit Registers := 66
25 Bit Registers := 2
24 Bit Registers := 7
18 Bit Registers := 1
16 Bit Registers := 4
12 Bit Registers := 2
10 Bit Registers := 2
9 Bit Registers := 1
8 Bit Registers := 14
7 Bit Registers := 1
6 Bit Registers := 9
5 Bit Registers := 2
4 Bit Registers := 9
3 Bit Registers := 11
2 Bit Registers := 6
1 Bit Registers := 48
+---RAMs :
64K Bit (2048 X 32 bit) RAMs := 1
32K Bit (1024 X 32 bit) RAMs := 1
64 Bit (8 X 8 bit) RAMs := 2
+---Muxes :
2 Input 256 Bit Muxes := 3
2 Input 160 Bit Muxes := 3
2 Input 128 Bit Muxes := 3
9 Input 128 Bit Muxes := 2
2 Input 80 Bit Muxes := 2
3 Input 80 Bit Muxes := 1
2 Input 68 Bit Muxes := 1
2 Input 64 Bit Muxes := 2
4 Input 64 Bit Muxes := 1
48 Input 64 Bit Muxes := 2
2 Input 33 Bit Muxes := 3
2 Input 32 Bit Muxes := 181
7 Input 32 Bit Muxes := 4
4 Input 32 Bit Muxes := 12
5 Input 32 Bit Muxes := 2
9 Input 32 Bit Muxes := 1
2 Input 25 Bit Muxes := 4
3 Input 24 Bit Muxes := 1
2 Input 24 Bit Muxes := 1
48 Input 24 Bit Muxes := 1
2 Input 17 Bit Muxes := 4
2 Input 16 Bit Muxes := 4
2 Input 12 Bit Muxes := 1
2 Input 10 Bit Muxes := 15
2 Input 8 Bit Muxes := 14
48 Input 8 Bit Muxes := 2
2 Input 7 Bit Muxes := 21
24 Input 7 Bit Muxes := 1
2 Input 6 Bit Muxes := 2
3 Input 6 Bit Muxes := 1
2 Input 5 Bit Muxes := 116
6 Input 5 Bit Muxes := 8
12 Input 5 Bit Muxes := 12
15 Input 5 Bit Muxes := 4
3 Input 5 Bit Muxes := 1
2 Input 4 Bit Muxes := 31
16 Input 4 Bit Muxes := 1
9 Input 4 Bit Muxes := 1
2 Input 3 Bit Muxes := 53
15 Input 3 Bit Muxes := 8
6 Input 3 Bit Muxes := 1
8 Input 3 Bit Muxes := 4
5 Input 3 Bit Muxes := 4
3 Input 3 Bit Muxes := 1
2 Input 2 Bit Muxes := 43
4 Input 2 Bit Muxes := 10
3 Input 2 Bit Muxes := 2
48 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 205
5 Input 1 Bit Muxes := 43
27 Input 1 Bit Muxes := 12
15 Input 1 Bit Muxes := 12
13 Input 1 Bit Muxes := 4
12 Input 1 Bit Muxes := 20
14 Input 1 Bit Muxes := 8
3 Input 1 Bit Muxes := 10
4 Input 1 Bit Muxes := 8
48 Input 1 Bit Muxes := 22
9 Input 1 Bit Muxes := 5
---------------------------------------------------------------------------------
Finished RTL Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 240 (col length:80)
BRAMs: 270 (col length: RAMB18 80 RAMB36 40)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\gen_rbank[0].rbank_reg[0][0] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\gen_rbank[0].rbank_reg[0][1] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\gen_rbank[0].rbank_reg[0][2] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\gen_rbank[0].rbank_reg[0][3] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\gen_rbank[0].rbank_reg[0][4] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\gen_rbank[0].rbank_reg[0][5] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\gen_rbank[0].rbank_reg[0][6] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\gen_rbank[0].rbank_reg[0][7] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\gen_rbank[0].rbank_reg[0][8] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\gen_rbank[0].rbank_reg[0][9] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\gen_rbank[0].rbank_reg[0][10] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\gen_rbank[0].rbank_reg[0][11] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\gen_rbank[0].rbank_reg[0][12] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\gen_rbank[0].rbank_reg[0][13] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\gen_rbank[0].rbank_reg[0][14] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\gen_rbank[0].rbank_reg[0][15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\gen_rbank[0].rbank_reg[0][16] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\gen_rbank[0].rbank_reg[0][17] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\gen_rbank[0].rbank_reg[0][18] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\gen_rbank[0].rbank_reg[0][19] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\gen_rbank[0].rbank_reg[0][20] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\gen_rbank[0].rbank_reg[0][21] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\gen_rbank[0].rbank_reg[0][22] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\gen_rbank[0].rbank_reg[0][23] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\gen_rbank[0].rbank_reg[0][24] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\gen_rbank[0].rbank_reg[0][25] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\gen_rbank[0].rbank_reg[0][26] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\gen_rbank[0].rbank_reg[0][27] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\gen_rbank[0].rbank_reg[0][28] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\gen_rbank[0].rbank_reg[0][29] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\gen_rbank[0].rbank_reg[0][30] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\gen_rbank[0].rbank_reg[0][31] )
INFO: [Synth 8-3886] merging instance 'i_bits/dump_vld_reg[3]' (FDC) to 'i_bits/dump_length_reg[2]'
INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Synth 8-3886] merging instance 'gen_mul[2].i_mul/calc_a_pos_reg[5]' (FDCE) to 'gen_mul[2].i_mul/calc_b_pos_reg[5]'
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\gen_mul[2].i_mul /\calc_b_pos_reg[5] )
INFO: [Synth 8-3886] merging instance 'gen_mul[0].i_mul/calc_a_pos_reg[5]' (FDCE) to 'gen_mul[0].i_mul/calc_b_pos_reg[5]'
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\gen_mul[0].i_mul /\calc_b_pos_reg[5] )
INFO: [Synth 8-3886] merging instance 'gen_mul[1].i_mul/calc_a_pos_reg[5]' (FDCE) to 'gen_mul[1].i_mul/calc_b_pos_reg[5]'
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\gen_mul[1].i_mul /\calc_b_pos_reg[5] )
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:01:35 ; elapsed = 00:02:06 . Memory (MB): peak = 2371.266 ; gain = 742.195 ; free physical = 169 ; free virtual = 20001
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
ROM: Preliminary Mapping Report
+------------+---------------------+---------------+----------------+
|Module Name | RTL Object | Depth x Width | Implemented As |
+------------+---------------------+---------------+----------------+
|Interpreter | memory_mux_selector | 256x1 | LUT |
|predictor | predict_bit0 | 32x1 | LUT |
|predictor | predict_bit1 | 32x1 | LUT |
|predictor | predict_bit2 | 32x1 | LUT |
|predictor | predict_bit3 | 32x1 | LUT |
|predictor | predict_bit4 | 32x1 | LUT |
|predictor | predict_bit5 | 32x1 | LUT |
|predictor | predict_bit6 | 32x1 | LUT |
|predictor | predict_bit7 | 32x1 | LUT |
|predictor | predict_bit8 | 32x1 | LUT |
|predictor | predict_bit9 | 32x1 | LUT |
|predictor | predict_bit10 | 32x1 | LUT |
|predictor | predict_bit11 | 32x1 | LUT |
|predictor | predict_bit12 | 32x1 | LUT |
|predictor | predict_bit13 | 32x1 | LUT |
|predictor | predict_bit14 | 32x1 | LUT |
|predictor | predict_bit | 32x1 | LUT |
|predictor | predict_bit0 | 32x1 | LUT |
|predictor | predict_bit1 | 32x1 | LUT |
|predictor | predict_bit2 | 32x1 | LUT |
|predictor | predict_bit3 | 32x1 | LUT |
|predictor | predict_bit4 | 32x1 | LUT |
|predictor | predict_bit5 | 32x1 | LUT |
|predictor | predict_bit6 | 32x1 | LUT |
|predictor | predict_bit7 | 32x1 | LUT |
|predictor | predict_bit8 | 32x1 | LUT |
|predictor | predict_bit9 | 32x1 | LUT |
|predictor | predict_bit10 | 32x1 | LUT |
|predictor | predict_bit11 | 32x1 | LUT |
|predictor | predict_bit12 | 32x1 | LUT |
|predictor | predict_bit13 | 32x1 | LUT |
|predictor | predict_bit14 | 32x1 | LUT |
|predictor | predict_bit | 32x1 | LUT |
|Interpreter | memory_mux_selector | 256x1 | LUT |
+------------+---------------------+---------------+----------------+
Distributed RAM: Preliminary Mapping Report (see note below)
+------------+------------------------------------------+-----------+----------------------+------------------+
|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
+------------+------------------------------------------+-----------+----------------------+------------------+
|fpga_top | u_Controller/Uart/tx_fifo/memory_reg | Implied | 8 x 8 | RAM32M x 2 |
|fpga_top | u_Controller/Uart/rx_fifo/memory_reg | Implied | 8 x 8 | RAM32M x 2 |
|fpga_top | u_Controller/Core_Memory/memory_reg | Implied | 2 K x 32 | RAM256X1S x 256 |
|fpga_top | u_Controller/Core_Data_Memory/memory_reg | Implied | 1 K x 32 | RAM256X1S x 128 |
+------------+------------------------------------------+-----------+----------------------+------------------+
Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once.
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:01:40 ; elapsed = 00:02:12 . Memory (MB): peak = 2371.266 ; gain = 742.195 ; free physical = 161 ; free virtual = 19994
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:02:01 ; elapsed = 00:02:33 . Memory (MB): peak = 2371.266 ; gain = 742.195 ; free physical = 165 ; free virtual = 20001
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
Distributed RAM: Final Mapping Report
+------------+------------------------------------------+-----------+----------------------+------------------+
|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
+------------+------------------------------------------+-----------+----------------------+------------------+
|fpga_top | u_Controller/Uart/tx_fifo/memory_reg | Implied | 8 x 8 | RAM32M x 2 |
|fpga_top | u_Controller/Uart/rx_fifo/memory_reg | Implied | 8 x 8 | RAM32M x 2 |
|fpga_top | u_Controller/Core_Memory/memory_reg | Implied | 2 K x 32 | RAM256X1S x 256 |
|fpga_top | u_Controller/Core_Data_Memory/memory_reg | Implied | 1 K x 32 | RAM256X1S x 128 |
+------------+------------------------------------------+-----------+----------------------+------------------+
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:02:08 ; elapsed = 00:02:48 . Memory (MB): peak = 2371.266 ; gain = 742.195 ; free physical = 163 ; free virtual = 19815
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
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Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:02:16 ; elapsed = 00:02:56 . Memory (MB): peak = 2371.266 ; gain = 742.195 ; free physical = 158 ; free virtual = 19808
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:02:16 ; elapsed = 00:02:56 . Memory (MB): peak = 2371.266 ; gain = 742.195 ; free physical = 158 ; free virtual = 19808
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:02:18 ; elapsed = 00:02:59 . Memory (MB): peak = 2371.266 ; gain = 742.195 ; free physical = 166 ; free virtual = 19809
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:02:19 ; elapsed = 00:02:59 . Memory (MB): peak = 2371.266 ; gain = 742.195 ; free physical = 166 ; free virtual = 19809
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:02:22 ; elapsed = 00:03:02 . Memory (MB): peak = 2371.266 ; gain = 742.195 ; free physical = 176 ; free virtual = 19809
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:02:22 ; elapsed = 00:03:02 . Memory (MB): peak = 2371.266 ; gain = 742.195 ; free physical = 176 ; free virtual = 19810
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------
Report BlackBoxes:
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+
Report Cell Usage:
+------+----------+------+
| |Cell |Count |
+------+----------+------+
|1 |BUFG | 3|
|2 |CARRY4 | 517|
|3 |LUT1 | 433|
|4 |LUT2 | 2145|
|5 |LUT3 | 3734|
|6 |LUT4 | 3404|
|7 |LUT5 | 6291|
|8 |LUT6 | 15669|
|9 |MUXF7 | 1104|
|10 |MUXF8 | 9|
|11 |RAM256X1S | 384|
|12 |RAM32M | 2|
|13 |RAM32X1D | 4|
|14 |FDCE | 5049|
|15 |FDPE | 2|
|16 |FDRE | 894|
|17 |FDSE | 4|
|18 |IBUF | 2|
|19 |OBUF | 2|
|20 |OBUFT | 1|
+------+----------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:02:22 ; elapsed = 00:03:02 . Memory (MB): peak = 2371.266 ; gain = 742.195 ; free physical = 178 ; free virtual = 19811
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 106 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:02:18 ; elapsed = 00:03:00 . Memory (MB): peak = 2371.266 ; gain = 605.410 ; free physical = 6670 ; free virtual = 26303
Synthesis Optimization Complete : Time (s): cpu = 00:02:25 ; elapsed = 00:03:05 . Memory (MB): peak = 2371.266 ; gain = 742.195 ; free physical = 6676 ; free virtual = 26303
INFO: [Project 1-571] Translating synthesized netlist
Netlist sorting complete. Time (s): cpu = 00:00:00.23 ; elapsed = 00:00:00.22 . Memory (MB): peak = 2371.266 ; gain = 0.000 ; free physical = 6665 ; free virtual = 26292
INFO: [Netlist 29-17] Analyzing 2020 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc]
WARNING: [Vivado 12-507] No nets matched 'sck_IBUF'. [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc:112]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc:112]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
Finished Parsing XDC File [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2459.273 ; gain = 0.000 ; free physical = 6666 ; free virtual = 26293
INFO: [Project 1-111] Unisim Transformation Summary:
A total of 390 instances were transformed.
RAM256X1S => RAM256X1S (MUXF7(x2), MUXF8, RAMS64E(x4)): 384 instances
RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 2 instances
RAM32X1D => RAM32X1D (RAMD32(x2)): 4 instances
Synth Design complete | Checksum: 7301d2c4
INFO: [Common 17-83] Releasing license: Synthesis
124 Infos, 121 Warnings, 2 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:02:37 ; elapsed = 00:03:16 . Memory (MB): peak = 2459.309 ; gain = 1139.309 ; free physical = 6666 ; free virtual = 26293
INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 8337.196; main = 1858.905; forked = 6846.293
INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 13299.574; main = 2459.277; forked = 10952.352
# opt_design
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command opt_design
Starting DRC Task
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.58 . Memory (MB): peak = 2523.305 ; gain = 63.996 ; free physical = 6666 ; free virtual = 26293
Starting Cache Timing Information Task
INFO: [Timing 38-35] Done setting XDC timing constraints.
Ending Cache Timing Information Task | Checksum: 215899fca
Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 2620.117 ; gain = 96.812 ; free physical = 6635 ; free virtual = 26262
Starting Logic Optimization Task
Phase 1 Initialization
Phase 1.1 Core Generation And Design Setup
Phase 1.1 Core Generation And Design Setup | Checksum: 215899fca
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2862.055 ; gain = 0.000 ; free physical = 6359 ; free virtual = 25986
Phase 1.2 Setup Constraints And Sort Netlist
Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 215899fca
Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2862.055 ; gain = 0.000 ; free physical = 6359 ; free virtual = 25986
Phase 1 Initialization | Checksum: 215899fca
Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2862.055 ; gain = 0.000 ; free physical = 6359 ; free virtual = 25986
Phase 2 Timer Update And Timing Data Collection
Phase 2.1 Timer Update
Phase 2.1 Timer Update | Checksum: 215899fca
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.42 . Memory (MB): peak = 2862.055 ; gain = 0.000 ; free physical = 6359 ; free virtual = 25986
Phase 2.2 Timing Data Collection
Phase 2.2 Timing Data Collection | Checksum: 215899fca
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.48 . Memory (MB): peak = 2862.055 ; gain = 0.000 ; free physical = 6359 ; free virtual = 25986
Phase 2 Timer Update And Timing Data Collection | Checksum: 215899fca
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.48 . Memory (MB): peak = 2862.055 ; gain = 0.000 ; free physical = 6359 ; free virtual = 25986
Phase 3 Retarget
INFO: [Opt 31-1566] Pulled 69 inverters resulting in an inversion of 1138 pins
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 3 Retarget | Checksum: 27bf452c6
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2862.055 ; gain = 0.000 ; free physical = 6342 ; free virtual = 25969
Retarget | Checksum: 27bf452c6
INFO: [Opt 31-389] Phase Retarget created 32 cells and removed 228 cells
Phase 4 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 4 Constant propagation | Checksum: 2243f8e31
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 2862.055 ; gain = 0.000 ; free physical = 6345 ; free virtual = 25972
Constant propagation | Checksum: 2243f8e31
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
Phase 5 Sweep
Phase 5 Sweep | Checksum: 23474fa3c
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 2862.055 ; gain = 0.000 ; free physical = 6345 ; free virtual = 25972
Sweep | Checksum: 23474fa3c
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 1 cells
Phase 6 BUFG optimization
Phase 6 BUFG optimization | Checksum: 23474fa3c
Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2894.070 ; gain = 32.016 ; free physical = 6345 ; free virtual = 25972
BUFG optimization | Checksum: 23474fa3c
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
Phase 7 Shift Register Optimization
INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
Phase 7 Shift Register Optimization | Checksum: 23474fa3c
Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2894.070 ; gain = 32.016 ; free physical = 6345 ; free virtual = 25972
Shift Register Optimization | Checksum: 23474fa3c
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
Phase 8 Post Processing Netlist
Phase 8 Post Processing Netlist | Checksum: 23474fa3c
Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2894.070 ; gain = 32.016 ; free physical = 6345 ; free virtual = 25972
Post Processing Netlist | Checksum: 23474fa3c
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
Phase 9 Finalization
Phase 9.1 Finalizing Design Cores and Updating Shapes
Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 264cdd3e2
Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 2894.070 ; gain = 32.016 ; free physical = 6345 ; free virtual = 25972
Phase 9.2 Verifying Netlist Connectivity
Starting Connectivity Check Task
Time (s): cpu = 00:00:00.1 ; elapsed = 00:00:00.09 . Memory (MB): peak = 2894.070 ; gain = 0.000 ; free physical = 6345 ; free virtual = 25972
Phase 9.2 Verifying Netlist Connectivity | Checksum: 264cdd3e2
Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 2894.070 ; gain = 32.016 ; free physical = 6345 ; free virtual = 25972
Phase 9 Finalization | Checksum: 264cdd3e2
Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 2894.070 ; gain = 32.016 ; free physical = 6345 ; free virtual = 25972
Opt_design Change Summary
=========================
-------------------------------------------------------------------------------------------------------------------------
| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
-------------------------------------------------------------------------------------------------------------------------
| Retarget | 32 | 228 | 0 |
| Constant propagation | 0 | 0 | 0 |
| Sweep | 0 | 1 | 0 |
| BUFG optimization | 0 | 0 | 0 |
| Shift Register Optimization | 0 | 0 | 0 |
| Post Processing Netlist | 0 | 0 | 0 |
-------------------------------------------------------------------------------------------------------------------------
Ending Logic Optimization Task | Checksum: 264cdd3e2
Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 2894.070 ; gain = 32.016 ; free physical = 6345 ; free virtual = 25972
INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8
Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2894.070 ; gain = 0.000 ; free physical = 6345 ; free virtual = 25972
Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
Ending Power Optimization Task | Checksum: 264cdd3e2
Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2894.070 ; gain = 0.000 ; free physical = 6345 ; free virtual = 25972
Starting Final Cleanup Task
Ending Final Cleanup Task | Checksum: 264cdd3e2
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2894.070 ; gain = 0.000 ; free physical = 6345 ; free virtual = 25972
Starting Netlist Obfuscation Task
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2894.070 ; gain = 0.000 ; free physical = 6345 ; free virtual = 25972
Ending Netlist Obfuscation Task | Checksum: 264cdd3e2
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2894.070 ; gain = 0.000 ; free physical = 6345 ; free virtual = 25972
INFO: [Common 17-83] Releasing license: Implementation
19 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:09 . Memory (MB): peak = 2894.070 ; gain = 434.762 ; free physical = 6345 ; free virtual = 25972
# place_design
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-83] Releasing license: Implementation
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs
Starting Placer Task
Phase 1 Placer Initialization
Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2926.086 ; gain = 0.000 ; free physical = 6350 ; free virtual = 25977
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1a8dd822c
Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2926.086 ; gain = 0.000 ; free physical = 6350 ; free virtual = 25977
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2926.086 ; gain = 0.000 ; free physical = 6350 ; free virtual = 25977
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 8f7540b8
Time (s): cpu = 00:00:06 ; elapsed = 00:00:02 . Memory (MB): peak = 2926.086 ; gain = 0.000 ; free physical = 6349 ; free virtual = 25976
Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: 11d8a6454
Time (s): cpu = 00:00:26 ; elapsed = 00:00:08 . Memory (MB): peak = 2933.113 ; gain = 7.027 ; free physical = 6339 ; free virtual = 25966
Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: 11d8a6454
Time (s): cpu = 00:00:26 ; elapsed = 00:00:08 . Memory (MB): peak = 2933.113 ; gain = 7.027 ; free physical = 6339 ; free virtual = 25966
Phase 1 Placer Initialization | Checksum: 11d8a6454
Time (s): cpu = 00:00:26 ; elapsed = 00:00:08 . Memory (MB): peak = 2933.113 ; gain = 7.027 ; free physical = 6339 ; free virtual = 25966
Phase 2 Global Placement
Phase 2.1 Floorplanning
Phase 2.1 Floorplanning | Checksum: 157e11878
Time (s): cpu = 00:00:27 ; elapsed = 00:00:08 . Memory (MB): peak = 2933.113 ; gain = 7.027 ; free physical = 6329 ; free virtual = 25956
Phase 2.2 Update Timing before SLR Path Opt
Phase 2.2 Update Timing before SLR Path Opt | Checksum: 114a8198c
Time (s): cpu = 00:00:27 ; elapsed = 00:00:08 . Memory (MB): peak = 2933.113 ; gain = 7.027 ; free physical = 6337 ; free virtual = 25964
Phase 2.3 Post-Processing in Floorplanning
Phase 2.3 Post-Processing in Floorplanning | Checksum: 114a8198c
Time (s): cpu = 00:00:27 ; elapsed = 00:00:08 . Memory (MB): peak = 2933.113 ; gain = 7.027 ; free physical = 6334 ; free virtual = 25961
Phase 2.4 Global Placement Core
Phase 2.4.1 UpdateTiming Before Physical Synthesis
Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 9cf4924d
Time (s): cpu = 00:00:56 ; elapsed = 00:00:18 . Memory (MB): peak = 2933.113 ; gain = 7.027 ; free physical = 6353 ; free virtual = 25981
Phase 2.4.2 Physical Synthesis In Placer
INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 1036 LUT instances to create LUTNM shape
INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0
INFO: [Physopt 32-1138] End 1 Pass. Optimized 338 nets or LUTs. Breaked 0 LUT, combined 338 existing LUTs and moved 0 existing LUT
INFO: [Physopt 32-65] No nets found for high-fanout optimization.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found. Shift Register to Pipeline Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found. URAM Register Optimization was not performed.
INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2933.113 ; gain = 0.000 ; free physical = 6352 ; free virtual = 25980
Summary of Physical Synthesis Optimizations
============================================
-----------------------------------------------------------------------------------------------------------------------------------------------------------
| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |
-----------------------------------------------------------------------------------------------------------------------------------------------------------
| LUT Combining | 0 | 338 | 338 | 0 | 1 | 00:00:02 |
| Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| Shift Register to Pipeline | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| URAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| Total | 0 | 338 | 338 | 0 | 4 | 00:00:02 |
-----------------------------------------------------------------------------------------------------------------------------------------------------------
Phase 2.4.2 Physical Synthesis In Placer | Checksum: 1195accf7
Time (s): cpu = 00:00:59 ; elapsed = 00:00:20 . Memory (MB): peak = 2933.113 ; gain = 7.027 ; free physical = 6330 ; free virtual = 25958
Phase 2.4 Global Placement Core | Checksum: 15a173b0f
Time (s): cpu = 00:01:02 ; elapsed = 00:00:21 . Memory (MB): peak = 2933.113 ; gain = 7.027 ; free physical = 6331 ; free virtual = 25970
Phase 2 Global Placement | Checksum: 15a173b0f
Time (s): cpu = 00:01:02 ; elapsed = 00:00:21 . Memory (MB): peak = 2933.113 ; gain = 7.027 ; free physical = 6331 ; free virtual = 25970
Phase 3 Detail Placement
Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: 129928a1b
Time (s): cpu = 00:01:03 ; elapsed = 00:00:21 . Memory (MB): peak = 2933.113 ; gain = 7.027 ; free physical = 6330 ; free virtual = 25970
Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 10f252707
Time (s): cpu = 00:01:03 ; elapsed = 00:00:22 . Memory (MB): peak = 2933.113 ; gain = 7.027 ; free physical = 6330 ; free virtual = 25970
Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 11518face
Time (s): cpu = 00:01:04 ; elapsed = 00:00:22 . Memory (MB): peak = 2933.113 ; gain = 7.027 ; free physical = 6330 ; free virtual = 25970
Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: eb57f2a2
Time (s): cpu = 00:01:04 ; elapsed = 00:00:22 . Memory (MB): peak = 2933.113 ; gain = 7.027 ; free physical = 6330 ; free virtual = 25970
Phase 3.5 Small Shape Detail Placement
Phase 3.5 Small Shape Detail Placement | Checksum: 13732aca5
Time (s): cpu = 00:01:15 ; elapsed = 00:00:32 . Memory (MB): peak = 2933.113 ; gain = 7.027 ; free physical = 6323 ; free virtual = 25963
Phase 3.6 Re-assign LUT pins
Phase 3.6 Re-assign LUT pins | Checksum: 128822570
Time (s): cpu = 00:01:17 ; elapsed = 00:00:35 . Memory (MB): peak = 2933.113 ; gain = 7.027 ; free physical = 6322 ; free virtual = 25962
Phase 3.7 Pipeline Register Optimization
Phase 3.7 Pipeline Register Optimization | Checksum: 151414dbc
Time (s): cpu = 00:01:17 ; elapsed = 00:00:35 . Memory (MB): peak = 2933.113 ; gain = 7.027 ; free physical = 6322 ; free virtual = 25962
Phase 3 Detail Placement | Checksum: 151414dbc
Time (s): cpu = 00:01:17 ; elapsed = 00:00:35 . Memory (MB): peak = 2933.113 ; gain = 7.027 ; free physical = 6322 ; free virtual = 25962
Phase 4 Post Placement Optimization and Clean-Up
Phase 4.1 Post Commit Optimization
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 4.1.1 Post Placement Optimization
Post Placement Optimization Initialization | Checksum: 10fcdcb9b
Phase 4.1.1.1 BUFG Insertion
Starting Physical Synthesis Task
Phase 1 Physical Synthesis Initialization
INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=8.860 | TNS=0.000 |
Phase 1 Physical Synthesis Initialization | Checksum: 18a930f6a
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.44 . Memory (MB): peak = 2933.113 ; gain = 0.000 ; free physical = 6312 ; free virtual = 25952
INFO: [Place 46-33] Processed net ptop/rst, BUFG insertion was skipped due to placement/routing conflicts.
INFO: [Place 46-56] BUFG insertion identified 1 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 1, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0.
Ending Physical Synthesis Task | Checksum: 18a930f6a
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 2933.113 ; gain = 0.000 ; free physical = 6310 ; free virtual = 25950
Phase 4.1.1.1 BUFG Insertion | Checksum: 10fcdcb9b
Time (s): cpu = 00:01:42 ; elapsed = 00:00:42 . Memory (MB): peak = 2933.113 ; gain = 7.027 ; free physical = 6309 ; free virtual = 25949
Phase 4.1.1.2 Post Placement Timing Optimization
INFO: [Place 30-746] Post Placement Timing Summary WNS=8.860. For the most accurate timing information please run report_timing.
Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 1c6b6e320
Time (s): cpu = 00:01:43 ; elapsed = 00:00:42 . Memory (MB): peak = 2933.113 ; gain = 7.027 ; free physical = 6310 ; free virtual = 25950
Time (s): cpu = 00:01:43 ; elapsed = 00:00:42 . Memory (MB): peak = 2933.113 ; gain = 7.027 ; free physical = 6310 ; free virtual = 25950
Phase 4.1 Post Commit Optimization | Checksum: 1c6b6e320
Time (s): cpu = 00:01:43 ; elapsed = 00:00:42 . Memory (MB): peak = 2933.113 ; gain = 7.027 ; free physical = 6310 ; free virtual = 25950
Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: 1c6b6e320
Time (s): cpu = 00:01:43 ; elapsed = 00:00:43 . Memory (MB): peak = 2933.113 ; gain = 7.027 ; free physical = 6310 ; free virtual = 25950
Phase 4.3 Placer Reporting
Phase 4.3.1 Print Estimated Congestion
INFO: [Place 30-612] Post-Placement Estimated Congestion
____________________________________________________
| | Global Congestion | Short Congestion |
| Direction | Region Size | Region Size |
|___________|___________________|___________________|
| North| 1x1| 4x4|
|___________|___________________|___________________|
| South| 2x2| 2x2|
|___________|___________________|___________________|
| East| 1x1| 1x1|
|___________|___________________|___________________|
| West| 1x1| 1x1|
|___________|___________________|___________________|
Phase 4.3.1 Print Estimated Congestion | Checksum: 1c6b6e320
Time (s): cpu = 00:01:43 ; elapsed = 00:00:43 . Memory (MB): peak = 2933.113 ; gain = 7.027 ; free physical = 6310 ; free virtual = 25950
Phase 4.3 Placer Reporting | Checksum: 1c6b6e320
Time (s): cpu = 00:01:44 ; elapsed = 00:00:43 . Memory (MB): peak = 2933.113 ; gain = 7.027 ; free physical = 6310 ; free virtual = 25950
Phase 4.4 Final Placement Cleanup
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2933.113 ; gain = 0.000 ; free physical = 6310 ; free virtual = 25950
Time (s): cpu = 00:01:44 ; elapsed = 00:00:43 . Memory (MB): peak = 2933.113 ; gain = 7.027 ; free physical = 6310 ; free virtual = 25950
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 20992412c
Time (s): cpu = 00:01:44 ; elapsed = 00:00:43 . Memory (MB): peak = 2933.113 ; gain = 7.027 ; free physical = 6310 ; free virtual = 25950
Ending Placer Task | Checksum: 1117e1bc0
Time (s): cpu = 00:01:44 ; elapsed = 00:00:43 . Memory (MB): peak = 2933.113 ; gain = 7.027 ; free physical = 6310 ; free virtual = 25950
30 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
place_design: Time (s): cpu = 00:01:47 ; elapsed = 00:00:44 . Memory (MB): peak = 2933.113 ; gain = 39.043 ; free physical = 6310 ; free virtual = 25950
# report_utilization -hierarchical -file digilent_arty_a7_utilization_hierarchical_place.rpt
# report_utilization -file digilent_arty_a7_utilization_place.rpt
# report_io -file digilent_arty_a7_io.rpt
report_io: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.06 . Memory (MB): peak = 2933.113 ; gain = 0.000 ; free physical = 6312 ; free virtual = 25952
# report_control_sets -verbose -file digilent_arty_a7_control_sets.rpt
report_control_sets: Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2933.113 ; gain = 0.000 ; free physical = 6311 ; free virtual = 25952
# report_clock_utilization -file digilent_arty_a7_clock_utilization.rpt
# route_design
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command route_design
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs
Phase 1 Build RT Design
Checksum: PlaceDB: be14924a ConstDB: 0 ShapeSum: 53698976 RouteDB: 0
Post Restoration Checksum: NetGraph: 5290a606 | NumContArr: bcdc5d51 | Constraints: c2a8fa9d | Timing: c2a8fa9d
Phase 1 Build RT Design | Checksum: 294bef891
Time (s): cpu = 00:00:55 ; elapsed = 00:00:29 . Memory (MB): peak = 2989.141 ; gain = 0.000 ; free physical = 6246 ; free virtual = 25887
Phase 2 Router Initialization
Phase 2.1 Fix Topology Constraints
Phase 2.1 Fix Topology Constraints | Checksum: 294bef891
Time (s): cpu = 00:00:55 ; elapsed = 00:00:29 . Memory (MB): peak = 2989.141 ; gain = 0.000 ; free physical = 6245 ; free virtual = 25886
Phase 2.2 Pre Route Cleanup
Phase 2.2 Pre Route Cleanup | Checksum: 294bef891
Time (s): cpu = 00:00:55 ; elapsed = 00:00:29 . Memory (MB): peak = 2989.141 ; gain = 0.000 ; free physical = 6245 ; free virtual = 25886
Number of Nodes with overlaps = 0
Phase 2.3 Update Timing
Phase 2.3 Update Timing | Checksum: 1d76b6c78
Time (s): cpu = 00:01:19 ; elapsed = 00:00:35 . Memory (MB): peak = 2989.141 ; gain = 0.000 ; free physical = 6209 ; free virtual = 25851
INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.782 | TNS=0.000 | WHS=0.001 | THS=0.000 |
Router Utilization Summary
Global Vertical Routing Utilization = 0.00474387 %
Global Horizontal Routing Utilization = 0.00362319 %
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
Number of Failed Nets = 31904
(Failed Nets is the sum of unrouted and partially routed nets)
Number of Unrouted Nets = 31867
Number of Partially Routed Nets = 37
Number of Node Overlaps = 33
Phase 2 Router Initialization | Checksum: 1f96bb7f3
Time (s): cpu = 00:01:30 ; elapsed = 00:00:37 . Memory (MB): peak = 3000.707 ; gain = 11.566 ; free physical = 6193 ; free virtual = 25835
Phase 3 Initial Routing
Phase 3.1 Global Routing
Phase 3.1 Global Routing | Checksum: 1f96bb7f3
Time (s): cpu = 00:01:30 ; elapsed = 00:00:37 . Memory (MB): peak = 3000.707 ; gain = 11.566 ; free physical = 6193 ; free virtual = 25835
Phase 3.2 Initial Net Routing
Phase 3.2 Initial Net Routing | Checksum: 20b1720ee
Time (s): cpu = 00:01:43 ; elapsed = 00:00:41 . Memory (MB): peak = 3028.207 ; gain = 39.066 ; free physical = 6182 ; free virtual = 25824
Phase 3 Initial Routing | Checksum: 20b1720ee
Time (s): cpu = 00:01:44 ; elapsed = 00:00:41 . Memory (MB): peak = 3028.207 ; gain = 39.066 ; free physical = 6182 ; free virtual = 25824
Phase 4 Rip-up And Reroute
Phase 4.1 Global Iteration 0
Number of Nodes with overlaps = 4798
Number of Nodes with overlaps = 13
Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=7.933 | TNS=0.000 | WHS=N/A | THS=N/A |
Phase 4.1 Global Iteration 0 | Checksum: 2617a5df2
Time (s): cpu = 00:02:15 ; elapsed = 00:00:53 . Memory (MB): peak = 3028.207 ; gain = 39.066 ; free physical = 6162 ; free virtual = 25804
Phase 4 Rip-up And Reroute | Checksum: 2617a5df2
Time (s): cpu = 00:02:15 ; elapsed = 00:00:53 . Memory (MB): peak = 3028.207 ; gain = 39.066 ; free physical = 6162 ; free virtual = 25804
Phase 5 Delay and Skew Optimization
Phase 5.1 Delay CleanUp
Phase 5.1 Delay CleanUp | Checksum: 2617a5df2
Time (s): cpu = 00:02:15 ; elapsed = 00:00:53 . Memory (MB): peak = 3028.207 ; gain = 39.066 ; free physical = 6157 ; free virtual = 25799
Phase 5.2 Clock Skew Optimization
Phase 5.2 Clock Skew Optimization | Checksum: 2617a5df2
Time (s): cpu = 00:02:15 ; elapsed = 00:00:53 . Memory (MB): peak = 3028.207 ; gain = 39.066 ; free physical = 6156 ; free virtual = 25798
Phase 5 Delay and Skew Optimization | Checksum: 2617a5df2
Time (s): cpu = 00:02:15 ; elapsed = 00:00:54 . Memory (MB): peak = 3028.207 ; gain = 39.066 ; free physical = 6154 ; free virtual = 25796
Phase 6 Post Hold Fix
Phase 6.1 Hold Fix Iter
Phase 6.1.1 Update Timing
Phase 6.1.1 Update Timing | Checksum: 2c32e29df
Time (s): cpu = 00:02:17 ; elapsed = 00:00:54 . Memory (MB): peak = 3028.207 ; gain = 39.066 ; free physical = 6150 ; free virtual = 25792
INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.029 | TNS=0.000 | WHS=0.719 | THS=0.000 |
Phase 6.1 Hold Fix Iter | Checksum: 2c32e29df
Time (s): cpu = 00:02:17 ; elapsed = 00:00:54 . Memory (MB): peak = 3028.207 ; gain = 39.066 ; free physical = 6150 ; free virtual = 25792
Phase 6 Post Hold Fix | Checksum: 2c32e29df
Time (s): cpu = 00:02:18 ; elapsed = 00:00:54 . Memory (MB): peak = 3028.207 ; gain = 39.066 ; free physical = 6150 ; free virtual = 25792
Phase 7 Route finalize
Router Utilization Summary
Global Vertical Routing Utilization = 8.9869 %
Global Horizontal Routing Utilization = 10.9008 %
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
Number of Failed Nets = 0
(Failed Nets is the sum of unrouted and partially routed nets)
Number of Unrouted Nets = 0
Number of Partially Routed Nets = 0
Number of Node Overlaps = 0
Phase 7 Route finalize | Checksum: 2c32e29df
Time (s): cpu = 00:02:18 ; elapsed = 00:00:54 . Memory (MB): peak = 3028.207 ; gain = 39.066 ; free physical = 6150 ; free virtual = 25792
Phase 8 Verifying routed nets
Verification completed successfully
Phase 8 Verifying routed nets | Checksum: 2c32e29df
Time (s): cpu = 00:02:18 ; elapsed = 00:00:55 . Memory (MB): peak = 3028.207 ; gain = 39.066 ; free physical = 6150 ; free virtual = 25792
Phase 9 Depositing Routes
Phase 9 Depositing Routes | Checksum: 2a89f1911
Time (s): cpu = 00:02:25 ; elapsed = 00:00:58 . Memory (MB): peak = 3028.207 ; gain = 39.066 ; free physical = 6148 ; free virtual = 25790
Phase 10 Post Router Timing
INFO: [Route 35-57] Estimated Timing Summary | WNS=8.029 | TNS=0.000 | WHS=0.719 | THS=0.000 |
INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
Phase 10 Post Router Timing | Checksum: 2a89f1911
Time (s): cpu = 00:02:26 ; elapsed = 00:00:58 . Memory (MB): peak = 3028.207 ; gain = 39.066 ; free physical = 6148 ; free virtual = 25790
INFO: [Route 35-16] Router Completed Successfully
Phase 11 Post-Route Event Processing
Phase 11 Post-Route Event Processing | Checksum: 14a369434
Time (s): cpu = 00:02:27 ; elapsed = 00:00:59 . Memory (MB): peak = 3028.207 ; gain = 39.066 ; free physical = 6148 ; free virtual = 25789
Ending Routing Task | Checksum: 14a369434
Time (s): cpu = 00:02:28 ; elapsed = 00:01:00 . Memory (MB): peak = 3028.207 ; gain = 39.066 ; free physical = 6148 ; free virtual = 25790
Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
12 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:02:33 ; elapsed = 00:01:03 . Memory (MB): peak = 3028.207 ; gain = 39.066 ; free physical = 6148 ; free virtual = 25790
# report_timing_summary -no_header -no_detailed_paths
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------
Enable Multi Corner Analysis : Yes
Enable Pessimism Removal : Yes
Pessimism Removal Resolution : Nearest Common Node
Enable Input Delay Default Clock : No
Enable Preset / Clear Arcs : No
Disable Flight Delays : No
Ignore I/O Paths : No
Timing Early Launch at Borrowing Latches : No
Borrow Time for Max Delay Exceptions : Yes
Merge Timing Exceptions : Yes
Inter-SLR Compensation : Conservative
Corner Analyze Analyze
Name Max Paths Min Paths
------ --------- ---------
Slow Yes Yes
Fast Yes Yes
------------------------------------------------------------------------------------------------
| Report Methodology
| ------------------
------------------------------------------------------------------------------------------------
No report available as report_methodology has not been run prior. Run report_methodology on the current design for the summary of methodology violations.
check_timing report
Table of Contents
-----------------
1. checking no_clock (174644)
2. checking constant_clock (0)
3. checking pulse_width_clock (0)
4. checking unconstrained_internal_endpoints (29717)
5. checking no_input_delay (1)
6. checking no_output_delay (1)
7. checking multiple_clock (0)
8. checking generated_clocks (0)
9. checking loops (0)
10. checking partial_input_delay (0)
11. checking partial_output_delay (0)
12. checking latch_loops (0)
1. checking no_clock (174644)
-----------------------------
There are 7508 register/latch pins with no clock driven by root clock pin: clk_o_reg/Q (HIGH)
There are 5223 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[0]/Q (HIGH)
There are 5223 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[10]/Q (HIGH)
There are 5223 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[11]/Q (HIGH)
There are 5223 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[12]/Q (HIGH)
There are 5223 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[13]/Q (HIGH)
There are 5223 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[14]/Q (HIGH)
There are 5223 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[15]/Q (HIGH)
There are 5223 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[16]/Q (HIGH)
There are 5223 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[17]/Q (HIGH)
There are 5223 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[18]/Q (HIGH)
There are 5223 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[19]/Q (HIGH)
There are 5223 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[1]/Q (HIGH)
There are 5223 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[20]/Q (HIGH)
There are 5223 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[21]/Q (HIGH)
There are 5223 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[22]/Q (HIGH)
There are 5223 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[23]/Q (HIGH)
There are 5223 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[24]/Q (HIGH)
There are 5223 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[25]/Q (HIGH)
There are 5223 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[26]/Q (HIGH)
There are 5223 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[27]/Q (HIGH)
There are 5223 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[28]/Q (HIGH)
There are 5223 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[29]/Q (HIGH)
There are 5223 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[2]/Q (HIGH)
There are 5223 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[30]/Q (HIGH)
There are 5223 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[31]/Q (HIGH)
There are 5223 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[3]/Q (HIGH)
There are 5223 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[4]/Q (HIGH)
There are 5223 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[5]/Q (HIGH)
There are 5223 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[6]/Q (HIGH)
There are 5223 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[7]/Q (HIGH)
There are 5223 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[8]/Q (HIGH)
There are 5223 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[9]/Q (HIGH)
2. checking constant_clock (0)
------------------------------
There are 0 register/latch pins with constant_clock.
3. checking pulse_width_clock (0)
---------------------------------
There are 0 register/latch pins which need pulse_width check
4. checking unconstrained_internal_endpoints (29717)
----------------------------------------------------
There are 29717 pins that are not constrained for maximum delay. (HIGH)
There are 0 pins that are not constrained for maximum delay due to constant clock.
5. checking no_input_delay (1)
------------------------------
There is 1 input port with no input delay specified. (HIGH)
There are 0 input ports with no input delay but user has a false path constraint.
6. checking no_output_delay (1)
-------------------------------
There is 1 port with no output delay specified. (HIGH)
There are 0 ports with no output delay but user has a false path constraint
There are 0 ports with no output delay but with a timing clock defined on it or propagating through it
7. checking multiple_clock (0)
------------------------------
There are 0 register/latch pins with multiple clocks.
8. checking generated_clocks (0)
--------------------------------
There are 0 generated clocks that are not connected to a clock source.
9. checking loops (0)
---------------------
There are 0 combinational loops in the design.
10. checking partial_input_delay (0)
------------------------------------
There are 0 input ports with partial input delay specified.
11. checking partial_output_delay (0)
-------------------------------------
There are 0 ports with partial output delay specified.
12. checking latch_loops (0)
----------------------------
There are 0 combinational latch loops in the design through latch input
------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------
WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
8.054 0.000 0 1 0.735 0.000 0 1 4.500 0.000 0 2
All user specified timing constraints are met.
------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------
Clock Waveform(ns) Period(ns) Frequency(MHz)
----- ------------ ---------- --------------
sck {0.000 50.000} 100.000 10.000
sys_clk_pin {0.000 5.000} 10.000 100.000
------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------
Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
sys_clk_pin 8.054 0.000 0 1 0.735 0.000 0 1 4.500 0.000 0 2
------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------
From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------
Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
report_timing_summary: Time (s): cpu = 00:00:25 ; elapsed = 00:00:05 . Memory (MB): peak = 3028.207 ; gain = 0.000 ; free physical = 6167 ; free virtual = 25809
# report_route_status -file digilent_arty_a7_route_status.rpt
# report_drc -file digilent_arty_a7_drc.rpt
Command: report_drc -file digilent_arty_a7_drc.rpt
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/eda/vivado/Vivado/2023.2/data/ip'.
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 2-168] The results of DRC are in file /var/jenkins_home/workspace/SuperScalar-RISCV-CPU/SuperScalar-RISCV-CPU/digilent_arty_a7_drc.rpt.
report_drc completed successfully
# report_timing_summary -datasheet -max_paths 10 -file digilent_arty_a7_timing.rpt
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
# report_power -file digilent_arty_a7_power.rpt
Command: report_power -file digilent_arty_a7_power.rpt
Running Vector-less Activity Propagation...
Finished Running Vector-less Activity Propagation
WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis.
Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report.
0 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
report_power: Time (s): cpu = 00:00:22 ; elapsed = 00:00:11 . Memory (MB): peak = 3189.711 ; gain = 73.461 ; free physical = 6074 ; free virtual = 25716
# write_bitstream -force "digilent_arty_a7_100t.bit"
Command: write_bitstream -force digilent_arty_a7_100t.bit
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command write_bitstream
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [DRC 23-27] Running DRC with 8 threads
WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
set_property CFGBVS value1 [current_design]
#where value1 is either VCCO or GND
set_property CONFIG_VOLTAGE value2 [current_design]
#where value2 is the voltage provided to configuration bank 0
Refer to the device configuration user guide for more information.
INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
INFO: [Designutils 20-2272] Running write_bitstream with 8 threads.
Loading data files...
Loading site data...
Loading route data...
Processing options...
Creating bitmap...
Creating bitstream...
Writing bitstream ./digilent_arty_a7_100t.bit...
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
INFO: [Project 1-1876] WebTalk data collection is mandatory when using a ULT device. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
INFO: [Common 17-83] Releasing license: Implementation
9 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
write_bitstream completed successfully
write_bitstream: Time (s): cpu = 00:00:51 ; elapsed = 00:00:21 . Memory (MB): peak = 3459.973 ; gain = 270.262 ; free physical = 5732 ; free virtual = 25378
# exit
INFO: [Common 17-206] Exiting Vivado at Sun Apr 12 01:51:18 2026...
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