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Started by user Julio Nunes Avelar
[Pipeline] Start of Pipeline
[Pipeline] node
Running on Jenkins in /var/lib/jenkins/workspace/Klessydra-T13@2
[Pipeline] {
[Pipeline] stage
[Pipeline] { (Git Clone)
[Pipeline] sh
+ rm -Rf T13x/ build/
[Pipeline] sh
+ git clone https://github.com/klessydra/T13x.git
Cloning into 'T13x'...
[Pipeline] sh
+ cd T13x
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (GHDL)
[Pipeline] sh
+ /eda/oss-cad-suite/bin/ghdl -a --std=08 T13x/klessydra-t1-3th/PKG_RiscV_Klessydra.vhd T13x/klessydra-t1-3th/RTL-Accumulator.vhd T13x/klessydra-t1-3th/RTL-CSR_Unit.vhd T13x/klessydra-t1-3th/RTL-Debug_Unit.vhd T13x/klessydra-t1-3th/RTL-DSP_Unit.vhd T13x/klessydra-t1-3th/RTL-ID_STAGE.vhd T13x/klessydra-t1-3th/RTL-IE_STAGE.vhd T13x/klessydra-t1-3th/RTL-IF_STAGE.vhd T13x/klessydra-t1-3th/RTL-Load_Store_Unit.vhd T13x/klessydra-t1-3th/RTL-Processing_Pipeline.vhd T13x/klessydra-t1-3th/RTL-Program_Counter_unit.vhd T13x/klessydra-t1-3th/RTL-Registerfile.vhd T13x/klessydra-t1-3th/RTL-Scratchpad_Memory_Interface.vhd T13x/klessydra-t1-3th/RTL-Scratchpad_Memory.vhd T13x/klessydra-t1-3th/STR-Klessydra_top.vhd
T13x/klessydra-t1-3th/RTL-Program_Counter_unit.vhd:109:12:warning: declaration of "MTVEC" hides port "MTVEC" [-Whide]
    signal MTVEC                         : in    std_logic_vector(31 downto 0);
           ^
T13x/klessydra-t1-3th/RTL-Program_Counter_unit.vhd:110:12:warning: declaration of "instr_gnt_i" hides port "instr_gnt_i" [-Whide]
    signal instr_gnt_i, taken_branch     : in    std_logic;
           ^
T13x/klessydra-t1-3th/RTL-Program_Counter_unit.vhd:110:25:warning: declaration of "taken_branch" hides port "taken_branch" [-Whide]
    signal instr_gnt_i, taken_branch     : in    std_logic;
                        ^
T13x/klessydra-t1-3th/RTL-Program_Counter_unit.vhd:111:12:warning: declaration of "set_wfi_condition" hides port "set_wfi_condition" [-Whide]
    signal set_wfi_condition             : in    std_logic;
           ^
T13x/klessydra-t1-3th/RTL-Program_Counter_unit.vhd:112:12:warning: declaration of "taken_branch_pending" hides port "taken_branch_pending" [-Whide]
    signal taken_branch_pending          : inout std_logic;
           ^
T13x/klessydra-t1-3th/RTL-Program_Counter_unit.vhd:113:12:warning: declaration of "irq_pending" hides port "irq_pending" [-Whide]
    signal irq_pending                   : in    std_logic;
           ^
T13x/klessydra-t1-3th/RTL-Program_Counter_unit.vhd:114:12:warning: declaration of "ie_except_condition" hides port "ie_except_condition" [-Whide]
    signal ie_except_condition           : in    std_logic;
           ^
T13x/klessydra-t1-3th/RTL-Program_Counter_unit.vhd:115:12:warning: declaration of "ls_except_condition" hides port "ls_except_condition" [-Whide]
    signal ls_except_condition           : in    std_logic;
           ^
T13x/klessydra-t1-3th/RTL-Program_Counter_unit.vhd:116:12:warning: declaration of "dsp_except_condition" hides port "dsp_except_condition" [-Whide]
    signal dsp_except_condition          : in    std_logic;
           ^
T13x/klessydra-t1-3th/RTL-Program_Counter_unit.vhd:117:12:warning: declaration of "set_except_condition" hides port "set_except_condition" [-Whide]
    signal set_except_condition          : in    std_logic;
           ^
T13x/klessydra-t1-3th/RTL-Program_Counter_unit.vhd:118:12:warning: declaration of "set_mret_condition" hides port "set_mret_condition" [-Whide]
    signal set_mret_condition            : in    std_logic;
           ^
T13x/klessydra-t1-3th/RTL-Program_Counter_unit.vhd:119:12:warning: declaration of "pc" hides signal "pc" [-Whide]
    signal pc                            : inout std_logic_vector(31 downto 0);
           ^
T13x/klessydra-t1-3th/RTL-Program_Counter_unit.vhd:120:12:warning: declaration of "taken_branch_pc_lat" hides port "taken_branch_pc_lat" [-Whide]
    signal taken_branch_pc_lat           : in    std_logic_vector(31 downto 0);
           ^
T13x/klessydra-t1-3th/RTL-Program_Counter_unit.vhd:122:12:warning: declaration of "incremented_pc" hides port "incremented_pc" [-Whide]
    signal incremented_pc                : in    std_logic_vector(31 downto 0);
           ^
T13x/klessydra-t1-3th/RTL-Program_Counter_unit.vhd:123:12:warning: declaration of "boot_pc" hides signal "boot_pc" [-Whide]
    signal boot_pc                       : in    std_logic_vector(31 downto 0);
           ^
T13x/klessydra-t1-3th/RTL-Program_Counter_unit.vhd:124:12:warning: declaration of "pc_update_enable" hides signal "pc_update_enable" [-Whide]
    signal pc_update_enable              : in    std_logic;
           ^
T13x/klessydra-t1-3th/RTL-Program_Counter_unit.vhd:125:12:warning: declaration of "served_ie_except_condition" hides port "served_ie_except_condition" [-Whide]
    signal served_ie_except_condition    : out   std_logic;
           ^
T13x/klessydra-t1-3th/RTL-Program_Counter_unit.vhd:126:12:warning: declaration of "served_ls_except_condition" hides port "served_ls_except_condition" [-Whide]
    signal served_ls_except_condition    : out   std_logic;
           ^
T13x/klessydra-t1-3th/RTL-Program_Counter_unit.vhd:127:12:warning: declaration of "served_dsp_except_condition" hides port "served_dsp_except_condition" [-Whide]
    signal served_dsp_except_condition   : out   std_logic;
           ^
T13x/klessydra-t1-3th/RTL-Program_Counter_unit.vhd:128:12:warning: declaration of "served_except_condition" hides port "served_except_condition" [-Whide]
    signal served_except_condition       : out   std_logic;
           ^
T13x/klessydra-t1-3th/RTL-Program_Counter_unit.vhd:129:12:warning: declaration of "served_mret_condition" hides port "served_mret_condition" [-Whide]
    signal served_mret_condition         : out   std_logic) is
           ^
T13x/klessydra-t1-3th/RTL-Registerfile.vhd:85:26:error: no "RS1_Data_IE" for attribute specification
  attribute ram_style of RS1_Data_IE        : signal is "reg";
                         ^
T13x/klessydra-t1-3th/RTL-Registerfile.vhd:86:26:error: no "RS2_Data_IE" for attribute specification
  attribute ram_style of RS2_Data_IE        : signal is "reg";
                         ^
T13x/klessydra-t1-3th/RTL-Registerfile.vhd:87:26:error: no "RD_Data_IE" for attribute specification
  attribute ram_style of RD_Data_IE         : signal is "reg";
                         ^
T13x/klessydra-t1-3th/RTL-Registerfile.vhd:265:3:warning: declaration of "RF_FF" hides if generate statement [-Whide]
  RF_FF : if LUTRAM_RF = 0 generate
  ^
T13x/klessydra-t1-3th/RTL-Registerfile.vhd:288:3:warning: declaration of "RF_LUTRAM" hides if generate statement [-Whide]
  RF_LUTRAM : if LUTRAM_RF = 1 generate
  ^
/eda/oss-cad-suite/libexec/ghdl:error: compilation error
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // node
[Pipeline] End of Pipeline
ERROR: script returned exit code 1
Finished: FAILURE