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Started by timer
[Pipeline] Start of Pipeline
[Pipeline] node
Running on Jenkins in /var/jenkins_home/workspace/Toooba
[Pipeline] {
[Pipeline] stage
[Pipeline] { (Git Clone)
[Pipeline] sh
+ rm -rf *.xml
[Pipeline] sh
+ rm -rf Toooba
[Pipeline] sh
+ git clone --recursive --depth=1 https://github.com/bluespec/Toooba Toooba
Cloning into 'Toooba'...
Submodule 'src_Core/BSV_Additional_Libs/BlueStuff' (https://github.com/CTSRD-CHERI/BlueStuff.git) registered for path 'src_Core/BSV_Additional_Libs/BlueStuff'
Cloning into '/var/jenkins_home/workspace/Toooba/Toooba/src_Core/BSV_Additional_Libs/BlueStuff'...
Submodule path 'src_Core/BSV_Additional_Libs/BlueStuff': checked out '7e3686c5dc361a7125e859cf60c609596a1a9b83'
Submodule 'BlueBasics' (https://github.com/CTSRD-CHERI/BlueBasics.git) registered for path 'src_Core/BSV_Additional_Libs/BlueStuff/BlueBasics'
Submodule 'SocketPacketUtils' (https://github.com/CTSRD-CHERI/SocketPacketUtils.git) registered for path 'src_Core/BSV_Additional_Libs/BlueStuff/SocketPacketUtils'
Cloning into '/var/jenkins_home/workspace/Toooba/Toooba/src_Core/BSV_Additional_Libs/BlueStuff/BlueBasics'...
Cloning into '/var/jenkins_home/workspace/Toooba/Toooba/src_Core/BSV_Additional_Libs/BlueStuff/SocketPacketUtils'...
Submodule path 'src_Core/BSV_Additional_Libs/BlueStuff/BlueBasics': checked out '9be88c5c0a7cd9c24a04ea85dda54c58b471ac3c'
Submodule path 'src_Core/BSV_Additional_Libs/BlueStuff/SocketPacketUtils': checked out 'e7df4dd0f3ef6cbb0275e880e7c8ec88c91a8fde'
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Simulation)
[Pipeline] dir
Running in /var/jenkins_home/workspace/Toooba/Toooba
[Pipeline] {
[Pipeline] echo
FPGA > Simulation
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Utilities)
[Pipeline] dir
Running in /var/jenkins_home/workspace/Toooba/Toooba
[Pipeline] {
[Pipeline] sh
+ pwd
+ python3 /eda/processor_ci/core/labeler_prototype.py -d /var/jenkins_home/workspace/Toooba/Toooba -c /eda/processor_ci/config -o /jenkins/processor_ci_utils/labels
Trying to read file: /var/jenkins_home/workspace/Toooba/Toooba/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkAXI4_Deburster_A.v
Trying to read file: /var/jenkins_home/workspace/Toooba/Toooba/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkAXI4_Deburster_A.v
Trying to read file: /var/jenkins_home/workspace/Toooba/Toooba/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkAluDispToRegFifo.v
Trying to read file: /var/jenkins_home/workspace/Toooba/Toooba/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkAluExeToFinFifo.v
Trying to read file: /var/jenkins_home/workspace/Toooba/Toooba/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkAluRegToExeFifo.v
Trying to read file: /var/jenkins_home/workspace/Toooba/Toooba/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkBht.v
Trying to read file: /var/jenkins_home/workspace/Toooba/Toooba/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkBoot_ROM.v
Trying to read file: /var/jenkins_home/workspace/Toooba/Toooba/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkCore.v
Cache-related signals in mkSplitLSQ.v
Cache-related signals in mkRobRowSynth.v
Possible cache file: mkLLCache.v
Cache-related signals in mkLLCache.v
Possible cache file: mkSplitTransCache.v
Cache-related signals in mkSplitTransCache.v
Cache-related signals in mkL2Tlb.v
Cache-related signals in mkDTlbSynth.v
Cache-related signals in mkAluExeToFinFifo.v
Cache-related signals in mkLSQIssueLdQ.v
Cache-related signals in mkLLPipeline.v
Cache-related signals in mkReorderBufferSynth.v
Cache-related signals in mkAluRegToExeFifo.v
Possible cache file: mkICoCache.v
Cache-related signals in mkFpuMulDivDispToRegFifo.v
Cache-related signals in mkIBankWrapper.v
Cache-related signals in mkITlb.v
Cache-related signals in mkAluDispToRegFifo.v
Cache-related signals in mkRegRenamingTable.v
Cache-related signals in mkFpuMulDivRegToExeFifo.v
Cache-related signals in mkCore.v
Cache-related signals in mkMemDispToRegFifo.v
Cache-related signals in mkProc.v
Cache-related signals in mkSimpleRespQ.v
Cache-related signals in mkMemRegToExeFifo.v
Cache-related signals in mkStoreBufferEhr.v
Possible cache file: mkNullTransCache.v
Cache-related signals in mkEpochManager.v
Possible cache file: mkLLCache.v
Possible cache file: mkSplitTransCache.v
Possible cache file: mkICoCache.v
Cache-related signals in mkProc.v
Possible cache file: mkNullTransCache.v
Possible cache file: mkLLCache.v
Possible cache file: mkSplitTransCache.v
Possible cache file: mkICoCache.v
Cache-related signals in mkProc.v
Possible cache file: mkNullTransCache.v
Cache-related signals in FIFO1.v
Possible cache file: mkLLCache.v
Possible cache file: mkSplitTransCache.v
Cache-related signals in SyncFIFOLevel.v
Cache-related signals in FIFO20.v
Cache-related signals in SizedFIFO0.v
Possible cache file: mkICoCache.v
Cache-related signals in FIFO2.v
Cache-related signals in FIFOL1.v
Cache-related signals in mkProc.v
Possible cache file: mkNullTransCache.v
Cache-related signals in FIFO10.v
Cache-related signals in FIFO1.v
Cache-related signals in SyncFIFOLevel.v
Cache-related signals in FIFO20.v
Cache-related signals in SizedFIFO0.v
Cache-related signals in FIFO2.v
Cache-related signals in FIFOL1.v
Cache-related signals in FIFO10.v
Results saved to /jenkins/processor_ci_utils/labels/Toooba.json
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (FPGA Build Pipeline)
[Pipeline] parallel
[Pipeline] { (Branch: digilent_arty_a7_100t)
[Pipeline] stage
[Pipeline] { (digilent_arty_a7_100t)
[Pipeline] lock
Trying to acquire lock on [Resource: digilent_arty_a7_100t]
Resource [digilent_arty_a7_100t] did not exist. Created.
Lock acquired on [Resource: digilent_arty_a7_100t]
[Pipeline] {
[Pipeline] stage
[Pipeline] { (Synthesis and PnR)
[Pipeline] dir
Running in /var/jenkins_home/workspace/Toooba/Toooba
[Pipeline] {
[Pipeline] echo
Starting synthesis for FPGA digilent_arty_a7_100t.
[Pipeline] sh
+ python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p Toooba -b digilent_arty_a7_100t
[LOCK] Criado: run.lock
File 'processor_ci_defines.vh' generated for board: 'digilent_arty_a7_100t'.
Final configuration file generated at /var/jenkins_home/workspace/Toooba/Toooba/build_digilent_arty_a7_100t.tcl
[LOCK] Removido: run.lock
Error executing Makefile.
ERROR: [Synth 8-36] 'v__h831' is not declared [/var/jenkins_home/workspace/Toooba/Toooba/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkTop_HW_Side.v:174]
ERROR: [Synth 8-36] 'TASK_testplusargs___d13' is not declared [/var/jenkins_home/workspace/Toooba/Toooba/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkTop_HW_Side.v:177]
ERROR: [Synth 8-36] 'TASK_testplusargs___d14' is not declared [/var/jenkins_home/workspace/Toooba/Toooba/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkTop_HW_Side.v:179]
ERROR: [Synth 8-36] 'fromhost_addr__h648' is not declared [/var/jenkins_home/workspace/Toooba/Toooba/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkTop_HW_Side.v:180]
ERROR: [Synth 8-36] 'tohost_addr__h647' is not declared [/var/jenkins_home/workspace/Toooba/Toooba/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkTop_HW_Side.v:181]
ERROR: [Synth 8-36] 'v__h831' is not declared [/var/jenkins_home/workspace/Toooba/Toooba/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkTop_HW_Side.v:192]
ERROR: [Synth 8-439] module 'uart_rx' not found [/eda/processor-ci-controller/modules/uart.sv:260]
ERROR: [Synth 8-6156] failed synthesizing module 'UART' [/eda/processor-ci-controller/modules/uart.sv:1]
ERROR: [Synth 8-6156] failed synthesizing module 'Controller' [/eda/processor-ci-controller/rtl/controller.sv:1]
ERROR: [Synth 8-6156] failed synthesizing module 'processorci_top' [/eda/processor_ci/rtl/Toooba.sv:7]
ERROR: [Synth 8-6156] failed synthesizing module 'fpga_top' [/eda/processor_ci/internal/fpga_top.sv:8]
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details
make: *** [/eda/processor_ci/makefiles/digilent_arty_a7_100t.mk:12: digilent_arty_a7_100t.bit] Error 1

Traceback (most recent call last):
  File "/eda/processor_ci/main.py", line 142, in <module>
    main(
  File "/eda/processor_ci/main.py", line 89, in main
    build(build_file_path, board_name, toolchain_path)
  File "/eda/processor_ci/core/fpga.py", line 299, in build
    raise subprocess.CalledProcessError(process.returncode, 'make')
subprocess.CalledProcessError: Command 'make' returned non-zero exit status 2.
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Flash digilent_arty_a7_100t)
Stage "Flash digilent_arty_a7_100t" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Test digilent_arty_a7_100t)
Stage "Test digilent_arty_a7_100t" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Lock released on resource [Resource: digilent_arty_a7_100t]
[Pipeline] // lock
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Failed in branch digilent_arty_a7_100t
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Declarative: Post Actions)
[Pipeline] junit
Recording test results
[Checks API] No suitable checks publisher found.
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // node
[Pipeline] End of Pipeline
ERROR: script returned exit code 1
Finished: FAILURE