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Start of Pipeline - (41 min in block)
node - (41 min in block)
node block - (24 sec in block)
stage - (8.6 sec in block)Git Clone
stage block (Git Clone) - (8.1 sec in block)
sh - (0.73 sec in self)rm -rf VexRiscv
sh - (7 sec in self)git clone --recursive --depth=1 https://github.com/SpinalHDL/VexRiscv VexRiscv
stage - (2.1 sec in block)Verilog Convert
stage block (Verilog Convert) - (1.5 sec in block)
dir - (1 sec in block)VexRiscv
dir block - (0.67 sec in block)
sh - (0.47 sec in self)sbt "runMain vexriscv.demo.GenFull"
stage - (0.96 sec in block)Simulation
stage block (Simulation) - (0.34 sec in block)
getContext - (0.15 sec in self)
stage - (0.91 sec in block)Utilities
stage block (Utilities) - (0.35 sec in block)
getContext - (0.16 sec in self)
stage - (10 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (9.7 sec in block)
getContext - (0.27 sec in self)
parallel - (9 sec in block)
parallel block (Branch: colorlight_i9) - (51 ms in block)
stage - (7.2 sec in block)colorlight_i9
stage block (colorlight_i9) - (6.8 sec in block)
getContext - (0.69 sec in self)
stage - (2.2 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (0.59 sec in block)
getContext - (0.17 sec in self)
stage - (1.7 sec in block)Flash colorlight_i9
stage block (Flash colorlight_i9) - (0.59 sec in block)
getContext - (0.17 sec in self)
stage - (1.2 sec in block)Test colorlight_i9
stage block (Test colorlight_i9) - (0.63 sec in block)
getContext - (0.16 sec in self)
parallel block (Branch: digilent_nexys4_ddr) - (8.1 sec in block)
stage - (7.2 sec in block)digilent_nexys4_ddr
stage block (digilent_nexys4_ddr) - (6.6 sec in block)
getContext - (0.63 sec in self)
stage - (2.3 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (0.7 sec in block)
getContext - (0.15 sec in self)
stage - (1.7 sec in block)Flash digilent_nexys4_ddr
stage block (Flash digilent_nexys4_ddr) - (0.73 sec in block)
getContext - (0.17 sec in self)
stage - (1.2 sec in block)Test digilent_nexys4_ddr
stage block (Test digilent_nexys4_ddr) - (0.7 sec in block)
getContext - (0.17 sec in self)
stage - (0.87 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (0.62 sec in block)
junit - (0.32 sec in self)**/test-reports/*.xml