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+ python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p airisc_core_complex -b digilent_nexys4_ddr
Final configuration file generated at /var/jenkins_home/workspace/airisc_core_complex/airisc_core_complex/build_digilent_nexys4_ddr.tcl
Error executing Makefile.
ERROR: [Synth 8-9263] cannot open include file 'airi5c_hasti_constants.vh' [/var/jenkins_home/workspace/airisc_core_complex/airisc_core_complex/fpga/src_ArtyA7/verilog/FPGA_Top.v:16]
ERROR: [Synth 8-9263] cannot open include file 'airi5c_dmi_constants.vh' [/var/jenkins_home/workspace/airisc_core_complex/airisc_core_complex/fpga/src_ArtyA7/verilog/FPGA_Top.v:17]
ERROR: [Synth 8-9263] cannot open include file 'airi5c_hasti_constants.vh' [/var/jenkins_home/workspace/airisc_core_complex/airisc_core_complex/fpga/src_CmodA7/verilog/FPGA_Top.v:16]
ERROR: [Synth 8-9263] cannot open include file 'airi5c_dmi_constants.vh' [/var/jenkins_home/workspace/airisc_core_complex/airisc_core_complex/fpga/src_CmodA7/verilog/FPGA_Top.v:17]
ERROR: [Synth 8-9263] cannot open include file 'airi5c_hasti_constants.vh' [/var/jenkins_home/workspace/airisc_core_complex/airisc_core_complex/fpga/src_NexysVideo/verilog/FPGA_Top.v:16]
ERROR: [Synth 8-9263] cannot open include file 'airi5c_dmi_constants.vh' [/var/jenkins_home/workspace/airisc_core_complex/airisc_core_complex/fpga/src_NexysVideo/verilog/FPGA_Top.v:17]
ERROR: [Synth 8-9263] cannot open include file 'modules/airi5c_fpu/airi5c_FPU_constants.vh' [/var/jenkins_home/workspace/airisc_core_complex/airisc_core_complex/src/modules/airi5c_fpu/airi5c_ftoi_converter.v:14]
ERROR: [Synth 8-9263] cannot open include file 'modules/airi5c_fpu/airi5c_FPU_constants.vh' [/var/jenkins_home/workspace/airisc_core_complex/airisc_core_complex/src/modules/airi5c_fpu/airi5c_post_processing.v:14]
ERROR: [Synth 8-9263] cannot open include file 'airi5c_hasti_constants.vh' [/var/jenkins_home/workspace/airisc_core_complex/airisc_core_complex/src/modules/airi5c_spi/src/airi5c_spi.v:14]
ERROR: [Synth 8-9263] cannot open include file 'airi5c_hasti_constants.vh' [/var/jenkins_home/workspace/airisc_core_complex/airisc_core_complex/src/modules/airi5c_trng/src/airi5c_trng.v:21]
ERROR: [Synth 8-9263] cannot open include file 'modules/airi5c_uart/src/airi5c_uart_constants.vh' [/var/jenkins_home/workspace/airisc_core_complex/airisc_core_complex/src/modules/airi5c_uart/src/airi5c_uart.v:14]
ERROR: [Synth 8-9263] cannot open include file 'airi5c_hasti_constants.vh' [/var/jenkins_home/workspace/airisc_core_complex/airisc_core_complex/fpga/src_ArtyA7/verilog/FPGA_Top.v:16]
ERROR: [Synth 8-9263] cannot open include file 'airi5c_dmi_constants.vh' [/var/jenkins_home/workspace/airisc_core_complex/airisc_core_complex/fpga/src_ArtyA7/verilog/FPGA_Top.v:17]
ERROR: [Synth 8-10157] use of undefined macro 'HASTI_ADDR_WIDTH' [/var/jenkins_home/workspace/airisc_core_complex/airisc_core_complex/fpga/src_ArtyA7/verilog/FPGA_Top.v:85]
ERROR: [Synth 8-10157] use of undefined macro 'HASTI_SIZE_WIDTH' [/var/jenkins_home/workspace/airisc_core_complex/airisc_core_complex/fpga/src_ArtyA7/verilog/FPGA_Top.v:87]
ERROR: [Synth 8-10157] use of undefined macro 'HASTI_BURST_WIDTH' [/var/jenkins_home/workspace/airisc_core_complex/airisc_core_complex/fpga/src_ArtyA7/verilog/FPGA_Top.v:88]
ERROR: [Synth 8-10157] use of undefined macro 'HASTI_PROT_WIDTH' [/var/jenkins_home/workspace/airisc_core_complex/airisc_core_complex/fpga/src_ArtyA7/verilog/FPGA_Top.v:90]
ERROR: [Synth 8-10157] use of undefined macro 'HASTI_TRANS_WIDTH' [/var/jenkins_home/workspace/airisc_core_complex/airisc_core_complex/fpga/src_ArtyA7/verilog/FPGA_Top.v:91]
ERROR: [Synth 8-10157] use of undefined macro 'HASTI_BUS_WIDTH' [/var/jenkins_home/workspace/airisc_core_complex/airisc_core_complex/fpga/src_ArtyA7/verilog/FPGA_Top.v:92]
ERROR: [Synth 8-10157] use of undefined macro 'HASTI_RESP_WIDTH' [/var/jenkins_home/workspace/airisc_core_complex/airisc_core_complex/fpga/src_ArtyA7/verilog/FPGA_Top.v:95]
ERROR: [Synth 8-10157] use of undefined macro 'DMI_ADDR_WIDTH' [/var/jenkins_home/workspace/airisc_core_complex/airisc_core_complex/fpga/src_ArtyA7/verilog/FPGA_Top.v:109]
ERROR: [Synth 8-10157] use of undefined macro 'DMI_WIDTH' [/var/jenkins_home/workspace/airisc_core_complex/airisc_core_complex/fpga/src_ArtyA7/verilog/FPGA_Top.v:110]
ERROR: [Synth 8-10157] use of undefined macro 'HASTI_RESP_OKAY' [/var/jenkins_home/workspace/airisc_core_complex/airisc_core_complex/fpga/src_ArtyA7/verilog/FPGA_Top.v:208]
ERROR: [Synth 8-2716] syntax error near ';' [/var/jenkins_home/workspace/airisc_core_complex/airisc_core_complex/fpga/src_ArtyA7/verilog/FPGA_Top.v:208]
ERROR: [Synth 8-2716] syntax error near ';' [/var/jenkins_home/workspace/airisc_core_complex/airisc_core_complex/fpga/src_ArtyA7/verilog/FPGA_Top.v:210]
ERROR: [Synth 8-439] module 'Controller' not found [/eda/processor_ci/rtl/airisc_core_complex.v:48]
ERROR: [Synth 8-6156] failed synthesizing module 'processorci_top' [/eda/processor_ci/rtl/airisc_core_complex.v:1]
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details
make: *** [/eda/processor_ci/makefiles/digilent_nexys4_ddr.mk:12: digilent_nexys4_ddr.bit] Error 1

Traceback (most recent call last):
  File "/eda/processor_ci/main.py", line 135, in <module>
    main(
  File "/eda/processor_ci/main.py", line 82, in main
    build(build_file_path, board_name, toolchain_path)
  File "/eda/processor_ci/core/fpga.py", line 218, in build
    raise subprocess.CalledProcessError(process.returncode, 'make')
subprocess.CalledProcessError: Command 'make' returned non-zero exit status 2.