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Start of Pipeline - (1 min 4 sec in block)
node - (1 min 3 sec in block)
node block - (1 min 3 sec in block)
stage - (9 sec in block)Git Clone
stage block (Git Clone) - (8.5 sec in block)
sh - (0.47 sec in self)rm -rf airisc_core_complex
sh - (7.8 sec in self)git clone --recursive --depth=1 https://github.com/Fraunhofer-IMS/airisc_core_complex airisc_core_complex
stage - (1.4 sec in block)Simulation
stage block (Simulation) - (0.97 sec in block)
dir - (0.6 sec in block)airisc_core_complex
dir block - (0.34 sec in block)
echo - (0.11 sec in self)simulation not supported for mixed VHDL and Verilog files
stage - (1.7 sec in block)Utilities
stage block (Utilities) - (1.2 sec in block)
dir - (0.89 sec in block)airisc_core_complex
dir block - (0.64 sec in block)
sh - (0.42 sec in self)python3 /eda/processor_ci/core/labeler_prototype.py -d $(pwd) -c /eda/processor_ci/config.json -o /jenkins/processor_ci_utils/labels.json
stage - (48 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (47 sec in block)
parallel - (47 sec in block)
parallel block (Branch: colorlight_i9) - (59 ms in block)
stage - (7 sec in block)colorlight_i9
stage block (colorlight_i9) - (6.7 sec in block)
lock - (5.9 sec in block)colorlight_i9
lock block - (5.3 sec in block)
stage - (2.8 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (2.2 sec in block)
dir - (1.5 sec in block)airisc_core_complex
dir block - (1.2 sec in block)
echo - (0.16 sec in self)Starting synthesis for FPGA colorlight_i9.
sh - (0.67 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p airisc_core_complex -b colorlight_i9
stage - (0.94 sec in block)Flash colorlight_i9
stage block (Flash colorlight_i9) - (0.35 sec in block)
getContext - (0.15 sec in self)
stage - (0.7 sec in block)Test colorlight_i9
stage block (Test colorlight_i9) - (0.37 sec in block)
getContext - (0.16 sec in self)
parallel block (Branch: digilent_nexys4_ddr) - (46 sec in block)
stage - (45 sec in block)digilent_nexys4_ddr
stage block (digilent_nexys4_ddr) - (45 sec in block)
lock - (44 sec in block)digilent_nexys4_ddr
lock block - (43 sec in block)
stage - (41 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (40 sec in block)
dir - (40 sec in block)airisc_core_complex
dir block - (39 sec in block)
echo - (0.17 sec in self)Starting synthesis for FPGA digilent_nexys4_ddr.
sh - (39 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p airisc_core_complex -b digilent_nexys4_ddr
stage - (0.96 sec in block)Flash digilent_nexys4_ddr
stage block (Flash digilent_nexys4_ddr) - (0.39 sec in block)
getContext - (0.17 sec in self)
stage - (0.74 sec in block)Test digilent_nexys4_ddr
stage block (Test digilent_nexys4_ddr) - (0.4 sec in block)
getContext - (0.17 sec in self)
stage - (1.4 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (1 sec in block)
junit - (0.49 sec in self)**/test-reports/*.xml