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Start of Pipeline - (39 min in block)
node - (39 min in block)
node block - (39 min in block)
stage - (2 sec in block)Git Clone
stage block (Git Clone) - (1.5 sec in block)
sh - (0.46 sec in self)rm -rf biriscv
sh - (0.9 sec in self)git clone --recursive --depth=1 https://github.com/ultraembedded/biriscv biriscv
stage - (1.7 sec in block)Simulation
stage block (Simulation) - (1.2 sec in block)
dir - (0.88 sec in block)biriscv
dir block - (0.64 sec in block)
sh - (0.41 sec in self)/eda/oss-cad-suite/bin/iverilog -o simulation.out -g2005 -s riscv_core -I src/core src/core/biriscv_alu.v src/core/biriscv_csr.v src/core/biriscv_csr_regfile.v src/core/biriscv_decode.v src/core/biriscv_decoder.v src/core/biriscv_defs.v src/core/biriscv_divider.v src/core/biriscv_exec.v src/core/biriscv_fetch.v src/core/biriscv_frontend.v src/core/biriscv_issue.v src/core/biriscv_lsu.v src/core/biriscv_mmu.v src/core/biriscv_multiplier.v src/core/biriscv_npc.v src/core/biriscv_pipe_ctrl.v src/core/biriscv_regfile.v src/core/biriscv_trace_sim.v src/core/biriscv_xilinx_2r1w.v src/core/riscv_core.v
stage - (1.7 sec in block)Utilities
stage block (Utilities) - (1.2 sec in block)
dir - (0.87 sec in block)biriscv
dir block - (0.61 sec in block)
sh - (0.4 sec in self)python3 /eda/processor_ci/core/labeler_prototype.py -d $(pwd) -c /eda/processor_ci/config.json -o /jenkins/processor_ci_utils/labels.json
stage - (39 min in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (38 min in block)
parallel - (38 min in block)
parallel block (Branch: colorlight_i9) - (58 ms in block)
stage - (38 min in block)colorlight_i9
stage block (colorlight_i9) - (38 min in block)
lock - (38 min in block)colorlight_i9
lock block - (38 min in block)
stage - (38 min in block)Synthesis and PnR
stage block (Synthesis and PnR) - (38 min in block)
dir - (38 min in block)biriscv
dir block - (38 min in block)
echo - (0.17 sec in self)Starting synthesis for FPGA colorlight_i9.
sh - (38 min in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p biriscv -b colorlight_i9
stage - (28 sec in block)Flash colorlight_i9
stage block (Flash colorlight_i9) - (28 sec in block)
dir - (27 sec in block)biriscv
dir block - (27 sec in block)
echo - (0.16 sec in self)Flashing FPGA colorlight_i9.
sh - (26 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p biriscv -b colorlight_i9 -l
stage - (1.6 sec in block)Test colorlight_i9
stage block (Test colorlight_i9) - (1.3 sec in block)
echo - (0.2 sec in self)Testing FPGA colorlight_i9.
dir - (0.89 sec in block)biriscv
dir block - (0.61 sec in block)
sh - (0.4 sec in self)echo "Test for FPGA in /dev/ttyACM0"
parallel block (Branch: digilent_nexys4_ddr) - (46 sec in block)
stage - (45 sec in block)digilent_nexys4_ddr
stage block (digilent_nexys4_ddr) - (45 sec in block)
lock - (44 sec in block)digilent_nexys4_ddr
lock block - (43 sec in block)
stage - (41 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (41 sec in block)
dir - (39 sec in block)biriscv
dir block - (39 sec in block)
echo - (0.15 sec in self)Starting synthesis for FPGA digilent_nexys4_ddr.
sh - (39 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p biriscv -b digilent_nexys4_ddr
stage - (0.91 sec in block)Flash digilent_nexys4_ddr
stage block (Flash digilent_nexys4_ddr) - (0.36 sec in block)
getContext - (0.15 sec in self)
stage - (0.68 sec in block)Test digilent_nexys4_ddr
stage block (Test digilent_nexys4_ddr) - (0.38 sec in block)
getContext - (0.16 sec in self)
stage - (1 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (0.69 sec in block)
junit - (0.42 sec in self)**/test-reports/*.xml