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Start of Pipeline - (2 min 56 sec in block)
node - (2 min 56 sec in block)
node block - (54 sec in block)
stage - (2.8 sec in block)Git Clone
stage block (Git Clone) - (2.3 sec in block)
sh - (0.56 sec in self)rm -rf *.xml
sh - (0.45 sec in self)rm -rf cv32e40x
sh - (0.9 sec in self)git clone --recursive --depth=1 https://github.com/openhwgroup/cv32e40x cv32e40x
stage - (1.2 sec in block)Simulation
stage block (Simulation) - (0.86 sec in block)
dir - (0.52 sec in block)cv32e40x
dir block - (0.3 sec in block)
echo - (0.11 sec in self)FPGA > Simulation
stage - (1.5 sec in block)Utilities
stage block (Utilities) - (1.1 sec in block)
dir - (0.79 sec in block)cv32e40x
dir block - (0.57 sec in block)
sh - (0.38 sec in self)python3 /eda/processor_ci/core/labeler_prototype.py -d $(pwd) -c /eda/processor_ci/config -o /jenkins/processor_ci_utils/labels
stage - (47 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (46 sec in block)
parallel - (46 sec in block)
parallel block (Branch: digilent_arty_a7_100t) - (45 sec in block)
stage - (45 sec in block)digilent_arty_a7_100t
stage block (digilent_arty_a7_100t) - (45 sec in block)
lock - (44 sec in block)digilent_arty_a7_100t
lock block - (22 sec in block)
stage - (20 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (20 sec in block)
dir - (19 sec in block)cv32e40x
dir block - (19 sec in block)
echo - (0.3 sec in self)Starting synthesis for FPGA digilent_arty_a7_100t.
sh - (18 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p cv32e40x -b digilent_arty_a7_100t
stage - (0.91 sec in block)Flash digilent_arty_a7_100t
stage block (Flash digilent_arty_a7_100t) - (0.36 sec in block)
getContext - (0.16 sec in self)
stage - (0.6 sec in block)Test digilent_arty_a7_100t
stage block (Test digilent_arty_a7_100t) - (0.33 sec in block)
getContext - (0.15 sec in self)
stage - (0.7 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (0.48 sec in block)
junit - (0.24 sec in self)**/*.xml