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Started by timer [Pipeline] Start of Pipeline [Pipeline] node Running on Jenkins in /var/jenkins_home/workspace/e203_hbirdv2 [Pipeline] { [Pipeline] stage [Pipeline] { (Git Clone) [Pipeline] sh + rm -rf e203_hbirdv2 [Pipeline] sh + git clone --recursive https://github.com/riscv-mcu/e203_hbirdv2 e203_hbirdv2 Cloning into 'e203_hbirdv2'... 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[Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Simulation) [Pipeline] dir Running in /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2 [Pipeline] { [Pipeline] sh + iverilog -o simulation.out -g2009 -DDISABLE_SV_ASSERTION=1 -gsupported-assertions -s e203_cpu_top -I rtl/e203/core/ rtl/e203/core/config.v rtl/e203/core/e203_biu.v rtl/e203/core/e203_clk_ctrl.v rtl/e203/core/e203_clkgate.v rtl/e203/core/e203_core.v rtl/e203/core/e203_cpu.v rtl/e203/core/e203_cpu_top.v rtl/e203/core/e203_defines.v rtl/e203/core/e203_dtcm_ctrl.v rtl/e203/core/e203_dtcm_ram.v rtl/e203/core/e203_extend_csr.v rtl/e203/core/e203_exu.v rtl/e203/core/e203_exu_alu.v rtl/e203/core/e203_exu_alu_bjp.v rtl/e203/core/e203_exu_alu_csrctrl.v rtl/e203/core/e203_exu_alu_dpath.v rtl/e203/core/e203_exu_alu_lsuagu.v rtl/e203/core/e203_exu_alu_muldiv.v rtl/e203/core/e203_exu_alu_rglr.v rtl/e203/core/e203_exu_branchslv.v rtl/e203/core/e203_exu_commit.v rtl/e203/core/e203_exu_csr.v rtl/e203/core/e203_exu_decode.v rtl/e203/core/e203_exu_disp.v rtl/e203/core/e203_exu_excp.v rtl/e203/core/e203_exu_longpwbck.v rtl/e203/core/e203_exu_nice.v rtl/e203/core/e203_exu_oitf.v rtl/e203/core/e203_exu_regfile.v rtl/e203/core/e203_exu_wbck.v rtl/e203/core/e203_ifu.v rtl/e203/core/e203_ifu_ifetch.v rtl/e203/core/e203_ifu_ift2icb.v rtl/e203/core/e203_ifu_litebpu.v rtl/e203/core/e203_ifu_minidec.v rtl/e203/core/e203_irq_sync.v rtl/e203/core/e203_itcm_ctrl.v rtl/e203/core/e203_itcm_ram.v rtl/e203/core/e203_lsu.v rtl/e203/core/e203_lsu_ctrl.v rtl/e203/core/e203_reset_ctrl.v rtl/e203/core/e203_srams.v rtl/e203/general/sirv_1cyc_sram_ctrl.v rtl/e203/general/sirv_gnrl_bufs.v rtl/e203/general/sirv_gnrl_dffs.v rtl/e203/general/sirv_gnrl_icbs.v rtl/e203/general/sirv_gnrl_ram.v rtl/e203/general/sirv_gnrl_xchecker.v rtl/e203/general/sirv_sim_ram.v rtl/e203/general/sirv_sram_icb_ctrl.v rtl/e203/subsys/e203_subsys_clint.v rtl/e203/subsys/e203_subsys_gfcm.v rtl/e203/subsys/e203_subsys_hclkgen.v rtl/e203/subsys/e203_subsys_hclkgen_rstsync.v rtl/e203/subsys/e203_subsys_main.v rtl/e203/subsys/e203_subsys_mems.v rtl/e203/subsys/e203_subsys_nice_core.v rtl/e203/subsys/e203_subsys_perips.v rtl/e203/subsys/e203_subsys_plic.v rtl/e203/subsys/e203_subsys_pll.v rtl/e203/subsys/e203_subsys_pllclkdiv.v rtl/e203/subsys/e203_subsys_top.v /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2@tmp/durable-9b0d0dc6/script.sh.copy: 1: iverilog: not found [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (FPGA Build Pipeline) Stage "FPGA Build Pipeline" skipped due to earlier failure(s) [Pipeline] getContext [Pipeline] parallel [Pipeline] { (Branch: colorlight_i9) [Pipeline] { (Branch: digilent_nexys4_ddr) [Pipeline] stage [Pipeline] { (colorlight_i9) [Pipeline] stage [Pipeline] { (digilent_nexys4_ddr) Stage "colorlight_i9" skipped due to earlier failure(s) [Pipeline] getContext Stage "digilent_nexys4_ddr" skipped due to earlier failure(s) [Pipeline] getContext [Pipeline] stage [Pipeline] { (Síntese e PnR) [Pipeline] stage [Pipeline] { (Síntese e PnR) Stage "colorlight_i9" skipped due to earlier failure(s) [Pipeline] getContext [Pipeline] } Stage "digilent_nexys4_ddr" skipped due to earlier failure(s) [Pipeline] getContext [Pipeline] } [Pipeline] // stage [Pipeline] // stage [Pipeline] stage [Pipeline] { (Flash colorlight_i9) [Pipeline] stage [Pipeline] { (Flash digilent_nexys4_ddr) Stage "colorlight_i9" skipped due to earlier failure(s) [Pipeline] getContext [Pipeline] } Stage "digilent_nexys4_ddr" skipped due to earlier failure(s) [Pipeline] getContext [Pipeline] } [Pipeline] // stage [Pipeline] // stage [Pipeline] stage [Pipeline] { (Teste colorlight_i9) [Pipeline] stage [Pipeline] { (Teste digilent_nexys4_ddr) Stage "colorlight_i9" skipped due to earlier failure(s) [Pipeline] getContext [Pipeline] } Stage "digilent_nexys4_ddr" skipped due to earlier failure(s) [Pipeline] getContext [Pipeline] } [Pipeline] // stage [Pipeline] // stage [Pipeline] } [Pipeline] } [Pipeline] // stage [Pipeline] // stage [Pipeline] } Failed in branch colorlight_i9 [Pipeline] } Failed in branch digilent_nexys4_ddr [Pipeline] // parallel [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Declarative: Post Actions) [Pipeline] dir Running in /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2 [Pipeline] { [Pipeline] sh + rm -rf LICENSE README.md doc e203_core.core e203_soc.core fpga pics riscv-tools rtl tb vsim [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] } [Pipeline] // node [Pipeline] End of Pipeline ERROR: script returned exit code 127 Finished: FAILURE