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Start of Pipeline - (45 min in block)
node - (45 min in block)
node block - (42 min in block)
stage - (10 sec in block)Git Clone
stage block (Git Clone) - (9.6 sec in block)
sh - (0.8 sec in self)rm -rf e203_hbirdv2
sh - (8.4 sec in self)git clone --recursive --depth=1 https://github.com/riscv-mcu/e203_hbirdv2 e203_hbirdv2
stage - (2.2 sec in block)Simulation
stage block (Simulation) - (1.7 sec in block)
dir - (1.4 sec in block)e203_hbirdv2
dir block - (1.1 sec in block)
sh - (0.91 sec in self)
stage - (1.8 sec in block)Utilities
stage block (Utilities) - (1.2 sec in block)
dir - (0.93 sec in block)e203_hbirdv2
dir block - (0.64 sec in block)
sh - (0.43 sec in self)python3 /eda/processor_ci/core/labeler_prototype.py -d $(pwd) -c /eda/processor_ci/config.json -o /jenkins/processor_ci_utils/labels.json
stage - (42 min in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (42 min in block)
parallel - (42 min in block)
parallel block (Branch: colorlight_i9) - (59 ms in block)
stage - (42 min in block)colorlight_i9
stage block (colorlight_i9) - (42 min in block)
lock - (42 min in block)colorlight_i9
lock block - (8.2 sec in block)
stage - (5 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (3.8 sec in block)
dir - (2.9 sec in block)e203_hbirdv2
dir block - (2.3 sec in block)
echo - (0.33 sec in self)Starting synthesis for FPGA colorlight_i9.
sh - (1.5 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p e203_hbirdv2 -b colorlight_i9
stage - (1.5 sec in block)Flash colorlight_i9
stage block (Flash colorlight_i9) - (0.76 sec in block)
getContext - (0.34 sec in self)
stage - (0.91 sec in block)Test colorlight_i9
stage block (Test colorlight_i9) - (0.52 sec in block)
getContext - (0.17 sec in self)
parallel block (Branch: digilent_nexys4_ddr) - (28 min in block)
stage - (28 min in block)digilent_nexys4_ddr
stage block (digilent_nexys4_ddr) - (28 min in block)
lock - (28 min in block)digilent_nexys4_ddr
lock block - (1 min 12 sec in block)
stage - (1 min 10 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (1 min 9 sec in block)
dir - (1 min 8 sec in block)e203_hbirdv2
dir block - (1 min 8 sec in block)
echo - (0.19 sec in self)Starting synthesis for FPGA digilent_nexys4_ddr.
sh - (1 min 8 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p e203_hbirdv2 -b digilent_nexys4_ddr
stage - (0.96 sec in block)Flash digilent_nexys4_ddr
stage block (Flash digilent_nexys4_ddr) - (0.36 sec in block)
getContext - (0.15 sec in self)
stage - (0.7 sec in block)Test digilent_nexys4_ddr
stage block (Test digilent_nexys4_ddr) - (0.35 sec in block)
getContext - (0.15 sec in self)
stage - (1.4 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (1 sec in block)
junit - (0.53 sec in self)**/test-reports/*.xml