Console Output

Started by user Gabriel Cabral
[Pipeline] Start of Pipeline
[Pipeline] node
Running on Jenkins in /var/lib/jenkins/workspace/e203
[Pipeline] {
[Pipeline] stage
[Pipeline] { (Git Clone)
[Pipeline] sh
+ rm -Rf e203_hbirdv2/ build/
[Pipeline] sh
+ git clone https://github.com/riscv-mcu/e203_hbirdv2.git
Cloning into 'e203_hbirdv2'...
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (IVerilog)
[Pipeline] sh
+ mkdir -p build
[Pipeline] sh
+ eda/oss-cad-suite/bin/iverilog -g2009 -gno-assertions -o build/out.o -s e203_cpu_top e203_hbirdv2/rtl/e203/core/config.v e203_hbirdv2/rtl/e203/core/e203_biu.v e203_hbirdv2/rtl/e203/core/e203_clk_ctrl.v e203_hbirdv2/rtl/e203/core/e203_clkgate.v e203_hbirdv2/rtl/e203/core/e203_core.v e203_hbirdv2/rtl/e203/core/e203_cpu.v e203_hbirdv2/rtl/e203/core/e203_cpu_top.v e203_hbirdv2/rtl/e203/core/e203_defines.v e203_hbirdv2/rtl/e203/core/e203_dtcm_ctrl.v e203_hbirdv2/rtl/e203/core/e203_dtcm_ram.v e203_hbirdv2/rtl/e203/core/e203_extend_csr.v e203_hbirdv2/rtl/e203/core/e203_exu.v e203_hbirdv2/rtl/e203/core/e203_exu_alu.v e203_hbirdv2/rtl/e203/core/e203_exu_alu_bjp.v e203_hbirdv2/rtl/e203/core/e203_exu_alu_csrctrl.v e203_hbirdv2/rtl/e203/core/e203_exu_alu_dpath.v e203_hbirdv2/rtl/e203/core/e203_exu_alu_lsuagu.v e203_hbirdv2/rtl/e203/core/e203_exu_alu_muldiv.v e203_hbirdv2/rtl/e203/core/e203_exu_alu_rglr.v e203_hbirdv2/rtl/e203/core/e203_exu_branchslv.v e203_hbirdv2/rtl/e203/core/e203_exu_commit.v e203_hbirdv2/rtl/e203/core/e203_exu_csr.v e203_hbirdv2/rtl/e203/core/e203_exu_decode.v e203_hbirdv2/rtl/e203/core/e203_exu_disp.v e203_hbirdv2/rtl/e203/core/e203_exu_excp.v e203_hbirdv2/rtl/e203/core/e203_exu_longpwbck.v e203_hbirdv2/rtl/e203/core/e203_exu_nice.v e203_hbirdv2/rtl/e203/core/e203_exu_oitf.v e203_hbirdv2/rtl/e203/core/e203_exu_regfile.v e203_hbirdv2/rtl/e203/core/e203_exu_wbck.v e203_hbirdv2/rtl/e203/core/e203_ifu.v e203_hbirdv2/rtl/e203/core/e203_ifu_ifetch.v e203_hbirdv2/rtl/e203/core/e203_ifu_ift2icb.v e203_hbirdv2/rtl/e203/core/e203_ifu_litebpu.v e203_hbirdv2/rtl/e203/core/e203_ifu_minidec.v e203_hbirdv2/rtl/e203/core/e203_irq_sync.v e203_hbirdv2/rtl/e203/core/e203_itcm_ctrl.v e203_hbirdv2/rtl/e203/core/e203_itcm_ram.v e203_hbirdv2/rtl/e203/core/e203_lsu.v e203_hbirdv2/rtl/e203/core/e203_lsu_ctrl.v e203_hbirdv2/rtl/e203/core/e203_reset_ctrl.v e203_hbirdv2/rtl/e203/core/e203_srams.v e203_hbirdv2/rtl/e203/general/sirv_1cyc_sram_ctrl.v e203_hbirdv2/rtl/e203/general/sirv_gnrl_bufs.v e203_hbirdv2/rtl/e203/general/sirv_gnrl_dffs.v e203_hbirdv2/rtl/e203/general/sirv_gnrl_icbs.v e203_hbirdv2/rtl/e203/general/sirv_gnrl_ram.v e203_hbirdv2/rtl/e203/general/sirv_gnrl_xchecker.v e203_hbirdv2/rtl/e203/general/sirv_sim_ram.v e203_hbirdv2/rtl/e203/general/sirv_sram_icb_ctrl.v e203_hbirdv2/rtl/e203/subsys/e203_subsys_clint.v e203_hbirdv2/rtl/e203/subsys/e203_subsys_gfcm.v e203_hbirdv2/rtl/e203/subsys/e203_subsys_hclkgen.v e203_hbirdv2/rtl/e203/subsys/e203_subsys_hclkgen_rstsync.v e203_hbirdv2/rtl/e203/subsys/e203_subsys_main.v e203_hbirdv2/rtl/e203/subsys/e203_subsys_mems.v e203_hbirdv2/rtl/e203/subsys/e203_subsys_nice_core.v e203_hbirdv2/rtl/e203/subsys/e203_subsys_perips.v e203_hbirdv2/rtl/e203/subsys/e203_subsys_plic.v e203_hbirdv2/rtl/e203/subsys/e203_subsys_pll.v e203_hbirdv2/rtl/e203/subsys/e203_subsys_pllclkdiv.v e203_hbirdv2/rtl/e203/subsys/e203_subsys_top.v
/var/lib/jenkins/workspace/e203@tmp/durable-9bdebc22/script.sh.copy: 2: eda/oss-cad-suite/bin/iverilog: not found
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // node
[Pipeline] End of Pipeline
ERROR: script returned exit code 127
Finished: FAILURE