![[Jenkins]](/jenkins/static/b6fe011e/images/svgs/logo.svg){kind=logo}
| Step | Arguments | Status | ||
|---|---|---|---|---|
| Start of Pipeline - (12 sec in block) | ||||
| node - (11 sec in block) | ||||
| node block - (11 sec in block) | ||||
| stage - (8 sec in block) | Git Clone | |||
| stage block (Git Clone) - (7.5 sec in block) | ||||
| sh - (0.46 sec in self) | rm -Rf e203_hbirdv2/ build/ | |||
| sh - (6.8 sec in self) | git clone https://github.com/riscv-mcu/e203_hbirdv2.git | |||
| stage - (2.7 sec in block) | IVerilog | |||
| stage block (IVerilog) - (2.4 sec in block) | ||||
| dir - (1.9 sec in block) | e203_hbirdv2/ | |||
| dir block - (1.6 sec in block) | ||||
| sh - (0.45 sec in self) | mkdir -p build | |||
| sh - (0.45 sec in self) | ls | |||
| sh - (0.49 sec in self) | /eda/oss-cad-suite/bin/iverilog -g2009 -gno-assertions -o build/out.o -s e203_cpu_top rtl/e203/core/*.v rtl/e203/general/*.v rtl/e203/subsys/*.v e203_defines.v |