Skip to content
[Jenkins]Jenkins
log in

Console Output

+ python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p maestro -b digilent_arty_a7_100t
[LOCK] Criado: run.lock
File 'processor_ci_defines.vh' generated for board: 'digilent_arty_a7_100t'.
Final configuration file generated at /var/jenkins_home/workspace/maestro/maestro/build_digilent_arty_a7_100t.tcl
[LOCK] Removido: run.lock
Error executing Makefile.
ERROR: [Synth 8-8902] 'if_id_div' is not a component [/var/jenkins_home/workspace/maestro/maestro/Project/Components/datapath.vhd:129]
ERROR: [Synth 8-8902] 'id_ex_div' is not a component [/var/jenkins_home/workspace/maestro/maestro/Project/Components/datapath.vhd:134]
ERROR: [Synth 8-8902] 'alu' is not a component [/var/jenkins_home/workspace/maestro/maestro/Project/Components/datapath.vhd:141]
ERROR: [Synth 8-8902] 'ex_mem_div' is not a component [/var/jenkins_home/workspace/maestro/maestro/Project/Components/datapath.vhd:145]
ERROR: [Synth 8-8902] 'mem_wb_div' is not a component [/var/jenkins_home/workspace/maestro/maestro/Project/Components/datapath.vhd:151]
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details
make: *** [/eda/processor_ci/makefiles/digilent_arty_a7_100t.mk:12: digilent_arty_a7_100t.bit] Error 1

Traceback (most recent call last):
  File "/eda/processor_ci/main.py", line 142, in <module>
    main(
  File "/eda/processor_ci/main.py", line 89, in main
    build(build_file_path, board_name, toolchain_path)
  File "/eda/processor_ci/core/fpga.py", line 299, in build
    raise subprocess.CalledProcessError(process.returncode, 'make')
subprocess.CalledProcessError: Command 'make' returned non-zero exit status 2.