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Start of Pipeline - (21 sec in block)
node - (19 sec in block)
node block - (19 sec in block)
stage - (6.6 sec in block)Git Clone
stage block (Git Clone) - (6 sec in block)
sh - (0.66 sec in self)rm -rf *.xml
sh - (3.1 sec in self)rm -rf microrv32
sh - (1.8 sec in self)git clone --recursive --depth=1 https://github.com/agra-uni-bremen/microrv32 microrv32
stage - (2.2 sec in block)Verilog Convert
stage block (Verilog Convert) - (1.5 sec in block)
dir - (1 sec in block)microrv32
dir block - (0.72 sec in block)
sh - (0.49 sec in self)cd microrv32 && sbt run
stage - (1 sec in block)Simulation
stage block (Simulation) - (0.42 sec in block)
getContext - (0.17 sec in self)
stage - (1 sec in block)Utilities
stage block (Utilities) - (0.4 sec in block)
getContext - (0.17 sec in self)
stage - (6.6 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (6 sec in block)
getContext - (0.29 sec in self)
parallel - (5.3 sec in block)
parallel block (Branch: digilent_arty_a7_100t) - (4.9 sec in block)
stage - (4.5 sec in block)digilent_arty_a7_100t
stage block (digilent_arty_a7_100t) - (4.1 sec in block)
getContext - (0.82 sec in self)
stage - (1 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (0.41 sec in block)
getContext - (0.17 sec in self)
stage - (1 sec in block)Flash digilent_arty_a7_100t
stage block (Flash digilent_arty_a7_100t) - (0.4 sec in block)
getContext - (0.17 sec in self)
stage - (0.73 sec in block)Test digilent_arty_a7_100t
stage block (Test digilent_arty_a7_100t) - (0.39 sec in block)
getContext - (0.17 sec in self)
stage - (0.85 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (0.59 sec in block)
junit - (0.31 sec in self)**/*.xml