Skip to content
[Jenkins]Jenkins
log in

Console Output

+ python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p mmRISC-1 -b digilent_nexys4_ddr
Final configuration file generated at /var/jenkins_home/workspace/mmRISC-1/mmRISC-1/build_digilent_nexys4_ddr.tcl
Error executing Makefile.
ERROR: [Synth 8-9263] cannot open include file 'defines_chip.v' [/var/jenkins_home/workspace/mmRISC-1/mmRISC-1/verilog/chip/chip_top.v:198]
ERROR: [Synth 8-9263] cannot open include file 'defines_core.v' [/var/jenkins_home/workspace/mmRISC-1/mmRISC-1/verilog/chip/chip_top.v:199]
ERROR: [Synth 8-9263] cannot open include file 'defines_chip.v' [/var/jenkins_home/workspace/mmRISC-1/mmRISC-1/verilog/chip/chip_top_wrap.v:196]
ERROR: [Synth 8-9263] cannot open include file 'defines_core.v' [/var/jenkins_home/workspace/mmRISC-1/mmRISC-1/verilog/chip/chip_top_wrap.v:197]
ERROR: [Synth 8-9263] cannot open include file 'defines_chip.v' [/var/jenkins_home/workspace/mmRISC-1/mmRISC-1/verilog/cjtag/cjtag_2_jtag.v:83]
ERROR: [Synth 8-9263] cannot open include file 'defines_core.v' [/var/jenkins_home/workspace/mmRISC-1/mmRISC-1/verilog/cjtag/cjtag_2_jtag.v:84]
ERROR: [Synth 8-9263] cannot open include file 'defines_chip.v' [/var/jenkins_home/workspace/mmRISC-1/mmRISC-1/verilog/cjtag/cjtag_adapter.v:13]
ERROR: [Synth 8-9263] cannot open include file 'defines_core.v' [/var/jenkins_home/workspace/mmRISC-1/mmRISC-1/verilog/cjtag/cjtag_adapter.v:14]
ERROR: [Synth 8-9263] cannot open include file 'defines_core.v' [/var/jenkins_home/workspace/mmRISC-1/mmRISC-1/verilog/cpu/cpu_csr.v:163]
ERROR: [Synth 8-9263] cannot open include file 'defines_core.v' [/var/jenkins_home/workspace/mmRISC-1/mmRISC-1/verilog/cpu/cpu_csr_dbg.v:77]
ERROR: [Synth 8-9263] cannot open include file 'defines_core.v' [/var/jenkins_home/workspace/mmRISC-1/mmRISC-1/verilog/cpu/cpu_csr_int.v:45]
ERROR: [Synth 8-9263] cannot open include file 'defines_core.v' [/var/jenkins_home/workspace/mmRISC-1/mmRISC-1/verilog/cpu/cpu_datapath.v:13]
ERROR: [Synth 8-9263] cannot open include file 'defines_core.v' [/var/jenkins_home/workspace/mmRISC-1/mmRISC-1/verilog/cpu/cpu_debug.v:13]
ERROR: [Synth 8-9263] cannot open include file 'defines_core.v' [/var/jenkins_home/workspace/mmRISC-1/mmRISC-1/verilog/cpu/cpu_fetch.v:123]
ERROR: [Synth 8-9263] cannot open include file 'defines_core.v' [/var/jenkins_home/workspace/mmRISC-1/mmRISC-1/verilog/cpu/cpu_fpu32.v:79]
ERROR: [Synth 8-9263] cannot open include file 'defines_core.v' [/var/jenkins_home/workspace/mmRISC-1/mmRISC-1/verilog/cpu/cpu_pipeline.v:75]
ERROR: [Synth 8-9263] cannot open include file 'defines_core.v' [/var/jenkins_home/workspace/mmRISC-1/mmRISC-1/verilog/cpu/cpu_top.v:15]
ERROR: [Synth 8-9263] cannot open include file 'defines_core.v' [/var/jenkins_home/workspace/mmRISC-1/mmRISC-1/verilog/debug/debug_dm.v:94]
ERROR: [Synth 8-9263] cannot open include file 'defines_core.v' [/var/jenkins_home/workspace/mmRISC-1/mmRISC-1/verilog/debug/debug_dtm_jtag.v:28]
ERROR: [Synth 8-10632] declarations are not allowed in an unnamed block [/var/jenkins_home/workspace/mmRISC-1/mmRISC-1/verilog/ahb_matrix/ahb_arb.v:45]
ERROR: [Synth 8-2716] syntax error near ''' [/var/jenkins_home/workspace/mmRISC-1/mmRISC-1/verilog/ahb_matrix/ahb_arb.v:71]
ERROR: [Synth 8-10632] declarations are not allowed in an unnamed block [/var/jenkins_home/workspace/mmRISC-1/mmRISC-1/verilog/ahb_matrix/ahb_arb.v:59]
ERROR: [Synth 8-2716] syntax error near ''' [/var/jenkins_home/workspace/mmRISC-1/mmRISC-1/verilog/ahb_matrix/ahb_arb.v:91]
ERROR: [Synth 8-2716] syntax error near ''' [/var/jenkins_home/workspace/mmRISC-1/mmRISC-1/verilog/ahb_matrix/ahb_arb.v:92]
ERROR: [Synth 8-2716] syntax error near ''' [/var/jenkins_home/workspace/mmRISC-1/mmRISC-1/verilog/ahb_matrix/ahb_arb.v:97]
ERROR: [Synth 8-2716] syntax error near ''' [/var/jenkins_home/workspace/mmRISC-1/mmRISC-1/verilog/ahb_matrix/ahb_arb.v:101]
ERROR: [Synth 8-10632] declarations are not allowed in an unnamed block [/var/jenkins_home/workspace/mmRISC-1/mmRISC-1/verilog/ahb_matrix/ahb_arb.v:88]
ERROR: [Synth 8-2716] syntax error near ''' [/var/jenkins_home/workspace/mmRISC-1/mmRISC-1/verilog/ahb_matrix/ahb_arb.v:142]
ERROR: [Synth 8-10632] declarations are not allowed in an unnamed block [/var/jenkins_home/workspace/mmRISC-1/mmRISC-1/verilog/ahb_matrix/ahb_arb.v:125]
ERROR: [Synth 8-10632] declarations are not allowed in an unnamed block [/var/jenkins_home/workspace/mmRISC-1/mmRISC-1/verilog/ahb_matrix/ahb_arb.v:173]
ERROR: [Synth 8-10632] declarations are not allowed in an unnamed block [/var/jenkins_home/workspace/mmRISC-1/mmRISC-1/verilog/ahb_matrix/ahb_arb.v:193]
ERROR: [Synth 8-9917] port 'ARB_PRIORITY' must not be declared to be an array [/var/jenkins_home/workspace/mmRISC-1/mmRISC-1/verilog/ahb_matrix/ahb_arb.v:27]
ERROR: [Synth 8-10632] declarations are not allowed in an unnamed block [/var/jenkins_home/workspace/mmRISC-1/mmRISC-1/verilog/ahb_matrix/ahb_arb.v:237]
ERROR: [Synth 8-10632] declarations are not allowed in an unnamed block [/var/jenkins_home/workspace/mmRISC-1/mmRISC-1/verilog/ahb_matrix/ahb_arb.v:254]
ERROR: [Synth 8-10632] declarations are not allowed in an unnamed block [/var/jenkins_home/workspace/mmRISC-1/mmRISC-1/verilog/ahb_matrix/ahb_arb.v:269]
ERROR: [Synth 8-439] module 'Controller' not found [/eda/processor_ci/rtl/mmRISC-1.v:48]
ERROR: [Synth 8-6156] failed synthesizing module 'processorci_top' [/eda/processor_ci/rtl/mmRISC-1.v:1]
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details
make: *** [/eda/processor_ci/makefiles/digilent_nexys4_ddr.mk:12: digilent_nexys4_ddr.bit] Error 1

Traceback (most recent call last):
  File "/eda/processor_ci/main.py", line 135, in <module>
    main(
  File "/eda/processor_ci/main.py", line 82, in main
    build(build_file_path, board_name, toolchain_path)
  File "/eda/processor_ci/core/fpga.py", line 218, in build
    raise subprocess.CalledProcessError(process.returncode, 'make')
subprocess.CalledProcessError: Command 'make' returned non-zero exit status 2.