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Start of Pipeline - (1 min 16 sec in block)
node - (1 min 15 sec in block)
node block - (1 min 14 sec in block)
stage - (19 sec in block)Git Clone
stage block (Git Clone) - (19 sec in block)
sh - (0.44 sec in self)rm -rf *.xml
sh - (0.46 sec in self)rm -rf mmRISC-1
sh - (18 sec in self)git clone --recursive --depth=1 https://github.com/munetomo-maruyama/mmRISC-1 mmRISC-1
stage - (1.3 sec in block)Simulation
stage block (Simulation) - (0.88 sec in block)
dir - (0.53 sec in block)mmRISC-1
dir block - (0.29 sec in block)
echo - (0.1 sec in self)FPGA > Simulation
stage - (1.6 sec in block)Utilities
stage block (Utilities) - (1.1 sec in block)
dir - (0.81 sec in block)mmRISC-1
dir block - (0.58 sec in block)
sh - (0.39 sec in self)python3 /eda/processor_ci/core/labeler_prototype.py -d $(pwd) -c /eda/processor_ci/config -o /jenkins/processor_ci_utils/labels
stage - (50 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (48 sec in block)
parallel - (47 sec in block)
parallel block (Branch: digilent_arty_a7_100t) - (46 sec in block)
stage - (46 sec in block)digilent_arty_a7_100t
stage block (digilent_arty_a7_100t) - (45 sec in block)
lock - (45 sec in block)digilent_arty_a7_100t
lock block - (44 sec in block)
stage - (35 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (28 sec in block)
dir - (27 sec in block)mmRISC-1
dir block - (27 sec in block)
echo - (0.15 sec in self)Starting synthesis for FPGA digilent_arty_a7_100t.
sh - (26 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p mmRISC-1 -b digilent_arty_a7_100t
stage - (7.3 sec in block)Flash digilent_arty_a7_100t
stage block (Flash digilent_arty_a7_100t) - (3.1 sec in block)
getContext - (1.6 sec in self)
stage - (1.2 sec in block)Test digilent_arty_a7_100t
stage block (Test digilent_arty_a7_100t) - (0.74 sec in block)
getContext - (0.36 sec in self)
stage - (1.4 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (0.98 sec in block)
junit - (0.47 sec in self)**/*.xml