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+ python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p mmRISC-1 -b digilent_arty_a7_100t
[LOCK] Criado: run.lock
File 'processor_ci_defines.vh' generated for board: 'digilent_arty_a7_100t'.
Final configuration file generated at /var/jenkins_home/workspace/mmRISC-1/mmRISC-1/build_digilent_arty_a7_100t.tcl
[LOCK] Removido: run.lock
Error executing Makefile.
ERROR: [Synth 8-10632] declarations are not allowed in an unnamed block [/var/jenkins_home/workspace/mmRISC-1/mmRISC-1/verilog/cpu/cpu_csr_dbg.v:470]
ERROR: [Synth 8-10632] declarations are not allowed in an unnamed block [/var/jenkins_home/workspace/mmRISC-1/mmRISC-1/verilog/cpu/cpu_csr_dbg.v:499]
ERROR: [Synth 8-10632] declarations are not allowed in an unnamed block [/var/jenkins_home/workspace/mmRISC-1/mmRISC-1/verilog/cpu/cpu_csr_dbg.v:601]
ERROR: [Synth 8-10632] declarations are not allowed in an unnamed block [/var/jenkins_home/workspace/mmRISC-1/mmRISC-1/verilog/cpu/cpu_csr_dbg.v:626]
ERROR: [Synth 8-10632] declarations are not allowed in an unnamed block [/var/jenkins_home/workspace/mmRISC-1/mmRISC-1/verilog/cpu/cpu_csr_dbg.v:638]
ERROR: [Synth 8-10632] declarations are not allowed in an unnamed block [/var/jenkins_home/workspace/mmRISC-1/mmRISC-1/verilog/cpu/cpu_csr_dbg.v:785]
ERROR: [Synth 8-10632] declarations are not allowed in an unnamed block [/var/jenkins_home/workspace/mmRISC-1/mmRISC-1/verilog/cpu/cpu_csr_dbg.v:811]
ERROR: [Synth 8-10632] declarations are not allowed in an unnamed block [/var/jenkins_home/workspace/mmRISC-1/mmRISC-1/verilog/cpu/cpu_csr_dbg.v:849]
ERROR: [Synth 8-10632] declarations are not allowed in an unnamed block [/var/jenkins_home/workspace/mmRISC-1/mmRISC-1/verilog/cpu/cpu_csr_dbg.v:864]
ERROR: [Synth 8-10632] declarations are not allowed in an unnamed block [/var/jenkins_home/workspace/mmRISC-1/mmRISC-1/verilog/cpu/cpu_csr_dbg.v:890]
ERROR: [Synth 8-10632] declarations are not allowed in an unnamed block [/var/jenkins_home/workspace/mmRISC-1/mmRISC-1/verilog/cpu/cpu_csr_dbg.v:912]
ERROR: [Synth 8-9917] port 'TRG_CND_BUS' must not be declared to be an array [/var/jenkins_home/workspace/mmRISC-1/mmRISC-1/verilog/cpu/cpu_csr_dbg.v:126]
ERROR: [Synth 8-9917] port 'TRG_CND_BUS_CHAIN' must not be declared to be an array [/var/jenkins_home/workspace/mmRISC-1/mmRISC-1/verilog/cpu/cpu_csr_dbg.v:127]
ERROR: [Synth 8-9917] port 'TRG_CND_BUS_ACTION' must not be declared to be an array [/var/jenkins_home/workspace/mmRISC-1/mmRISC-1/verilog/cpu/cpu_csr_dbg.v:128]
ERROR: [Synth 8-9917] port 'TRG_CND_BUS_MATCH' must not be declared to be an array [/var/jenkins_home/workspace/mmRISC-1/mmRISC-1/verilog/cpu/cpu_csr_dbg.v:129]
ERROR: [Synth 8-9917] port 'TRG_CND_BUS_MASK' must not be declared to be an array [/var/jenkins_home/workspace/mmRISC-1/mmRISC-1/verilog/cpu/cpu_csr_dbg.v:130]
ERROR: [Synth 8-9917] port 'TRG_CND_BUS_HIT' must not be declared to be an array [/var/jenkins_home/workspace/mmRISC-1/mmRISC-1/verilog/cpu/cpu_csr_dbg.v:131]
ERROR: [Synth 8-9917] port 'TRG_CND_TDATA2' must not be declared to be an array [/var/jenkins_home/workspace/mmRISC-1/mmRISC-1/verilog/cpu/cpu_csr_dbg.v:132]
ERROR: [Synth 8-439] module 'uart_rx' not found [/eda/processor-ci-controller/modules/uart.sv:260]
ERROR: [Synth 8-6156] failed synthesizing module 'UART' [/eda/processor-ci-controller/modules/uart.sv:1]
ERROR: [Synth 8-6156] failed synthesizing module 'Controller' [/eda/processor-ci-controller/rtl/controller.sv:1]
ERROR: [Synth 8-6156] failed synthesizing module 'processorci_top' [/eda/processor_ci/rtl/mmRISC-1.sv:7]
ERROR: [Synth 8-6156] failed synthesizing module 'fpga_top' [/eda/processor_ci/internal/fpga_top.sv:8]
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details
make: *** [/eda/processor_ci/makefiles/digilent_arty_a7_100t.mk:12: digilent_arty_a7_100t.bit] Error 1

Traceback (most recent call last):
  File "/eda/processor_ci/main.py", line 142, in <module>
    main(
  File "/eda/processor_ci/main.py", line 89, in main
    build(build_file_path, board_name, toolchain_path)
  File "/eda/processor_ci/core/fpga.py", line 299, in build
    raise subprocess.CalledProcessError(process.returncode, 'make')
subprocess.CalledProcessError: Command 'make' returned non-zero exit status 2.