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Start of Pipeline - (6 min 59 sec in block)
node - (6 min 57 sec in block)
node block - (42 sec in block)
stage - (21 sec in block)Git Clone
stage block (Git Clone) - (20 sec in block)
sh - (0.56 sec in self)rm -rf *.xml
sh - (0.48 sec in self)rm -rf mmRISC-1
sh - (19 sec in self)git clone --recursive --depth=1 https://github.com/munetomo-maruyama/mmRISC-1 mmRISC-1
stage - (3.9 sec in block)Simulation
stage block (Simulation) - (2.7 sec in block)
dir - (1.7 sec in block)mmRISC-1
dir block - (1.1 sec in block)
sh - (0.69 sec in self)/eda/oss-cad-suite/bin/iverilog -o simulation.out -g2005 -s CPU_TOP -I verilog/common/ verilog/cpu/cpu_csr.v verilog/cpu/cpu_csr_dbg.v verilog/cpu/cpu_csr_int.v verilog/cpu/cpu_datapath.v verilog/cpu/cpu_debug.v verilog/cpu/cpu_fetch.v verilog/cpu/cpu_fpu32.v verilog/cpu/cpu_pipeline.v verilog/cpu/cpu_top.v
stage - (1.9 sec in block)Utilities
stage block (Utilities) - (0.82 sec in block)
getContext - (0.36 sec in self)
stage - (12 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (11 sec in block)
getContext - (0.58 sec in self)
parallel - (10 sec in block)
parallel block (Branch: digilent_arty_a7_100t) - (9.4 sec in block)
stage - (8.5 sec in block)digilent_arty_a7_100t
stage block (digilent_arty_a7_100t) - (7.9 sec in block)
getContext - (0.81 sec in self)
stage - (2.2 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (0.78 sec in block)
getContext - (0.36 sec in self)
stage - (2.4 sec in block)Flash digilent_arty_a7_100t
stage block (Flash digilent_arty_a7_100t) - (1 sec in block)
getContext - (0.5 sec in self)
stage - (1.5 sec in block)Test digilent_arty_a7_100t
stage block (Test digilent_arty_a7_100t) - (0.82 sec in block)
getContext - (0.36 sec in self)
stage - (1.6 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (1.1 sec in block)
junit - (0.55 sec in self)**/*.xml