Console Output

+ /eda/oss-cad-suite/bin/iverilog -o simulation.out -g2005 -s bench/formal/f_multiclock_op.v bench/formal/fspr_master.v bench/formal/fspr_slave.v bench/formal/fwb_master.v bench/verilog/mor1kx_monitor.v bench/verilog/mor1kx_traceport_monitor.v rtl/verilog/mor1kx-defines.v rtl/verilog/mor1kx-sprs.v rtl/verilog/mor1kx.v rtl/verilog/mor1kx_branch_prediction.v rtl/verilog/mor1kx_branch_predictor_gshare.v rtl/verilog/mor1kx_branch_predictor_saturation_counter.v rtl/verilog/mor1kx_branch_predictor_simple.v rtl/verilog/mor1kx_bus_if_wb32.v rtl/verilog/mor1kx_cache_lru.v rtl/verilog/mor1kx_cfgrs.v rtl/verilog/mor1kx_cpu.v rtl/verilog/mor1kx_cpu_cappuccino.v rtl/verilog/mor1kx_cpu_espresso.v rtl/verilog/mor1kx_cpu_prontoespresso.v rtl/verilog/mor1kx_ctrl_cappuccino.v rtl/verilog/mor1kx_ctrl_espresso.v rtl/verilog/mor1kx_ctrl_prontoespresso.v rtl/verilog/mor1kx_dcache.v rtl/verilog/mor1kx_decode.v rtl/verilog/mor1kx_decode_execute_cappuccino.v rtl/verilog/mor1kx_dmmu.v rtl/verilog/mor1kx_execute_alu.v rtl/verilog/mor1kx_execute_ctrl_cappuccino.v rtl/verilog/mor1kx_fetch_cappuccino.v rtl/verilog/mor1kx_fetch_espresso.v rtl/verilog/mor1kx_fetch_prontoespresso.v rtl/verilog/mor1kx_fetch_tcm_prontoespresso.v rtl/verilog/mor1kx_icache.v rtl/verilog/mor1kx_immu.v rtl/verilog/mor1kx_lsu_cappuccino.v rtl/verilog/mor1kx_lsu_espresso.v rtl/verilog/mor1kx_pcu.v rtl/verilog/mor1kx_pic.v rtl/verilog/mor1kx_rf_cappuccino.v rtl/verilog/mor1kx_rf_espresso.v rtl/verilog/mor1kx_simple_dpram_sclk.v rtl/verilog/mor1kx_store_buffer.v rtl/verilog/mor1kx_ticktimer.v rtl/verilog/mor1kx_true_dpram_sclk.v rtl/verilog/mor1kx_wb_mux_cappuccino.v rtl/verilog/mor1kx_wb_mux_espresso.v rtl/verilog/pfpu32/pfpu32_addsub.v rtl/verilog/pfpu32/pfpu32_cmp.v rtl/verilog/pfpu32/pfpu32_f2i.v rtl/verilog/pfpu32/pfpu32_i2f.v rtl/verilog/pfpu32/pfpu32_muldiv.v rtl/verilog/pfpu32/pfpu32_rnd.v rtl/verilog/pfpu32/pfpu32_top.v
bench/formal/fspr_master.v:44: warning: macro OR1K_SPR_ICBIR_ADDR undefined (and assumed null) at this point.
bench/formal/fspr_master.v:45: warning: macro OR1K_SPR_DCBIR_ADDR undefined (and assumed null) at this point.
bench/formal/fspr_master.v:46: warning: macro OR1K_SPR_DCBFR_ADDR undefined (and assumed null) at this point.
bench/formal/fspr_slave.v:37: warning: macro OR1K_SPR_ICBIR_ADDR undefined (and assumed null) at this point.
bench/formal/fspr_slave.v:39: warning: macro OR1K_SPR_DCBIR_ADDR undefined (and assumed null) at this point.
bench/formal/fspr_slave.v:40: warning: macro OR1K_SPR_DCBFR_ADDR undefined (and assumed null) at this point.
bench/verilog/mor1kx_monitor.v:35: Include file mor1kx-defines.v not found
bench/formal/fspr_master.v:44: syntax error
bench/formal/fspr_master.v:42: error: Syntax error in continuous assignment
bench/formal/fspr_slave.v:37: syntax error
bench/formal/fspr_slave.v:35: error: Syntax error in continuous assignment
bench/formal/fwb_master.v:58: error: Local parameter in module parameter port list requires SystemVerilog.
bench/formal/fwb_master.v:60: error: Local parameter in module parameter port list requires SystemVerilog.