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Start of Pipeline - (23 sec in block)
node - (22 sec in block)
node block - (22 sec in block)
stage - (3.7 sec in block)Git Clone
stage block (Git Clone) - (2.6 sec in block)
sh - (0.63 sec in self)rm -rf *.xml
sh - (0.62 sec in self)rm -rf mr1
sh - (1 sec in self)git clone --recursive --depth=1 https://github.com/tomverbeure/mr1 mr1
stage - (4.8 sec in block)Verilog Convert
stage block (Verilog Convert) - (3.3 sec in block)
dir - (2.1 sec in block)mr1
dir block - (1.3 sec in block)
sh - (0.85 sec in self)sbt "run-main mr1.MR1Verilog"
stage - (1.4 sec in block)Simulation
stage block (Simulation) - (0.59 sec in block)
getContext - (0.27 sec in self)
stage - (1.4 sec in block)Utilities
stage block (Utilities) - (0.54 sec in block)
getContext - (0.27 sec in self)
stage - (8.7 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (7.8 sec in block)
getContext - (0.46 sec in self)
parallel - (6.6 sec in block)
parallel block (Branch: digilent_arty_a7_100t) - (6.1 sec in block)
stage - (5.5 sec in block)digilent_arty_a7_100t
stage block (digilent_arty_a7_100t) - (5 sec in block)
getContext - (0.65 sec in self)
stage - (1.4 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (0.56 sec in block)
getContext - (0.26 sec in self)
stage - (1.4 sec in block)Flash digilent_arty_a7_100t
stage block (Flash digilent_arty_a7_100t) - (0.52 sec in block)
getContext - (0.25 sec in self)
stage - (1 sec in block)Test digilent_arty_a7_100t
stage block (Test digilent_arty_a7_100t) - (0.59 sec in block)
getContext - (0.27 sec in self)
stage - (1 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (0.74 sec in block)
junit - (0.35 sec in self)**/*.xml