Console Output

+ /eda/oss-cad-suite/bin/iverilog -o simulation.out -g2005 -s quartus_mr1/altera_models/cpu_ram.v quartus_mr1/altera_models/cpu_ram_bb.v quartus_mr1/altera_models/cpu_ram_inst.v quartus_pico/altera_models/cpu_ram.v quartus_pico/altera_models/cpu_ram_bb.v quartus_pico/altera_models/cpu_ram_inst.v
quartus_mr1/altera_models/cpu_ram_inst.v:1: syntax error
I give up.