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Started by timer
[Pipeline] Start of Pipeline
[Pipeline] node
Running on Jenkins in /var/jenkins_home/workspace/openc910
[Pipeline] {
[Pipeline] stage
[Pipeline] { (Git Clone)
[Pipeline] sh
+ rm -rf *.xml
[Pipeline] sh
+ rm -rf openc910
[Pipeline] sh
+ git clone --recursive --depth=1 https://github.com/XUANTIE-RV/openc910/ openc910
Cloning into 'openc910'...
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Simulation)
[Pipeline] dir
Running in /var/jenkins_home/workspace/openc910/openc910
[Pipeline] {
[Pipeline] echo
FPGA > Simulation
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Utilities)
[Pipeline] dir
Running in /var/jenkins_home/workspace/openc910/openc910
[Pipeline] {
[Pipeline] sh
+ pwd
+ python3 /eda/processor_ci/core/labeler_prototype.py -d /var/jenkins_home/workspace/openc910/openc910 -c /eda/processor_ci/config -o /jenkins/processor_ci_utils/labels
Trying to read file: /var/jenkins_home/workspace/openc910/openc910/C910_RTL_FACTORY/gen_rtl/biu/rtl/ct_biu_csr_req_arbiter.v
Cache-related signals in cpu_btb_mem_test_tb.v
Cache-related signals in cpu_imem_test_tb.v
Cache-related signals in cpu_l2_mem_test_tb.v
Cache-related signals in cpu_icg_test_tb.v
Cache-related signals in cpu_ifupred_mem_test_tb.v
Cache-related signals in cpu_dmem_test_tb.v
Cache-related signals in cpu_mmu_mem_test_tb.v
Cache-related signals in tap2_sm.v
Possible cache file: ct_lsu_dcache_info_update.v
Cache-related signals in ct_lsu_dcache_info_update.v
Cache-related signals in ct_lsu_vb_sdb_data_entry.v
Possible cache file: ct_lsu_dcache_arb.v
Cache-related signals in ct_lsu_dcache_arb.v
Cache-related signals in ct_lsu_snoop_snq.v
Possible cache file: ct_lsu_dcache_top.v
Cache-related signals in ct_lsu_dcache_top.v
Cache-related signals in ct_lsu_st_da.v
Possible cache file: ct_lsu_dcache_data_array.v
Cache-related signals in ct_lsu_st_ag.v
Cache-related signals in ct_lsu_mcic.v
Possible cache file: ct_lsu_dcache_dirty_array.v
Cache-related signals in ct_lsu_wmb.v
Cache-related signals in ct_lsu_vb.v
Cache-related signals in ct_lsu_st_dc.v
Cache-related signals in ct_lsu_icc.v
Possible cache file: ct_lsu_dcache_ld_tag_array.v
Cache-related signals in ct_lsu_ld_ag.v
Cache-related signals in ct_lsu_ld_da.v
Possible cache file: ct_lsu_dcache_tag_array.v
Cache-related signals in ct_lsu_rb.v
Possible cache file: ct_lsu_cache_buffer.v
Cache-related signals in ct_lsu_ld_dc.v
Cache-related signals in ct_lsu_idfifo_8.v
Cache-related signals in ct_lsu_snoop_snq_entry.v
Cache-related signals in ct_lsu_snoop_ctcq_entry.v
Cache-related signals in ct_lsu_lfb.v
Cache-related signals in ct_ciu_snb_sab_entry.v
Cache-related signals in ct_ciu_vb.v
Cache-related signals in ct_prio.v
Cache-related signals in ct_ciu_ctcq.v
Cache-related signals in ct_piu_top.v
Cache-related signals in ct_ciu_bmbif_kid.v
Cache-related signals in ct_ciu_ebiuif.v
Cache-related signals in ct_ciu_snb_arb.v
Cache-related signals in ct_ciu_ncq.v
Cache-related signals in ct_vfmau_mult_simd_half.v
Cache-related signals in ct_vfmau_mult1.v
Cache-related signals in ct_fadd_half_dp.v
Cache-related signals in ct_fadd_double_dp.v
Possible cache file: ct_l2cache_data_array.v
Cache-related signals in ct_l2c_icc.v
Cache-related signals in ct_l2c_tag.v
Possible cache file: ct_l2cache_dirty_array_16way.v
Possible cache file: ct_l2cache_top.v
Cache-related signals in ct_l2cache_top.v
Possible cache file: ct_l2cache_tag_array_16way.v
Cache-related signals in ct_l2c_cmp.v
Cache-related signals in ct_biu_write_channel.v
Cache-related signals in ct_idu_id_ctrl.v
Cache-related signals in ct_idu_is_pipe_entry.v
Cache-related signals in ct_idu_is_viq0.v
Cache-related signals in ct_idu_rf_prf_eregfile.v
Cache-related signals in ct_idu_rf_ctrl.v
Cache-related signals in ct_idu_ir_ctrl.v
Cache-related signals in ct_idu_ir_dp.v
Cache-related signals in ct_idu_is_biq.v
Cache-related signals in ct_idu_is_aiq0.v
Cache-related signals in ct_idu_is_biq_entry.v
Cache-related signals in ct_idu_id_decd.v
Cache-related signals in ct_idu_dep_reg_src2_entry.v
Cache-related signals in ct_idu_is_ctrl.v
Cache-related signals in ct_idu_is_viq0_entry.v
Cache-related signals in ct_idu_ir_frt.v
Cache-related signals in ct_idu_is_aiq1_entry.v
Cache-related signals in ct_idu_dep_vreg_srcv2_entry.v
Cache-related signals in ct_idu_is_lsiq_entry.v
Cache-related signals in ct_idu_is_aiq0_entry.v
Cache-related signals in ct_idu_is_dp.v
Cache-related signals in ct_idu_is_aiq1.v
Cache-related signals in ct_idu_is_sdiq.v
Cache-related signals in ct_idu_dep_reg_entry.v
Cache-related signals in ct_idu_is_viq1_entry.v
Cache-related signals in ct_idu_ir_rt.v
Cache-related signals in ct_idu_is_viq1.v
Cache-related signals in ct_idu_dep_vreg_entry.v
Cache-related signals in ct_idu_is_lsiq.v
Cache-related signals in ct_idu_is_sdiq_entry.v
Cache-related signals in ct_cp0_iui.v
Cache-related signals in ct_cp0_regs.v
Cache-related signals in ct_mmu_ptw.v
Cache-related signals in ct_mmu_jtlb.v
Cache-related signals in ct_mmu_dutlb_read.v
Cache-related signals in ct_mmu_arb.v
Cache-related signals in ct_mmu_regs.v
Cache-related signals in ct_mmu_iutlb.v
Cache-related signals in ct_mmu_tlboper.v
Cache-related signals in ct_had_common_dbg_info.v
Cache-related signals in ct_had_trace.v
Cache-related signals in ct_had_dbg_info.v
Cache-related signals in ct_had_bkpt.v
Cache-related signals in ct_vfpu_dp.v
Cache-related signals in ct_vfpu_ctrl.v
Cache-related signals in ct_iu_special.v
Cache-related signals in multiplier_65x65_3_stage.v
Cache-related signals in ct_iu_bju_pcfifo.v
Cache-related signals in ct_iu_alu.v
Cache-related signals in ct_iu_mult.v
Cache-related signals in ct_rtu_retire.v
Cache-related signals in ct_rtu_rob_rt.v
Cache-related signals in ct_rtu_rob.v
Cache-related signals in ct_rtu_pst_ereg.v
Cache-related signals in ct_rtu_pst_vreg.v
Cache-related signals in ct_rtu_pst_preg.v
Cache-related signals in plic_granu_arb.v
Cache-related signals in ct_ifu_ibctrl.v
Cache-related signals in ct_ifu_btb.v
Cache-related signals in ct_ifu_ipdp.v
Cache-related signals in ct_ifu_ifctrl.v
Cache-related signals in ct_ifu_sfp.v
Cache-related signals in ct_ifu_l0_btb.v
Possible cache file: ct_ifu_icache_predecd_array1.v
Cache-related signals in ct_ifu_ras.v
Cache-related signals in ct_ifu_ipctrl.v
Possible cache file: ct_ifu_icache_predecd_array0.v
Possible cache file: ct_ifu_icache_data_array1.v
Cache-related signals in ct_ifu_lbuf_entry.v
Cache-related signals in ct_ifu_bht.v
Cache-related signals in ct_ifu_ibuf.v
Cache-related signals in ct_ifu_l0_btb_entry.v
Cache-related signals in ct_ifu_ibuf_entry.v
Cache-related signals in ct_ifu_lbuf.v
Possible cache file: ct_ifu_icache_data_array0.v
Cache-related signals in ct_ifu_pcfifo_if.v
Cache-related signals in ct_ifu_ibdp.v
Possible cache file: ct_ifu_icache_tag_array.v
Possible cache file: ct_ifu_icache_if.v
Cache-related signals in ct_ifu_icache_if.v
Cache-related signals in ct_ifu_l1_refill.v
Cache-related signals in ct_vfdsu_round.v
Results saved to /jenkins/processor_ci_utils/labels/openc910.json
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (FPGA Build Pipeline)
[Pipeline] parallel
[Pipeline] { (Branch: digilent_arty_a7_100t)
[Pipeline] stage
[Pipeline] { (digilent_arty_a7_100t)
[Pipeline] lock
Trying to acquire lock on [Resource: digilent_arty_a7_100t]
The resource [digilent_arty_a7_100t] is locked by build T13x #648 #648 since Apr 12, 2026, 2:36 AM.
[Resource: digilent_arty_a7_100t] is not free, waiting for execution ...
[Required resources: [digilent_arty_a7_100t]] added into queue at position 0
Lock acquired on [Resource: digilent_arty_a7_100t]
[Pipeline] {
[Pipeline] stage
[Pipeline] { (Synthesis and PnR)
[Pipeline] dir
Running in /var/jenkins_home/workspace/openc910/openc910
[Pipeline] {
[Pipeline] echo
Starting synthesis for FPGA digilent_arty_a7_100t.
[Pipeline] sh
+ python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p openc910 -b digilent_arty_a7_100t
[LOCK] Criado: run.lock
File 'processor_ci_defines.vh' generated for board: 'digilent_arty_a7_100t'.
Final configuration file generated at /var/jenkins_home/workspace/openc910/openc910/build_digilent_arty_a7_100t.tcl
[LOCK] Removido: run.lock
Error executing Makefile.
ERROR: [Synth 8-10157] use of undefined macro 'PA_WIDTH' [/var/jenkins_home/workspace/openc910/openc910/C910_RTL_FACTORY/gen_rtl/biu/rtl/ct_biu_read_channel.v:293]
ERROR: [Synth 8-439] module 'uart_rx' not found [/eda/processor-ci-controller/modules/uart.sv:260]
ERROR: [Synth 8-6156] failed synthesizing module 'UART' [/eda/processor-ci-controller/modules/uart.sv:1]
ERROR: [Synth 8-6156] failed synthesizing module 'Controller' [/eda/processor-ci-controller/rtl/controller.sv:1]
ERROR: [Synth 8-6156] failed synthesizing module 'processorci_top' [/eda/processor_ci/rtl/openc910.sv:7]
ERROR: [Synth 8-6156] failed synthesizing module 'fpga_top' [/eda/processor_ci/internal/fpga_top.sv:8]
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details
make: *** [/eda/processor_ci/makefiles/digilent_arty_a7_100t.mk:12: digilent_arty_a7_100t.bit] Error 1

Traceback (most recent call last):
  File "/eda/processor_ci/main.py", line 142, in <module>
    main(
  File "/eda/processor_ci/main.py", line 89, in main
    build(build_file_path, board_name, toolchain_path)
  File "/eda/processor_ci/core/fpga.py", line 299, in build
    raise subprocess.CalledProcessError(process.returncode, 'make')
subprocess.CalledProcessError: Command 'make' returned non-zero exit status 2.
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Flash digilent_arty_a7_100t)
Stage "Flash digilent_arty_a7_100t" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Test digilent_arty_a7_100t)
Stage "Test digilent_arty_a7_100t" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Lock released on resource [Resource: digilent_arty_a7_100t]
[Pipeline] // lock
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Failed in branch digilent_arty_a7_100t
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Declarative: Post Actions)
[Pipeline] junit
Recording test results
No test report files were found. Configuration error?
Error when executing always post condition:
Also:   org.jenkinsci.plugins.workflow.actions.ErrorAction$ErrorId: 7f558713-70a3-45a2-b580-443bc20c7fd7
hudson.AbortException: No test report files were found. Configuration error?
	at PluginClassLoader for junit//hudson.tasks.junit.JUnitParser$ParseResultCallable.invoke(JUnitParser.java:253)
	at hudson.FilePath.act(FilePath.java:1234)
	at hudson.FilePath.act(FilePath.java:1217)
	at PluginClassLoader for junit//hudson.tasks.junit.JUnitParser.parseResult(JUnitParser.java:146)
	at PluginClassLoader for junit//hudson.tasks.junit.JUnitResultArchiver.parse(JUnitResultArchiver.java:177)
	at PluginClassLoader for junit//hudson.tasks.junit.JUnitResultArchiver.parseAndSummarize(JUnitResultArchiver.java:282)
	at PluginClassLoader for junit//hudson.tasks.junit.pipeline.JUnitResultsStepExecution.run(JUnitResultsStepExecution.java:62)
	at PluginClassLoader for junit//hudson.tasks.junit.pipeline.JUnitResultsStepExecution.run(JUnitResultsStepExecution.java:27)
	at PluginClassLoader for workflow-step-api//org.jenkinsci.plugins.workflow.steps.SynchronousNonBlockingStepExecution.lambda$start$0(SynchronousNonBlockingStepExecution.java:49)
	at java.base/java.util.concurrent.Executors$RunnableAdapter.call(Unknown Source)
	at java.base/java.util.concurrent.FutureTask.run(Unknown Source)
	at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(Unknown Source)
	at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(Unknown Source)
	at java.base/java.lang.Thread.run(Unknown Source)

[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // node
[Pipeline] End of Pipeline
ERROR: script returned exit code 1
Finished: FAILURE