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Start of Pipeline - (3 min 11 sec in block)
node - (3 min 11 sec in block)
node block - (3 min 10 sec in block)
stage - (2.6 sec in block)Git Clone
stage block (Git Clone) - (1.7 sec in block)
sh - (0.54 sec in self)rm -rf riscado-v
sh - (1 sec in self)git clone --recursive --depth=1 https://github.com/zxmarcos/riscado-v riscado-v
stage - (2.1 sec in block)Simulation
stage block (Simulation) - (1.6 sec in block)
dir - (1 sec in block)riscado-v
dir block - (0.69 sec in block)
sh - (0.42 sec in self)/eda/oss-cad-suite/bin/iverilog -o simulation.out -g2005 -s RISCV alu.v control_unit.v program_counter.v register_file.v riscv.v load_store.v
stage - (1.7 sec in block)Utilities
stage block (Utilities) - (1.2 sec in block)
dir - (0.86 sec in block)riscado-v
dir block - (0.62 sec in block)
sh - (0.41 sec in self)python3 /eda/processor_ci/core/labeler_prototype.py -d $(pwd) -c /eda/processor_ci/config.json -o /jenkins/processor_ci_utils/labels.json
stage - (3 min 3 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (3 min 2 sec in block)
parallel - (3 min 2 sec in block)
parallel block (Branch: colorlight_i9) - (58 ms in block)
stage - (3 min 1 sec in block)colorlight_i9
stage block (colorlight_i9) - (3 min 0 sec in block)
lock - (3 min 0 sec in block)colorlight_i9
lock block - (2 min 43 sec in block)
stage - (2 min 24 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (2 min 23 sec in block)
dir - (2 min 22 sec in block)riscado-v
dir block - (2 min 22 sec in block)
echo - (0.34 sec in self)Starting synthesis for FPGA colorlight_i9.
sh - (2 min 21 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p riscado-v -b colorlight_i9
stage - (16 sec in block)Flash colorlight_i9
stage block (Flash colorlight_i9) - (16 sec in block)
dir - (15 sec in block)riscado-v
dir block - (15 sec in block)
echo - (0.15 sec in self)Flashing FPGA colorlight_i9.
sh - (15 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p riscado-v -b colorlight_i9 -l
stage - (1.6 sec in block)Test colorlight_i9
stage block (Test colorlight_i9) - (1.4 sec in block)
echo - (0.22 sec in self)Testing FPGA colorlight_i9.
dir - (0.84 sec in block)riscado-v
dir block - (0.6 sec in block)
sh - (0.41 sec in self)echo "Test for FPGA in /dev/ttyACM0"
parallel block (Branch: digilent_nexys4_ddr) - (33 sec in block)
stage - (32 sec in block)digilent_nexys4_ddr
stage block (digilent_nexys4_ddr) - (32 sec in block)
lock - (31 sec in block)digilent_nexys4_ddr
lock block - (30 sec in block)
stage - (28 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (27 sec in block)
dir - (27 sec in block)riscado-v
dir block - (27 sec in block)
echo - (0.17 sec in self)Starting synthesis for FPGA digilent_nexys4_ddr.
sh - (26 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p riscado-v -b digilent_nexys4_ddr
stage - (0.96 sec in block)Flash digilent_nexys4_ddr
stage block (Flash digilent_nexys4_ddr) - (0.37 sec in block)
getContext - (0.17 sec in self)
stage - (0.7 sec in block)Test digilent_nexys4_ddr
stage block (Test digilent_nexys4_ddr) - (0.37 sec in block)
getContext - (0.17 sec in self)
stage - (0.76 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (0.49 sec in block)
junit - (0.24 sec in self)**/test-reports/*.xml