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Start of Pipeline - (11 min in block)
node - (11 min in block)
node block - (11 min in block)
stage - (2.8 sec in block)Git Clone
stage block (Git Clone) - (2.4 sec in block)
sh - (0.49 sec in self)rm -rf riscado-v
sh - (1.7 sec in self)git clone --recursive --depth=1 https://github.com/zxmarcos/riscado-v riscado-v
stage - (1.7 sec in block)Simulation
stage block (Simulation) - (1.2 sec in block)
dir - (0.87 sec in block)riscado-v
dir block - (0.63 sec in block)
sh - (0.4 sec in self)/eda/oss-cad-suite/bin/iverilog -o simulation.out -g2005 -s RISCV alu.v control_unit.v program_counter.v register_file.v riscv.v load_store.v
stage - (1.8 sec in block)Utilities
stage block (Utilities) - (1.3 sec in block)
dir - (0.9 sec in block)riscado-v
dir block - (0.63 sec in block)
sh - (0.42 sec in self)python3 /eda/processor_ci/core/labeler_prototype.py -d $(pwd) -c /eda/processor_ci/config.json -o /jenkins/processor_ci_utils/labels.json
stage - (11 min in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (11 min in block)
parallel - (11 min in block)
parallel block (Branch: colorlight_i9) - (59 ms in block)
stage - (11 min in block)colorlight_i9
stage block (colorlight_i9) - (11 min in block)
lock - (11 min in block)colorlight_i9
lock block - (6 min 13 sec in block)
stage - (5 min 54 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (5 min 53 sec in block)
dir - (5 min 52 sec in block)riscado-v
dir block - (5 min 52 sec in block)
echo - (0.31 sec in self)Starting synthesis for FPGA colorlight_i9.
sh - (5 min 51 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p riscado-v -b colorlight_i9
stage - (16 sec in block)Flash colorlight_i9
stage block (Flash colorlight_i9) - (16 sec in block)
dir - (15 sec in block)riscado-v
dir block - (15 sec in block)
echo - (0.18 sec in self)Flashing FPGA colorlight_i9.
sh - (15 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p riscado-v -b colorlight_i9 -l
stage - (1.7 sec in block)Test colorlight_i9
stage block (Test colorlight_i9) - (1.4 sec in block)
echo - (0.23 sec in self)Testing FPGA colorlight_i9.
dir - (0.9 sec in block)riscado-v
dir block - (0.63 sec in block)
sh - (0.4 sec in self)echo "Test for FPGA in /dev/ttyACM0"
parallel block (Branch: digilent_nexys4_ddr) - (45 sec in block)
stage - (44 sec in block)digilent_nexys4_ddr
stage block (digilent_nexys4_ddr) - (44 sec in block)
lock - (43 sec in block)digilent_nexys4_ddr
lock block - (42 sec in block)
stage - (40 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (40 sec in block)
dir - (39 sec in block)riscado-v
dir block - (39 sec in block)
echo - (0.15 sec in self)Starting synthesis for FPGA digilent_nexys4_ddr.
sh - (39 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p riscado-v -b digilent_nexys4_ddr
stage - (0.98 sec in block)Flash digilent_nexys4_ddr
stage block (Flash digilent_nexys4_ddr) - (0.38 sec in block)
getContext - (0.16 sec in self)
stage - (0.7 sec in block)Test digilent_nexys4_ddr
stage block (Test digilent_nexys4_ddr) - (0.37 sec in block)
getContext - (0.15 sec in self)
stage - (0.77 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (0.54 sec in block)
junit - (0.28 sec in self)**/test-reports/*.xml