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Start of Pipeline - (30 min in block)
node - (30 min in block)
node block - (30 min in block)
stage - (2 sec in block)Git Clone
stage block (Git Clone) - (1.5 sec in block)
sh - (0.46 sec in self)rm -rf riscado-v
sh - (0.91 sec in self)git clone --recursive https://github.com/zxmarcos/riscado-v riscado-v
stage - (1.6 sec in block)Simulation
stage block (Simulation) - (1.2 sec in block)
dir - (0.87 sec in block)riscado-v
dir block - (0.61 sec in block)
sh - (0.41 sec in self)iverilog -o simulation.out -g2005 -s RISCV alu.v control_unit.v program_counter.v register_file.v riscv.v load_store.v
stage - (30 min in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (30 min in block)
parallel - (30 min in block)
parallel block (Branch: colorlight_i9) - (56 ms in block)
stage - (10 min in block)colorlight_i9
stage block (colorlight_i9) - (10 min in block)
lock - (10 min in block)colorlight_i9
lock block - (5 min 32 sec in block)
stage - (5 min 8 sec in block)Síntese e PnR
stage block (Síntese e PnR) - (5 min 8 sec in block)
dir - (5 min 7 sec in block)riscado-v
dir block - (5 min 7 sec in block)
echo - (0.24 sec in self)Iniciando síntese para FPGA colorlight_i9.
sh - (5 min 6 sec in self)python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p riscado-v -b colorlight_i9
stage - (16 sec in block)Flash colorlight_i9
stage block (Flash colorlight_i9) - (16 sec in block)
dir - (15 sec in block)riscado-v
dir block - (15 sec in block)
echo - (0.15 sec in self)FPGA colorlight_i9 bloqueada para flash.
sh - (15 sec in self)python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p riscado-v -b colorlight_i9 -l
stage - (6.2 sec in block)Teste colorlight_i9
stage block (Teste colorlight_i9) - (5.9 sec in block)
echo - (0.22 sec in self)Testando FPGA colorlight_i9.
dir - (5.4 sec in block)riscado-v
dir block - (5.2 sec in block)
sh - (4.9 sec in self)PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyACM0 python /eda/processor-ci-communication/run_tests.py
parallel block (Branch: digilent_nexys4_ddr) - (29 min in block)
stage - (29 min in block)digilent_nexys4_ddr
stage block (digilent_nexys4_ddr) - (29 min in block)
lock - (29 min in block)digilent_nexys4_ddr
lock block - (12 min in block)
stage - (12 min in block)Síntese e PnR
stage block (Síntese e PnR) - (12 min in block)
dir - (12 min in block)riscado-v
dir block - (12 min in block)
echo - (0.42 sec in self)Iniciando síntese para FPGA digilent_nexys4_ddr.
sh - (12 min in self)python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p riscado-v -b digilent_nexys4_ddr
stage - (14 sec in block)Flash digilent_nexys4_ddr
stage block (Flash digilent_nexys4_ddr) - (13 sec in block)
dir - (13 sec in block)riscado-v
dir block - (13 sec in block)
echo - (0.18 sec in self)FPGA digilent_nexys4_ddr bloqueada para flash.
sh - (12 sec in self)python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p riscado-v -b digilent_nexys4_ddr -l
stage - (1.2 sec in block)Teste digilent_nexys4_ddr
stage block (Teste digilent_nexys4_ddr) - (0.98 sec in block)
echo - (0.22 sec in self)Testando FPGA digilent_nexys4_ddr.
dir - (0.41 sec in block)riscado-v
dir block - (0.15 sec in block)
stage - (0.79 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (0.55 sec in block)
junit - (0.34 sec in self)**/test-reports/*.xml